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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2023, Linaro Limited4 */5 6#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_7#define QCOM_PHY_QMP_PCS_UFS_V6_H_8 9/* Only for QMP V6 PHY - UFS PCS registers */10#define QPHY_V6_PCS_UFS_PHY_START 0x00011#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x00412#define QPHY_V6_PCS_UFS_SW_RESET 0x00813#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c14#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x01015#define QPHY_V6_PCS_UFS_PCS_CTRL1 0x02016#define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c17#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x03018#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03819#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x06020#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x07421#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc22#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c23#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x15824#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c25#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x18426#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c27#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x17828#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x17429#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a830#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f431#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc32#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x22033#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4 0x24034#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5 0x24435#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6 0x24836#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7 0x24c37 38#endif39