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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.4 */5 6#ifndef QCOM_PHY_QMP_PCS_V4_H_7#define QCOM_PHY_QMP_PCS_V4_H_8 9/* Only for QMP V4 PHY - USB/PCIe PCS registers */10#define QPHY_V4_PCS_SW_RESET 0x00011#define QPHY_V4_PCS_REVISION_ID0 0x00412#define QPHY_V4_PCS_REVISION_ID1 0x00813#define QPHY_V4_PCS_REVISION_ID2 0x00c14#define QPHY_V4_PCS_REVISION_ID3 0x01015#define QPHY_V4_PCS_PCS_STATUS1 0x01416#define QPHY_V4_PCS_PCS_STATUS2 0x01817#define QPHY_V4_PCS_PCS_STATUS3 0x01c18#define QPHY_V4_PCS_PCS_STATUS4 0x02019#define QPHY_V4_PCS_PCS_STATUS5 0x02420#define QPHY_V4_PCS_PCS_STATUS6 0x02821#define QPHY_V4_PCS_PCS_STATUS7 0x02c22#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x03023#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x03424#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x03825#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c26#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x04027#define QPHY_V4_PCS_START_CONTROL 0x04428#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x04829#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c30#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x05031#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x05432#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x05833#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c34#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x06035#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x06436#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x06837#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c38#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x07039#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x07440#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x07841#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c42#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x08043#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x08444#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x08845#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c46#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x09047#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x09448#define QPHY_V4_PCS_FLL_CNTRL1 0x09849#define QPHY_V4_PCS_FLL_CNTRL2 0x09c50#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a051#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a452#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a853#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac54#define QPHY_V4_PCS_TEST_CONTROL2 0x0b055#define QPHY_V4_PCS_TEST_CONTROL3 0x0b456#define QPHY_V4_PCS_TEST_CONTROL4 0x0b857#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc58#define QPHY_V4_PCS_TEST_CONTROL6 0x0c059#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c460#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c861#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc62#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d063#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d464#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d865#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc66#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e067#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e468#define QPHY_V4_PCS_BIST_CTRL 0x0e869#define QPHY_V4_PCS_PRBS_POLY0 0x0ec70#define QPHY_V4_PCS_PRBS_POLY1 0x0f071#define QPHY_V4_PCS_FIXED_PAT0 0x0f472#define QPHY_V4_PCS_FIXED_PAT1 0x0f873#define QPHY_V4_PCS_FIXED_PAT2 0x0fc74#define QPHY_V4_PCS_FIXED_PAT3 0x10075#define QPHY_V4_PCS_FIXED_PAT4 0x10476#define QPHY_V4_PCS_FIXED_PAT5 0x10877#define QPHY_V4_PCS_FIXED_PAT6 0x10c78#define QPHY_V4_PCS_FIXED_PAT7 0x11079#define QPHY_V4_PCS_FIXED_PAT8 0x11480#define QPHY_V4_PCS_FIXED_PAT9 0x11881#define QPHY_V4_PCS_FIXED_PAT10 0x11c82#define QPHY_V4_PCS_FIXED_PAT11 0x12083#define QPHY_V4_PCS_FIXED_PAT12 0x12484#define QPHY_V4_PCS_FIXED_PAT13 0x12885#define QPHY_V4_PCS_FIXED_PAT14 0x12c86#define QPHY_V4_PCS_FIXED_PAT15 0x13087#define QPHY_V4_PCS_TXMGN_CONFIG 0x13488#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x13889#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c90#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x14091#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x14492#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x14893#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c94#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x15095#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x15496#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x15897#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c98#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x16099#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164100#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168101#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c102#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170103#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174104#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178105#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c106#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180107#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184108#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188109#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c110#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190111#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194112#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198113#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c114#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0115#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4116#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8117#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac118#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0119#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4120#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8121#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc122#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0123#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4124#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8125#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc126#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0127#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4128#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8129#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc130#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0131#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4132#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8133#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec134 135#endif136