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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.4 */5 6#ifndef QCOM_PHY_QMP_QSERDES_PLL_H_7#define QCOM_PHY_QMP_QSERDES_PLL_H_8 9/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */10#define QSERDES_PLL_BG_TIMER 0x00c11#define QSERDES_PLL_SSC_EN_CENTER 0x01012#define QSERDES_PLL_SSC_ADJ_PER1 0x01413#define QSERDES_PLL_SSC_ADJ_PER2 0x01814#define QSERDES_PLL_SSC_PER1 0x01c15#define QSERDES_PLL_SSC_PER2 0x02016#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x02417#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x02818#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c19#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x03020#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c21#define QSERDES_PLL_CLK_ENABLE1 0x04022#define QSERDES_PLL_SYS_CLK_CTRL 0x04423#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x04824#define QSERDES_PLL_PLL_IVCO 0x05025#define QSERDES_PLL_LOCK_CMP1_MODE0 0x05426#define QSERDES_PLL_LOCK_CMP2_MODE0 0x05827#define QSERDES_PLL_LOCK_CMP1_MODE1 0x06028#define QSERDES_PLL_LOCK_CMP2_MODE1 0x06429#define QSERDES_PLL_BG_TRIM 0x07430#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x07831#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c32#define QSERDES_PLL_CP_CTRL_MODE0 0x08033#define QSERDES_PLL_CP_CTRL_MODE1 0x08434#define QSERDES_PLL_PLL_RCTRL_MODE0 0x08835#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c36#define QSERDES_PLL_PLL_CCTRL_MODE0 0x09037#define QSERDES_PLL_PLL_CCTRL_MODE1 0x09438#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a439#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a840#define QSERDES_PLL_RESETSM_CNTRL 0x0b041#define QSERDES_PLL_LOCK_CMP_EN 0x0c442#define QSERDES_PLL_DEC_START_MODE0 0x0cc43#define QSERDES_PLL_DEC_START_MODE1 0x0d044#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d845#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc46#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e047#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e448#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e849#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec50#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x10051#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x10452#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x10853#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c54#define QSERDES_PLL_VCO_TUNE_MAP 0x12055#define QSERDES_PLL_VCO_TUNE1_MODE0 0x12456#define QSERDES_PLL_VCO_TUNE2_MODE0 0x12857#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c58#define QSERDES_PLL_VCO_TUNE2_MODE1 0x13059#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c60#define QSERDES_PLL_VCO_TUNE_TIMER2 0x14061#define QSERDES_PLL_CLK_SELECT 0x16c62#define QSERDES_PLL_HSCLK_SEL 0x17063#define QSERDES_PLL_CORECLK_DIV 0x17c64#define QSERDES_PLL_CORE_CLK_EN 0x18465#define QSERDES_PLL_CMN_CONFIG 0x18c66#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x19467#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b468 69#endif70