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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.4 */5 6#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V3_H_7#define QCOM_PHY_QMP_QSERDES_TXRX_V3_H_8 9/* Only for QMP V3 PHY - TX registers */10#define QSERDES_V3_TX_BIST_MODE_LANENO 0x00011#define QSERDES_V3_TX_CLKBUF_ENABLE 0x00812#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c13#define QSERDES_V3_TX_TX_DRV_LVL 0x01c14#define QSERDES_V3_TX_RESET_TSYNC_EN 0x02415#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x02816#define QSERDES_V3_TX_TX_BAND 0x02c17#define QSERDES_V3_TX_SLEW_CNTL 0x03018#define QSERDES_V3_TX_INTERFACE_SELECT 0x03419#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c20#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x04021#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x04422#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x04823#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x05824#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c25#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x06026#define QSERDES_V3_TX_TX_POL_INV 0x06427#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x06828#define QSERDES_V3_TX_LANE_MODE_1 0x08c29#define QSERDES_V3_TX_LANE_MODE_2 0x09030#define QSERDES_V3_TX_LANE_MODE_3 0x09431#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a432#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c033#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c434#define QSERDES_V3_TX_VMODE_CTRL1 0x0f035 36/* Only for QMP V3 PHY - RX registers */37#define QSERDES_V3_RX_UCDR_FO_GAIN 0x00838#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c39#define QSERDES_V3_RX_UCDR_SO_GAIN 0x01440#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x02441#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x02842#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c43#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x03044#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x03445#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c46#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x04047#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x04448#define QSERDES_V3_RX_RX_TERM_BW 0x07c49#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc50#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c051#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c852#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc53#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d054#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d455#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d856#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc57#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f858#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc59#define QSERDES_V3_RX_SIGDET_ENABLES 0x10060#define QSERDES_V3_RX_SIGDET_CNTRL 0x10461#define QSERDES_V3_RX_SIGDET_LVL 0x10862#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c63#define QSERDES_V3_RX_RX_BAND 0x11064#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c65#define QSERDES_V3_RX_RX_MODE_00 0x16466#define QSERDES_V3_RX_RX_MODE_01 0x16867 68#endif69