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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.4 */5 6#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_7#define QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_8 9/* Only for QMP V4_20 PHY - TX registers */10#define QSERDES_V4_20_TX_LANE_MODE_1 0x8811#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c12#define QSERDES_V4_20_TX_LANE_MODE_3 0x9013#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc414#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe015 16/* Only for QMP V4_20 PHY - RX registers */17#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x00818#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x05819#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac20#define QSERDES_V4_20_RX_DFE_3 0x11021#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x13422#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x13823#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x15024#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x17825#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c826#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc27#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d028#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d429#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d830#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc31#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e032#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e433#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e834#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec35#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f036#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f437#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f838#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc39#define QSERDES_V4_20_RX_PHPRE_CTRL 0x20040#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c41#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c42 43#endif44