232 lines · c
1 2/* SPDX-License-Identifier: GPL-2.0 */3/*4 * Copyright (c) 2017, The Linux Foundation. All rights reserved.5 */6 7#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_8#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_9 10/* Only for QMP V5 PHY - TX registers */11#define QSERDES_V5_TX_BIST_MODE_LANENO 0x00012#define QSERDES_V5_TX_BIST_INVERT 0x00413#define QSERDES_V5_TX_CLKBUF_ENABLE 0x00814#define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c15#define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x01016#define QSERDES_V5_TX_TX_DRV_LVL 0x01417#define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x01818#define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c19#define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x02020#define QSERDES_V5_TX_TX_BAND 0x02421#define QSERDES_V5_TX_SLEW_CNTL 0x02822#define QSERDES_V5_TX_INTERFACE_SELECT 0x02c23#define QSERDES_V5_TX_LPB_EN 0x03024#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x03425#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x03826#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c27#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x04028#define QSERDES_V5_TX_PERL_LENGTH1 0x04429#define QSERDES_V5_TX_PERL_LENGTH2 0x04830#define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c31#define QSERDES_V5_TX_DEBUG_BUS_SEL 0x05032#define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x05433#define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x05834#define QSERDES_V5_TX_TX_POL_INV 0x05c35#define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x06036#define QSERDES_V5_TX_BIST_PATTERN1 0x06437#define QSERDES_V5_TX_BIST_PATTERN2 0x06838#define QSERDES_V5_TX_BIST_PATTERN3 0x06c39#define QSERDES_V5_TX_BIST_PATTERN4 0x07040#define QSERDES_V5_TX_BIST_PATTERN5 0x07441#define QSERDES_V5_TX_BIST_PATTERN6 0x07842#define QSERDES_V5_TX_BIST_PATTERN7 0x07c43#define QSERDES_V5_TX_BIST_PATTERN8 0x08044#define QSERDES_V5_TX_LANE_MODE_1 0x08445#define QSERDES_V5_TX_LANE_MODE_2 0x08846#define QSERDES_V5_TX_LANE_MODE_3 0x08c47#define QSERDES_V5_TX_LANE_MODE_4 0x09048#define QSERDES_V5_TX_LANE_MODE_5 0x09449#define QSERDES_V5_TX_ATB_SEL1 0x09850#define QSERDES_V5_TX_ATB_SEL2 0x09c51#define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a052#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a453#define QSERDES_V5_TX_PRBS_SEED1 0x0a854#define QSERDES_V5_TX_PRBS_SEED2 0x0ac55#define QSERDES_V5_TX_PRBS_SEED3 0x0b056#define QSERDES_V5_TX_PRBS_SEED4 0x0b457#define QSERDES_V5_TX_RESET_GEN 0x0b858#define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc59#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c060#define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c461#define QSERDES_V5_TX_VMODE_CTRL1 0x0c862#define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc63#define QSERDES_V5_TX_BIST_STATUS 0x0d064#define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d465#define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d866#define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc67#define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e068#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e469#define QSERDES_V5_TX_PRE_EMPH 0x0e870#define QSERDES_V5_TX_SW_RESET 0x0ec71#define QSERDES_V5_TX_DCC_OFFSET 0x0f072#define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f473#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f874#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc75#define QSERDES_V5_TX_DIG_BKUP_CTRL 0x10076#define QSERDES_V5_TX_DEBUG_BUS0 0x10477#define QSERDES_V5_TX_DEBUG_BUS1 0x10878#define QSERDES_V5_TX_DEBUG_BUS2 0x10c79#define QSERDES_V5_TX_DEBUG_BUS3 0x11080#define QSERDES_V5_TX_READ_EQCODE 0x11481#define QSERDES_V5_TX_READ_OFFSETCODE 0x11882#define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c83#define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x12084#define QSERDES_V5_TX_VGA_READ_CODE 0x12485#define QSERDES_V5_TX_VTH_READ_CODE 0x12886#define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c87#define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x13088#define QSERDES_V5_TX_IDAC_STATUS_I 0x13489#define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x13890#define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c91#define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x14092#define QSERDES_V5_TX_IDAC_STATUS_A 0x14493#define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x14894#define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c95#define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x15096#define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x15497#define QSERDES_V5_TX_DCC_CAL_STATUS 0x15898#define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c99 100/* Only for QMP V5 PHY - RX registers */101#define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000102#define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004103#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008104#define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c105#define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010106#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014107#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018108#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c109#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020110#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024111#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028112#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c113#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030114#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034115#define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038116#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c117#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040118#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044119#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048120#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c121#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050122#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054123#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058124#define QSERDES_V5_RX_AUX_CONTROL 0x05c125#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060126#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064127#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068128#define QSERDES_V5_RX_AC_JTAG_INITP 0x06c129#define QSERDES_V5_RX_AC_JTAG_INITN 0x070130#define QSERDES_V5_RX_AC_JTAG_LVL 0x074131#define QSERDES_V5_RX_AC_JTAG_MODE 0x078132#define QSERDES_V5_RX_AC_JTAG_RESET 0x07c133#define QSERDES_V5_RX_RX_TERM_BW 0x080134#define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084135#define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088136#define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c137#define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090138#define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094139#define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098140#define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c141#define QSERDES_V5_RX_RX_IDAC_EN 0x0a0142#define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4143#define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8144#define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac145#define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0146#define QSERDES_V5_RX_DFE_1 0x0b4147#define QSERDES_V5_RX_DFE_2 0x0b8148#define QSERDES_V5_RX_DFE_3 0x0bc149#define QSERDES_V5_RX_DFE_4 0x0c0150#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4151#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8152#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc153#define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0154#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4155#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8156#define QSERDES_V5_RX_GM_CAL 0x0dc157#define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0158#define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4159#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8160#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec161#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0162#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4163#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8164#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc165#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100166#define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104167#define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108168#define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c169#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110170#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114171#define QSERDES_V5_RX_SIGDET_ENABLES 0x118172#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c173#define QSERDES_V5_RX_SIGDET_LVL 0x120174#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124175#define QSERDES_V5_RX_RX_BAND 0x128176#define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c177#define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130178#define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134179#define QSERDES_V5_RX_JITTER_GEN_MODE 0x138180#define QSERDES_V5_RX_SJ_AMP1 0x13c181#define QSERDES_V5_RX_SJ_AMP2 0x140182#define QSERDES_V5_RX_SJ_PER1 0x144183#define QSERDES_V5_RX_SJ_PER2 0x148184#define QSERDES_V5_RX_PPM_OFFSET1 0x14c185#define QSERDES_V5_RX_PPM_OFFSET2 0x150186#define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154187#define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158188#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c189#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160190#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164191#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168192#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c193#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170194#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174195#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178196#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c197#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180198#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184199#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188200#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c201#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190202#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194203#define QSERDES_V5_RX_PHPRE_CTRL 0x198204#define QSERDES_V5_RX_PHPRE_INITVAL 0x19c205#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0206#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4207#define QSERDES_V5_RX_DCC_CTRL1 0x1a8208#define QSERDES_V5_RX_DCC_CTRL2 0x1ac209#define QSERDES_V5_RX_VTH_CODE 0x1b0210#define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4211#define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8212#define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc213#define QSERDES_V5_RX_PI_CTRL1 0x1c0214#define QSERDES_V5_RX_PI_CTRL2 0x1c4215#define QSERDES_V5_RX_PI_QUAD 0x1c8216#define QSERDES_V5_RX_IDATA1 0x1cc217#define QSERDES_V5_RX_IDATA2 0x1d0218#define QSERDES_V5_RX_AUX_DATA1 0x1d4219#define QSERDES_V5_RX_AUX_DATA2 0x1d8220#define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc221#define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0222#define QSERDES_V5_RX_RX_SIGDET 0x1e4223#define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8224 225/* Only for QMP V5 UFS ? */226#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178227#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c228#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180229#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184230 231#endif232