87 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.4 */5 6#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_7#define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_8 9/* Only for QMP V5_20 PHY - TX registers */10#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x3011#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x3412#define QSERDES_V5_20_TX_LANE_MODE_1 0x7813#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c14#define QSERDES_V5_20_TX_LANE_MODE_3 0x8015#define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x9016#define QSERDES_V5_20_TX_VMODE_CTRL1 0xb017#define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc18 19/* Only for QMP V5_20 PHY - RX registers */20#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x00821#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c22#define QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3 0x01c23#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x02024#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c25#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x03026#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c27#define QSERDES_V5_20_RX_DFE_1 0x08828#define QSERDES_V5_20_RX_DFE_2 0x08c29#define QSERDES_V5_20_RX_DFE_3 0x09030#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b431#define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1 0x0bc32#define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2 0x0c033#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c434#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c835#define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1 0x0cc36#define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2 0x0d037#define QSERDES_V5_20_RX_VGA_CAL_CNTRL1 0x0d438#define QSERDES_V5_20_RX_VGA_CAL_CNTRL2 0x0d839#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc40#define QSERDES_V5_20_RX_GM_CAL 0x0ec41#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2 0x10042#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3 0x10443#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x10844#define QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x11845#define QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x11c46#define QSERDES_V5_20_RX_SIGDET_ENABLES 0x12047#define QSERDES_V5_20_RX_SIGDET_CNTRL 0x12448#define QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL 0x12c49#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0 0x16050#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x16451#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x16852#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c53#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4 0x17054#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x17455#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x17856#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c57#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x18058#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x18459#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x18860#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c61#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x19062#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x19463#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x19864#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c65#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a066#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a467#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a868#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac69#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b070#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b471#define QSERDES_V5_20_RX_DFE_DAC_ENABLE2 0x1b872#define QSERDES_V5_20_RX_DFE_EN_TIMER 0x1bc73#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c074#define QSERDES_V5_20_RX_DCC_CTRL1 0x1c475#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f476#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f877#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc78#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x20079#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x20480#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x20881#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x21082#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x21883#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x22084#define QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x23885 86#endif87