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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.4 */5 6#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_7#define QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_8 9/* Only for QMP V5 5NM PHY - TX registers */10#define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x0011#define QSERDES_V5_5NM_TX_BIST_INVERT 0x0412#define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x0813#define QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL 0x0c14#define QSERDES_V5_5NM_TX_TX_IDLE_LVL_LARGE_AMP 0x1015#define QSERDES_V5_5NM_TX_TX_DRV_LVL 0x1416#define QSERDES_V5_5NM_TX_TX_DRV_LVL_OFFSET 0x1817#define QSERDES_V5_5NM_TX_RESET_TSYNC_EN 0x1c18#define QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN 0x2019#define QSERDES_V5_5NM_TX_LPB_EN 0x2420#define QSERDES_V5_5NM_TX_RES_CODE_LANE_TX 0x2821#define QSERDES_V5_5NM_TX_RES_CODE_LANE_RX 0x2c22#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX 0x3023#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX 0x3424#define QSERDES_V5_5NM_TX_PERL_LENGTH1 0x3825#define QSERDES_V5_5NM_TX_PERL_LENGTH2 0x3c26#define QSERDES_V5_5NM_TX_SERDES_BYP_EN_OUT 0x4027#define QSERDES_V5_5NM_TX_DEBUG_BUS_SEL 0x4428#define QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN 0x4829#define QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN 0x4c30#define QSERDES_V5_5NM_TX_TX_POL_INV 0x5031#define QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN 0x5432#define QSERDES_V5_5NM_TX_BIST_PATTERN1 0x5833#define QSERDES_V5_5NM_TX_BIST_PATTERN2 0x5c34#define QSERDES_V5_5NM_TX_BIST_PATTERN3 0x6035#define QSERDES_V5_5NM_TX_BIST_PATTERN4 0x6436#define QSERDES_V5_5NM_TX_BIST_PATTERN5 0x6837#define QSERDES_V5_5NM_TX_BIST_PATTERN6 0x6c38#define QSERDES_V5_5NM_TX_BIST_PATTERN7 0x7039#define QSERDES_V5_5NM_TX_BIST_PATTERN8 0x7440#define QSERDES_V5_5NM_TX_LANE_MODE_1 0x7841#define QSERDES_V5_5NM_TX_LANE_MODE_2 0x7c42#define QSERDES_V5_5NM_TX_LANE_MODE_3 0x8043#define QSERDES_V5_5NM_TX_ATB_SEL1 0x8444#define QSERDES_V5_5NM_TX_ATB_SEL2 0x8845#define QSERDES_V5_5NM_TX_RCV_DETECT_LVL 0x8c46#define QSERDES_V5_5NM_TX_RCV_DETECT_LVL_2 0x9047#define QSERDES_V5_5NM_TX_PRBS_SEED1 0x9448#define QSERDES_V5_5NM_TX_PRBS_SEED2 0x9849#define QSERDES_V5_5NM_TX_PRBS_SEED3 0x9c50#define QSERDES_V5_5NM_TX_PRBS_SEED4 0xa051#define QSERDES_V5_5NM_TX_RESET_GEN 0xa452#define QSERDES_V5_5NM_TX_RESET_GEN_MUXES 0xa853#define QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN 0xac54#define QSERDES_V5_5NM_TX_VMODE_CTRL1 0xb055#define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_CTRL_1 0xb456#define QSERDES_V5_5NM_TX_BIST_STATUS 0xb857#define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT1 0xbc58#define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT2 0xc059#define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_STATUS_1 0xc460#define QSERDES_V5_5NM_TX_LANE_DIG_CONFIG 0xc861#define QSERDES_V5_5NM_TX_PI_QEC_CTRL 0xcc62#define QSERDES_V5_5NM_TX_PRE_EMPH 0xd063#define QSERDES_V5_5NM_TX_SW_RESET 0xd464#define QSERDES_V5_5NM_TX_TX_BAND 0xd865#define QSERDES_V5_5NM_TX_SLEW_CNTL0 0xdc66#define QSERDES_V5_5NM_TX_SLEW_CNTL1 0xe067#define QSERDES_V5_5NM_TX_INTERFACE_SELECT 0xe468#define QSERDES_V5_5NM_TX_DIG_BKUP_CTRL 0xe869#define QSERDES_V5_5NM_TX_DEBUG_BUS0 0xec70#define QSERDES_V5_5NM_TX_DEBUG_BUS1 0xf071#define QSERDES_V5_5NM_TX_DEBUG_BUS2 0xf472#define QSERDES_V5_5NM_TX_DEBUG_BUS3 0xf873#define QSERDES_V5_5NM_TX_TX_BKUP_RO_BUS 0xfc74 75/* Only for QMP V5 5NM PHY - RX registers */76#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE0 0x00077#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE1 0x00478#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x00879#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE3 0x00c80#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE0 0x01081#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE1 0x01482#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE2 0x01883#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE3 0x01c84#define QSERDES_V5_5NM_RX_UCDR_SO_SATURATION 0x02085#define QSERDES_V5_5NM_RX_UCDR_FO_TO_SO_DELAY 0x02486#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE0 0x02887#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE0 0x02c88#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE1 0x03089#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE1 0x03490#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE2 0x03891#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE2 0x03c92#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE3 0x04093#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE3 0x04494#define QSERDES_V5_5NM_RX_UCDR_PI_CTRL1 0x04895#define QSERDES_V5_5NM_RX_UCDR_PI_CTRL2 0x04c96#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE0 0x05097#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE1 0x05498#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE2 0x05899#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE3 0x05c100#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE0 0x060101#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE1 0x064102#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE2 0x068103#define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE3 0x06c104#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE0 0x070105#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE1 0x074106#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE2 0x078107#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE3 0x07c108#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE0 0x080109#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE1 0x084110#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2 0x088111#define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE3 0x08c112#define QSERDES_V5_5NM_RX_RXCLK_DIV2_CTRL 0x090113#define QSERDES_V5_5NM_RX_RX_BAND 0x094114#define QSERDES_V5_5NM_RX_RX_TERM_BW 0x098115#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE0 0x09c116#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE1 0x0a0117#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2 0x0a4118#define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE3 0x0a8119#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE0 0x0ac120#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE1 0x0b0121#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2 0x0b4122#define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE3 0x0b8123#define QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS 0x0bc124#define QSERDES_V5_5NM_RX_UCDR_PD_DATA_FILTER_ENABLES 0x0c0125#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE0 0x0c4126#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE1 0x0c8127#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE2 0x0cc128#define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x0d0129#define QSERDES_V5_5NM_RX_AUX_CONTROL 0x0d4130#define QSERDES_V5_5NM_RX_AUXDATA_TB 0x0d8131#define QSERDES_V5_5NM_RX_RCLK_AUXDATA_SEL 0x0dc132#define QSERDES_V5_5NM_RX_EOM_CTRL 0x0e0133#define QSERDES_V5_5NM_RX_AC_JTAG_ENABLE 0x0e4134#define QSERDES_V5_5NM_RX_AC_JTAG_INITP 0x0e8135#define QSERDES_V5_5NM_RX_AC_JTAG_INITN 0x0ec136#define QSERDES_V5_5NM_RX_AC_JTAG_LVL 0x0f0137#define QSERDES_V5_5NM_RX_AC_JTAG_MODE 0x0f4138#define QSERDES_V5_5NM_RX_AC_JTAG_RESET 0x0f8139#define QSERDES_V5_5NM_RX_RX_RCVR_IQ_EN 0x0fc140#define QSERDES_V5_5NM_RX_RX_Q_EN_RATES 0x100141#define QSERDES_V5_5NM_RX_RX_IDAC_I0_DC_OFFSETS 0x104142#define QSERDES_V5_5NM_RX_RX_IDAC_I0BAR_DC_OFFSETS 0x108143#define QSERDES_V5_5NM_RX_RX_IDAC_I1_DC_OFFSETS 0x10c144#define QSERDES_V5_5NM_RX_RX_IDAC_I1BAR_DC_OFFSETS 0x110145#define QSERDES_V5_5NM_RX_RX_IDAC_Q_DC_OFFSETS 0x114146#define QSERDES_V5_5NM_RX_RX_IDAC_QBAR_DC_OFFSETS 0x118147#define QSERDES_V5_5NM_RX_RX_IDAC_A_DC_OFFSETS 0x11c148#define QSERDES_V5_5NM_RX_RX_IDAC_ABAR_DC_OFFSETS 0x120149#define QSERDES_V5_5NM_RX_RX_IDAC_EN 0x124150#define QSERDES_V5_5NM_RX_RX_IDAC_ENABLES 0x128151#define QSERDES_V5_5NM_RX_RX_IDAC_SIGN 0x12c152#define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE 0x130153#define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL1 0x134154#define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2 0x138155#define QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET 0x13c156#define QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE 0x140157#define QSERDES_V5_5NM_RX_RX_HIGHZ_PARRATE 0x144158#define QSERDES_V5_5NM_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x148159#define QSERDES_V5_5NM_RX_DFE_1 0x14c160#define QSERDES_V5_5NM_RX_DFE_2 0x150161#define QSERDES_V5_5NM_RX_DFE_3 0x154162#define QSERDES_V5_5NM_RX_DFE_4 0x158163#define QSERDES_V5_5NM_RX_DFE_TAP3_CTRL 0x15c164#define QSERDES_V5_5NM_RX_DFE_TAP3_MANVAL_KTAP 0x160165#define QSERDES_V5_5NM_RX_DFE_TAP4_CTRL 0x164166#define QSERDES_V5_5NM_RX_DFE_TAP4_MANVAL_KTAP 0x168167#define QSERDES_V5_5NM_RX_DFE_TAP5_CTRL 0x16c168#define QSERDES_V5_5NM_RX_DFE_TAP5_MANVAL_KTAP 0x170169#define QSERDES_V5_5NM_RX_TX_ADPT_CTRL 0x174170#define QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1 0x178171#define QSERDES_V5_5NM_RX_DFE_DAC_ENABLE2 0x17c172#define QSERDES_V5_5NM_RX_TX_ADAPT_PRE_THRESH1 0x180173#define QSERDES_V5_5NM_RX_TX_ADAPT_PRE_THRESH2 0x184174#define QSERDES_V5_5NM_RX_TX_ADAPT_POST_THRESH1 0x188175#define QSERDES_V5_5NM_RX_TX_ADAPT_POST_THRESH2 0x18c176#define QSERDES_V5_5NM_RX_TX_ADAPT_MAIN_THRESH1 0x190177#define QSERDES_V5_5NM_RX_TX_ADAPT_MAIN_THRESH2 0x194178#define QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1 0x198179#define QSERDES_V5_5NM_RX_VGA_CAL_CNTRL2 0x19c180#define QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL 0x1a0181#define QSERDES_V5_5NM_RX_VTHRESH_CAL_CNTRL1 0x1a4182#define QSERDES_V5_5NM_RX_VTHRESH_CAL_CNTRL2 0x1a8183#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE0 0x1ac184#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE1 0x1b0185#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE2 0x1b4186#define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE3 0x1b8187#define QSERDES_V5_5NM_RX_GM_CAL 0x1bc188#define QSERDES_V5_5NM_RX_RX_VGA_GAIN2_BLK1 0x1c0189#define QSERDES_V5_5NM_RX_RX_VGA_GAIN2_BLK2 0x1c4190#define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL2 0x1c8191#define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL3 0x1cc192#define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL4 0x1d0193#define QSERDES_V5_5NM_RX_RX_IDAC_TSETTLE_LOW 0x1d4194#define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_LSB 0x1d8195#define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_MSB 0x1dc196#define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1e0197#define QSERDES_V5_5NM_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x1e4198#define QSERDES_V5_5NM_RX_SIGDET_ENABLES 0x1e8199#define QSERDES_V5_5NM_RX_SIGDET_CNTRL 0x1ec200#define QSERDES_V5_5NM_RX_SIGDET_LVL 0x1f0201#define QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL 0x1f4202#define QSERDES_V5_5NM_RX_CDR_FREEZE_UP_DN 0x1f8203#define QSERDES_V5_5NM_RX_CDR_RESET_OVERRIDE 0x1fc204#define QSERDES_V5_5NM_RX_RX_INTERFACE_MODE 0x200205#define QSERDES_V5_5NM_RX_JITTER_GEN_MODE 0x204206#define QSERDES_V5_5NM_RX_SJ_AMP1 0x208207#define QSERDES_V5_5NM_RX_SJ_AMP2 0x20c208#define QSERDES_V5_5NM_RX_SJ_PER1 0x210209#define QSERDES_V5_5NM_RX_SJ_PER2 0x214210#define QSERDES_V5_5NM_RX_PPM_OFFSET1 0x218211#define QSERDES_V5_5NM_RX_PPM_OFFSET2 0x21c212#define QSERDES_V5_5NM_RX_SIGN_PPM_PERIOD1 0x220213#define QSERDES_V5_5NM_RX_SIGN_PPM_PERIOD2 0x224214#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0 0x228215#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1 0x22c216#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2 0x230217#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3 0x234218#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4 0x238219#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5 0x23c220#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6 0x240221#define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7 0x244222#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0 0x248223#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1 0x24c224#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2 0x250225#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3 0x254226#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4 0x258227#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5 0x25c228#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6 0x260229#define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7 0x264230#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B0 0x268231#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B1 0x26c232#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B2 0x270233#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B3 0x274234#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B4 0x278235#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B5 0x27c236#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B6 0x280237#define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B7 0x284238#define QSERDES_V5_5NM_RX_PHPRE_CTRL 0x288239#define QSERDES_V5_5NM_RX_PHPRE_INITVAL 0x28c240#define QSERDES_V5_5NM_RX_DFE_EN_TIMER 0x290241#define QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET 0x294242#define QSERDES_V5_5NM_RX_DCC_CTRL1 0x298243#define QSERDES_V5_5NM_RX_DCC_CTRL2 0x29c244#define QSERDES_V5_5NM_RX_DCC_OFFSET 0x2a0245#define QSERDES_V5_5NM_RX_DCC_CMUX_POSTCAL_OFFSET 0x2a4246#define QSERDES_V5_5NM_RX_DCC_CMUX_CAL_CTRL1 0x2a8247#define QSERDES_V5_5NM_RX_DCC_CMUX_CAL_CTRL2 0x2ac248#define QSERDES_V5_5NM_RX_ALOG_OBSV_BUS_CTRL_1 0x2b0249#define QSERDES_V5_5NM_RX_RX_MARG_CTRL1 0x2b4250#define QSERDES_V5_5NM_RX_RX_MARG_CTRL2 0x2b8251#define QSERDES_V5_5NM_RX_RX_MARG_CTRL3 0x2bc252#define QSERDES_V5_5NM_RX_RX_MARG_CTRL_4 0x2c0253#define QSERDES_V5_5NM_RX_RX_MARG_CFG_RATE_0_1 0x2c4254#define QSERDES_V5_5NM_RX_RX_MARG_CFG_RATE_2_3 0x2c8255#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_CTRL1 0x2cc256#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_CTRL2 0x2d0257#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH1_RATE210 0x2d4258#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH1_RATE3 0x2d8259#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH2_RATE210 0x2dc260#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH2_RATE3 0x2e0261#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH3_RATE210 0x2e4262#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH3_RATE3 0x2e8263#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH4_RATE210 0x2ec264#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH4_RATE3 0x2f0265#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH5_RATE210 0x2f4266#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH5_RATE3 0x2f8267#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH6_RATE210 0x2fc268#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH6_RATE3 0x300269#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH7_RATE210 0x304270#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH7_RATE3 0x308271#define QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE10 0x30c272#define QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x310273#define QSERDES_V5_5NM_RX_RX_MARG_VERTICAL_CTRL 0x314274#define QSERDES_V5_5NM_RX_RX_MARG_VERTICAL_CODE 0x318275#define QSERDES_V5_5NM_RX_RES_CODE_THRESH_HIGH_AND_BYP 0x31c276#define QSERDES_V5_5NM_RX_RES_CODE_THRESH_LOW 0x320277#define QSERDES_V5_5NM_RX_RX_BKUP_CTRL1 0x324278#define QSERDES_V5_5NM_RX_RX_BKUP_CTRL2 0x328279#define QSERDES_V5_5NM_RX_RX_BKUP_CTRL3 0x32c280#define QSERDES_V5_5NM_RX_PI_CTRL1 0x330281#define QSERDES_V5_5NM_RX_PI_CTRL2 0x334282#define QSERDES_V5_5NM_RX_PI_QUAD 0x338283#define QSERDES_V5_5NM_RX_QPI_CTRL1 0x33c284#define QSERDES_V5_5NM_RX_QPI_CTRL2 0x340285#define QSERDES_V5_5NM_RX_QPI_QUAD 0x344286#define QSERDES_V5_5NM_RX_IDATA1 0x348287#define QSERDES_V5_5NM_RX_IDATA2 0x34c288#define QSERDES_V5_5NM_RX_IDATA3 0x350289#define QSERDES_V5_5NM_RX_AC_JTAG_OUTP 0x354290#define QSERDES_V5_5NM_RX_AC_JTAG_OUTN 0x358291#define QSERDES_V5_5NM_RX_RX_SIGDET 0x35c292#define QSERDES_V5_5NM_RX_ALOG_OBSV_BUS_STATUS_1 0x360293#define QSERDES_V5_5NM_RX_READ_EQCODE 0x364294#define QSERDES_V5_5NM_RX_READ_OFFSETCODE 0x368295#define QSERDES_V5_5NM_RX_IA_ERROR_COUNTER_LOW 0x36c296#define QSERDES_V5_5NM_RX_IA_ERROR_COUNTER_HIGH 0x370297#define QSERDES_V5_5NM_RX_VGA_READ_CODE 0x374298#define QSERDES_V5_5NM_RX_VTHRESH_READ_CODE 0x378299#define QSERDES_V5_5NM_RX_DFE_TAP1_READ_CODE 0x37c300#define QSERDES_V5_5NM_RX_DFE_TAP2_READ_CODE 0x380301#define QSERDES_V5_5NM_RX_DFE_TAP3_READ_CODE 0x384302#define QSERDES_V5_5NM_RX_DFE_TAP4_READ_CODE 0x388303#define QSERDES_V5_5NM_RX_DFE_TAP5_READ_CODE 0x38c304#define QSERDES_V5_5NM_RX_IDAC_STATUS_I0 0x390305#define QSERDES_V5_5NM_RX_IDAC_STATUS_I0BAR 0x394306#define QSERDES_V5_5NM_RX_IDAC_STATUS_I1 0x398307#define QSERDES_V5_5NM_RX_IDAC_STATUS_I1BAR 0x39c308#define QSERDES_V5_5NM_RX_IDAC_STATUS_Q 0x3a0309#define QSERDES_V5_5NM_RX_IDAC_STATUS_QBAR 0x3a4310#define QSERDES_V5_5NM_RX_IDAC_STATUS_A 0x3a8311#define QSERDES_V5_5NM_RX_IDAC_STATUS_ABAR 0x3ac312#define QSERDES_V5_5NM_RX_IDAC_STATUS_SM_ON 0x3b0313#define QSERDES_V5_5NM_RX_IDAC_STATUS_SIGNERROR 0x3b4314#define QSERDES_V5_5NM_RX_IVCM_CAL_STATUS 0x3b8315#define QSERDES_V5_5NM_RX_IVCM_CAL_DEBUG_STATUS 0x3bc316#define QSERDES_V5_5NM_RX_DCC_CAL_STATUS 0x3c0317#define QSERDES_V5_5NM_RX_DCC_READ_CODE_STATUS 0x3c4318#define QSERDES_V5_5NM_RX_RX_MARG_DEBUG1_STATUS 0x3c8319#define QSERDES_V5_5NM_RX_RX_MARG_DEBUG2_STATUS 0x3cc320#define QSERDES_V5_5NM_RX_RX_MARG_READ_CODE_STATUS 0x3d0321#define QSERDES_V5_5NM_RX_EOM_ERR_CNT_LSB_STATUS 0x3d4322#define QSERDES_V5_5NM_RX_EOM_ERR_CNT_MSB_STATUS 0x3d8323#define QSERDES_V5_5NM_RX_RX_MARG_COARSE_TUNE_STATUS 0x3dc324#define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS1_STATUS 0x3e0325#define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS2_STATUS 0x3e4326#define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS3_STATUS 0x3e8327 328#endif329