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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2023, Linaro Limited4 */5 6#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_7#define QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_8 9#define QSERDES_V6_N4_TX_CLKBUF_ENABLE 0x0810#define QSERDES_V6_N4_TX_TX_EMP_POST1_LVL 0x0c11#define QSERDES_V6_N4_TX_TX_DRV_LVL 0x1412#define QSERDES_V6_N4_TX_RESET_TSYNC_EN 0x1c13#define QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN 0x2014#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX 0x3015#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX 0x3416#define QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN 0x4817#define QSERDES_V6_N4_TX_HIGHZ_DRVR_EN 0x4c18#define QSERDES_V6_N4_TX_TX_POL_INV 0x5019#define QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN 0x5420#define QSERDES_V6_N4_TX_LANE_MODE_1 0x7821#define QSERDES_V6_N4_TX_LANE_MODE_2 0x7c22#define QSERDES_V6_N4_TX_LANE_MODE_3 0x8023#define QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN 0xac24#define QSERDES_V6_N4_TX_TX_BAND 0xd825#define QSERDES_V6_N4_TX_INTERFACE_SELECT 0xe426#define QSERDES_V6_N4_TX_VMODE_CTRL1 0xb027 28#define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2 0x829#define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2 0x1830#define QSERDES_V6_N4_RX_UCDR_PI_CONTROLS 0x2031#define QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE 0x9432#define QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2 0x9c33#define QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET 0xa034#define QSERDES_V6_N4_RX_DFE_3 0xb435#define QSERDES_V6_N4_RX_VGA_CAL_CNTRL1 0xe036#define QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL 0xe837#define QSERDES_V6_N4_RX_GM_CAL 0x10c38#define QSERDES_V6_N4_RX_SIGDET_ENABLES 0x14839#define QSERDES_V6_N4_RX_SIGDET_CNTRL 0x14c40#define QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL 0x15441#define QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET 0x19442#define QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc43#define QSERDES_V6_N4_RX_UCDR_PI_CTRL1 0x23c44#define QSERDES_V6_N4_RX_UCDR_PI_CTRL2 0x24045#define QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2 0x27c46#define QSERDES_V6_N4_RX_DFE_DAC_ENABLE1 0x29847#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B0 0x2b848#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B1 0x2bc49#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B2 0x2c050#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B3 0x2c451#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B4 0x2c852#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B5 0x2cc53#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B6 0x2d054#define QSERDES_V6_N4_RX_MODE_RATE2_B0 0x2d455#define QSERDES_V6_N4_RX_MODE_RATE2_B1 0x2d856#define QSERDES_V6_N4_RX_MODE_RATE2_B2 0x2dc57#define QSERDES_V6_N4_RX_MODE_RATE2_B3 0x2e058#define QSERDES_V6_N4_RX_MODE_RATE2_B4 0x2e459#define QSERDES_V6_N4_RX_MODE_RATE2_B5 0x2e860#define QSERDES_V6_N4_RX_MODE_RATE2_B6 0x2ec61#define QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE 0x30c62#define QSERDES_V6_N4_RX_RX_BKUP_CTRL1 0x31063 64#endif65