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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.4 */5 6#ifndef QCOM_PHY_QMP_QSERDES_TXRX_H_7#define QCOM_PHY_QMP_QSERDES_TXRX_H_8 9/* Only for QMP V2 PHY - TX registers */10#define QSERDES_TX_BIST_MODE_LANENO 0x00011#define QSERDES_TX_BIST_INVERT 0x00412#define QSERDES_TX_CLKBUF_ENABLE 0x00813#define QSERDES_TX_CMN_CONTROL_ONE 0x00c14#define QSERDES_TX_CMN_CONTROL_TWO 0x01015#define QSERDES_TX_CMN_CONTROL_THREE 0x01416#define QSERDES_TX_TX_EMP_POST1_LVL 0x01817#define QSERDES_TX_TX_POST2_EMPH 0x01c18#define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x02019#define QSERDES_TX_HP_PD_ENABLES 0x02420#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x02821#define QSERDES_TX_TX_DRV_LVL 0x02c22#define QSERDES_TX_TX_DRV_LVL_OFFSET 0x03023#define QSERDES_TX_RESET_TSYNC_EN 0x03424#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x03825#define QSERDES_TX_TX_BAND 0x03c26#define QSERDES_TX_SLEW_CNTL 0x04027#define QSERDES_TX_INTERFACE_SELECT 0x04428#define QSERDES_TX_LPB_EN 0x04829#define QSERDES_TX_RES_CODE_LANE_TX 0x04c30#define QSERDES_TX_RES_CODE_LANE_RX 0x05031#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x05432#define QSERDES_TX_PERL_LENGTH1 0x05833#define QSERDES_TX_PERL_LENGTH2 0x05c34#define QSERDES_TX_SERDES_BYP_EN_OUT 0x06035#define QSERDES_TX_DEBUG_BUS_SEL 0x06436#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x06837#define QSERDES_TX_TX_POL_INV 0x06c38#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x07039#define QSERDES_TX_BIST_PATTERN1 0x07440#define QSERDES_TX_BIST_PATTERN2 0x07841#define QSERDES_TX_BIST_PATTERN3 0x07c42#define QSERDES_TX_BIST_PATTERN4 0x08043#define QSERDES_TX_BIST_PATTERN5 0x08444#define QSERDES_TX_BIST_PATTERN6 0x08845#define QSERDES_TX_BIST_PATTERN7 0x08c46#define QSERDES_TX_BIST_PATTERN8 0x09047#define QSERDES_TX_LANE_MODE 0x09448#define QSERDES_TX_IDAC_CAL_LANE_MODE 0x09849#define QSERDES_TX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x09c50#define QSERDES_TX_ATB_SEL1 0x0a051#define QSERDES_TX_ATB_SEL2 0x0a452#define QSERDES_TX_RCV_DETECT_LVL 0x0a853#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac54#define QSERDES_TX_PRBS_SEED1 0x0b055#define QSERDES_TX_PRBS_SEED2 0x0b456#define QSERDES_TX_PRBS_SEED3 0x0b857#define QSERDES_TX_PRBS_SEED4 0x0bc58#define QSERDES_TX_RESET_GEN 0x0c059#define QSERDES_TX_RESET_GEN_MUXES 0x0c460#define QSERDES_TX_TRAN_DRVR_EMP_EN 0x0c861#define QSERDES_TX_TX_INTERFACE_MODE 0x0cc62#define QSERDES_TX_PWM_CTRL 0x0d063#define QSERDES_TX_PWM_ENCODED_OR_DATA 0x0d464#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0d865#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0dc66#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0e067#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0e468#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0e869#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0ec70#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0f071#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0f472#define QSERDES_TX_VMODE_CTRL1 0x0f873#define QSERDES_TX_VMODE_CTRL2 0x0fc74#define QSERDES_TX_TX_ALOG_INTF_OBSV_CNTL 0x10075#define QSERDES_TX_BIST_STATUS 0x10476#define QSERDES_TX_BIST_ERROR_COUNT1 0x10877#define QSERDES_TX_BIST_ERROR_COUNT2 0x10c78#define QSERDES_TX_TX_ALOG_INTF_OBSV 0x11079 80/* Only for QMP V2 PHY - RX registers */81#define QSERDES_RX_UCDR_FO_GAIN_HALF 0x00082#define QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x00483#define QSERDES_RX_UCDR_FO_GAIN_EIGHTH 0x00884#define QSERDES_RX_UCDR_FO_GAIN 0x00c85#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x01086#define QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x01487#define QSERDES_RX_UCDR_SO_GAIN_EIGHTH 0x01888#define QSERDES_RX_UCDR_SO_GAIN 0x01c89#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x02090#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x02491#define QSERDES_RX_UCDR_SVS_FO_GAIN_EIGHTH 0x02892#define QSERDES_RX_UCDR_SVS_FO_GAIN 0x02c93#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x03094#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x03495#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x03896#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c97#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x04098#define QSERDES_RX_UCDR_FD_GAIN 0x04499#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048100#define QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x04c101#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x050102#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x054103#define QSERDES_RX_UCDR_MODULATE 0x058104#define QSERDES_RX_UCDR_PI_CONTROLS 0x05c105#define QSERDES_RX_RBIST_CONTROL 0x060106#define QSERDES_RX_AUX_CONTROL 0x064107#define QSERDES_RX_AUX_DATA_TCOARSE 0x068108#define QSERDES_RX_AUX_DATA_TFINE_LSB 0x06c109#define QSERDES_RX_AUX_DATA_TFINE_MSB 0x070110#define QSERDES_RX_RCLK_AUXDATA_SEL 0x074111#define QSERDES_RX_AC_JTAG_ENABLE 0x078112#define QSERDES_RX_AC_JTAG_INITP 0x07c113#define QSERDES_RX_AC_JTAG_INITN 0x080114#define QSERDES_RX_AC_JTAG_LVL 0x084115#define QSERDES_RX_AC_JTAG_MODE 0x088116#define QSERDES_RX_AC_JTAG_RESET 0x08c117#define QSERDES_RX_RX_TERM_BW 0x090118#define QSERDES_RX_RX_RCVR_IQ_EN 0x094119#define QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x098120#define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x09c121#define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x0a0122#define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x0a4123#define QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x0a8124#define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x0ac125#define QSERDES_RX_RX_IDAC_EN 0x0b0126#define QSERDES_RX_RX_IDAC_ENABLES 0x0b4127#define QSERDES_RX_RX_IDAC_SIGN 0x0b8128#define QSERDES_RX_RX_HIGHZ_HIGHRATE 0x0bc129#define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0c0130#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4131#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8132#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc133#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0134#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d4135#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8136#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc137#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0138#define QSERDES_RX_RX_IDAC_CAL_CONFIGURATION 0x0e4139#define QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x0e8140#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x0ec141#define QSERDES_RX_RX_IDAC_ENDSAMP_LOW 0x0f0142#define QSERDES_RX_RX_IDAC_ENDSAMP_HIGH 0x0f4143#define QSERDES_RX_RX_IDAC_MIDPOINT_LOW 0x0f8144#define QSERDES_RX_RX_IDAC_MIDPOINT_HIGH 0x0fc145#define QSERDES_RX_RX_EQ_OFFSET_LSB 0x100146#define QSERDES_RX_RX_EQ_OFFSET_MSB 0x104147#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108148#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c149#define QSERDES_RX_SIGDET_ENABLES 0x110150#define QSERDES_RX_SIGDET_CNTRL 0x114151#define QSERDES_RX_SIGDET_LVL 0x118152#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c153#define QSERDES_RX_RX_BAND 0x120154#define QSERDES_RX_CDR_FREEZE_UP_DN 0x124155#define QSERDES_RX_CDR_RESET_OVERRIDE 0x128156#define QSERDES_RX_RX_INTERFACE_MODE 0x12c157#define QSERDES_RX_JITTER_GEN_MODE 0x130158#define QSERDES_RX_BUJ_AMP 0x134159#define QSERDES_RX_SJ_AMP1 0x138160#define QSERDES_RX_SJ_AMP2 0x13c161#define QSERDES_RX_SJ_PER1 0x140162#define QSERDES_RX_SJ_PER2 0x144163#define QSERDES_RX_BUJ_STEP_FREQ1 0x148164#define QSERDES_RX_BUJ_STEP_FREQ2 0x14c165#define QSERDES_RX_PPM_OFFSET1 0x150166#define QSERDES_RX_PPM_OFFSET2 0x154167#define QSERDES_RX_SIGN_PPM_PERIOD1 0x158168#define QSERDES_RX_SIGN_PPM_PERIOD2 0x15c169#define QSERDES_RX_SSC_CTRL 0x160170#define QSERDES_RX_SSC_COUNT1 0x164171#define QSERDES_RX_SSC_COUNT2 0x168172#define QSERDES_RX_RX_ALOG_INTF_OBSV_CNTL 0x16c173#define QSERDES_RX_RX_PWM_ENABLE_AND_DATA 0x170174#define QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x174175#define QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x178176#define QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x17c177#define QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x180178#define QSERDES_RX_PI_CTRL1 0x184179#define QSERDES_RX_PI_CTRL2 0x188180#define QSERDES_RX_PI_QUAD 0x18c181#define QSERDES_RX_IDATA1 0x190182#define QSERDES_RX_IDATA2 0x194183#define QSERDES_RX_AUX_DATA1 0x198184#define QSERDES_RX_AUX_DATA2 0x19c185#define QSERDES_RX_AC_JTAG_OUTP 0x1a0186#define QSERDES_RX_AC_JTAG_OUTN 0x1a4187#define QSERDES_RX_RX_SIGDET 0x1a8188#define QSERDES_RX_RX_VDCOFF 0x1ac189#define QSERDES_RX_IDAC_CAL_ON 0x1b0190#define QSERDES_RX_IDAC_STATUS_I 0x1b4191#define QSERDES_RX_IDAC_STATUS_IBAR 0x1b8192#define QSERDES_RX_IDAC_STATUS_Q 0x1bc193#define QSERDES_RX_IDAC_STATUS_QBAR 0x1c0194#define QSERDES_RX_IDAC_STATUS_A 0x1c4195#define QSERDES_RX_IDAC_STATUS_ABAR 0x1c8196#define QSERDES_RX_CALST_STATUS_I 0x1cc197#define QSERDES_RX_CALST_STATUS_Q 0x1d0198#define QSERDES_RX_CALST_STATUS_A 0x1d4199#define QSERDES_RX_RX_ALOG_INTF_OBSV 0x1d8200#define QSERDES_RX_READ_EQCODE 0x1dc201#define QSERDES_RX_READ_OFFSETCODE 0x1e0202#define QSERDES_RX_IA_ERROR_COUNTER_LOW 0x1e4203#define QSERDES_RX_IA_ERROR_COUNTER_HIGH 0x1e8204 205#endif206