2305 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.4 */5 6#include <linux/clk.h>7#include <linux/clk-provider.h>8#include <linux/delay.h>9#include <linux/err.h>10#include <linux/io.h>11#include <linux/iopoll.h>12#include <linux/kernel.h>13#include <linux/module.h>14#include <linux/of.h>15#include <linux/of_address.h>16#include <linux/phy/phy.h>17#include <linux/platform_device.h>18#include <linux/regulator/consumer.h>19#include <linux/reset.h>20#include <linux/slab.h>21 22#include "phy-qcom-qmp-common.h"23 24#include "phy-qcom-qmp.h"25#include "phy-qcom-qmp-pcs-misc-v3.h"26#include "phy-qcom-qmp-pcs-misc-v4.h"27#include "phy-qcom-qmp-pcs-usb-v4.h"28#include "phy-qcom-qmp-pcs-usb-v5.h"29#include "phy-qcom-qmp-pcs-usb-v6.h"30#include "phy-qcom-qmp-pcs-usb-v7.h"31 32#define PHY_INIT_COMPLETE_TIMEOUT 1000033 34/* set of registers with offsets different per-PHY */35enum qphy_reg_layout {36 /* PCS registers */37 QPHY_SW_RESET,38 QPHY_START_CTRL,39 QPHY_PCS_STATUS,40 QPHY_PCS_AUTONOMOUS_MODE_CTRL,41 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,42 QPHY_PCS_POWER_DOWN_CONTROL,43 QPHY_PCS_MISC_CLAMP_ENABLE,44 /* Keep last to ensure regs_layout arrays are properly initialized */45 QPHY_LAYOUT_SIZE46};47 48static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {49 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,50 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,51 [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS,52 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,53 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,54 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,55};56 57static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {58 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,59 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,60 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,61 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,62 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,63 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,64 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE,65};66 67static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {68 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,69 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,70 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,71 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,72 73 /* In PCS_USB */74 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,75 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,76 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V4_PCS_MISC_CLAMP_ENABLE,77};78 79static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {80 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,81 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,82 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,83 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,84 85 /* In PCS_USB */86 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,87 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,88};89 90static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {91 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,92 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,93 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,94 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,95 96 /* In PCS_USB */97 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,98 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,99};100 101static const unsigned int qmp_v7_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {102 [QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET,103 [QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL,104 [QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1,105 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL,106 107 /* In PCS_USB */108 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL,109 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,110};111 112static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {113 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),114 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),115 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),116 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),117 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),118 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),119 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),120 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),121 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),122 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),123 /* PLL and Loop filter settings */124 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),125 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),126 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),127 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),128 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),129 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),130 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),131 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),132 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),133 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),134 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),135 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),136 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),137 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),138 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),139 /* SSC settings */140 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),141 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),142 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),143 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),144 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),145 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),146 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),147};148 149static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {150 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),151 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),152 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),153};154 155static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {156 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),157 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),158 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),159 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),160 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),161 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),162 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),163 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),164 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),165 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),166};167 168static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),177 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),178 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),179 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),180 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),181 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),192};193 194static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {195 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),196 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),197 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),198 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),199 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),200 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),201 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),202 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),203 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),204 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),205 /* PLL and Loop filter settings */206 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),207 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),208 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),209 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),210 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),211 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),212 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),213 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),214 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),215 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),216 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),217 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),218 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),219 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),220 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),221 /* SSC settings */222 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),223 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),224 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),225 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),226 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),227 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),228 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),229};230 231static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {232 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),233 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),234 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),235 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),236 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),237 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),238 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),239 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),240 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),241};242 243static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {244 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),245 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),246 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),247 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),248 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),249 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),250 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),251 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),252 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),253 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),254 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),255 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),256 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),257 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),258 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),259 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),260 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),261 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),262 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),263 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),264 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),265 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),266 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),267};268 269static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {270 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),271 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),272 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),273 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),274 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),275 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),276 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),277 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),278 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),279 /* PLL and Loop filter settings */280 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),281 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),282 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),283 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),284 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),285 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),286 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),287 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),288 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),289 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),290 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),291 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),292 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),293 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),294 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),295 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),296 /* SSC settings */297 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),298 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),299 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),300 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),301 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),302 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),303 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),304};305 306static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {307 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),308 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),309 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),310};311 312static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {313 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),314 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),315 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),316 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),317 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),318 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),319 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),320 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),321 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),322 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),323};324 325static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {326 /* FLL settings */327 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),328 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),329 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),330 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),331 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),332 333 /* Lock Det settings */334 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),335 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),336 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),337 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),338};339 340static const struct qmp_phy_init_tbl qdu1000_usb3_uniphy_pcs_tbl[] = {341 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xc4),342 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x89),343 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),344 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),345 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),346 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),347 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),348 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),349 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),350 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),351 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),352 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),353 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),354 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),355};356 357static const struct qmp_phy_init_tbl qdu1000_usb3_uniphy_pcs_usb_tbl[] = {358 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),359 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),360 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),361};362 363static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {364 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),365 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),366 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),367 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),368 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),369 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),370 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),371 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),372 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),373 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),374 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),375 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),376 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),377 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),378 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),379 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),380 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),381 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),382 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),383 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),384 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),385 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),386 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),387 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),388 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),389 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),390 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),391 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),392 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),393 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),394 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),400};401 402static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {403 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),404 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),405 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),406 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),407 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),408};409 410static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {411 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),412 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),413 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),414 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),415 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),416 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),417 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),418 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),419 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),420 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),421 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),422};423 424static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {425 /* FLL settings */426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),429 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),431 432 /* Lock Det settings */433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),434 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),437 438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),442 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),443 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),444 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),457 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),469 470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),472};473 474static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),486 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),487 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),488 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),490 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),491 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),492 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),493 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),494 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),495 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),496 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),497 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),513 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),514 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),515};516 517static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {518 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),519 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),520 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),521 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),522};523 524static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),540 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),541 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),542 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),560 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),561};562 563static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {564 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),565 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),566 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),567 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),568 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),569 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),570 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),571 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),572 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),573 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),574 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),575 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),576 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),577 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),578};579 580static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {581 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),582 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),583};584 585static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {586 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),587 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),588 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),589 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),590 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),591 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),592};593 594static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),615 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),616 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),617 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),618 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),621 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),622 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),623 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),631};632 633static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {634 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),635 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),636 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),637 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),638 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),639 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),640 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),641 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),642 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),643 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),645 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),646 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),647 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),648};649 650static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {651 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),652 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),653};654 655static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {656 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),657 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),658 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),659 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),660 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),661};662 663static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),700};701 702static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {703 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),704 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),705 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),706 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),707 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),708 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),709 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),710};711 712static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {713 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),714 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),715 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),716 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),717 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),718 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),719 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),720 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),721 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),722 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),723 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),724 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),725 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),726 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),727 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),728 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),729 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),730 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),731 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),732 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),733 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),734 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),735 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),736 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),737 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),738 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),739 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),740 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),741 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),742 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),743 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),744};745 746static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_serdes_tbl[] = {747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x9e),748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06),749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),752 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),753 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e),754 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82),755 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),756 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),757 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xea),758 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7),763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7),765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x9e),767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06),768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),770 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),771 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12),772 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34),773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),774 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),775 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea),776 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02),777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),785 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),786 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),787 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),788 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),792 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),793};794 795static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_tx_tbl[] = {796 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),797 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),798 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),799 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),800 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),801 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),802 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),803 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),804 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),805 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x21),806};807 808static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_rx_tbl[] = {809 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),810 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),811 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),812 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),813 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),814 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),815 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),816 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),817 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),818 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),819 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),820 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),821 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),822 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),823 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),824 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),825 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),826 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),827 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),828 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),829 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),830 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),831 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),832 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),833 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),834 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff),835 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf),836 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed),837 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),838 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),839 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),840 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),841 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),842 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),843 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),844 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),845 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),846 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),847 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),848};849 850static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_tbl[] = {851 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),852 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),853 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),854 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),855 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),856 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0xaa),857 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),858 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),859 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),860 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),861 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),862 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),863 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),864 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),865};866 867static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_usb_tbl[] = {868 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),869 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),870 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),871 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),872};873 874static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {875 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),876 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),877 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),878 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),879 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),880 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),881 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),882};883 884static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {885 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),886 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),887 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),888 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),889 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),890 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),891 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),892 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),893 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),894 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),895 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),896 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),897 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),898 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),899 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),900 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),901 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),902 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),903 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),904 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),905 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),906 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),907 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),908 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),909 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),910 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),911 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),912 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),913 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),914 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),915 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),916};917 918static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {919 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),920 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),921 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),922 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),923 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),924 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),925 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),926 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),927 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),928 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),929 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),930 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),931 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),932 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),933};934 935static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {936 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),937 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),938};939 940static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {941 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),942 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),943 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),944 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),945 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),946 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),947 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),948 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),949 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),950 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),951 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),952 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),953 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),954 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),955 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),956 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),957 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),958 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),959 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),960 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),961 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),962 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),963 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),964 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),965 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),966 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),967 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),968 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),969 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),970 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),971 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),972 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),973 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),974 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),975 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),976 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),977 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),978 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),979 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),980};981 982static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {983 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),984 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),985 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),986 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),987 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),988 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),989 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),990};991 992static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {993 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),994 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),995 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),996 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),997 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),998 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),999 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),1000 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),1001 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),1002 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),1003 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),1004 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),1005 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),1006 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),1007 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),1008 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),1009 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),1010 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),1011 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),1012 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),1013 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),1014 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),1015 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),1016 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),1017 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),1018 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),1019 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),1020 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),1021 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),1022 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),1023 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),1024};1025 1026static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {1027 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),1028 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),1029 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),1030 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),1031 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),1032 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),1033 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),1034 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),1035 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),1036 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),1037 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),1038 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),1039 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),1040 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),1041};1042 1043static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = {1044 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),1045 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),1046};1047 1048static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = {1049 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4),1050 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89),1051 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),1052 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),1053 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),1054 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),1055 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),1056 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),1057 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),1058 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),1059 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),1060 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),1061 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),1062 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),1063};1064 1065static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = {1066 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),1067 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),1068 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),1069};1070 1071static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_serdes_tbl[] = {1072 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0xc0),1073 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01),1074 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02),1075 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16),1076 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36),1077 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04),1078 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x16),1079 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x41),1080 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x41),1081 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55),1082 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x75),1083 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01),1084 QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01),1085 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE1, 0x25),1086 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE1, 0x02),1087 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),1088 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),1089 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),1090 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),1091 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xc0),1092 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01),1093 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02),1094 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16),1095 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36),1096 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x08),1097 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x1a),1098 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41),1099 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0x55),1100 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0x75),1101 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01),1102 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE0, 0x25),1103 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE0, 0x02),1104 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a),1105 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x01),1106 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62),1107 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02),1108 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_BUF_ENABLE, 0x0a),1109 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x1a),1110 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_CFG, 0x14),1111 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x04),1112 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0x20),1113 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16),1114 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),1115 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),1116 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),1117 QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC, 0x0c),1118};1119 1120static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_tx_tbl[] = {1121 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_TX, 0x00),1122 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_RX, 0x00),1123 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),1124 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x09),1125 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0xf5),1126 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x3f),1127 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x3f),1128 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x5f),1129 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RCV_DETECT_LVL_2, 0x12),1130 QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x21),1131};1132 1133static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_rx_tbl[] = {1134 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x0a),1135 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x06),1136 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),1137 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),1138 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),1139 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),1140 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_PI_CONTROLS, 0x99),1141 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08),1142 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08),1143 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN1, 0x00),1144 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN2, 0x0a),1145 QMP_PHY_INIT_CFG(QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),1146 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL1, 0x54),1147 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x0f),1148 QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x13),1149 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),1150 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),1151 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),1152 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07),1153 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH, 0x00),1154 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),1155 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x04),1156 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),1157 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3f),1158 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xbf),1159 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xff),1160 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xdf),1161 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xed),1162 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xdc),1163 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x5c),1164 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x9c),1165 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1d),1166 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x09),1167 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_EN_TIMER, 0x04),1168 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),1169 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DCC_CTRL1, 0x0c),1170 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VTH_CODE, 0x10),1171 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_CTRL1, 0x14),1172 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08),1173};1174 1175static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_tbl[] = {1176 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG1, 0xc4),1177 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG2, 0x89),1178 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG3, 0x20),1179 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG6, 0x13),1180 QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x21),1181 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0xaa),1182 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),1183 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),1184 QMP_PHY_INIT_CFG(QPHY_V7_PCS_CDR_RESET_TIME, 0x0a),1185 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG1, 0x88),1186 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG2, 0x13),1187 QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x0c),1188 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG1, 0x4b),1189 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG5, 0x10),1190};1191 1192static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_usb_tbl[] = {1193 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),1194 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),1195 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),1196 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),1197};1198 1199struct qmp_usb_offsets {1200 u16 serdes;1201 u16 pcs;1202 u16 pcs_misc;1203 u16 pcs_usb;1204 u16 tx;1205 u16 rx;1206};1207 1208/* struct qmp_phy_cfg - per-PHY initialization config */1209struct qmp_phy_cfg {1210 const struct qmp_usb_offsets *offsets;1211 1212 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */1213 const struct qmp_phy_init_tbl *serdes_tbl;1214 int serdes_tbl_num;1215 const struct qmp_phy_init_tbl *tx_tbl;1216 int tx_tbl_num;1217 const struct qmp_phy_init_tbl *rx_tbl;1218 int rx_tbl_num;1219 const struct qmp_phy_init_tbl *pcs_tbl;1220 int pcs_tbl_num;1221 const struct qmp_phy_init_tbl *pcs_usb_tbl;1222 int pcs_usb_tbl_num;1223 1224 /* regulators to be requested */1225 const char * const *vreg_list;1226 int num_vregs;1227 1228 /* array of registers with different offsets */1229 const unsigned int *regs;1230 1231 /* true, if PHY needs delay after POWER_DOWN */1232 bool has_pwrdn_delay;1233 1234 /* Offset from PCS to PCS_USB region */1235 unsigned int pcs_usb_offset;1236};1237 1238struct qmp_usb {1239 struct device *dev;1240 1241 const struct qmp_phy_cfg *cfg;1242 1243 void __iomem *serdes;1244 void __iomem *pcs;1245 void __iomem *pcs_misc;1246 void __iomem *pcs_usb;1247 void __iomem *tx;1248 void __iomem *rx;1249 1250 struct clk *pipe_clk;1251 struct clk_bulk_data *clks;1252 int num_clks;1253 int num_resets;1254 struct reset_control_bulk_data *resets;1255 struct regulator_bulk_data *vregs;1256 1257 enum phy_mode mode;1258 1259 struct phy *phy;1260 1261 struct clk_fixed_rate pipe_clk_fixed;1262};1263 1264static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)1265{1266 u32 reg;1267 1268 reg = readl(base + offset);1269 reg |= val;1270 writel(reg, base + offset);1271 1272 /* ensure that above write is through */1273 readl(base + offset);1274}1275 1276static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)1277{1278 u32 reg;1279 1280 reg = readl(base + offset);1281 reg &= ~val;1282 writel(reg, base + offset);1283 1284 /* ensure that above write is through */1285 readl(base + offset);1286}1287 1288/* list of clocks required by phy */1289static const char * const qmp_usb_phy_clk_l[] = {1290 "aux", "cfg_ahb", "ref", "com_aux",1291};1292 1293/* list of resets */1294static const char * const usb3phy_legacy_reset_l[] = {1295 "phy", "common",1296};1297 1298static const char * const usb3phy_reset_l[] = {1299 "phy_phy", "phy",1300};1301 1302/* list of regulators */1303static const char * const qmp_phy_vreg_l[] = {1304 "vdda-phy", "vdda-pll",1305};1306 1307static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {1308 .serdes = 0,1309 .pcs = 0x800,1310 .pcs_misc = 0x600,1311 .tx = 0x200,1312 .rx = 0x400,1313};1314 1315static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {1316 .serdes = 0,1317 .pcs = 0x800,1318 .pcs_usb = 0x800,1319 .tx = 0x200,1320 .rx = 0x400,1321};1322 1323static const struct qmp_usb_offsets qmp_usb_offsets_v3_msm8996 = {1324 .serdes = 0,1325 .pcs = 0x600,1326 .tx = 0x200,1327 .rx = 0x400,1328};1329 1330static const struct qmp_usb_offsets qmp_usb_offsets_v4 = {1331 .serdes = 0,1332 .pcs = 0x0800,1333 .pcs_usb = 0x0e00,1334 .tx = 0x0200,1335 .rx = 0x0400,1336};1337 1338static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {1339 .serdes = 0,1340 .pcs = 0x0200,1341 .pcs_usb = 0x1200,1342 .tx = 0x0e00,1343 .rx = 0x1000,1344};1345 1346static const struct qmp_usb_offsets qmp_usb_offsets_v6 = {1347 .serdes = 0,1348 .pcs = 0x0200,1349 .pcs_usb = 0x1200,1350 .tx = 0x0e00,1351 .rx = 0x1000,1352};1353 1354static const struct qmp_usb_offsets qmp_usb_offsets_v7 = {1355 .serdes = 0,1356 .pcs = 0x0200,1357 .pcs_usb = 0x1200,1358 .tx = 0x0e00,1359 .rx = 0x1000,1360};1361 1362static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {1363 .offsets = &qmp_usb_offsets_v3,1364 1365 .serdes_tbl = ipq9574_usb3_serdes_tbl,1366 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),1367 .tx_tbl = msm8996_usb3_tx_tbl,1368 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),1369 .rx_tbl = ipq8074_usb3_rx_tbl,1370 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),1371 .pcs_tbl = ipq8074_usb3_pcs_tbl,1372 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),1373 .vreg_list = qmp_phy_vreg_l,1374 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1375 .regs = qmp_v3_usb3phy_regs_layout,1376};1377 1378static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {1379 .offsets = &qmp_usb_offsets_v3,1380 1381 .serdes_tbl = ipq8074_usb3_serdes_tbl,1382 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),1383 .tx_tbl = msm8996_usb3_tx_tbl,1384 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),1385 .rx_tbl = ipq8074_usb3_rx_tbl,1386 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),1387 .pcs_tbl = ipq8074_usb3_pcs_tbl,1388 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),1389 .vreg_list = qmp_phy_vreg_l,1390 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1391 .regs = qmp_v3_usb3phy_regs_layout,1392};1393 1394static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {1395 .offsets = &qmp_usb_offsets_ipq9574,1396 1397 .serdes_tbl = ipq9574_usb3_serdes_tbl,1398 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),1399 .tx_tbl = ipq9574_usb3_tx_tbl,1400 .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),1401 .rx_tbl = ipq9574_usb3_rx_tbl,1402 .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),1403 .pcs_tbl = ipq9574_usb3_pcs_tbl,1404 .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),1405 .vreg_list = qmp_phy_vreg_l,1406 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1407 .regs = qmp_v3_usb3phy_regs_layout,1408};1409 1410static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {1411 .offsets = &qmp_usb_offsets_v3_msm8996,1412 1413 .serdes_tbl = msm8996_usb3_serdes_tbl,1414 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),1415 .tx_tbl = msm8996_usb3_tx_tbl,1416 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),1417 .rx_tbl = msm8996_usb3_rx_tbl,1418 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),1419 .pcs_tbl = msm8996_usb3_pcs_tbl,1420 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),1421 .vreg_list = qmp_phy_vreg_l,1422 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1423 .regs = qmp_v2_usb3phy_regs_layout,1424};1425 1426static const struct qmp_phy_cfg qdu1000_usb3_uniphy_cfg = {1427 .offsets = &qmp_usb_offsets_v5,1428 1429 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,1430 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),1431 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,1432 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),1433 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,1434 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),1435 .pcs_tbl = qdu1000_usb3_uniphy_pcs_tbl,1436 .pcs_tbl_num = ARRAY_SIZE(qdu1000_usb3_uniphy_pcs_tbl),1437 .pcs_usb_tbl = qdu1000_usb3_uniphy_pcs_usb_tbl,1438 .pcs_usb_tbl_num = ARRAY_SIZE(qdu1000_usb3_uniphy_pcs_usb_tbl),1439 .vreg_list = qmp_phy_vreg_l,1440 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1441 .regs = qmp_v4_usb3phy_regs_layout,1442 .pcs_usb_offset = 0x1000,1443 1444 .has_pwrdn_delay = true,1445};1446 1447static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {1448 .offsets = &qmp_usb_offsets_v5,1449 1450 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,1451 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),1452 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,1453 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),1454 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,1455 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),1456 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl,1457 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),1458 .pcs_usb_tbl = sa8775p_usb3_uniphy_pcs_usb_tbl,1459 .pcs_usb_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl),1460 .vreg_list = qmp_phy_vreg_l,1461 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1462 .regs = qmp_v5_usb3phy_regs_layout,1463};1464 1465static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {1466 .offsets = &qmp_usb_offsets_v5,1467 1468 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,1469 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),1470 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,1471 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),1472 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,1473 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),1474 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl,1475 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),1476 .pcs_usb_tbl = sc8280xp_usb3_uniphy_pcs_usb_tbl,1477 .pcs_usb_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl),1478 .vreg_list = qmp_phy_vreg_l,1479 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1480 .regs = qmp_v5_usb3phy_regs_layout,1481};1482 1483static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {1484 .offsets = &qmp_usb_offsets_v3,1485 1486 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,1487 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),1488 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,1489 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),1490 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,1491 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),1492 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,1493 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),1494 .vreg_list = qmp_phy_vreg_l,1495 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1496 .regs = qmp_v3_usb3phy_regs_layout,1497 1498 .has_pwrdn_delay = true,1499};1500 1501static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {1502 .offsets = &qmp_usb_offsets_v4,1503 1504 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,1505 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),1506 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,1507 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),1508 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,1509 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),1510 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,1511 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),1512 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl,1513 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),1514 .vreg_list = qmp_phy_vreg_l,1515 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1516 .regs = qmp_v4_usb3phy_regs_layout,1517 .pcs_usb_offset = 0x600,1518 1519 .has_pwrdn_delay = true,1520};1521 1522static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {1523 .offsets = &qmp_usb_offsets_v4,1524 1525 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,1526 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),1527 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,1528 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),1529 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,1530 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),1531 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,1532 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),1533 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,1534 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),1535 .vreg_list = qmp_phy_vreg_l,1536 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1537 .regs = qmp_v4_usb3phy_regs_layout,1538 .pcs_usb_offset = 0x600,1539 1540 .has_pwrdn_delay = true,1541};1542 1543static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {1544 .offsets = &qmp_usb_offsets_v4,1545 1546 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,1547 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),1548 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,1549 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),1550 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,1551 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),1552 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,1553 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),1554 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,1555 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),1556 .vreg_list = qmp_phy_vreg_l,1557 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1558 .regs = qmp_v4_usb3phy_regs_layout,1559 .pcs_usb_offset = 0x600,1560 1561 .has_pwrdn_delay = true,1562};1563 1564static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {1565 .offsets = &qmp_usb_offsets_v5,1566 1567 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,1568 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),1569 .tx_tbl = sdx65_usb3_uniphy_tx_tbl,1570 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),1571 .rx_tbl = sdx65_usb3_uniphy_rx_tbl,1572 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),1573 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,1574 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),1575 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,1576 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),1577 .vreg_list = qmp_phy_vreg_l,1578 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1579 .regs = qmp_v5_usb3phy_regs_layout,1580 .pcs_usb_offset = 0x1000,1581 1582 .has_pwrdn_delay = true,1583};1584 1585static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = {1586 .offsets = &qmp_usb_offsets_v6,1587 1588 .serdes_tbl = sdx75_usb3_uniphy_serdes_tbl,1589 .serdes_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl),1590 .tx_tbl = sdx75_usb3_uniphy_tx_tbl,1591 .tx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl),1592 .rx_tbl = sdx75_usb3_uniphy_rx_tbl,1593 .rx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl),1594 .pcs_tbl = sdx75_usb3_uniphy_pcs_tbl,1595 .pcs_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl),1596 .pcs_usb_tbl = sdx75_usb3_uniphy_pcs_usb_tbl,1597 .pcs_usb_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl),1598 .vreg_list = qmp_phy_vreg_l,1599 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1600 .regs = qmp_v6_usb3phy_regs_layout,1601 .pcs_usb_offset = 0x1000,1602 1603 .has_pwrdn_delay = true,1604};1605 1606static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {1607 .offsets = &qmp_usb_offsets_v5,1608 1609 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,1610 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),1611 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,1612 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),1613 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,1614 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),1615 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,1616 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),1617 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,1618 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),1619 .vreg_list = qmp_phy_vreg_l,1620 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1621 .regs = qmp_v5_usb3phy_regs_layout,1622 .pcs_usb_offset = 0x1000,1623 1624 .has_pwrdn_delay = true,1625};1626 1627static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = {1628 .offsets = &qmp_usb_offsets_v7,1629 1630 .serdes_tbl = x1e80100_usb3_uniphy_serdes_tbl,1631 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_serdes_tbl),1632 .tx_tbl = x1e80100_usb3_uniphy_tx_tbl,1633 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_tx_tbl),1634 .rx_tbl = x1e80100_usb3_uniphy_rx_tbl,1635 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_rx_tbl),1636 .pcs_tbl = x1e80100_usb3_uniphy_pcs_tbl,1637 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_tbl),1638 .pcs_usb_tbl = x1e80100_usb3_uniphy_pcs_usb_tbl,1639 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_usb_tbl),1640 .vreg_list = qmp_phy_vreg_l,1641 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),1642 .regs = qmp_v7_usb3phy_regs_layout,1643};1644 1645static int qmp_usb_serdes_init(struct qmp_usb *qmp)1646{1647 const struct qmp_phy_cfg *cfg = qmp->cfg;1648 void __iomem *serdes = qmp->serdes;1649 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;1650 int serdes_tbl_num = cfg->serdes_tbl_num;1651 1652 qmp_configure(qmp->dev, serdes, serdes_tbl, serdes_tbl_num);1653 1654 return 0;1655}1656 1657static int qmp_usb_init(struct phy *phy)1658{1659 struct qmp_usb *qmp = phy_get_drvdata(phy);1660 const struct qmp_phy_cfg *cfg = qmp->cfg;1661 void __iomem *pcs = qmp->pcs;1662 int ret;1663 1664 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);1665 if (ret) {1666 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);1667 return ret;1668 }1669 1670 ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);1671 if (ret) {1672 dev_err(qmp->dev, "reset assert failed\n");1673 goto err_disable_regulators;1674 }1675 1676 ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets);1677 if (ret) {1678 dev_err(qmp->dev, "reset deassert failed\n");1679 goto err_disable_regulators;1680 }1681 1682 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);1683 if (ret)1684 goto err_assert_reset;1685 1686 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);1687 1688 return 0;1689 1690err_assert_reset:1691 reset_control_bulk_assert(qmp->num_resets, qmp->resets);1692err_disable_regulators:1693 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);1694 1695 return ret;1696}1697 1698static int qmp_usb_exit(struct phy *phy)1699{1700 struct qmp_usb *qmp = phy_get_drvdata(phy);1701 const struct qmp_phy_cfg *cfg = qmp->cfg;1702 1703 reset_control_bulk_assert(qmp->num_resets, qmp->resets);1704 1705 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);1706 1707 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);1708 1709 return 0;1710}1711 1712static int qmp_usb_power_on(struct phy *phy)1713{1714 struct qmp_usb *qmp = phy_get_drvdata(phy);1715 const struct qmp_phy_cfg *cfg = qmp->cfg;1716 void __iomem *tx = qmp->tx;1717 void __iomem *rx = qmp->rx;1718 void __iomem *pcs = qmp->pcs;1719 void __iomem *pcs_usb = qmp->pcs_usb;1720 void __iomem *status;1721 unsigned int val;1722 int ret;1723 1724 qmp_usb_serdes_init(qmp);1725 1726 ret = clk_prepare_enable(qmp->pipe_clk);1727 if (ret) {1728 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);1729 return ret;1730 }1731 1732 /* Tx, Rx, and PCS configurations */1733 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);1734 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);1735 1736 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);1737 1738 if (pcs_usb)1739 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);1740 1741 if (cfg->has_pwrdn_delay)1742 usleep_range(10, 20);1743 1744 /* Pull PHY out of reset state */1745 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);1746 1747 /* start SerDes and Phy-Coding-Sublayer */1748 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);1749 1750 status = pcs + cfg->regs[QPHY_PCS_STATUS];1751 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,1752 PHY_INIT_COMPLETE_TIMEOUT);1753 if (ret) {1754 dev_err(qmp->dev, "phy initialization timed-out\n");1755 goto err_disable_pipe_clk;1756 }1757 1758 return 0;1759 1760err_disable_pipe_clk:1761 clk_disable_unprepare(qmp->pipe_clk);1762 1763 return ret;1764}1765 1766static int qmp_usb_power_off(struct phy *phy)1767{1768 struct qmp_usb *qmp = phy_get_drvdata(phy);1769 const struct qmp_phy_cfg *cfg = qmp->cfg;1770 1771 clk_disable_unprepare(qmp->pipe_clk);1772 1773 /* PHY reset */1774 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);1775 1776 /* stop SerDes and Phy-Coding-Sublayer */1777 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],1778 SERDES_START | PCS_START);1779 1780 /* Put PHY into POWER DOWN state: active low */1781 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],1782 SW_PWRDN);1783 1784 return 0;1785}1786 1787static int qmp_usb_enable(struct phy *phy)1788{1789 int ret;1790 1791 ret = qmp_usb_init(phy);1792 if (ret)1793 return ret;1794 1795 ret = qmp_usb_power_on(phy);1796 if (ret)1797 qmp_usb_exit(phy);1798 1799 return ret;1800}1801 1802static int qmp_usb_disable(struct phy *phy)1803{1804 int ret;1805 1806 ret = qmp_usb_power_off(phy);1807 if (ret)1808 return ret;1809 return qmp_usb_exit(phy);1810}1811 1812static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)1813{1814 struct qmp_usb *qmp = phy_get_drvdata(phy);1815 1816 qmp->mode = mode;1817 1818 return 0;1819}1820 1821static const struct phy_ops qmp_usb_phy_ops = {1822 .init = qmp_usb_enable,1823 .exit = qmp_usb_disable,1824 .set_mode = qmp_usb_set_mode,1825 .owner = THIS_MODULE,1826};1827 1828static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)1829{1830 const struct qmp_phy_cfg *cfg = qmp->cfg;1831 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;1832 void __iomem *pcs_misc = qmp->pcs_misc;1833 u32 intr_mask;1834 1835 if (qmp->mode == PHY_MODE_USB_HOST_SS ||1836 qmp->mode == PHY_MODE_USB_DEVICE_SS)1837 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;1838 else1839 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;1840 1841 /* Clear any pending interrupts status */1842 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);1843 /* Writing 1 followed by 0 clears the interrupt */1844 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);1845 1846 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],1847 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);1848 1849 /* Enable required PHY autonomous mode interrupts */1850 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);1851 1852 /* Enable i/o clamp_n for autonomous mode */1853 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])1854 qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);1855}1856 1857static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)1858{1859 const struct qmp_phy_cfg *cfg = qmp->cfg;1860 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;1861 void __iomem *pcs_misc = qmp->pcs_misc;1862 1863 /* Disable i/o clamp_n on resume for normal mode */1864 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])1865 qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);1866 1867 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],1868 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);1869 1870 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);1871 /* Writing 1 followed by 0 clears the interrupt */1872 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);1873}1874 1875static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)1876{1877 struct qmp_usb *qmp = dev_get_drvdata(dev);1878 1879 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);1880 1881 if (!qmp->phy->init_count) {1882 dev_vdbg(dev, "PHY not initialized, bailing out\n");1883 return 0;1884 }1885 1886 qmp_usb_enable_autonomous_mode(qmp);1887 1888 clk_disable_unprepare(qmp->pipe_clk);1889 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);1890 1891 return 0;1892}1893 1894static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)1895{1896 struct qmp_usb *qmp = dev_get_drvdata(dev);1897 int ret = 0;1898 1899 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);1900 1901 if (!qmp->phy->init_count) {1902 dev_vdbg(dev, "PHY not initialized, bailing out\n");1903 return 0;1904 }1905 1906 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);1907 if (ret)1908 return ret;1909 1910 ret = clk_prepare_enable(qmp->pipe_clk);1911 if (ret) {1912 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);1913 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);1914 return ret;1915 }1916 1917 qmp_usb_disable_autonomous_mode(qmp);1918 1919 return 0;1920}1921 1922static const struct dev_pm_ops qmp_usb_pm_ops = {1923 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,1924 qmp_usb_runtime_resume, NULL)1925};1926 1927static int qmp_usb_vreg_init(struct qmp_usb *qmp)1928{1929 const struct qmp_phy_cfg *cfg = qmp->cfg;1930 struct device *dev = qmp->dev;1931 int num = cfg->num_vregs;1932 int i;1933 1934 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);1935 if (!qmp->vregs)1936 return -ENOMEM;1937 1938 for (i = 0; i < num; i++)1939 qmp->vregs[i].supply = cfg->vreg_list[i];1940 1941 return devm_regulator_bulk_get(dev, num, qmp->vregs);1942}1943 1944static int qmp_usb_reset_init(struct qmp_usb *qmp,1945 const char *const *reset_list,1946 int num_resets)1947{1948 struct device *dev = qmp->dev;1949 int i;1950 int ret;1951 1952 qmp->resets = devm_kcalloc(dev, num_resets,1953 sizeof(*qmp->resets), GFP_KERNEL);1954 if (!qmp->resets)1955 return -ENOMEM;1956 1957 for (i = 0; i < num_resets; i++)1958 qmp->resets[i].id = reset_list[i];1959 1960 qmp->num_resets = num_resets;1961 1962 ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets);1963 if (ret)1964 return dev_err_probe(dev, ret, "failed to get resets\n");1965 1966 return 0;1967}1968 1969static int qmp_usb_clk_init(struct qmp_usb *qmp)1970{1971 struct device *dev = qmp->dev;1972 int num = ARRAY_SIZE(qmp_usb_phy_clk_l);1973 int i;1974 1975 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);1976 if (!qmp->clks)1977 return -ENOMEM;1978 1979 for (i = 0; i < num; i++)1980 qmp->clks[i].id = qmp_usb_phy_clk_l[i];1981 1982 qmp->num_clks = num;1983 1984 return devm_clk_bulk_get_optional(dev, num, qmp->clks);1985}1986 1987static void phy_clk_release_provider(void *res)1988{1989 of_clk_del_provider(res);1990}1991 1992/*1993 * Register a fixed rate pipe clock.1994 *1995 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate1996 * controls it. The <s>_pipe_clk coming out of the GCC is requested1997 * by the PHY driver for its operations.1998 * We register the <s>_pipe_clksrc here. The gcc driver takes care1999 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.2000 * Below picture shows this relationship.2001 *2002 * +---------------+2003 * | PHY block |<<---------------------------------------+2004 * | | |2005 * | +-------+ | +-----+ |2006 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+2007 * clk | +-------+ | +-----+2008 * +---------------+2009 */2010static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)2011{2012 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;2013 struct clk_init_data init = { };2014 int ret;2015 2016 ret = of_property_read_string(np, "clock-output-names", &init.name);2017 if (ret) {2018 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);2019 return ret;2020 }2021 2022 init.ops = &clk_fixed_rate_ops;2023 2024 /* controllers using QMP phys use 125MHz pipe clock interface */2025 fixed->fixed_rate = 125000000;2026 fixed->hw.init = &init;2027 2028 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);2029 if (ret)2030 return ret;2031 2032 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);2033 if (ret)2034 return ret;2035 2036 /*2037 * Roll a devm action because the clock provider is the child node, but2038 * the child node is not actually a device.2039 */2040 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);2041}2042 2043static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,2044 int index, bool exclusive)2045{2046 struct resource res;2047 2048 if (!exclusive) {2049 if (of_address_to_resource(np, index, &res))2050 return IOMEM_ERR_PTR(-EINVAL);2051 2052 return devm_ioremap(dev, res.start, resource_size(&res));2053 }2054 2055 return devm_of_iomap(dev, np, index, NULL);2056}2057 2058static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)2059{2060 struct platform_device *pdev = to_platform_device(qmp->dev);2061 const struct qmp_phy_cfg *cfg = qmp->cfg;2062 struct device *dev = qmp->dev;2063 bool exclusive = true;2064 int ret;2065 2066 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);2067 if (IS_ERR(qmp->serdes))2068 return PTR_ERR(qmp->serdes);2069 2070 /*2071 * FIXME: These bindings should be fixed to not rely on overlapping2072 * mappings for PCS.2073 */2074 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))2075 exclusive = false;2076 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))2077 exclusive = false;2078 2079 /*2080 * Get memory resources for the PHY:2081 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.2082 * For single lane PHYs: pcs_misc (optional) -> 3.2083 */2084 qmp->tx = devm_of_iomap(dev, np, 0, NULL);2085 if (IS_ERR(qmp->tx))2086 return PTR_ERR(qmp->tx);2087 2088 qmp->rx = devm_of_iomap(dev, np, 1, NULL);2089 if (IS_ERR(qmp->rx))2090 return PTR_ERR(qmp->rx);2091 2092 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);2093 if (IS_ERR(qmp->pcs))2094 return PTR_ERR(qmp->pcs);2095 2096 if (cfg->pcs_usb_offset)2097 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;2098 2099 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);2100 2101 if (IS_ERR(qmp->pcs_misc)) {2102 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");2103 qmp->pcs_misc = NULL;2104 }2105 2106 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);2107 if (IS_ERR(qmp->pipe_clk)) {2108 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),2109 "failed to get pipe clock\n");2110 }2111 2112 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);2113 if (ret < 0)2114 return ret;2115 2116 qmp->num_clks = ret;2117 2118 ret = qmp_usb_reset_init(qmp, usb3phy_legacy_reset_l,2119 ARRAY_SIZE(usb3phy_legacy_reset_l));2120 if (ret)2121 return ret;2122 2123 return 0;2124}2125 2126static int qmp_usb_parse_dt(struct qmp_usb *qmp)2127{2128 struct platform_device *pdev = to_platform_device(qmp->dev);2129 const struct qmp_phy_cfg *cfg = qmp->cfg;2130 const struct qmp_usb_offsets *offs = cfg->offsets;2131 struct device *dev = qmp->dev;2132 void __iomem *base;2133 int ret;2134 2135 if (!offs)2136 return -EINVAL;2137 2138 base = devm_platform_ioremap_resource(pdev, 0);2139 if (IS_ERR(base))2140 return PTR_ERR(base);2141 2142 qmp->serdes = base + offs->serdes;2143 qmp->pcs = base + offs->pcs;2144 if (offs->pcs_usb)2145 qmp->pcs_usb = base + offs->pcs_usb;2146 if (offs->pcs_misc)2147 qmp->pcs_misc = base + offs->pcs_misc;2148 qmp->tx = base + offs->tx;2149 qmp->rx = base + offs->rx;2150 2151 ret = qmp_usb_clk_init(qmp);2152 if (ret)2153 return ret;2154 2155 qmp->pipe_clk = devm_clk_get(dev, "pipe");2156 if (IS_ERR(qmp->pipe_clk)) {2157 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),2158 "failed to get pipe clock\n");2159 }2160 2161 ret = qmp_usb_reset_init(qmp, usb3phy_reset_l,2162 ARRAY_SIZE(usb3phy_reset_l));2163 if (ret)2164 return ret;2165 2166 return 0;2167}2168 2169static int qmp_usb_probe(struct platform_device *pdev)2170{2171 struct device *dev = &pdev->dev;2172 struct phy_provider *phy_provider;2173 struct device_node *np;2174 struct qmp_usb *qmp;2175 int ret;2176 2177 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);2178 if (!qmp)2179 return -ENOMEM;2180 2181 qmp->dev = dev;2182 dev_set_drvdata(dev, qmp);2183 2184 qmp->cfg = of_device_get_match_data(dev);2185 if (!qmp->cfg)2186 return -EINVAL;2187 2188 ret = qmp_usb_vreg_init(qmp);2189 if (ret)2190 return ret;2191 2192 /* Check for legacy binding with child node. */2193 np = of_get_next_available_child(dev->of_node, NULL);2194 if (np) {2195 ret = qmp_usb_parse_dt_legacy(qmp, np);2196 } else {2197 np = of_node_get(dev->of_node);2198 ret = qmp_usb_parse_dt(qmp);2199 }2200 if (ret)2201 goto err_node_put;2202 2203 pm_runtime_set_active(dev);2204 ret = devm_pm_runtime_enable(dev);2205 if (ret)2206 goto err_node_put;2207 /*2208 * Prevent runtime pm from being ON by default. Users can enable2209 * it using power/control in sysfs.2210 */2211 pm_runtime_forbid(dev);2212 2213 ret = phy_pipe_clk_register(qmp, np);2214 if (ret)2215 goto err_node_put;2216 2217 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops);2218 if (IS_ERR(qmp->phy)) {2219 ret = PTR_ERR(qmp->phy);2220 dev_err(dev, "failed to create PHY: %d\n", ret);2221 goto err_node_put;2222 }2223 2224 phy_set_drvdata(qmp->phy, qmp);2225 2226 of_node_put(np);2227 2228 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);2229 2230 return PTR_ERR_OR_ZERO(phy_provider);2231 2232err_node_put:2233 of_node_put(np);2234 return ret;2235}2236 2237static const struct of_device_id qmp_usb_of_match_table[] = {2238 {2239 .compatible = "qcom,ipq6018-qmp-usb3-phy",2240 .data = &ipq6018_usb3phy_cfg,2241 }, {2242 .compatible = "qcom,ipq8074-qmp-usb3-phy",2243 .data = &ipq8074_usb3phy_cfg,2244 }, {2245 .compatible = "qcom,ipq9574-qmp-usb3-phy",2246 .data = &ipq9574_usb3phy_cfg,2247 }, {2248 .compatible = "qcom,msm8996-qmp-usb3-phy",2249 .data = &msm8996_usb3phy_cfg,2250 }, {2251 .compatible = "qcom,qdu1000-qmp-usb3-uni-phy",2252 .data = &qdu1000_usb3_uniphy_cfg,2253 }, {2254 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy",2255 .data = &sa8775p_usb3_uniphy_cfg,2256 }, {2257 .compatible = "qcom,sc8180x-qmp-usb3-uni-phy",2258 .data = &sm8150_usb3_uniphy_cfg,2259 }, {2260 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",2261 .data = &sc8280xp_usb3_uniphy_cfg,2262 }, {2263 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",2264 .data = &qmp_v3_usb3_uniphy_cfg,2265 }, {2266 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",2267 .data = &sdx55_usb3_uniphy_cfg,2268 }, {2269 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",2270 .data = &sdx65_usb3_uniphy_cfg,2271 }, {2272 .compatible = "qcom,sdx75-qmp-usb3-uni-phy",2273 .data = &sdx75_usb3_uniphy_cfg,2274 }, {2275 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",2276 .data = &sm8150_usb3_uniphy_cfg,2277 }, {2278 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",2279 .data = &sm8250_usb3_uniphy_cfg,2280 }, {2281 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",2282 .data = &sm8350_usb3_uniphy_cfg,2283 }, {2284 .compatible = "qcom,x1e80100-qmp-usb3-uni-phy",2285 .data = &x1e80100_usb3_uniphy_cfg,2286 },2287 { },2288};2289MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);2290 2291static struct platform_driver qmp_usb_driver = {2292 .probe = qmp_usb_probe,2293 .driver = {2294 .name = "qcom-qmp-usb-phy",2295 .pm = &qmp_usb_pm_ops,2296 .of_match_table = qmp_usb_of_match_table,2297 },2298};2299 2300module_platform_driver(qmp_usb_driver);2301 2302MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");2303MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");2304MODULE_LICENSE("GPL v2");2305