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1// SPDX-License-Identifier: GPL-2.02/*3 * Rockchip PCIE3.0 phy driver4 *5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.6 */7 8#include <linux/clk.h>9#include <linux/delay.h>10#include <linux/io.h>11#include <linux/iopoll.h>12#include <linux/kernel.h>13#include <linux/mfd/syscon.h>14#include <linux/module.h>15#include <linux/of.h>16#include <linux/phy/pcie.h>17#include <linux/phy/phy.h>18#include <linux/platform_device.h>19#include <linux/regmap.h>20#include <linux/reset.h>21 22/* Register for RK3568 */23#define GRF_PCIE30PHY_CON1 0x424#define GRF_PCIE30PHY_CON6 0x1825#define GRF_PCIE30PHY_CON9 0x2426#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))27#define GRF_PCIE30PHY_STATUS0 0x8028#define GRF_PCIE30PHY_WR_EN (0xf << 16)29#define SRAM_INIT_DONE(reg) (reg & BIT(14))30 31#define RK3568_BIFURCATION_LANE_0_1 BIT(0)32 33/* Register for RK3588 */34#define PHP_GRF_PCIESEL_CON 0x10035#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x036#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x90437#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa0438#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x100439#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x110440#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x200441#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x210442#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))43 44#define RK3588_BIFURCATION_LANE_0_1 BIT(0)45#define RK3588_BIFURCATION_LANE_2_3 BIT(1)46#define RK3588_LANE_AGGREGATION BIT(2)47#define RK3588_RX_CMN_REFCLK_MODE_EN ((BIT(7) << 16) | BIT(7))48#define RK3588_RX_CMN_REFCLK_MODE_DIS (BIT(7) << 16)49#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)50#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)51 52struct rockchip_p3phy_ops;53 54struct rockchip_p3phy_priv {55 const struct rockchip_p3phy_ops *ops;56 void __iomem *mmio;57 /* mode: RC, EP */58 int mode;59 /* pcie30_phymode: Aggregation, Bifurcation */60 int pcie30_phymode;61 struct regmap *phy_grf;62 struct regmap *pipe_grf;63 struct reset_control *p30phy;64 struct phy *phy;65 struct clk_bulk_data *clks;66 int num_clks;67 int num_lanes;68 u32 lanes[4];69 u32 rx_cmn_refclk_mode[4];70};71 72struct rockchip_p3phy_ops {73 int (*phy_init)(struct rockchip_p3phy_priv *priv);74};75 76static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)77{78 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);79 80 /* Actually We don't care EP/RC mode, but just record it */81 switch (submode) {82 case PHY_MODE_PCIE_RC:83 priv->mode = PHY_MODE_PCIE_RC;84 break;85 case PHY_MODE_PCIE_EP:86 priv->mode = PHY_MODE_PCIE_EP;87 break;88 default:89 dev_err(&phy->dev, "%s, invalid mode\n", __func__);90 return -EINVAL;91 }92 93 return 0;94}95 96static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)97{98 struct phy *phy = priv->phy;99 bool bifurcation = false;100 int ret;101 u32 reg;102 103 /* Deassert PCIe PMA output clamp mode */104 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);105 106 for (int i = 0; i < priv->num_lanes; i++) {107 dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);108 if (priv->lanes[i] > 1)109 bifurcation = true;110 }111 112 /* Set bifurcation if needed, and it doesn't care RC/EP */113 if (bifurcation) {114 dev_info(&phy->dev, "bifurcation enabled\n");115 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,116 GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1);117 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,118 GRF_PCIE30PHY_DA_OCM);119 } else {120 dev_dbg(&phy->dev, "bifurcation disabled\n");121 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,122 GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);123 }124 125 reset_control_deassert(priv->p30phy);126 127 ret = regmap_read_poll_timeout(priv->phy_grf,128 GRF_PCIE30PHY_STATUS0,129 reg, SRAM_INIT_DONE(reg),130 0, 500);131 if (ret)132 dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",133 __func__, reg);134 return ret;135}136 137static const struct rockchip_p3phy_ops rk3568_ops = {138 .phy_init = rockchip_p3phy_rk3568_init,139};140 141static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)142{143 u32 reg = 0;144 u8 mode = RK3588_LANE_AGGREGATION; /* default */145 int ret;146 147 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1,148 priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN :149 RK3588_RX_CMN_REFCLK_MODE_DIS);150 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1,151 priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN :152 RK3588_RX_CMN_REFCLK_MODE_DIS);153 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1,154 priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN :155 RK3588_RX_CMN_REFCLK_MODE_DIS);156 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1,157 priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN :158 RK3588_RX_CMN_REFCLK_MODE_DIS);159 160 /* Deassert PCIe PMA output clamp mode */161 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));162 163 /* Set bifurcation if needed */164 for (int i = 0; i < priv->num_lanes; i++) {165 if (priv->lanes[i] > 1)166 mode &= ~RK3588_LANE_AGGREGATION;167 if (priv->lanes[i] == 3)168 mode |= RK3588_BIFURCATION_LANE_0_1;169 if (priv->lanes[i] == 4)170 mode |= RK3588_BIFURCATION_LANE_2_3;171 }172 173 reg = mode;174 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,175 RK3588_PCIE30_PHY_MODE_EN | reg);176 177 /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */178 if (!IS_ERR(priv->pipe_grf)) {179 reg = mode & (RK3588_BIFURCATION_LANE_0_1 | RK3588_BIFURCATION_LANE_2_3);180 if (reg)181 regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,182 RK3588_PCIE1LN_SEL_EN | reg);183 }184 185 reset_control_deassert(priv->p30phy);186 187 ret = regmap_read_poll_timeout(priv->phy_grf,188 RK3588_PCIE3PHY_GRF_PHY0_STATUS1,189 reg, RK3588_SRAM_INIT_DONE(reg),190 0, 500);191 ret |= regmap_read_poll_timeout(priv->phy_grf,192 RK3588_PCIE3PHY_GRF_PHY1_STATUS1,193 reg, RK3588_SRAM_INIT_DONE(reg),194 0, 500);195 if (ret)196 dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",197 reg);198 return ret;199}200 201static const struct rockchip_p3phy_ops rk3588_ops = {202 .phy_init = rockchip_p3phy_rk3588_init,203};204 205static int rockchip_p3phy_init(struct phy *phy)206{207 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);208 int ret;209 210 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);211 if (ret) {212 dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret);213 return ret;214 }215 216 reset_control_assert(priv->p30phy);217 udelay(1);218 219 if (priv->ops->phy_init) {220 ret = priv->ops->phy_init(priv);221 if (ret)222 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);223 }224 225 return ret;226}227 228static int rockchip_p3phy_exit(struct phy *phy)229{230 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);231 232 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);233 reset_control_assert(priv->p30phy);234 return 0;235}236 237static const struct phy_ops rockchip_p3phy_ops = {238 .init = rockchip_p3phy_init,239 .exit = rockchip_p3phy_exit,240 .set_mode = rockchip_p3phy_set_mode,241 .owner = THIS_MODULE,242};243 244static int rockchip_p3phy_probe(struct platform_device *pdev)245{246 struct phy_provider *phy_provider;247 struct device *dev = &pdev->dev;248 struct rockchip_p3phy_priv *priv;249 struct device_node *np = dev->of_node;250 int ret;251 252 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);253 if (!priv)254 return -ENOMEM;255 256 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);257 if (IS_ERR(priv->mmio)) {258 ret = PTR_ERR(priv->mmio);259 return ret;260 }261 262 priv->ops = of_device_get_match_data(&pdev->dev);263 if (!priv->ops) {264 dev_err(dev, "no of match data provided\n");265 return -EINVAL;266 }267 268 priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");269 if (IS_ERR(priv->phy_grf)) {270 dev_err(dev, "failed to find rockchip,phy_grf regmap\n");271 return PTR_ERR(priv->phy_grf);272 }273 274 if (of_device_is_compatible(np, "rockchip,rk3588-pcie3-phy")) {275 priv->pipe_grf =276 syscon_regmap_lookup_by_phandle(dev->of_node,277 "rockchip,pipe-grf");278 if (IS_ERR(priv->pipe_grf))279 dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");280 } else {281 priv->pipe_grf = NULL;282 }283 284 priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes",285 priv->lanes, 2,286 ARRAY_SIZE(priv->lanes));287 288 /* if no data-lanes assume aggregation */289 if (priv->num_lanes == -EINVAL) {290 dev_dbg(dev, "no data-lanes property found\n");291 priv->num_lanes = 1;292 priv->lanes[0] = 1;293 } else if (priv->num_lanes < 0) {294 dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes);295 return priv->num_lanes;296 }297 298 ret = of_property_read_variable_u32_array(dev->of_node,299 "rockchip,rx-common-refclk-mode",300 priv->rx_cmn_refclk_mode, 1,301 ARRAY_SIZE(priv->rx_cmn_refclk_mode));302 /*303 * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in304 * order to be DT backwards compatible. (Since HW reset val is enabled.)305 */306 if (ret == -EINVAL) {307 for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++)308 priv->rx_cmn_refclk_mode[i] = 1;309 } else if (ret < 0) {310 dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n",311 ret);312 return ret;313 }314 315 priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);316 if (IS_ERR(priv->phy)) {317 dev_err(dev, "failed to create combphy\n");318 return PTR_ERR(priv->phy);319 }320 321 priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy");322 if (IS_ERR(priv->p30phy)) {323 return dev_err_probe(dev, PTR_ERR(priv->p30phy),324 "failed to get phy reset control\n");325 }326 if (!priv->p30phy)327 dev_info(dev, "no phy reset control specified\n");328 329 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);330 if (priv->num_clks < 1)331 return -ENODEV;332 333 dev_set_drvdata(dev, priv);334 phy_set_drvdata(priv->phy, priv);335 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);336 return PTR_ERR_OR_ZERO(phy_provider);337}338 339static const struct of_device_id rockchip_p3phy_of_match[] = {340 { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },341 { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },342 { },343};344MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);345 346static struct platform_driver rockchip_p3phy_driver = {347 .probe = rockchip_p3phy_probe,348 .driver = {349 .name = "rockchip-snps-pcie3-phy",350 .of_match_table = rockchip_p3phy_of_match,351 },352};353module_platform_driver(rockchip_p3phy_driver);354MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");355MODULE_LICENSE("GPL");356