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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * UFS PHY driver data for Samsung EXYNOSAUTO v9 SoC4 *5 * Copyright (C) 2021 Samsung Electronics Co., Ltd.6 */7 8#include "phy-samsung-ufs.h"9 10#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x72811#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x112#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)13#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e14 15#define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \16 PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)17 18/* Calibration for phy initialization */19static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = {20 PHY_COMN_REG_CFG(0x023, 0x80, PWR_MODE_ANY),21 PHY_COMN_REG_CFG(0x01d, 0x10, PWR_MODE_ANY),22 23 PHY_TRSV_REG_CFG_AUTOV9(0x044, 0xb5, PWR_MODE_ANY),24 PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x43, PWR_MODE_ANY),25 PHY_TRSV_REG_CFG_AUTOV9(0x05b, 0x20, PWR_MODE_ANY),26 PHY_TRSV_REG_CFG_AUTOV9(0x05e, 0xc0, PWR_MODE_ANY),27 PHY_TRSV_REG_CFG_AUTOV9(0x038, 0x12, PWR_MODE_ANY),28 PHY_TRSV_REG_CFG_AUTOV9(0x059, 0x58, PWR_MODE_ANY),29 PHY_TRSV_REG_CFG_AUTOV9(0x06c, 0x18, PWR_MODE_ANY),30 PHY_TRSV_REG_CFG_AUTOV9(0x06d, 0x02, PWR_MODE_ANY),31 32 PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),33 PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),34 35 PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),36 PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),37 38 END_UFS_PHY_CFG,39};40 41/* Calibration for HS mode series A/B */42static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {43 PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),44 PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),45 PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),46 47 PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),48 PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |49 PWR_MODE_HS_G3_SER_B),50 PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),51 52 END_UFS_PHY_CFG,53};54 55static const struct samsung_ufs_phy_cfg *exynosautov9_ufs_phy_cfgs[CFG_TAG_MAX] = {56 [CFG_PRE_INIT] = exynosautov9_pre_init_cfg,57 [CFG_PRE_PWR_HS] = exynosautov9_pre_pwr_hs_cfg,58};59 60static const char * const exynosautov9_ufs_phy_clks[] = {61 "ref_clk",62};63 64const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {65 .cfgs = exynosautov9_ufs_phy_cfgs,66 .isol = {67 .offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL,68 .mask = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK,69 .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,70 },71 .clk_list = exynosautov9_ufs_phy_clks,72 .num_clks = ARRAY_SIZE(exynosautov9_ufs_phy_clks),73 .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,74 .wait_for_cdr = samsung_ufs_phy_wait_for_lock_acq,75};76