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1// SPDX-License-Identifier: GPL-2.0+2/*3 * P2U (PIPE to UPHY) driver for Tegra T194 SoC4 *5 * Copyright (C) 2019-2022 NVIDIA Corporation.6 *7 * Author: Vidya Sagar <vidyas@nvidia.com>8 */9 10#include <linux/err.h>11#include <linux/io.h>12#include <linux/module.h>13#include <linux/of.h>14#include <linux/phy/phy.h>15#include <linux/platform_device.h>16 17#define P2U_CONTROL_CMN 0x7418#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE BIT(13)19#define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20)20 21#define P2U_PERIODIC_EQ_CTRL_GEN3 0xc022#define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)23#define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1)24#define P2U_PERIODIC_EQ_CTRL_GEN4 0xc425#define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN BIT(1)26 27#define P2U_RX_DEBOUNCE_TIME 0xa428#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xffff29#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 16030 31#define P2U_DIR_SEARCH_CTRL 0xd432#define P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE BIT(18)33 34struct tegra_p2u_of_data {35 bool one_dir_search;36};37 38struct tegra_p2u {39 void __iomem *base;40 bool skip_sz_protection_en; /* Needed to support two retimers */41 struct tegra_p2u_of_data *of_data;42};43 44static inline void p2u_writel(struct tegra_p2u *phy, const u32 value,45 const u32 reg)46{47 writel_relaxed(value, phy->base + reg);48}49 50static inline u32 p2u_readl(struct tegra_p2u *phy, const u32 reg)51{52 return readl_relaxed(phy->base + reg);53}54 55static int tegra_p2u_power_on(struct phy *x)56{57 struct tegra_p2u *phy = phy_get_drvdata(x);58 u32 val;59 60 if (phy->skip_sz_protection_en) {61 val = p2u_readl(phy, P2U_CONTROL_CMN);62 val |= P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN;63 p2u_writel(phy, val, P2U_CONTROL_CMN);64 }65 66 val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3);67 val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;68 val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;69 p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN3);70 71 val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN4);72 val |= P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN;73 p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN4);74 75 val = p2u_readl(phy, P2U_RX_DEBOUNCE_TIME);76 val &= ~P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK;77 val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;78 p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME);79 80 if (phy->of_data->one_dir_search) {81 val = p2u_readl(phy, P2U_DIR_SEARCH_CTRL);82 val &= ~P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE;83 p2u_writel(phy, val, P2U_DIR_SEARCH_CTRL);84 }85 86 return 0;87}88 89static int tegra_p2u_calibrate(struct phy *x)90{91 struct tegra_p2u *phy = phy_get_drvdata(x);92 u32 val;93 94 val = p2u_readl(phy, P2U_CONTROL_CMN);95 val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE;96 p2u_writel(phy, val, P2U_CONTROL_CMN);97 98 return 0;99}100 101static const struct phy_ops ops = {102 .power_on = tegra_p2u_power_on,103 .calibrate = tegra_p2u_calibrate,104 .owner = THIS_MODULE,105};106 107static int tegra_p2u_probe(struct platform_device *pdev)108{109 struct phy_provider *phy_provider;110 struct device *dev = &pdev->dev;111 struct phy *generic_phy;112 struct tegra_p2u *phy;113 114 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);115 if (!phy)116 return -ENOMEM;117 118 phy->of_data =119 (struct tegra_p2u_of_data *)of_device_get_match_data(dev);120 if (!phy->of_data)121 return -EINVAL;122 123 phy->base = devm_platform_ioremap_resource_byname(pdev, "ctl");124 if (IS_ERR(phy->base))125 return PTR_ERR(phy->base);126 127 phy->skip_sz_protection_en =128 of_property_read_bool(dev->of_node,129 "nvidia,skip-sz-protect-en");130 131 platform_set_drvdata(pdev, phy);132 133 generic_phy = devm_phy_create(dev, NULL, &ops);134 if (IS_ERR(generic_phy))135 return PTR_ERR(generic_phy);136 137 phy_set_drvdata(generic_phy, phy);138 139 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);140 if (IS_ERR(phy_provider))141 return PTR_ERR(phy_provider);142 143 return 0;144}145 146static const struct tegra_p2u_of_data tegra194_p2u_of_data = {147 .one_dir_search = false,148};149 150static const struct tegra_p2u_of_data tegra234_p2u_of_data = {151 .one_dir_search = true,152};153 154static const struct of_device_id tegra_p2u_id_table[] = {155 {156 .compatible = "nvidia,tegra194-p2u",157 .data = &tegra194_p2u_of_data,158 },159 {160 .compatible = "nvidia,tegra234-p2u",161 .data = &tegra234_p2u_of_data,162 },163 {}164};165MODULE_DEVICE_TABLE(of, tegra_p2u_id_table);166 167static struct platform_driver tegra_p2u_driver = {168 .probe = tegra_p2u_probe,169 .driver = {170 .name = "tegra194-p2u",171 .of_match_table = tegra_p2u_id_table,172 },173};174module_platform_driver(tegra_p2u_driver);175 176MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");177MODULE_DESCRIPTION("NVIDIA Tegra194 PIPE2UPHY PHY driver");178MODULE_LICENSE("GPL v2");179