3296 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.4 * Copyright (C) 2015 Google, Inc.5 */6 7#include <linux/clk.h>8#include <linux/clk/tegra.h>9#include <linux/delay.h>10#include <linux/io.h>11#include <linux/mailbox_client.h>12#include <linux/module.h>13#include <linux/of.h>14#include <linux/of_platform.h>15#include <linux/phy/phy.h>16#include <linux/platform_device.h>17#include <linux/regmap.h>18#include <linux/regulator/consumer.h>19#include <linux/reset.h>20#include <linux/slab.h>21 22#include <soc/tegra/fuse.h>23 24#include "xusb.h"25 26#define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) \27 ((x) ? (11 + ((x) - 1) * 6) : 0)28#define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f29#define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT 730#define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf31 32#define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 033#define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f34 35#define XUSB_PADCTL_USB2_PAD_MUX 0x00436#define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT 1637#define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x338#define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x139#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT 1840#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x341#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x142 43#define XUSB_PADCTL_USB2_PORT_CAP 0x00844#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))45#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))46#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))47#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))48#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))49 50#define XUSB_PADCTL_SS_PORT_MAP 0x01451#define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))52#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 5)53#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5))54#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))55#define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x756 57#define XUSB_PADCTL_ELPG_PROGRAM_0 0x2058#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x))59#define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)60#define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)61#define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)62#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)63#define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)64#define ALL_WAKE_EVENTS ( \65 USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \66 USB2_PORT_WAKEUP_EVENT(2) | USB2_PORT_WAKEUP_EVENT(3) | \67 SS_PORT_WAKEUP_EVENT(0) | SS_PORT_WAKEUP_EVENT(1) | \68 SS_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(3) | \69 USB2_HSIC_PORT_WAKEUP_EVENT(0))70 71#define XUSB_PADCTL_ELPG_PROGRAM1 0x02472#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)73#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)74#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)75#define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))76#define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(x) \77 (1 << (1 + (x) * 3))78#define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3))79 80#define XUSB_PADCTL_USB3_PAD_MUX 0x02881#define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))82#define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x)))83 84#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(x) (0x080 + (x) * 0x40)85#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP (1 << 18)86#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN (1 << 22)87 88#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40)89#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT 790#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x391#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x192#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6)93 94#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)95#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29)96#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 (1 << 27)97#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD (1 << 26)98#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 099#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f100 101#define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40)102#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT 26103#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f104#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT 3105#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf106#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)107#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1)108#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)109#define RPD_CTRL(x) (((x) & 0x1f) << 26)110#define RPD_CTRL_VALUE(x) (((x) >> 26) & 0x1f)111 112#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284113#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11)114#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 3115#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7116#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7117#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0118#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7119#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2120 121#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288122#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26)123#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT 19124#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f125#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a126#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12127#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f128#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e129#define TCTRL_VALUE(x) (((x) & 0x3f) >> 0)130#define PCTRL_VALUE(x) (((x) >> 6) & 0x3f)131 132#define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)133#define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18)134#define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 (1 << 17)135#define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 (1 << 16)136#define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE (1 << 15)137#define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 (1 << 14)138#define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 (1 << 13)139#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9)140#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8)141#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7)142#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6)143#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5)144#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)145#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3)146#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)147#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1)148 149#define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20)150#define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0151#define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf152 153#define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20)154#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT 8155#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf156#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0157#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff158 159#define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340160#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK (1 << 19)161#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT 12162#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f163#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a164#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT 5165#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f166#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e167 168#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344169 170#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360171#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT 20172#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff173#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19174#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e175#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT 16176#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3177#define XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS (1 << 15)178#define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4)179#define XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE (1 << 3)180#define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT 1181#define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3182#define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0)183 184#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364185#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT 4186#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff187#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136188#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2)189#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE (1 << 1)190#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0)191 192#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c193#define XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN (1 << 19)194#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN (1 << 15)195#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT 12196#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3197#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2198#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0199#define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN (1 << 8)200#define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT 4201#define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf202 203#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370204#define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT 16205#define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff206#define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a207 208#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c209#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE (1 << 31)210#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD (1 << 15)211#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN (1 << 13)212#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN (1 << 12)213 214#define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40)215#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT 20216#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3217#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1218#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18)219#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13)220 221#define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(x) (0x464 + (x) * 0x40)222#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ BIT(0)223#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD BIT(1)224#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK GENMASK(5, 4)225#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL GENMASK(5, 4)226#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD BIT(24)227#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ BIT(8)228#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD BIT(9)229#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK GENMASK(13, 12)230#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL GENMASK(13, 12)231#define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD BIT(25)232 233#define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860234 235#define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864236 237#define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c238 239#define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870240 241#define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c242 243#define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960244#define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2 0x964245 246#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)247#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT 16248#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3249#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2250 251#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40)252#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0253#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff254#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc255 256#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40)257#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f258 259#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40)260#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT 16261#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff262#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7263 264#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40)265#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368266 267#define XUSB_PADCTL_USB2_VBUS_ID 0xc60268#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON (1 << 14)269#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT 18270#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK 0xf271#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING 8272#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED 0273 274/* USB2 SLEEPWALK registers */275#define UTMIP(_port, _offset1, _offset2) \276 (((_port) <= 2) ? (_offset1) : (_offset2))277 278#define PMC_UTMIP_UHSIC_SLEEP_CFG(x) UTMIP(x, 0x1fc, 0x4d0)279#define UTMIP_MASTER_ENABLE(x) UTMIP(x, BIT(8 * (x)), BIT(0))280#define UTMIP_FSLS_USE_PMC(x) UTMIP(x, BIT(8 * (x) + 1), \281 BIT(1))282#define UTMIP_PCTRL_USE_PMC(x) UTMIP(x, BIT(8 * (x) + 2), \283 BIT(2))284#define UTMIP_TCTRL_USE_PMC(x) UTMIP(x, BIT(8 * (x) + 3), \285 BIT(3))286#define UTMIP_WAKE_VAL(_port, _value) (((_value) & 0xf) << \287 (UTMIP(_port, 8 * (_port) + 4, 4)))288#define UTMIP_WAKE_VAL_NONE(_port) UTMIP_WAKE_VAL(_port, 12)289#define UTMIP_WAKE_VAL_ANY(_port) UTMIP_WAKE_VAL(_port, 15)290 291#define PMC_UTMIP_UHSIC_SLEEP_CFG1 (0x4d0)292#define UTMIP_RPU_SWITC_LOW_USE_PMC_PX(x) BIT((x) + 8)293#define UTMIP_RPD_CTRL_USE_PMC_PX(x) BIT((x) + 16)294 295#define PMC_UTMIP_MASTER_CONFIG (0x274)296#define UTMIP_PWR(x) UTMIP(x, BIT(x), BIT(4))297#define UHSIC_PWR BIT(3)298 299#define PMC_USB_DEBOUNCE_DEL (0xec)300#define DEBOUNCE_VAL(x) (((x) & 0xffff) << 0)301#define UTMIP_LINE_DEB_CNT(x) (((x) & 0xf) << 16)302#define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 20)303 304#define PMC_UTMIP_UHSIC_FAKE(x) UTMIP(x, 0x218, 0x294)305#define UTMIP_FAKE_USBOP_VAL(x) UTMIP(x, BIT(4 * (x)), BIT(8))306#define UTMIP_FAKE_USBON_VAL(x) UTMIP(x, BIT(4 * (x) + 1), \307 BIT(9))308#define UTMIP_FAKE_USBOP_EN(x) UTMIP(x, BIT(4 * (x) + 2), \309 BIT(10))310#define UTMIP_FAKE_USBON_EN(x) UTMIP(x, BIT(4 * (x) + 3), \311 BIT(11))312 313#define PMC_UTMIP_UHSIC_SLEEPWALK_CFG(x) UTMIP(x, 0x200, 0x288)314#define UTMIP_LINEVAL_WALK_EN(x) UTMIP(x, BIT(8 * (x) + 7), \315 BIT(15))316 317#define PMC_USB_AO (0xf0)318#define USBOP_VAL_PD(x) UTMIP(x, BIT(4 * (x)), BIT(20))319#define USBON_VAL_PD(x) UTMIP(x, BIT(4 * (x) + 1), \320 BIT(21))321#define STROBE_VAL_PD BIT(12)322#define DATA0_VAL_PD BIT(13)323#define DATA1_VAL_PD BIT(24)324 325#define PMC_UTMIP_UHSIC_SAVED_STATE(x) UTMIP(x, 0x1f0, 0x280)326#define SPEED(_port, _value) (((_value) & 0x3) << \327 (UTMIP(_port, 8 * (_port), 8)))328#define UTMI_HS(_port) SPEED(_port, 0)329#define UTMI_FS(_port) SPEED(_port, 1)330#define UTMI_LS(_port) SPEED(_port, 2)331#define UTMI_RST(_port) SPEED(_port, 3)332 333#define PMC_UTMIP_UHSIC_TRIGGERS (0x1ec)334#define UTMIP_CLR_WALK_PTR(x) UTMIP(x, BIT(x), BIT(16))335#define UTMIP_CAP_CFG(x) UTMIP(x, BIT((x) + 4), BIT(17))336#define UTMIP_CLR_WAKE_ALARM(x) UTMIP(x, BIT((x) + 12), \337 BIT(19))338#define UHSIC_CLR_WALK_PTR BIT(3)339#define UHSIC_CLR_WAKE_ALARM BIT(15)340 341#define PMC_UTMIP_SLEEPWALK_PX(x) UTMIP(x, 0x204 + (4 * (x)), \342 0x4e0)343/* phase A */344#define UTMIP_USBOP_RPD_A BIT(0)345#define UTMIP_USBON_RPD_A BIT(1)346#define UTMIP_AP_A BIT(4)347#define UTMIP_AN_A BIT(5)348#define UTMIP_HIGHZ_A BIT(6)349/* phase B */350#define UTMIP_USBOP_RPD_B BIT(8)351#define UTMIP_USBON_RPD_B BIT(9)352#define UTMIP_AP_B BIT(12)353#define UTMIP_AN_B BIT(13)354#define UTMIP_HIGHZ_B BIT(14)355/* phase C */356#define UTMIP_USBOP_RPD_C BIT(16)357#define UTMIP_USBON_RPD_C BIT(17)358#define UTMIP_AP_C BIT(20)359#define UTMIP_AN_C BIT(21)360#define UTMIP_HIGHZ_C BIT(22)361/* phase D */362#define UTMIP_USBOP_RPD_D BIT(24)363#define UTMIP_USBON_RPD_D BIT(25)364#define UTMIP_AP_D BIT(28)365#define UTMIP_AN_D BIT(29)366#define UTMIP_HIGHZ_D BIT(30)367 368#define PMC_UTMIP_UHSIC_LINE_WAKEUP (0x26c)369#define UTMIP_LINE_WAKEUP_EN(x) UTMIP(x, BIT(x), BIT(4))370#define UHSIC_LINE_WAKEUP_EN BIT(3)371 372#define PMC_UTMIP_TERM_PAD_CFG (0x1f8)373#define PCTRL_VAL(x) (((x) & 0x3f) << 1)374#define TCTRL_VAL(x) (((x) & 0x3f) << 7)375 376#define PMC_UTMIP_PAD_CFGX(x) (0x4c0 + (4 * (x)))377#define RPD_CTRL_PX(x) (((x) & 0x1f) << 22)378 379#define PMC_UHSIC_SLEEP_CFG PMC_UTMIP_UHSIC_SLEEP_CFG(0)380#define UHSIC_MASTER_ENABLE BIT(24)381#define UHSIC_WAKE_VAL(_value) (((_value) & 0xf) << 28)382#define UHSIC_WAKE_VAL_SD10 UHSIC_WAKE_VAL(2)383#define UHSIC_WAKE_VAL_NONE UHSIC_WAKE_VAL(12)384 385#define PMC_UHSIC_FAKE PMC_UTMIP_UHSIC_FAKE(0)386#define UHSIC_FAKE_STROBE_VAL BIT(12)387#define UHSIC_FAKE_DATA_VAL BIT(13)388#define UHSIC_FAKE_STROBE_EN BIT(14)389#define UHSIC_FAKE_DATA_EN BIT(15)390 391#define PMC_UHSIC_SAVED_STATE PMC_UTMIP_UHSIC_SAVED_STATE(0)392#define UHSIC_MODE(_value) (((_value) & 0x1) << 24)393#define UHSIC_HS UHSIC_MODE(0)394#define UHSIC_RST UHSIC_MODE(1)395 396#define PMC_UHSIC_SLEEPWALK_CFG PMC_UTMIP_UHSIC_SLEEPWALK_CFG(0)397#define UHSIC_WAKE_WALK_EN BIT(30)398#define UHSIC_LINEVAL_WALK_EN BIT(31)399 400#define PMC_UHSIC_SLEEPWALK_P0 (0x210)401#define UHSIC_DATA0_RPD_A BIT(1)402#define UHSIC_DATA0_RPU_B BIT(11)403#define UHSIC_DATA0_RPU_C BIT(19)404#define UHSIC_DATA0_RPU_D BIT(27)405#define UHSIC_STROBE_RPU_A BIT(2)406#define UHSIC_STROBE_RPD_B BIT(8)407#define UHSIC_STROBE_RPD_C BIT(16)408#define UHSIC_STROBE_RPD_D BIT(24)409 410struct tegra210_xusb_fuse_calibration {411 u32 hs_curr_level[4];412 u32 hs_term_range_adj;413 u32 rpd_ctrl;414};415 416struct tegra210_xusb_padctl_context {417 u32 usb2_pad_mux;418 u32 usb2_port_cap;419 u32 ss_port_map;420 u32 usb3_pad_mux;421};422 423struct tegra210_xusb_padctl {424 struct tegra_xusb_padctl base;425 struct regmap *regmap;426 427 struct tegra210_xusb_fuse_calibration fuse;428 struct tegra210_xusb_padctl_context context;429};430 431static inline struct tegra210_xusb_padctl *432to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl)433{434 return container_of(padctl, struct tegra210_xusb_padctl, base);435}436 437static const struct tegra_xusb_lane_map tegra210_usb3_map[] = {438 { 0, "pcie", 6 },439 { 1, "pcie", 5 },440 { 2, "pcie", 0 },441 { 2, "pcie", 3 },442 { 3, "pcie", 4 },443 { 3, "sata", 0 },444 { 0, NULL, 0 }445};446 447static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane)448{449 const struct tegra_xusb_lane_map *map;450 451 for (map = tegra210_usb3_map; map->type; map++) {452 if (map->index == lane->index &&453 strcmp(map->type, lane->pad->soc->name) == 0) {454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n",455 lane->pad->soc->lanes[lane->index].name, map->port);456 return map->port;457 }458 }459 460 return -EINVAL;461}462 463/* must be called under padctl->lock */464static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)465{466 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);467 unsigned long timeout;468 u32 value;469 unsigned int i;470 int err;471 472 if (pcie->enable)473 return 0;474 475 err = clk_prepare_enable(pcie->pll);476 if (err < 0)477 return err;478 479 if (tegra210_plle_hw_sequence_is_enabled())480 goto skip_pll_init;481 482 err = reset_control_deassert(pcie->rst);483 if (err < 0)484 goto disable;485 486 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);487 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<488 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);489 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<490 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;491 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);492 493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);494 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<495 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);496 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<497 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);499 500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);501 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;502 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);503 504 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);505 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;506 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);507 508 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);509 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;510 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);511 512 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);513 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<514 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |515 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK <<516 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT));517 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<518 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |519 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;520 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);521 522 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);523 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<524 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) |525 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK <<526 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT));527 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<528 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;529 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);530 531 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);532 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;533 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);534 535 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);536 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<537 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT);538 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);539 540 usleep_range(10, 20);541 542 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);543 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;544 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);545 546 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);547 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;548 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);549 550 timeout = jiffies + msecs_to_jiffies(100);551 552 while (time_before(jiffies, timeout)) {553 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);554 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)555 break;556 557 usleep_range(10, 20);558 }559 560 if (time_after_eq(jiffies, timeout)) {561 err = -ETIMEDOUT;562 goto reset;563 }564 565 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);566 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;567 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);568 569 timeout = jiffies + msecs_to_jiffies(100);570 571 while (time_before(jiffies, timeout)) {572 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);573 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))574 break;575 576 usleep_range(10, 20);577 }578 579 if (time_after_eq(jiffies, timeout)) {580 err = -ETIMEDOUT;581 goto reset;582 }583 584 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);585 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;586 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);587 588 timeout = jiffies + msecs_to_jiffies(100);589 590 while (time_before(jiffies, timeout)) {591 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);592 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)593 break;594 595 usleep_range(10, 20);596 }597 598 if (time_after_eq(jiffies, timeout)) {599 err = -ETIMEDOUT;600 goto reset;601 }602 603 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);604 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |605 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;606 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);607 608 timeout = jiffies + msecs_to_jiffies(100);609 610 while (time_before(jiffies, timeout)) {611 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);612 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)613 break;614 615 usleep_range(10, 20);616 }617 618 if (time_after_eq(jiffies, timeout)) {619 err = -ETIMEDOUT;620 goto reset;621 }622 623 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);624 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;625 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);626 627 timeout = jiffies + msecs_to_jiffies(100);628 629 while (time_before(jiffies, timeout)) {630 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);631 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))632 break;633 634 usleep_range(10, 20);635 }636 637 if (time_after_eq(jiffies, timeout)) {638 err = -ETIMEDOUT;639 goto reset;640 }641 642 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);643 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;644 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);645 646 tegra210_xusb_pll_hw_control_enable();647 648 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);649 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;650 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);651 652 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);653 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;654 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);655 656 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);657 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;658 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);659 660 usleep_range(10, 20);661 662 tegra210_xusb_pll_hw_sequence_start();663 664skip_pll_init:665 pcie->enable = true;666 667 for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {668 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);669 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(i);670 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);671 }672 673 return 0;674 675reset:676 reset_control_assert(pcie->rst);677disable:678 clk_disable_unprepare(pcie->pll);679 return err;680}681 682static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl)683{684 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);685 u32 value;686 unsigned int i;687 688 if (WARN_ON(!pcie->enable))689 return;690 691 pcie->enable = false;692 693 for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {694 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);695 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(i);696 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);697 }698 699 clk_disable_unprepare(pcie->pll);700}701 702/* must be called under padctl->lock */703static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl)704{705 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0);707 unsigned long timeout;708 u32 value;709 unsigned int i;710 int err;711 bool usb;712 713 if (sata->enable)714 return 0;715 716 if (IS_ERR(lane))717 return 0;718 719 if (tegra210_plle_hw_sequence_is_enabled())720 goto skip_pll_init;721 722 usb = tegra_xusb_lane_check(lane, "usb3-ss");723 724 err = clk_prepare_enable(sata->pll);725 if (err < 0)726 return err;727 728 err = reset_control_deassert(sata->rst);729 if (err < 0)730 goto disable;731 732 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);733 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<734 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);735 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<736 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;737 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);738 739 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5);740 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<741 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);742 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<743 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;744 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5);745 746 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);747 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;748 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);749 750 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);751 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;752 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);753 754 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);755 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;756 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);757 758 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);759 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<760 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |761 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK <<762 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT));763 value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;764 765 if (usb)766 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<767 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT);768 else769 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL <<770 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT);771 772 value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN;773 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);774 775 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);776 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<777 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) |778 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK <<779 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT));780 781 if (usb)782 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<783 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;784 else785 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL <<786 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;787 788 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);789 790 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);791 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;792 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);793 794 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);795 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<796 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT);797 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);798 799 usleep_range(10, 20);800 801 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);802 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;803 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);804 805 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);806 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;807 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);808 809 timeout = jiffies + msecs_to_jiffies(100);810 811 while (time_before(jiffies, timeout)) {812 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);813 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)814 break;815 816 usleep_range(10, 20);817 }818 819 if (time_after_eq(jiffies, timeout)) {820 err = -ETIMEDOUT;821 goto reset;822 }823 824 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);825 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;826 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);827 828 timeout = jiffies + msecs_to_jiffies(100);829 830 while (time_before(jiffies, timeout)) {831 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);832 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))833 break;834 835 usleep_range(10, 20);836 }837 838 if (time_after_eq(jiffies, timeout)) {839 err = -ETIMEDOUT;840 goto reset;841 }842 843 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);844 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;845 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);846 847 timeout = jiffies + msecs_to_jiffies(100);848 849 while (time_before(jiffies, timeout)) {850 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);851 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)852 break;853 854 usleep_range(10, 20);855 }856 857 if (time_after_eq(jiffies, timeout)) {858 err = -ETIMEDOUT;859 goto reset;860 }861 862 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);863 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |864 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;865 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);866 867 timeout = jiffies + msecs_to_jiffies(100);868 869 while (time_before(jiffies, timeout)) {870 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);871 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)872 break;873 874 usleep_range(10, 20);875 }876 877 if (time_after_eq(jiffies, timeout)) {878 err = -ETIMEDOUT;879 goto reset;880 }881 882 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);883 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;884 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);885 886 timeout = jiffies + msecs_to_jiffies(100);887 888 while (time_before(jiffies, timeout)) {889 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);890 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))891 break;892 893 usleep_range(10, 20);894 }895 896 if (time_after_eq(jiffies, timeout)) {897 err = -ETIMEDOUT;898 goto reset;899 }900 901 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);902 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;903 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);904 905 tegra210_sata_pll_hw_control_enable();906 907 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);908 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;909 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);910 911 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);912 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;913 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);914 915 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);916 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;917 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);918 919 usleep_range(10, 20);920 921 tegra210_sata_pll_hw_sequence_start();922 923skip_pll_init:924 sata->enable = true;925 926 for (i = 0; i < padctl->sata->soc->num_lanes; i++) {927 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);928 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(i);929 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);930 }931 932 return 0;933 934reset:935 reset_control_assert(sata->rst);936disable:937 clk_disable_unprepare(sata->pll);938 return err;939}940 941static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl)942{943 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);944 u32 value;945 unsigned int i;946 947 if (WARN_ON(!sata->enable))948 return;949 950 sata->enable = false;951 952 for (i = 0; i < padctl->sata->soc->num_lanes; i++) {953 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);954 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(i);955 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);956 }957 958 clk_disable_unprepare(sata->pll);959}960 961static void tegra210_aux_mux_lp0_clamp_disable(struct tegra_xusb_padctl *padctl)962{963 u32 value;964 965 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);966 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;967 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);968 969 usleep_range(100, 200);970 971 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);972 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;973 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);974 975 usleep_range(100, 200);976 977 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);978 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;979 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);980}981 982static void tegra210_aux_mux_lp0_clamp_enable(struct tegra_xusb_padctl *padctl)983{984 u32 value;985 986 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);987 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;988 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);989 990 usleep_range(100, 200);991 992 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);993 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;994 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);995 996 usleep_range(100, 200);997 998 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);999 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;1000 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);1001}1002 1003static int tegra210_uphy_init(struct tegra_xusb_padctl *padctl)1004{1005 if (padctl->pcie)1006 tegra210_pex_uphy_enable(padctl);1007 1008 if (padctl->sata)1009 tegra210_sata_uphy_enable(padctl);1010 1011 if (!tegra210_plle_hw_sequence_is_enabled())1012 tegra210_plle_hw_sequence_start();1013 else1014 dev_dbg(padctl->dev, "PLLE is already in HW control\n");1015 1016 tegra210_aux_mux_lp0_clamp_disable(padctl);1017 1018 return 0;1019}1020 1021static void __maybe_unused1022tegra210_uphy_deinit(struct tegra_xusb_padctl *padctl)1023{1024 tegra210_aux_mux_lp0_clamp_enable(padctl);1025 1026 if (padctl->sata)1027 tegra210_sata_uphy_disable(padctl);1028 1029 if (padctl->pcie)1030 tegra210_pex_uphy_disable(padctl);1031}1032 1033static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl,1034 unsigned int index, bool idle)1035{1036 u32 value;1037 1038 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));1039 1040 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |1041 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 |1042 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE);1043 1044 if (idle)1045 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |1046 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |1047 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE;1048 else1049 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |1050 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |1051 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE);1052 1053 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));1054 1055 return 0;1056}1057 1058static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,1059 enum usb_device_speed speed)1060{1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1062 int port = tegra210_usb3_lane_map(lane);1063 struct device *dev = padctl->dev;1064 u32 value;1065 1066 if (port < 0) {1067 dev_err(dev, "invalid usb3 port number\n");1068 return -EINVAL;1069 }1070 1071 mutex_lock(&padctl->lock);1072 1073 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);1074 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port);1075 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);1076 1077 usleep_range(100, 200);1078 1079 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);1080 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port);1081 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);1082 1083 usleep_range(250, 350);1084 1085 mutex_unlock(&padctl->lock);1086 1087 return 0;1088}1089 1090static int tegra210_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)1091{1092 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1093 int port = tegra210_usb3_lane_map(lane);1094 struct device *dev = padctl->dev;1095 u32 value;1096 1097 if (port < 0) {1098 dev_err(dev, "invalid usb3 port number\n");1099 return -EINVAL;1100 }1101 1102 mutex_lock(&padctl->lock);1103 1104 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);1105 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port);1106 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);1107 1108 usleep_range(100, 200);1109 1110 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);1111 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port);1112 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);1113 1114 mutex_unlock(&padctl->lock);1115 1116 return 0;1117}1118 1119static int tegra210_usb3_enable_phy_wake(struct tegra_xusb_lane *lane)1120{1121 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1122 int port = tegra210_usb3_lane_map(lane);1123 struct device *dev = padctl->dev;1124 u32 value;1125 1126 if (port < 0) {1127 dev_err(dev, "invalid usb3 port number\n");1128 return -EINVAL;1129 }1130 1131 mutex_lock(&padctl->lock);1132 1133 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1134 value &= ~ALL_WAKE_EVENTS;1135 value |= SS_PORT_WAKEUP_EVENT(port);1136 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1137 1138 usleep_range(10, 20);1139 1140 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1141 value &= ~ALL_WAKE_EVENTS;1142 value |= SS_PORT_WAKE_INTERRUPT_ENABLE(port);1143 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1144 1145 mutex_unlock(&padctl->lock);1146 1147 return 0;1148}1149 1150static int tegra210_usb3_disable_phy_wake(struct tegra_xusb_lane *lane)1151{1152 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1153 int port = tegra210_usb3_lane_map(lane);1154 struct device *dev = padctl->dev;1155 u32 value;1156 1157 if (port < 0) {1158 dev_err(dev, "invalid usb3 port number\n");1159 return -EINVAL;1160 }1161 1162 mutex_lock(&padctl->lock);1163 1164 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1165 value &= ~ALL_WAKE_EVENTS;1166 value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(port);1167 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1168 1169 usleep_range(10, 20);1170 1171 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1172 value &= ~ALL_WAKE_EVENTS;1173 value |= SS_PORT_WAKEUP_EVENT(port);1174 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1175 1176 mutex_unlock(&padctl->lock);1177 1178 return 0;1179}1180 1181static bool tegra210_usb3_phy_remote_wake_detected(struct tegra_xusb_lane *lane)1182{1183 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1184 int index = tegra210_usb3_lane_map(lane);1185 u32 value;1186 1187 if (index < 0)1188 return false;1189 1190 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1191 if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index)))1192 return true;1193 1194 return false;1195}1196 1197static int tegra210_utmi_enable_phy_wake(struct tegra_xusb_lane *lane)1198{1199 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1200 unsigned int index = lane->index;1201 u32 value;1202 1203 mutex_lock(&padctl->lock);1204 1205 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1206 value &= ~ALL_WAKE_EVENTS;1207 value |= USB2_PORT_WAKEUP_EVENT(index);1208 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1209 1210 usleep_range(10, 20);1211 1212 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1213 value &= ~ALL_WAKE_EVENTS;1214 value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);1215 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1216 1217 mutex_unlock(&padctl->lock);1218 1219 return 0;1220}1221 1222static int tegra210_utmi_disable_phy_wake(struct tegra_xusb_lane *lane)1223{1224 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1225 unsigned int index = lane->index;1226 u32 value;1227 1228 mutex_lock(&padctl->lock);1229 1230 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1231 value &= ~ALL_WAKE_EVENTS;1232 value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);1233 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1234 1235 usleep_range(10, 20);1236 1237 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1238 value &= ~ALL_WAKE_EVENTS;1239 value |= USB2_PORT_WAKEUP_EVENT(index);1240 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1241 1242 mutex_unlock(&padctl->lock);1243 1244 return 0;1245}1246 1247static bool tegra210_utmi_phy_remote_wake_detected(struct tegra_xusb_lane *lane)1248{1249 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1250 unsigned int index = lane->index;1251 u32 value;1252 1253 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1254 if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) &&1255 (value & USB2_PORT_WAKEUP_EVENT(index)))1256 return true;1257 1258 return false;1259}1260 1261static int tegra210_hsic_enable_phy_wake(struct tegra_xusb_lane *lane)1262{1263 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1264 unsigned int index = lane->index;1265 u32 value;1266 1267 mutex_lock(&padctl->lock);1268 1269 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1270 value &= ~ALL_WAKE_EVENTS;1271 value |= USB2_HSIC_PORT_WAKEUP_EVENT(index);1272 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1273 1274 usleep_range(10, 20);1275 1276 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1277 value &= ~ALL_WAKE_EVENTS;1278 value |= USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index);1279 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1280 1281 mutex_unlock(&padctl->lock);1282 1283 return 0;1284}1285 1286static int tegra210_hsic_disable_phy_wake(struct tegra_xusb_lane *lane)1287{1288 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1289 unsigned int index = lane->index;1290 u32 value;1291 1292 mutex_lock(&padctl->lock);1293 1294 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1295 value &= ~ALL_WAKE_EVENTS;1296 value &= ~USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index);1297 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1298 1299 usleep_range(10, 20);1300 1301 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1302 value &= ~ALL_WAKE_EVENTS;1303 value |= USB2_HSIC_PORT_WAKEUP_EVENT(index);1304 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);1305 1306 mutex_unlock(&padctl->lock);1307 1308 return 0;1309}1310 1311static bool tegra210_hsic_phy_remote_wake_detected(struct tegra_xusb_lane *lane)1312{1313 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1314 unsigned int index = lane->index;1315 u32 value;1316 1317 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);1318 if ((value & USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index)) &&1319 (value & USB2_HSIC_PORT_WAKEUP_EVENT(index)))1320 return true;1321 1322 return false;1323}1324 1325#define padctl_pmc_readl(_priv, _offset) \1326({ \1327 u32 value; \1328 WARN(regmap_read(_priv->regmap, _offset, &value), "read %s failed\n", #_offset);\1329 value; \1330})1331 1332#define padctl_pmc_writel(_priv, _value, _offset) \1333 WARN(regmap_write(_priv->regmap, _offset, _value), "write %s failed\n", #_offset)1334 1335static int tegra210_pmc_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,1336 enum usb_device_speed speed)1337{1338 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1339 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);1340 unsigned int port = lane->index;1341 u32 value, tctrl, pctrl, rpd_ctrl;1342 1343 if (!priv->regmap)1344 return -EOPNOTSUPP;1345 1346 if (speed > USB_SPEED_HIGH)1347 return -EINVAL;1348 1349 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);1350 tctrl = TCTRL_VALUE(value);1351 pctrl = PCTRL_VALUE(value);1352 1353 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(port));1354 rpd_ctrl = RPD_CTRL_VALUE(value);1355 1356 /* ensure sleepwalk logic is disabled */1357 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1358 value &= ~UTMIP_MASTER_ENABLE(port);1359 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1360 1361 /* ensure sleepwalk logics are in low power mode */1362 value = padctl_pmc_readl(priv, PMC_UTMIP_MASTER_CONFIG);1363 value |= UTMIP_PWR(port);1364 padctl_pmc_writel(priv, value, PMC_UTMIP_MASTER_CONFIG);1365 1366 /* set debounce time */1367 value = padctl_pmc_readl(priv, PMC_USB_DEBOUNCE_DEL);1368 value &= ~UTMIP_LINE_DEB_CNT(~0);1369 value |= UTMIP_LINE_DEB_CNT(0x1);1370 padctl_pmc_writel(priv, value, PMC_USB_DEBOUNCE_DEL);1371 1372 /* ensure fake events of sleepwalk logic are desiabled */1373 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_FAKE(port));1374 value &= ~(UTMIP_FAKE_USBOP_VAL(port) | UTMIP_FAKE_USBON_VAL(port) |1375 UTMIP_FAKE_USBOP_EN(port) | UTMIP_FAKE_USBON_EN(port));1376 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_FAKE(port));1377 1378 /* ensure wake events of sleepwalk logic are not latched */1379 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);1380 value &= ~UTMIP_LINE_WAKEUP_EN(port);1381 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);1382 1383 /* disable wake event triggers of sleepwalk logic */1384 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1385 value &= ~UTMIP_WAKE_VAL(port, ~0);1386 value |= UTMIP_WAKE_VAL_NONE(port);1387 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1388 1389 /* power down the line state detectors of the pad */1390 value = padctl_pmc_readl(priv, PMC_USB_AO);1391 value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port));1392 padctl_pmc_writel(priv, value, PMC_USB_AO);1393 1394 /* save state per speed */1395 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SAVED_STATE(port));1396 value &= ~SPEED(port, ~0);1397 1398 switch (speed) {1399 case USB_SPEED_HIGH:1400 value |= UTMI_HS(port);1401 break;1402 1403 case USB_SPEED_FULL:1404 value |= UTMI_FS(port);1405 break;1406 1407 case USB_SPEED_LOW:1408 value |= UTMI_LS(port);1409 break;1410 1411 default:1412 value |= UTMI_RST(port);1413 break;1414 }1415 1416 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SAVED_STATE(port));1417 1418 /* enable the trigger of the sleepwalk logic */1419 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port));1420 value |= UTMIP_LINEVAL_WALK_EN(port);1421 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port));1422 1423 /*1424 * Reset the walk pointer and clear the alarm of the sleepwalk logic,1425 * as well as capture the configuration of the USB2.0 pad.1426 */1427 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);1428 value |= UTMIP_CLR_WALK_PTR(port) | UTMIP_CLR_WAKE_ALARM(port) | UTMIP_CAP_CFG(port);1429 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);1430 1431 /* program electrical parameters read from XUSB PADCTL */1432 value = padctl_pmc_readl(priv, PMC_UTMIP_TERM_PAD_CFG);1433 value &= ~(TCTRL_VAL(~0) | PCTRL_VAL(~0));1434 value |= (TCTRL_VAL(tctrl) | PCTRL_VAL(pctrl));1435 padctl_pmc_writel(priv, value, PMC_UTMIP_TERM_PAD_CFG);1436 1437 value = padctl_pmc_readl(priv, PMC_UTMIP_PAD_CFGX(port));1438 value &= ~RPD_CTRL_PX(~0);1439 value |= RPD_CTRL_PX(rpd_ctrl);1440 padctl_pmc_writel(priv, value, PMC_UTMIP_PAD_CFGX(port));1441 1442 /*1443 * Set up the pull-ups and pull-downs of the signals during the four1444 * stages of sleepwalk. If a device is connected, program sleepwalk1445 * logic to maintain a J and keep driving K upon seeing remote wake.1446 */1447 value = padctl_pmc_readl(priv, PMC_UTMIP_SLEEPWALK_PX(port));1448 value = UTMIP_USBOP_RPD_A | UTMIP_USBOP_RPD_B | UTMIP_USBOP_RPD_C | UTMIP_USBOP_RPD_D;1449 value |= UTMIP_USBON_RPD_A | UTMIP_USBON_RPD_B | UTMIP_USBON_RPD_C | UTMIP_USBON_RPD_D;1450 1451 switch (speed) {1452 case USB_SPEED_HIGH:1453 case USB_SPEED_FULL:1454 /* J state: D+/D- = high/low, K state: D+/D- = low/high */1455 value |= UTMIP_HIGHZ_A;1456 value |= UTMIP_AP_A;1457 value |= UTMIP_AN_B | UTMIP_AN_C | UTMIP_AN_D;1458 break;1459 1460 case USB_SPEED_LOW:1461 /* J state: D+/D- = low/high, K state: D+/D- = high/low */1462 value |= UTMIP_HIGHZ_A;1463 value |= UTMIP_AN_A;1464 value |= UTMIP_AP_B | UTMIP_AP_C | UTMIP_AP_D;1465 break;1466 1467 default:1468 value |= UTMIP_HIGHZ_A | UTMIP_HIGHZ_B | UTMIP_HIGHZ_C | UTMIP_HIGHZ_D;1469 break;1470 }1471 1472 padctl_pmc_writel(priv, value, PMC_UTMIP_SLEEPWALK_PX(port));1473 1474 /* power up the line state detectors of the pad */1475 value = padctl_pmc_readl(priv, PMC_USB_AO);1476 value &= ~(USBOP_VAL_PD(port) | USBON_VAL_PD(port));1477 padctl_pmc_writel(priv, value, PMC_USB_AO);1478 1479 usleep_range(50, 100);1480 1481 /* switch the electric control of the USB2.0 pad to PMC */1482 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1483 value |= UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) | UTMIP_TCTRL_USE_PMC(port);1484 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1485 1486 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG1);1487 value |= UTMIP_RPD_CTRL_USE_PMC_PX(port) | UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port);1488 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG1);1489 1490 /* set the wake signaling trigger events */1491 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1492 value &= ~UTMIP_WAKE_VAL(port, ~0);1493 value |= UTMIP_WAKE_VAL_ANY(port);1494 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1495 1496 /* enable the wake detection */1497 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1498 value |= UTMIP_MASTER_ENABLE(port);1499 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1500 1501 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);1502 value |= UTMIP_LINE_WAKEUP_EN(port);1503 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);1504 1505 return 0;1506}1507 1508static int tegra210_pmc_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)1509{1510 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1511 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);1512 unsigned int port = lane->index;1513 u32 value;1514 1515 if (!priv->regmap)1516 return -EOPNOTSUPP;1517 1518 /* disable the wake detection */1519 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1520 value &= ~UTMIP_MASTER_ENABLE(port);1521 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1522 1523 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);1524 value &= ~UTMIP_LINE_WAKEUP_EN(port);1525 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);1526 1527 /* switch the electric control of the USB2.0 pad to XUSB or USB2 */1528 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1529 value &= ~(UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) |1530 UTMIP_TCTRL_USE_PMC(port));1531 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1532 1533 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG1);1534 value &= ~(UTMIP_RPD_CTRL_USE_PMC_PX(port) | UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port));1535 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG1);1536 1537 /* disable wake event triggers of sleepwalk logic */1538 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1539 value &= ~UTMIP_WAKE_VAL(port, ~0);1540 value |= UTMIP_WAKE_VAL_NONE(port);1541 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));1542 1543 /* power down the line state detectors of the port */1544 value = padctl_pmc_readl(priv, PMC_USB_AO);1545 value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port));1546 padctl_pmc_writel(priv, value, PMC_USB_AO);1547 1548 /* clear alarm of the sleepwalk logic */1549 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);1550 value |= UTMIP_CLR_WAKE_ALARM(port);1551 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);1552 1553 return 0;1554}1555 1556static int tegra210_pmc_hsic_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,1557 enum usb_device_speed speed)1558{1559 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1560 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);1561 u32 value;1562 1563 if (!priv->regmap)1564 return -EOPNOTSUPP;1565 1566 /* ensure sleepwalk logic is disabled */1567 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);1568 value &= ~UHSIC_MASTER_ENABLE;1569 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);1570 1571 /* ensure sleepwalk logics are in low power mode */1572 value = padctl_pmc_readl(priv, PMC_UTMIP_MASTER_CONFIG);1573 value |= UHSIC_PWR;1574 padctl_pmc_writel(priv, value, PMC_UTMIP_MASTER_CONFIG);1575 1576 /* set debounce time */1577 value = padctl_pmc_readl(priv, PMC_USB_DEBOUNCE_DEL);1578 value &= ~UHSIC_LINE_DEB_CNT(~0);1579 value |= UHSIC_LINE_DEB_CNT(0x1);1580 padctl_pmc_writel(priv, value, PMC_USB_DEBOUNCE_DEL);1581 1582 /* ensure fake events of sleepwalk logic are desiabled */1583 value = padctl_pmc_readl(priv, PMC_UHSIC_FAKE);1584 value &= ~(UHSIC_FAKE_STROBE_VAL | UHSIC_FAKE_DATA_VAL |1585 UHSIC_FAKE_STROBE_EN | UHSIC_FAKE_DATA_EN);1586 padctl_pmc_writel(priv, value, PMC_UHSIC_FAKE);1587 1588 /* ensure wake events of sleepwalk logic are not latched */1589 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);1590 value &= ~UHSIC_LINE_WAKEUP_EN;1591 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);1592 1593 /* disable wake event triggers of sleepwalk logic */1594 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);1595 value &= ~UHSIC_WAKE_VAL(~0);1596 value |= UHSIC_WAKE_VAL_NONE;1597 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);1598 1599 /* power down the line state detectors of the port */1600 value = padctl_pmc_readl(priv, PMC_USB_AO);1601 value |= STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD;1602 padctl_pmc_writel(priv, value, PMC_USB_AO);1603 1604 /* save state, HSIC always comes up as HS */1605 value = padctl_pmc_readl(priv, PMC_UHSIC_SAVED_STATE);1606 value &= ~UHSIC_MODE(~0);1607 value |= UHSIC_HS;1608 padctl_pmc_writel(priv, value, PMC_UHSIC_SAVED_STATE);1609 1610 /* enable the trigger of the sleepwalk logic */1611 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEPWALK_CFG);1612 value |= UHSIC_WAKE_WALK_EN | UHSIC_LINEVAL_WALK_EN;1613 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEPWALK_CFG);1614 1615 /*1616 * Reset the walk pointer and clear the alarm of the sleepwalk logic,1617 * as well as capture the configuration of the USB2.0 port.1618 */1619 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);1620 value |= UHSIC_CLR_WALK_PTR | UHSIC_CLR_WAKE_ALARM;1621 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);1622 1623 /*1624 * Set up the pull-ups and pull-downs of the signals during the four1625 * stages of sleepwalk. Maintain a HSIC IDLE and keep driving HSIC1626 * RESUME upon remote wake.1627 */1628 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEPWALK_P0);1629 value = UHSIC_DATA0_RPD_A | UHSIC_DATA0_RPU_B | UHSIC_DATA0_RPU_C | UHSIC_DATA0_RPU_D |1630 UHSIC_STROBE_RPU_A | UHSIC_STROBE_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_STROBE_RPD_D;1631 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEPWALK_P0);1632 1633 /* power up the line state detectors of the port */1634 value = padctl_pmc_readl(priv, PMC_USB_AO);1635 value &= ~(STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD);1636 padctl_pmc_writel(priv, value, PMC_USB_AO);1637 1638 usleep_range(50, 100);1639 1640 /* set the wake signaling trigger events */1641 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);1642 value &= ~UHSIC_WAKE_VAL(~0);1643 value |= UHSIC_WAKE_VAL_SD10;1644 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);1645 1646 /* enable the wake detection */1647 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);1648 value |= UHSIC_MASTER_ENABLE;1649 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);1650 1651 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);1652 value |= UHSIC_LINE_WAKEUP_EN;1653 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);1654 1655 return 0;1656}1657 1658static int tegra210_pmc_hsic_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)1659{1660 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1661 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);1662 u32 value;1663 1664 if (!priv->regmap)1665 return -EOPNOTSUPP;1666 1667 /* disable the wake detection */1668 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);1669 value &= ~UHSIC_MASTER_ENABLE;1670 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);1671 1672 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);1673 value &= ~UHSIC_LINE_WAKEUP_EN;1674 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);1675 1676 /* disable wake event triggers of sleepwalk logic */1677 value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);1678 value &= ~UHSIC_WAKE_VAL(~0);1679 value |= UHSIC_WAKE_VAL_NONE;1680 padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);1681 1682 /* power down the line state detectors of the port */1683 value = padctl_pmc_readl(priv, PMC_USB_AO);1684 value |= STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD;1685 padctl_pmc_writel(priv, value, PMC_USB_AO);1686 1687 /* clear alarm of the sleepwalk logic */1688 value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);1689 value |= UHSIC_CLR_WAKE_ALARM;1690 padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);1691 1692 return 0;1693}1694 1695static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,1696 unsigned int index, bool enable)1697{1698 struct tegra_xusb_port *port;1699 struct tegra_xusb_lane *lane;1700 u32 value, offset;1701 1702 port = tegra_xusb_find_port(padctl, "usb3", index);1703 if (!port)1704 return -ENODEV;1705 1706 lane = port->lane;1707 1708 if (lane->pad == padctl->pcie)1709 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index);1710 else1711 offset = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1;1712 1713 value = padctl_readl(padctl, offset);1714 1715 value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK <<1716 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) |1717 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN |1718 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD);1719 1720 if (!enable) {1721 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL <<1722 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) |1723 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN |1724 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD;1725 }1726 1727 padctl_writel(padctl, value, offset);1728 1729 return 0;1730}1731 1732#define TEGRA210_LANE(_name, _offset, _shift, _mask, _type) \1733 { \1734 .name = _name, \1735 .offset = _offset, \1736 .shift = _shift, \1737 .mask = _mask, \1738 .num_funcs = ARRAY_SIZE(tegra210_##_type##_functions), \1739 .funcs = tegra210_##_type##_functions, \1740 }1741 1742static const char *tegra210_usb2_functions[] = {1743 "snps",1744 "xusb",1745 "uart"1746};1747 1748static const struct tegra_xusb_lane_soc tegra210_usb2_lanes[] = {1749 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2),1750 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2),1751 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2),1752 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2),1753};1754 1755static struct tegra_xusb_lane *1756tegra210_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,1757 unsigned int index)1758{1759 struct tegra_xusb_usb2_lane *usb2;1760 int err;1761 1762 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);1763 if (!usb2)1764 return ERR_PTR(-ENOMEM);1765 1766 INIT_LIST_HEAD(&usb2->base.list);1767 usb2->base.soc = &pad->soc->lanes[index];1768 usb2->base.index = index;1769 usb2->base.pad = pad;1770 usb2->base.np = np;1771 1772 err = tegra_xusb_lane_parse_dt(&usb2->base, np);1773 if (err < 0) {1774 kfree(usb2);1775 return ERR_PTR(err);1776 }1777 1778 return &usb2->base;1779}1780 1781static void tegra210_usb2_lane_remove(struct tegra_xusb_lane *lane)1782{1783 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);1784 1785 kfree(usb2);1786}1787 1788static const struct tegra_xusb_lane_ops tegra210_usb2_lane_ops = {1789 .probe = tegra210_usb2_lane_probe,1790 .remove = tegra210_usb2_lane_remove,1791 .enable_phy_sleepwalk = tegra210_pmc_utmi_enable_phy_sleepwalk,1792 .disable_phy_sleepwalk = tegra210_pmc_utmi_disable_phy_sleepwalk,1793 .enable_phy_wake = tegra210_utmi_enable_phy_wake,1794 .disable_phy_wake = tegra210_utmi_disable_phy_wake,1795 .remote_wake_detected = tegra210_utmi_phy_remote_wake_detected,1796};1797 1798static int tegra210_usb2_phy_init(struct phy *phy)1799{1800 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);1801 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1802 unsigned int index = lane->index;1803 struct tegra_xusb_usb2_port *port;1804 int err;1805 u32 value;1806 1807 port = tegra_xusb_find_usb2_port(padctl, index);1808 if (!port) {1809 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);1810 return -ENODEV;1811 }1812 1813 if (port->supply && port->mode == USB_DR_MODE_HOST) {1814 err = regulator_enable(port->supply);1815 if (err)1816 return err;1817 }1818 1819 mutex_lock(&padctl->lock);1820 1821 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);1822 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK <<1823 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT);1824 value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB <<1825 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT;1826 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);1827 1828 mutex_unlock(&padctl->lock);1829 1830 return 0;1831}1832 1833static int tegra210_usb2_phy_exit(struct phy *phy)1834{1835 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);1836 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1837 struct tegra_xusb_usb2_port *port;1838 int err;1839 1840 port = tegra_xusb_find_usb2_port(padctl, lane->index);1841 if (!port) {1842 dev_err(&phy->dev, "no port found for USB2 lane %u\n", lane->index);1843 return -ENODEV;1844 }1845 1846 if (port->supply && port->mode == USB_DR_MODE_HOST) {1847 err = regulator_disable(port->supply);1848 if (err)1849 return err;1850 }1851 1852 return 0;1853}1854 1855static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,1856 bool status)1857{1858 u32 value;1859 1860 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");1861 1862 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);1863 1864 if (status) {1865 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;1866 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<1867 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);1868 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING <<1869 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;1870 } else {1871 value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;1872 }1873 1874 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);1875 1876 return 0;1877}1878 1879static int tegra210_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,1880 bool status)1881{1882 u32 value;1883 1884 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");1885 1886 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);1887 1888 if (status) {1889 if (value & XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON) {1890 value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;1891 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);1892 usleep_range(1000, 2000);1893 1894 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);1895 }1896 1897 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<1898 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);1899 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED <<1900 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;1901 } else {1902 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<1903 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);1904 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING <<1905 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;1906 }1907 1908 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);1909 1910 return 0;1911}1912 1913static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode,1914 int submode)1915{1916 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);1917 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1918 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,1919 lane->index);1920 int err = 0;1921 1922 mutex_lock(&padctl->lock);1923 1924 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);1925 1926 if (mode == PHY_MODE_USB_OTG) {1927 if (submode == USB_ROLE_HOST) {1928 tegra210_xusb_padctl_id_override(padctl, true);1929 1930 err = regulator_enable(port->supply);1931 } else if (submode == USB_ROLE_DEVICE) {1932 tegra210_xusb_padctl_vbus_override(padctl, true);1933 } else if (submode == USB_ROLE_NONE) {1934 /*1935 * When port is peripheral only or role transitions to1936 * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not1937 * be enabled.1938 */1939 if (regulator_is_enabled(port->supply))1940 regulator_disable(port->supply);1941 1942 tegra210_xusb_padctl_id_override(padctl, false);1943 tegra210_xusb_padctl_vbus_override(padctl, false);1944 }1945 }1946 1947 mutex_unlock(&padctl->lock);1948 1949 return err;1950}1951 1952static int tegra210_usb2_phy_power_on(struct phy *phy)1953{1954 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);1955 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);1956 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);1957 struct tegra_xusb_padctl *padctl = lane->pad->padctl;1958 struct tegra210_xusb_padctl *priv;1959 struct tegra_xusb_usb2_port *port;1960 unsigned int index = lane->index;1961 u32 value;1962 int err;1963 1964 port = tegra_xusb_find_usb2_port(padctl, index);1965 if (!port) {1966 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);1967 return -ENODEV;1968 }1969 1970 priv = to_tegra210_xusb_padctl(padctl);1971 1972 mutex_lock(&padctl->lock);1973 1974 if (port->usb3_port_fake != -1) {1975 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);1976 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(1977 port->usb3_port_fake);1978 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(1979 port->usb3_port_fake, index);1980 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);1981 1982 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);1983 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(1984 port->usb3_port_fake);1985 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);1986 1987 usleep_range(100, 200);1988 1989 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);1990 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(1991 port->usb3_port_fake);1992 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);1993 1994 usleep_range(100, 200);1995 1996 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);1997 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(1998 port->usb3_port_fake);1999 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);2000 }2001 2002 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);2003 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK <<2004 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT) |2005 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK <<2006 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT));2007 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL <<2008 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT);2009 2010 if (tegra_sku_info.revision < TEGRA_REVISION_A02)2011 value |=2012 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL <<2013 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT);2014 2015 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);2016 2017 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);2018 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index);2019 if (port->mode == USB_DR_MODE_UNKNOWN)2020 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index);2021 else if (port->mode == USB_DR_MODE_PERIPHERAL)2022 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index);2023 else if (port->mode == USB_DR_MODE_HOST)2024 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index);2025 else if (port->mode == USB_DR_MODE_OTG)2026 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index);2027 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);2028 2029 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));2030 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK <<2031 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT) |2032 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD |2033 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 |2034 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);2035 value |= (priv->fuse.hs_curr_level[index] +2036 usb2->hs_curr_level_offset) <<2037 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT;2038 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));2039 2040 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));2041 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK <<2042 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |2043 (XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK <<2044 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT) |2045 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR |2046 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD |2047 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD);2048 value |= (priv->fuse.hs_term_range_adj <<2049 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |2050 (priv->fuse.rpd_ctrl <<2051 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT);2052 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));2053 2054 value = padctl_readl(padctl,2055 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));2056 value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK <<2057 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT);2058 if (port->mode == USB_DR_MODE_HOST)2059 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;2060 else2061 value |=2062 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL <<2063 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT;2064 padctl_writel(padctl, value,2065 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));2066 2067 if (pad->enable > 0) {2068 pad->enable++;2069 mutex_unlock(&padctl->lock);2070 return 0;2071 }2072 2073 err = clk_prepare_enable(pad->clk);2074 if (err)2075 goto out;2076 2077 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);2078 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK <<2079 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |2080 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK <<2081 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT));2082 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL <<2083 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |2084 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL <<2085 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT);2086 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);2087 2088 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);2089 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;2090 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);2091 2092 udelay(1);2093 2094 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);2095 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK;2096 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);2097 2098 udelay(50);2099 2100 clk_disable_unprepare(pad->clk);2101 2102 pad->enable++;2103 mutex_unlock(&padctl->lock);2104 2105 return 0;2106 2107out:2108 mutex_unlock(&padctl->lock);2109 return err;2110}2111 2112static int tegra210_usb2_phy_power_off(struct phy *phy)2113{2114 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2115 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);2116 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2117 struct tegra_xusb_usb2_port *port;2118 u32 value;2119 2120 port = tegra_xusb_find_usb2_port(padctl, lane->index);2121 if (!port) {2122 dev_err(&phy->dev, "no port found for USB2 lane %u\n",2123 lane->index);2124 return -ENODEV;2125 }2126 2127 mutex_lock(&padctl->lock);2128 2129 if (port->usb3_port_fake != -1) {2130 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);2131 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(2132 port->usb3_port_fake);2133 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);2134 2135 usleep_range(100, 200);2136 2137 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);2138 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(2139 port->usb3_port_fake);2140 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);2141 2142 usleep_range(250, 350);2143 2144 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);2145 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(2146 port->usb3_port_fake);2147 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);2148 2149 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);2150 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake,2151 XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED);2152 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);2153 }2154 2155 if (WARN_ON(pad->enable == 0))2156 goto out;2157 2158 if (--pad->enable > 0)2159 goto out;2160 2161 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);2162 value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;2163 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);2164 2165out:2166 mutex_unlock(&padctl->lock);2167 return 0;2168}2169 2170static const struct phy_ops tegra210_usb2_phy_ops = {2171 .init = tegra210_usb2_phy_init,2172 .exit = tegra210_usb2_phy_exit,2173 .power_on = tegra210_usb2_phy_power_on,2174 .power_off = tegra210_usb2_phy_power_off,2175 .set_mode = tegra210_usb2_phy_set_mode,2176 .owner = THIS_MODULE,2177};2178 2179static struct tegra_xusb_pad *2180tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl,2181 const struct tegra_xusb_pad_soc *soc,2182 struct device_node *np)2183{2184 struct tegra_xusb_usb2_pad *usb2;2185 struct tegra_xusb_pad *pad;2186 int err;2187 2188 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);2189 if (!usb2)2190 return ERR_PTR(-ENOMEM);2191 2192 pad = &usb2->base;2193 pad->ops = &tegra210_usb2_lane_ops;2194 pad->soc = soc;2195 2196 err = tegra_xusb_pad_init(pad, padctl, np);2197 if (err < 0) {2198 kfree(usb2);2199 goto out;2200 }2201 2202 usb2->clk = devm_clk_get(&pad->dev, "trk");2203 if (IS_ERR(usb2->clk)) {2204 err = PTR_ERR(usb2->clk);2205 dev_err(&pad->dev, "failed to get trk clock: %d\n", err);2206 goto unregister;2207 }2208 2209 err = tegra_xusb_pad_register(pad, &tegra210_usb2_phy_ops);2210 if (err < 0)2211 goto unregister;2212 2213 dev_set_drvdata(&pad->dev, pad);2214 2215 return pad;2216 2217unregister:2218 device_unregister(&pad->dev);2219out:2220 return ERR_PTR(err);2221}2222 2223static void tegra210_usb2_pad_remove(struct tegra_xusb_pad *pad)2224{2225 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);2226 2227 kfree(usb2);2228}2229 2230static const struct tegra_xusb_pad_ops tegra210_usb2_ops = {2231 .probe = tegra210_usb2_pad_probe,2232 .remove = tegra210_usb2_pad_remove,2233};2234 2235static const struct tegra_xusb_pad_soc tegra210_usb2_pad = {2236 .name = "usb2",2237 .num_lanes = ARRAY_SIZE(tegra210_usb2_lanes),2238 .lanes = tegra210_usb2_lanes,2239 .ops = &tegra210_usb2_ops,2240};2241 2242static const char *tegra210_hsic_functions[] = {2243 "snps",2244 "xusb",2245};2246 2247static const struct tegra_xusb_lane_soc tegra210_hsic_lanes[] = {2248 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),2249};2250 2251static struct tegra_xusb_lane *2252tegra210_hsic_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,2253 unsigned int index)2254{2255 struct tegra_xusb_hsic_lane *hsic;2256 int err;2257 2258 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);2259 if (!hsic)2260 return ERR_PTR(-ENOMEM);2261 2262 INIT_LIST_HEAD(&hsic->base.list);2263 hsic->base.soc = &pad->soc->lanes[index];2264 hsic->base.index = index;2265 hsic->base.pad = pad;2266 hsic->base.np = np;2267 2268 err = tegra_xusb_lane_parse_dt(&hsic->base, np);2269 if (err < 0) {2270 kfree(hsic);2271 return ERR_PTR(err);2272 }2273 2274 return &hsic->base;2275}2276 2277static void tegra210_hsic_lane_remove(struct tegra_xusb_lane *lane)2278{2279 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);2280 2281 kfree(hsic);2282}2283 2284static const struct tegra_xusb_lane_ops tegra210_hsic_lane_ops = {2285 .probe = tegra210_hsic_lane_probe,2286 .remove = tegra210_hsic_lane_remove,2287 .enable_phy_sleepwalk = tegra210_pmc_hsic_enable_phy_sleepwalk,2288 .disable_phy_sleepwalk = tegra210_pmc_hsic_disable_phy_sleepwalk,2289 .enable_phy_wake = tegra210_hsic_enable_phy_wake,2290 .disable_phy_wake = tegra210_hsic_disable_phy_wake,2291 .remote_wake_detected = tegra210_hsic_phy_remote_wake_detected,2292};2293 2294static int tegra210_hsic_phy_init(struct phy *phy)2295{2296 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2297 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2298 u32 value;2299 2300 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);2301 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK <<2302 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT);2303 value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB <<2304 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT;2305 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);2306 2307 return 0;2308}2309 2310static int tegra210_hsic_phy_exit(struct phy *phy)2311{2312 return 0;2313}2314 2315static int tegra210_hsic_phy_power_on(struct phy *phy)2316{2317 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2318 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);2319 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);2320 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2321 unsigned int index = lane->index;2322 u32 value;2323 int err;2324 2325 err = regulator_enable(pad->supply);2326 if (err)2327 return err;2328 2329 padctl_writel(padctl, hsic->strobe_trim,2330 XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL);2331 2332 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));2333 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK <<2334 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT);2335 value |= (hsic->tx_rtune_p <<2336 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT);2337 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));2338 2339 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index));2340 value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK <<2341 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |2342 (XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK <<2343 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT));2344 value |= (hsic->rx_strobe_trim <<2345 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |2346 (hsic->rx_data_trim <<2347 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT);2348 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index));2349 2350 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));2351 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |2352 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 |2353 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE |2354 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |2355 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 |2356 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE |2357 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 |2358 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 |2359 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE |2360 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 |2361 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 |2362 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE);2363 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |2364 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |2365 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE;2366 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));2367 2368 err = clk_prepare_enable(pad->clk);2369 if (err)2370 goto disable;2371 2372 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);2373 value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK <<2374 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) |2375 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK <<2376 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT));2377 value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL <<2378 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) |2379 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL <<2380 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT);2381 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);2382 2383 udelay(1);2384 2385 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);2386 value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK;2387 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);2388 2389 udelay(50);2390 2391 clk_disable_unprepare(pad->clk);2392 2393 return 0;2394 2395disable:2396 regulator_disable(pad->supply);2397 return err;2398}2399 2400static int tegra210_hsic_phy_power_off(struct phy *phy)2401{2402 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2403 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);2404 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2405 unsigned int index = lane->index;2406 u32 value;2407 2408 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));2409 value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |2410 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 |2411 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE |2412 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 |2413 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 |2414 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE |2415 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 |2416 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 |2417 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE;2418 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));2419 2420 regulator_disable(pad->supply);2421 2422 return 0;2423}2424 2425static const struct phy_ops tegra210_hsic_phy_ops = {2426 .init = tegra210_hsic_phy_init,2427 .exit = tegra210_hsic_phy_exit,2428 .power_on = tegra210_hsic_phy_power_on,2429 .power_off = tegra210_hsic_phy_power_off,2430 .owner = THIS_MODULE,2431};2432 2433static struct tegra_xusb_pad *2434tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl,2435 const struct tegra_xusb_pad_soc *soc,2436 struct device_node *np)2437{2438 struct tegra_xusb_hsic_pad *hsic;2439 struct tegra_xusb_pad *pad;2440 int err;2441 2442 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);2443 if (!hsic)2444 return ERR_PTR(-ENOMEM);2445 2446 pad = &hsic->base;2447 pad->ops = &tegra210_hsic_lane_ops;2448 pad->soc = soc;2449 2450 err = tegra_xusb_pad_init(pad, padctl, np);2451 if (err < 0) {2452 kfree(hsic);2453 goto out;2454 }2455 2456 hsic->clk = devm_clk_get(&pad->dev, "trk");2457 if (IS_ERR(hsic->clk)) {2458 err = PTR_ERR(hsic->clk);2459 dev_err(&pad->dev, "failed to get trk clock: %d\n", err);2460 goto unregister;2461 }2462 2463 err = tegra_xusb_pad_register(pad, &tegra210_hsic_phy_ops);2464 if (err < 0)2465 goto unregister;2466 2467 dev_set_drvdata(&pad->dev, pad);2468 2469 return pad;2470 2471unregister:2472 device_unregister(&pad->dev);2473out:2474 return ERR_PTR(err);2475}2476 2477static void tegra210_hsic_pad_remove(struct tegra_xusb_pad *pad)2478{2479 struct tegra_xusb_hsic_pad *hsic = to_hsic_pad(pad);2480 2481 kfree(hsic);2482}2483 2484static const struct tegra_xusb_pad_ops tegra210_hsic_ops = {2485 .probe = tegra210_hsic_pad_probe,2486 .remove = tegra210_hsic_pad_remove,2487};2488 2489static const struct tegra_xusb_pad_soc tegra210_hsic_pad = {2490 .name = "hsic",2491 .num_lanes = ARRAY_SIZE(tegra210_hsic_lanes),2492 .lanes = tegra210_hsic_lanes,2493 .ops = &tegra210_hsic_ops,2494};2495 2496static void tegra210_uphy_lane_iddq_enable(struct tegra_xusb_lane *lane)2497{2498 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2499 u32 value;2500 2501 value = padctl_readl(padctl, lane->soc->regs.misc_ctl2);2502 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD;2503 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;2504 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD;2505 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD;2506 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ;2507 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK;2508 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL;2509 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;2510 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK;2511 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL;2512 padctl_writel(padctl, value, lane->soc->regs.misc_ctl2);2513}2514 2515static void tegra210_uphy_lane_iddq_disable(struct tegra_xusb_lane *lane)2516{2517 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2518 u32 value;2519 2520 value = padctl_readl(padctl, lane->soc->regs.misc_ctl2);2521 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD;2522 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;2523 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD;2524 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD;2525 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ;2526 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK;2527 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL;2528 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;2529 value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK;2530 value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL;2531 padctl_writel(padctl, value, lane->soc->regs.misc_ctl2);2532}2533 2534#define TEGRA210_UPHY_LANE(_name, _offset, _shift, _mask, _type, _misc) \2535 { \2536 .name = _name, \2537 .offset = _offset, \2538 .shift = _shift, \2539 .mask = _mask, \2540 .num_funcs = ARRAY_SIZE(tegra210_##_type##_functions), \2541 .funcs = tegra210_##_type##_functions, \2542 .regs.misc_ctl2 = _misc, \2543 }2544 2545static const char *tegra210_pcie_functions[] = {2546 "pcie-x1",2547 "usb3-ss",2548 "sata",2549 "pcie-x4",2550};2551 2552static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = {2553 TEGRA210_UPHY_LANE("pcie-0", 0x028, 12, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),2554 TEGRA210_UPHY_LANE("pcie-1", 0x028, 14, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(1)),2555 TEGRA210_UPHY_LANE("pcie-2", 0x028, 16, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(2)),2556 TEGRA210_UPHY_LANE("pcie-3", 0x028, 18, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(3)),2557 TEGRA210_UPHY_LANE("pcie-4", 0x028, 20, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(4)),2558 TEGRA210_UPHY_LANE("pcie-5", 0x028, 22, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(5)),2559 TEGRA210_UPHY_LANE("pcie-6", 0x028, 24, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(6)),2560};2561 2562static struct tegra_xusb_usb3_port *2563tegra210_lane_to_usb3_port(struct tegra_xusb_lane *lane)2564{2565 int port;2566 2567 if (!lane || !lane->pad || !lane->pad->padctl)2568 return NULL;2569 2570 port = tegra210_usb3_lane_map(lane);2571 if (port < 0)2572 return NULL;2573 2574 return tegra_xusb_find_usb3_port(lane->pad->padctl, port);2575}2576 2577static int tegra210_usb3_phy_power_on(struct phy *phy)2578{2579 struct device *dev = &phy->dev;2580 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2581 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2582 struct tegra_xusb_usb3_port *usb3 = tegra210_lane_to_usb3_port(lane);2583 unsigned int index;2584 u32 value;2585 2586 if (!usb3) {2587 dev_err(dev, "no USB3 port found for lane %u\n", lane->index);2588 return -ENODEV;2589 }2590 2591 index = usb3->base.index;2592 2593 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);2594 2595 if (!usb3->internal)2596 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);2597 else2598 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);2599 2600 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);2601 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);2602 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);2603 2604 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));2605 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK <<2606 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT);2607 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL <<2608 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT;2609 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));2610 2611 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));2612 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK <<2613 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT);2614 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL <<2615 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT;2616 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));2617 2618 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL,2619 XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index));2620 2621 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));2622 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK <<2623 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT);2624 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL <<2625 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT;2626 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));2627 2628 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL,2629 XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index));2630 2631 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);2632 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);2633 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);2634 2635 usleep_range(100, 200);2636 2637 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);2638 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);2639 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);2640 2641 usleep_range(100, 200);2642 2643 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);2644 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);2645 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);2646 2647 return 0;2648}2649 2650static int tegra210_usb3_phy_power_off(struct phy *phy)2651{2652 struct device *dev = &phy->dev;2653 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2654 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2655 struct tegra_xusb_usb3_port *usb3 = tegra210_lane_to_usb3_port(lane);2656 unsigned int index;2657 u32 value;2658 2659 if (!usb3) {2660 dev_err(dev, "no USB3 port found for lane %u\n", lane->index);2661 return -ENODEV;2662 }2663 2664 index = usb3->base.index;2665 2666 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);2667 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);2668 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);2669 2670 usleep_range(100, 200);2671 2672 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);2673 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);2674 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);2675 2676 usleep_range(250, 350);2677 2678 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);2679 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);2680 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);2681 2682 return 0;2683}2684static struct tegra_xusb_lane *2685tegra210_pcie_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,2686 unsigned int index)2687{2688 struct tegra_xusb_pcie_lane *pcie;2689 int err;2690 2691 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);2692 if (!pcie)2693 return ERR_PTR(-ENOMEM);2694 2695 INIT_LIST_HEAD(&pcie->base.list);2696 pcie->base.soc = &pad->soc->lanes[index];2697 pcie->base.index = index;2698 pcie->base.pad = pad;2699 pcie->base.np = np;2700 2701 err = tegra_xusb_lane_parse_dt(&pcie->base, np);2702 if (err < 0) {2703 kfree(pcie);2704 return ERR_PTR(err);2705 }2706 2707 return &pcie->base;2708}2709 2710static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane)2711{2712 struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane);2713 2714 kfree(pcie);2715}2716 2717static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops = {2718 .probe = tegra210_pcie_lane_probe,2719 .remove = tegra210_pcie_lane_remove,2720 .iddq_enable = tegra210_uphy_lane_iddq_enable,2721 .iddq_disable = tegra210_uphy_lane_iddq_disable,2722 .enable_phy_sleepwalk = tegra210_usb3_enable_phy_sleepwalk,2723 .disable_phy_sleepwalk = tegra210_usb3_disable_phy_sleepwalk,2724 .enable_phy_wake = tegra210_usb3_enable_phy_wake,2725 .disable_phy_wake = tegra210_usb3_disable_phy_wake,2726 .remote_wake_detected = tegra210_usb3_phy_remote_wake_detected,2727};2728 2729static int tegra210_pcie_phy_init(struct phy *phy)2730{2731 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2732 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2733 2734 mutex_lock(&padctl->lock);2735 2736 tegra210_uphy_init(padctl);2737 2738 mutex_unlock(&padctl->lock);2739 2740 return 0;2741}2742 2743static int tegra210_pcie_phy_power_on(struct phy *phy)2744{2745 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2746 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2747 int err = 0;2748 2749 mutex_lock(&padctl->lock);2750 2751 if (tegra_xusb_lane_check(lane, "usb3-ss"))2752 err = tegra210_usb3_phy_power_on(phy);2753 2754 mutex_unlock(&padctl->lock);2755 return err;2756}2757 2758static int tegra210_pcie_phy_power_off(struct phy *phy)2759{2760 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2761 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2762 int err = 0;2763 2764 mutex_lock(&padctl->lock);2765 2766 if (tegra_xusb_lane_check(lane, "usb3-ss"))2767 err = tegra210_usb3_phy_power_off(phy);2768 2769 mutex_unlock(&padctl->lock);2770 return err;2771}2772 2773static const struct phy_ops tegra210_pcie_phy_ops = {2774 .init = tegra210_pcie_phy_init,2775 .power_on = tegra210_pcie_phy_power_on,2776 .power_off = tegra210_pcie_phy_power_off,2777 .owner = THIS_MODULE,2778};2779 2780static struct tegra_xusb_pad *2781tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl,2782 const struct tegra_xusb_pad_soc *soc,2783 struct device_node *np)2784{2785 struct tegra_xusb_pcie_pad *pcie;2786 struct tegra_xusb_pad *pad;2787 int err;2788 2789 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);2790 if (!pcie)2791 return ERR_PTR(-ENOMEM);2792 2793 pad = &pcie->base;2794 pad->ops = &tegra210_pcie_lane_ops;2795 pad->soc = soc;2796 2797 err = tegra_xusb_pad_init(pad, padctl, np);2798 if (err < 0) {2799 kfree(pcie);2800 goto out;2801 }2802 2803 pcie->pll = devm_clk_get(&pad->dev, "pll");2804 if (IS_ERR(pcie->pll)) {2805 err = PTR_ERR(pcie->pll);2806 dev_err(&pad->dev, "failed to get PLL: %d\n", err);2807 goto unregister;2808 }2809 2810 pcie->rst = devm_reset_control_get(&pad->dev, "phy");2811 if (IS_ERR(pcie->rst)) {2812 err = PTR_ERR(pcie->rst);2813 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err);2814 goto unregister;2815 }2816 2817 err = tegra_xusb_pad_register(pad, &tegra210_pcie_phy_ops);2818 if (err < 0)2819 goto unregister;2820 2821 dev_set_drvdata(&pad->dev, pad);2822 2823 return pad;2824 2825unregister:2826 device_unregister(&pad->dev);2827out:2828 return ERR_PTR(err);2829}2830 2831static void tegra210_pcie_pad_remove(struct tegra_xusb_pad *pad)2832{2833 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(pad);2834 2835 kfree(pcie);2836}2837 2838static const struct tegra_xusb_pad_ops tegra210_pcie_ops = {2839 .probe = tegra210_pcie_pad_probe,2840 .remove = tegra210_pcie_pad_remove,2841};2842 2843static const struct tegra_xusb_pad_soc tegra210_pcie_pad = {2844 .name = "pcie",2845 .num_lanes = ARRAY_SIZE(tegra210_pcie_lanes),2846 .lanes = tegra210_pcie_lanes,2847 .ops = &tegra210_pcie_ops,2848};2849 2850static const struct tegra_xusb_lane_soc tegra210_sata_lanes[] = {2851 TEGRA210_UPHY_LANE("sata-0", 0x028, 30, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2),2852};2853 2854static struct tegra_xusb_lane *2855tegra210_sata_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,2856 unsigned int index)2857{2858 struct tegra_xusb_sata_lane *sata;2859 int err;2860 2861 sata = kzalloc(sizeof(*sata), GFP_KERNEL);2862 if (!sata)2863 return ERR_PTR(-ENOMEM);2864 2865 INIT_LIST_HEAD(&sata->base.list);2866 sata->base.soc = &pad->soc->lanes[index];2867 sata->base.index = index;2868 sata->base.pad = pad;2869 sata->base.np = np;2870 2871 err = tegra_xusb_lane_parse_dt(&sata->base, np);2872 if (err < 0) {2873 kfree(sata);2874 return ERR_PTR(err);2875 }2876 2877 return &sata->base;2878}2879 2880static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane)2881{2882 struct tegra_xusb_sata_lane *sata = to_sata_lane(lane);2883 2884 kfree(sata);2885}2886 2887static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops = {2888 .probe = tegra210_sata_lane_probe,2889 .remove = tegra210_sata_lane_remove,2890 .iddq_enable = tegra210_uphy_lane_iddq_enable,2891 .iddq_disable = tegra210_uphy_lane_iddq_disable,2892 .enable_phy_sleepwalk = tegra210_usb3_enable_phy_sleepwalk,2893 .disable_phy_sleepwalk = tegra210_usb3_disable_phy_sleepwalk,2894 .enable_phy_wake = tegra210_usb3_enable_phy_wake,2895 .disable_phy_wake = tegra210_usb3_disable_phy_wake,2896 .remote_wake_detected = tegra210_usb3_phy_remote_wake_detected,2897};2898 2899static int tegra210_sata_phy_init(struct phy *phy)2900{2901 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2902 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2903 2904 mutex_lock(&padctl->lock);2905 2906 tegra210_uphy_init(padctl);2907 2908 mutex_unlock(&padctl->lock);2909 return 0;2910}2911 2912static int tegra210_sata_phy_power_on(struct phy *phy)2913{2914 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2915 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2916 int err = 0;2917 2918 mutex_lock(&padctl->lock);2919 2920 if (tegra_xusb_lane_check(lane, "usb3-ss"))2921 err = tegra210_usb3_phy_power_on(phy);2922 2923 mutex_unlock(&padctl->lock);2924 return err;2925}2926 2927static int tegra210_sata_phy_power_off(struct phy *phy)2928{2929 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);2930 struct tegra_xusb_padctl *padctl = lane->pad->padctl;2931 int err = 0;2932 2933 mutex_lock(&padctl->lock);2934 2935 if (tegra_xusb_lane_check(lane, "usb3-ss"))2936 err = tegra210_usb3_phy_power_off(phy);2937 2938 mutex_unlock(&padctl->lock);2939 return err;2940}2941 2942static const struct phy_ops tegra210_sata_phy_ops = {2943 .init = tegra210_sata_phy_init,2944 .power_on = tegra210_sata_phy_power_on,2945 .power_off = tegra210_sata_phy_power_off,2946 .owner = THIS_MODULE,2947};2948 2949static struct tegra_xusb_pad *2950tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl,2951 const struct tegra_xusb_pad_soc *soc,2952 struct device_node *np)2953{2954 struct tegra_xusb_sata_pad *sata;2955 struct tegra_xusb_pad *pad;2956 int err;2957 2958 sata = kzalloc(sizeof(*sata), GFP_KERNEL);2959 if (!sata)2960 return ERR_PTR(-ENOMEM);2961 2962 pad = &sata->base;2963 pad->ops = &tegra210_sata_lane_ops;2964 pad->soc = soc;2965 2966 err = tegra_xusb_pad_init(pad, padctl, np);2967 if (err < 0) {2968 kfree(sata);2969 goto out;2970 }2971 2972 sata->rst = devm_reset_control_get(&pad->dev, "phy");2973 if (IS_ERR(sata->rst)) {2974 err = PTR_ERR(sata->rst);2975 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err);2976 goto unregister;2977 }2978 2979 err = tegra_xusb_pad_register(pad, &tegra210_sata_phy_ops);2980 if (err < 0)2981 goto unregister;2982 2983 dev_set_drvdata(&pad->dev, pad);2984 2985 return pad;2986 2987unregister:2988 device_unregister(&pad->dev);2989out:2990 return ERR_PTR(err);2991}2992 2993static void tegra210_sata_pad_remove(struct tegra_xusb_pad *pad)2994{2995 struct tegra_xusb_sata_pad *sata = to_sata_pad(pad);2996 2997 kfree(sata);2998}2999 3000static const struct tegra_xusb_pad_ops tegra210_sata_ops = {3001 .probe = tegra210_sata_pad_probe,3002 .remove = tegra210_sata_pad_remove,3003};3004 3005static const struct tegra_xusb_pad_soc tegra210_sata_pad = {3006 .name = "sata",3007 .num_lanes = ARRAY_SIZE(tegra210_sata_lanes),3008 .lanes = tegra210_sata_lanes,3009 .ops = &tegra210_sata_ops,3010};3011 3012static const struct tegra_xusb_pad_soc * const tegra210_pads[] = {3013 &tegra210_usb2_pad,3014 &tegra210_hsic_pad,3015 &tegra210_pcie_pad,3016 &tegra210_sata_pad,3017};3018 3019static int tegra210_usb2_port_enable(struct tegra_xusb_port *port)3020{3021 return 0;3022}3023 3024static void tegra210_usb2_port_disable(struct tegra_xusb_port *port)3025{3026}3027 3028static struct tegra_xusb_lane *3029tegra210_usb2_port_map(struct tegra_xusb_port *port)3030{3031 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);3032}3033 3034static const struct tegra_xusb_port_ops tegra210_usb2_port_ops = {3035 .release = tegra_xusb_usb2_port_release,3036 .remove = tegra_xusb_usb2_port_remove,3037 .enable = tegra210_usb2_port_enable,3038 .disable = tegra210_usb2_port_disable,3039 .map = tegra210_usb2_port_map,3040};3041 3042static int tegra210_hsic_port_enable(struct tegra_xusb_port *port)3043{3044 return 0;3045}3046 3047static void tegra210_hsic_port_disable(struct tegra_xusb_port *port)3048{3049}3050 3051static struct tegra_xusb_lane *3052tegra210_hsic_port_map(struct tegra_xusb_port *port)3053{3054 return tegra_xusb_find_lane(port->padctl, "hsic", port->index);3055}3056 3057static const struct tegra_xusb_port_ops tegra210_hsic_port_ops = {3058 .release = tegra_xusb_hsic_port_release,3059 .enable = tegra210_hsic_port_enable,3060 .disable = tegra210_hsic_port_disable,3061 .map = tegra210_hsic_port_map,3062};3063 3064static int tegra210_usb3_port_enable(struct tegra_xusb_port *port)3065{3066 return 0;3067}3068 3069static void tegra210_usb3_port_disable(struct tegra_xusb_port *port)3070{3071}3072 3073static struct tegra_xusb_lane *3074tegra210_usb3_port_map(struct tegra_xusb_port *port)3075{3076 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss");3077}3078 3079static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = {3080 .release = tegra_xusb_usb3_port_release,3081 .enable = tegra210_usb3_port_enable,3082 .disable = tegra210_usb3_port_disable,3083 .map = tegra210_usb3_port_map,3084};3085 3086static int tegra210_utmi_port_reset(struct phy *phy)3087{3088 struct tegra_xusb_padctl *padctl;3089 struct tegra_xusb_lane *lane;3090 u32 value;3091 3092 lane = phy_get_drvdata(phy);3093 padctl = lane->pad->padctl;3094 3095 value = padctl_readl(padctl,3096 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(lane->index));3097 3098 if ((value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP) ||3099 (value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN)) {3100 tegra210_xusb_padctl_vbus_override(padctl, false);3101 tegra210_xusb_padctl_vbus_override(padctl, true);3102 return 1;3103 }3104 3105 return 0;3106}3107 3108static int3109tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse)3110{3111 unsigned int i;3112 u32 value;3113 int err;3114 3115 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);3116 if (err < 0)3117 return err;3118 3119 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) {3120 fuse->hs_curr_level[i] =3121 (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) &3122 FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK;3123 }3124 3125 fuse->hs_term_range_adj =3126 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) &3127 FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK;3128 3129 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);3130 if (err < 0)3131 return err;3132 3133 fuse->rpd_ctrl =3134 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) &3135 FUSE_USB_CALIB_EXT_RPD_CTRL_MASK;3136 3137 return 0;3138}3139 3140static struct tegra_xusb_padctl *3141tegra210_xusb_padctl_probe(struct device *dev,3142 const struct tegra_xusb_padctl_soc *soc)3143{3144 struct tegra210_xusb_padctl *padctl;3145 struct platform_device *pdev;3146 struct device_node *np;3147 int err;3148 3149 padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL);3150 if (!padctl)3151 return ERR_PTR(-ENOMEM);3152 3153 padctl->base.dev = dev;3154 padctl->base.soc = soc;3155 3156 err = tegra210_xusb_read_fuse_calibration(&padctl->fuse);3157 if (err < 0)3158 return ERR_PTR(err);3159 3160 np = of_parse_phandle(dev->of_node, "nvidia,pmc", 0);3161 if (!np) {3162 dev_warn(dev, "nvidia,pmc property is missing\n");3163 goto out;3164 }3165 3166 pdev = of_find_device_by_node(np);3167 if (!pdev) {3168 dev_warn(dev, "PMC device is not available\n");3169 goto out;3170 }3171 3172 if (!platform_get_drvdata(pdev))3173 return ERR_PTR(-EPROBE_DEFER);3174 3175 padctl->regmap = dev_get_regmap(&pdev->dev, "usb_sleepwalk");3176 if (!padctl->regmap)3177 dev_info(dev, "failed to find PMC regmap\n");3178 3179out:3180 return &padctl->base;3181}3182 3183static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)3184{3185}3186 3187static void tegra210_xusb_padctl_save(struct tegra_xusb_padctl *padctl)3188{3189 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);3190 3191 priv->context.usb2_pad_mux =3192 padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);3193 priv->context.usb2_port_cap =3194 padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);3195 priv->context.ss_port_map =3196 padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);3197 priv->context.usb3_pad_mux =3198 padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);3199}3200 3201static void tegra210_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)3202{3203 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);3204 struct tegra_xusb_lane *lane;3205 3206 padctl_writel(padctl, priv->context.usb2_pad_mux,3207 XUSB_PADCTL_USB2_PAD_MUX);3208 padctl_writel(padctl, priv->context.usb2_port_cap,3209 XUSB_PADCTL_USB2_PORT_CAP);3210 padctl_writel(padctl, priv->context.ss_port_map,3211 XUSB_PADCTL_SS_PORT_MAP);3212 3213 list_for_each_entry(lane, &padctl->lanes, list) {3214 if (lane->pad->ops->iddq_enable)3215 tegra210_uphy_lane_iddq_enable(lane);3216 }3217 3218 padctl_writel(padctl, priv->context.usb3_pad_mux,3219 XUSB_PADCTL_USB3_PAD_MUX);3220 3221 list_for_each_entry(lane, &padctl->lanes, list) {3222 if (lane->pad->ops->iddq_disable)3223 tegra210_uphy_lane_iddq_disable(lane);3224 }3225}3226 3227static int tegra210_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)3228{3229 mutex_lock(&padctl->lock);3230 3231 tegra210_uphy_deinit(padctl);3232 3233 tegra210_xusb_padctl_save(padctl);3234 3235 mutex_unlock(&padctl->lock);3236 return 0;3237}3238 3239static int tegra210_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)3240{3241 mutex_lock(&padctl->lock);3242 3243 tegra210_xusb_padctl_restore(padctl);3244 3245 tegra210_uphy_init(padctl);3246 3247 mutex_unlock(&padctl->lock);3248 return 0;3249}3250 3251static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = {3252 .probe = tegra210_xusb_padctl_probe,3253 .remove = tegra210_xusb_padctl_remove,3254 .suspend_noirq = tegra210_xusb_padctl_suspend_noirq,3255 .resume_noirq = tegra210_xusb_padctl_resume_noirq,3256 .usb3_set_lfps_detect = tegra210_usb3_set_lfps_detect,3257 .hsic_set_idle = tegra210_hsic_set_idle,3258 .vbus_override = tegra210_xusb_padctl_vbus_override,3259 .utmi_port_reset = tegra210_utmi_port_reset,3260};3261 3262static const char * const tegra210_xusb_padctl_supply_names[] = {3263 "avdd-pll-utmip",3264 "avdd-pll-uerefe",3265 "dvdd-pex-pll",3266 "hvdd-pex-pll-e",3267};3268 3269const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = {3270 .num_pads = ARRAY_SIZE(tegra210_pads),3271 .pads = tegra210_pads,3272 .ports = {3273 .usb2 = {3274 .ops = &tegra210_usb2_port_ops,3275 .count = 4,3276 },3277 .hsic = {3278 .ops = &tegra210_hsic_port_ops,3279 .count = 1,3280 },3281 .usb3 = {3282 .ops = &tegra210_usb3_port_ops,3283 .count = 4,3284 },3285 },3286 .ops = &tegra210_xusb_padctl_ops,3287 .supply_names = tegra210_xusb_padctl_supply_names,3288 .num_supplies = ARRAY_SIZE(tegra210_xusb_padctl_supply_names),3289 .need_fake_usb3_port = true,3290};3291EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc);3292 3293MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");3294MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver");3295MODULE_LICENSE("GPL v2");3296