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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Actions Semi S500 SoC Pinctrl driver4 *5 * Copyright (c) 2014 Actions Semi Inc.6 * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>7 */8 9#include <linux/module.h>10#include <linux/of.h>11#include <linux/platform_device.h>12#include <linux/pinctrl/pinconf-generic.h>13#include <linux/pinctrl/pinctrl.h>14#include "pinctrl-owl.h"15 16/* Pinctrl registers offset */17#define MFCTL0 (0x0040)18#define MFCTL1 (0x0044)19#define MFCTL2 (0x0048)20#define MFCTL3 (0x004C)21#define PAD_PULLCTL0 (0x0060)22#define PAD_PULLCTL1 (0x0064)23#define PAD_PULLCTL2 (0x0068)24#define PAD_ST0 (0x006C)25#define PAD_ST1 (0x0070)26#define PAD_CTL (0x0074)27#define PAD_DRV0 (0x0080)28#define PAD_DRV1 (0x0084)29#define PAD_DRV2 (0x0088)30 31#define _GPIOA(offset) (offset)32#define _GPIOB(offset) (32 + (offset))33#define _GPIOC(offset) (64 + (offset))34#define _GPIOD(offset) (96 + (offset))35#define _GPIOE(offset) (128 + (offset))36 37#define NUM_GPIOS (_GPIOE(3) + 1)38#define _PIN(offset) (NUM_GPIOS + (offset))39 40#define DNAND_DQS _GPIOA(12)41#define DNAND_DQSN _GPIOA(13)42#define ETH_TXD0 _GPIOA(14)43#define ETH_TXD1 _GPIOA(15)44#define ETH_TXEN _GPIOA(16)45#define ETH_RXER _GPIOA(17)46#define ETH_CRS_DV _GPIOA(18)47#define ETH_RXD1 _GPIOA(19)48#define ETH_RXD0 _GPIOA(20)49#define ETH_REF_CLK _GPIOA(21)50#define ETH_MDC _GPIOA(22)51#define ETH_MDIO _GPIOA(23)52#define SIRQ0 _GPIOA(24)53#define SIRQ1 _GPIOA(25)54#define SIRQ2 _GPIOA(26)55#define I2S_D0 _GPIOA(27)56#define I2S_BCLK0 _GPIOA(28)57#define I2S_LRCLK0 _GPIOA(29)58#define I2S_MCLK0 _GPIOA(30)59#define I2S_D1 _GPIOA(31)60 61#define I2S_BCLK1 _GPIOB(0)62#define I2S_LRCLK1 _GPIOB(1)63#define I2S_MCLK1 _GPIOB(2)64#define KS_IN0 _GPIOB(3)65#define KS_IN1 _GPIOB(4)66#define KS_IN2 _GPIOB(5)67#define KS_IN3 _GPIOB(6)68#define KS_OUT0 _GPIOB(7)69#define KS_OUT1 _GPIOB(8)70#define KS_OUT2 _GPIOB(9)71#define LVDS_OEP _GPIOB(10)72#define LVDS_OEN _GPIOB(11)73#define LVDS_ODP _GPIOB(12)74#define LVDS_ODN _GPIOB(13)75#define LVDS_OCP _GPIOB(14)76#define LVDS_OCN _GPIOB(15)77#define LVDS_OBP _GPIOB(16)78#define LVDS_OBN _GPIOB(17)79#define LVDS_OAP _GPIOB(18)80#define LVDS_OAN _GPIOB(19)81#define LVDS_EEP _GPIOB(20)82#define LVDS_EEN _GPIOB(21)83#define LVDS_EDP _GPIOB(22)84#define LVDS_EDN _GPIOB(23)85#define LVDS_ECP _GPIOB(24)86#define LVDS_ECN _GPIOB(25)87#define LVDS_EBP _GPIOB(26)88#define LVDS_EBN _GPIOB(27)89#define LVDS_EAP _GPIOB(28)90#define LVDS_EAN _GPIOB(29)91#define LCD0_D18 _GPIOB(30)92#define LCD0_D17 _GPIOB(31)93 94#define DSI_DP3 _GPIOC(0)95#define DSI_DN3 _GPIOC(1)96#define DSI_DP1 _GPIOC(2)97#define DSI_DN1 _GPIOC(3)98#define DSI_CP _GPIOC(4)99#define DSI_CN _GPIOC(5)100#define DSI_DP0 _GPIOC(6)101#define DSI_DN0 _GPIOC(7)102#define DSI_DP2 _GPIOC(8)103#define DSI_DN2 _GPIOC(9)104#define SD0_D0 _GPIOC(10)105#define SD0_D1 _GPIOC(11)106#define SD0_D2 _GPIOC(12)107#define SD0_D3 _GPIOC(13)108#define SD1_D0 _GPIOC(14) /* SD0_D4 */109#define SD1_D1 _GPIOC(15) /* SD0_D5 */110#define SD1_D2 _GPIOC(16) /* SD0_D6 */111#define SD1_D3 _GPIOC(17) /* SD0_D7 */112#define SD0_CMD _GPIOC(18)113#define SD0_CLK _GPIOC(19)114#define SD1_CMD _GPIOC(20)115#define SD1_CLK _GPIOC(21)116#define SPI0_SCLK _GPIOC(22)117#define SPI0_SS _GPIOC(23)118#define SPI0_MISO _GPIOC(24)119#define SPI0_MOSI _GPIOC(25)120#define UART0_RX _GPIOC(26)121#define UART0_TX _GPIOC(27)122#define I2C0_SCLK _GPIOC(28)123#define I2C0_SDATA _GPIOC(29)124#define SENSOR0_PCLK _GPIOC(31)125 126#define SENSOR0_CKOUT _GPIOD(10)127#define DNAND_ALE _GPIOD(12)128#define DNAND_CLE _GPIOD(13)129#define DNAND_CEB0 _GPIOD(14)130#define DNAND_CEB1 _GPIOD(15)131#define DNAND_CEB2 _GPIOD(16)132#define DNAND_CEB3 _GPIOD(17)133#define UART2_RX _GPIOD(18)134#define UART2_TX _GPIOD(19)135#define UART2_RTSB _GPIOD(20)136#define UART2_CTSB _GPIOD(21)137#define UART3_RX _GPIOD(22)138#define UART3_TX _GPIOD(23)139#define UART3_RTSB _GPIOD(24)140#define UART3_CTSB _GPIOD(25)141#define PCM1_IN _GPIOD(28)142#define PCM1_CLK _GPIOD(29)143#define PCM1_SYNC _GPIOD(30)144#define PCM1_OUT _GPIOD(31)145 146#define I2C1_SCLK _GPIOE(0)147#define I2C1_SDATA _GPIOE(1)148#define I2C2_SCLK _GPIOE(2)149#define I2C2_SDATA _GPIOE(3)150 151#define CSI_DN0 _PIN(0)152#define CSI_DP0 _PIN(1)153#define CSI_DN1 _PIN(2)154#define CSI_DP1 _PIN(3)155#define CSI_CN _PIN(4)156#define CSI_CP _PIN(5)157#define CSI_DN2 _PIN(6)158#define CSI_DP2 _PIN(7)159#define CSI_DN3 _PIN(8)160#define CSI_DP3 _PIN(9)161 162#define DNAND_D0 _PIN(10)163#define DNAND_D1 _PIN(11)164#define DNAND_D2 _PIN(12)165#define DNAND_D3 _PIN(13)166#define DNAND_D4 _PIN(14)167#define DNAND_D5 _PIN(15)168#define DNAND_D6 _PIN(16)169#define DNAND_D7 _PIN(17)170#define DNAND_WRB _PIN(18)171#define DNAND_RDB _PIN(19)172#define DNAND_RDBN _PIN(20)173#define DNAND_RB _PIN(21)174 175#define PORB _PIN(22)176#define CLKO_25M _PIN(23)177#define BSEL _PIN(24)178#define PKG0 _PIN(25)179#define PKG1 _PIN(26)180#define PKG2 _PIN(27)181#define PKG3 _PIN(28)182 183#define _FIRSTPAD _GPIOA(0)184#define _LASTPAD PKG3185#define NUM_PADS (_PIN(28) + 1)186 187static const struct pinctrl_pin_desc s500_pads[] = {188 PINCTRL_PIN(DNAND_DQS, "dnand_dqs"),189 PINCTRL_PIN(DNAND_DQSN, "dnand_dqsn"),190 PINCTRL_PIN(ETH_TXD0, "eth_txd0"),191 PINCTRL_PIN(ETH_TXD1, "eth_txd1"),192 PINCTRL_PIN(ETH_TXEN, "eth_txen"),193 PINCTRL_PIN(ETH_RXER, "eth_rxer"),194 PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),195 PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),196 PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),197 PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),198 PINCTRL_PIN(ETH_MDC, "eth_mdc"),199 PINCTRL_PIN(ETH_MDIO, "eth_mdio"),200 PINCTRL_PIN(SIRQ0, "sirq0"),201 PINCTRL_PIN(SIRQ1, "sirq1"),202 PINCTRL_PIN(SIRQ2, "sirq2"),203 PINCTRL_PIN(I2S_D0, "i2s_d0"),204 PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),205 PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),206 PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),207 PINCTRL_PIN(I2S_D1, "i2s_d1"),208 PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),209 PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),210 PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),211 PINCTRL_PIN(KS_IN0, "ks_in0"),212 PINCTRL_PIN(KS_IN1, "ks_in1"),213 PINCTRL_PIN(KS_IN2, "ks_in2"),214 PINCTRL_PIN(KS_IN3, "ks_in3"),215 PINCTRL_PIN(KS_OUT0, "ks_out0"),216 PINCTRL_PIN(KS_OUT1, "ks_out1"),217 PINCTRL_PIN(KS_OUT2, "ks_out2"),218 PINCTRL_PIN(LVDS_OEP, "lvds_oep"),219 PINCTRL_PIN(LVDS_OEN, "lvds_oen"),220 PINCTRL_PIN(LVDS_ODP, "lvds_odp"),221 PINCTRL_PIN(LVDS_ODN, "lvds_odn"),222 PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),223 PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),224 PINCTRL_PIN(LVDS_OBP, "lvds_obp"),225 PINCTRL_PIN(LVDS_OBN, "lvds_obn"),226 PINCTRL_PIN(LVDS_OAP, "lvds_oap"),227 PINCTRL_PIN(LVDS_OAN, "lvds_oan"),228 PINCTRL_PIN(LVDS_EEP, "lvds_eep"),229 PINCTRL_PIN(LVDS_EEN, "lvds_een"),230 PINCTRL_PIN(LVDS_EDP, "lvds_edp"),231 PINCTRL_PIN(LVDS_EDN, "lvds_edn"),232 PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),233 PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),234 PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),235 PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),236 PINCTRL_PIN(LVDS_EAP, "lvds_eap"),237 PINCTRL_PIN(LVDS_EAN, "lvds_ean"),238 PINCTRL_PIN(LCD0_D18, "lcd0_d18"),239 PINCTRL_PIN(LCD0_D17, "lcd0_d17"),240 PINCTRL_PIN(DSI_DP3, "dsi_dp3"),241 PINCTRL_PIN(DSI_DN3, "dsi_dn3"),242 PINCTRL_PIN(DSI_DP1, "dsi_dp1"),243 PINCTRL_PIN(DSI_DN1, "dsi_dn1"),244 PINCTRL_PIN(DSI_CP, "dsi_cp"),245 PINCTRL_PIN(DSI_CN, "dsi_cn"),246 PINCTRL_PIN(DSI_DP0, "dsi_dp0"),247 PINCTRL_PIN(DSI_DN0, "dsi_dn0"),248 PINCTRL_PIN(DSI_DP2, "dsi_dp2"),249 PINCTRL_PIN(DSI_DN2, "dsi_dn2"),250 PINCTRL_PIN(SD0_D0, "sd0_d0"),251 PINCTRL_PIN(SD0_D1, "sd0_d1"),252 PINCTRL_PIN(SD0_D2, "sd0_d2"),253 PINCTRL_PIN(SD0_D3, "sd0_d3"),254 PINCTRL_PIN(SD1_D0, "sd1_d0"),255 PINCTRL_PIN(SD1_D1, "sd1_d1"),256 PINCTRL_PIN(SD1_D2, "sd1_d2"),257 PINCTRL_PIN(SD1_D3, "sd1_d3"),258 PINCTRL_PIN(SD0_CMD, "sd0_cmd"),259 PINCTRL_PIN(SD0_CLK, "sd0_clk"),260 PINCTRL_PIN(SD1_CMD, "sd1_cmd"),261 PINCTRL_PIN(SD1_CLK, "sd1_clk"),262 PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"),263 PINCTRL_PIN(SPI0_SS, "spi0_ss"),264 PINCTRL_PIN(SPI0_MISO, "spi0_miso"),265 PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"),266 PINCTRL_PIN(UART0_RX, "uart0_rx"),267 PINCTRL_PIN(UART0_TX, "uart0_tx"),268 PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),269 PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),270 PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),271 PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),272 PINCTRL_PIN(DNAND_ALE, "dnand_ale"),273 PINCTRL_PIN(DNAND_CLE, "dnand_cle"),274 PINCTRL_PIN(DNAND_CEB0, "dnand_ceb0"),275 PINCTRL_PIN(DNAND_CEB1, "dnand_ceb1"),276 PINCTRL_PIN(DNAND_CEB2, "dnand_ceb2"),277 PINCTRL_PIN(DNAND_CEB3, "dnand_ceb3"),278 PINCTRL_PIN(UART2_RX, "uart2_rx"),279 PINCTRL_PIN(UART2_TX, "uart2_tx"),280 PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),281 PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),282 PINCTRL_PIN(UART3_RX, "uart3_rx"),283 PINCTRL_PIN(UART3_TX, "uart3_tx"),284 PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),285 PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),286 PINCTRL_PIN(PCM1_IN, "pcm1_in"),287 PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),288 PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),289 PINCTRL_PIN(PCM1_OUT, "pcm1_out"),290 PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),291 PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),292 PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),293 PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),294 PINCTRL_PIN(CSI_DN0, "csi_dn0"),295 PINCTRL_PIN(CSI_DP0, "csi_dp0"),296 PINCTRL_PIN(CSI_DN1, "csi_dn1"),297 PINCTRL_PIN(CSI_DP1, "csi_dp1"),298 PINCTRL_PIN(CSI_DN2, "csi_dn2"),299 PINCTRL_PIN(CSI_DP2, "csi_dp2"),300 PINCTRL_PIN(CSI_DN3, "csi_dn3"),301 PINCTRL_PIN(CSI_DP3, "csi_dp3"),302 PINCTRL_PIN(CSI_CN, "csi_cn"),303 PINCTRL_PIN(CSI_CP, "csi_cp"),304 PINCTRL_PIN(DNAND_D0, "dnand_d0"),305 PINCTRL_PIN(DNAND_D1, "dnand_d1"),306 PINCTRL_PIN(DNAND_D2, "dnand_d2"),307 PINCTRL_PIN(DNAND_D3, "dnand_d3"),308 PINCTRL_PIN(DNAND_D4, "dnand_d4"),309 PINCTRL_PIN(DNAND_D5, "dnand_d5"),310 PINCTRL_PIN(DNAND_D6, "dnand_d6"),311 PINCTRL_PIN(DNAND_D7, "dnand_d7"),312 PINCTRL_PIN(DNAND_RB, "dnand_rb"),313 PINCTRL_PIN(DNAND_RDB, "dnand_rdb"),314 PINCTRL_PIN(DNAND_RDBN, "dnand_rdbn"),315 PINCTRL_PIN(DNAND_WRB, "dnand_wrb"),316 PINCTRL_PIN(PORB, "porb"),317 PINCTRL_PIN(CLKO_25M, "clko_25m"),318 PINCTRL_PIN(BSEL, "bsel"),319 PINCTRL_PIN(PKG0, "pkg0"),320 PINCTRL_PIN(PKG1, "pkg1"),321 PINCTRL_PIN(PKG2, "pkg2"),322 PINCTRL_PIN(PKG3, "pkg3"),323};324 325enum s500_pinmux_functions {326 S500_MUX_NOR,327 S500_MUX_ETH_RMII,328 S500_MUX_ETH_SMII,329 S500_MUX_SPI0,330 S500_MUX_SPI1,331 S500_MUX_SPI2,332 S500_MUX_SPI3,333 S500_MUX_SENS0,334 S500_MUX_SENS1,335 S500_MUX_UART0,336 S500_MUX_UART1,337 S500_MUX_UART2,338 S500_MUX_UART3,339 S500_MUX_UART4,340 S500_MUX_UART5,341 S500_MUX_UART6,342 S500_MUX_I2S0,343 S500_MUX_I2S1,344 S500_MUX_PCM1,345 S500_MUX_PCM0,346 S500_MUX_KS,347 S500_MUX_JTAG,348 S500_MUX_PWM0,349 S500_MUX_PWM1,350 S500_MUX_PWM2,351 S500_MUX_PWM3,352 S500_MUX_PWM4,353 S500_MUX_PWM5,354 S500_MUX_P0,355 S500_MUX_SD0,356 S500_MUX_SD1,357 S500_MUX_SD2,358 S500_MUX_I2C0,359 S500_MUX_I2C1,360 /*S500_MUX_I2C2,*/361 S500_MUX_I2C3,362 S500_MUX_DSI,363 S500_MUX_LVDS,364 S500_MUX_USB30,365 S500_MUX_CLKO_25M,366 S500_MUX_MIPI_CSI,367 S500_MUX_NAND,368 S500_MUX_SPDIF,369 /*S500_MUX_SIRQ0,*/370 /*S500_MUX_SIRQ1,*/371 /*S500_MUX_SIRQ2,*/372 S500_MUX_TS,373 S500_MUX_LCD0,374 S500_MUX_RESERVED,375};376 377/* MFPCTL group data */378/* mfp0_31_26 reserved */379/* mfp0_25_23 */380static unsigned int lcd0_d18_mfp_pads[] = { LCD0_D18 };381static unsigned int lcd0_d18_mfp_funcs[] = { S500_MUX_NOR,382 S500_MUX_SENS1,383 S500_MUX_PWM2,384 S500_MUX_PWM4,385 S500_MUX_LCD0 };386/* mfp0_22_20 */387static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV };388static unsigned int rmii_crs_dv_mfp_funcs[] = { S500_MUX_ETH_RMII,389 S500_MUX_ETH_SMII,390 S500_MUX_SPI2,391 S500_MUX_UART4,392 S500_MUX_PWM4 };393/* mfp0_18_16_eth_txd0 */394static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 };395static unsigned int rmii_txd0_mfp_funcs[] = { S500_MUX_ETH_RMII,396 S500_MUX_ETH_SMII,397 S500_MUX_SPI2,398 S500_MUX_UART6,399 S500_MUX_PWM4 };400/* mfp0_18_16_eth_txd1 */401static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 };402static unsigned int rmii_txd1_mfp_funcs[] = { S500_MUX_ETH_RMII,403 S500_MUX_ETH_SMII,404 S500_MUX_SPI2,405 S500_MUX_UART6,406 S500_MUX_PWM5 };407/* mfp0_15_13_rmii_txen */408static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN };409static unsigned int rmii_txen_mfp_funcs[] = { S500_MUX_ETH_RMII,410 S500_MUX_UART2,411 S500_MUX_SPI3,412 S500_MUX_PWM0 };413/* mfp0_15_13_rmii_rxen */414static unsigned int rmii_rxen_mfp_pads[] = { ETH_RXER };415static unsigned int rmii_rxen_mfp_funcs[] = { S500_MUX_ETH_RMII,416 S500_MUX_UART2,417 S500_MUX_SPI3,418 S500_MUX_PWM1 };419/* mfp0_12_11 reserved */420 421/* mfp0_10_8_rmii_rxd1 */422static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 };423static unsigned int rmii_rxd1_mfp_funcs[] = { S500_MUX_ETH_RMII,424 S500_MUX_UART2,425 S500_MUX_SPI3,426 S500_MUX_PWM2,427 S500_MUX_UART5 };428/* mfp0_10_8_rmii_rxd0 */429static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 };430static unsigned int rmii_rxd0_mfp_funcs[] = { S500_MUX_ETH_RMII,431 S500_MUX_UART2,432 S500_MUX_SPI3,433 S500_MUX_PWM3,434 S500_MUX_UART5 };435/* mfp0_7_6 */436static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };437static unsigned int rmii_ref_clk_mfp_funcs[] = { S500_MUX_ETH_RMII,438 S500_MUX_UART4,439 S500_MUX_SPI2,440 S500_MUX_RESERVED,441 S500_MUX_ETH_SMII };442/* mfp0_5 */443static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };444static unsigned int i2s_d0_mfp_funcs[] = { S500_MUX_I2S0,445 S500_MUX_NOR };446/* mfp0_4_3 */447static unsigned int i2s_pcm1_mfp_pads[] = { I2S_LRCLK0, I2S_MCLK0 };448static unsigned int i2s_pcm1_mfp_funcs[] = { S500_MUX_I2S0,449 S500_MUX_NOR,450 S500_MUX_PCM1 };451/* mfp0_2_1_i2s0 */452static unsigned int i2s0_pcm0_mfp_pads[] = { I2S_BCLK0 };453static unsigned int i2s0_pcm0_mfp_funcs[] = { S500_MUX_I2S0,454 S500_MUX_NOR,455 S500_MUX_PCM0 };456/* mfp0_2_1_i2s1 */457static unsigned int i2s1_pcm0_mfp_pads[] = { I2S_BCLK1, I2S_LRCLK1,458 I2S_MCLK1 };459static unsigned int i2s1_pcm0_mfp_funcs[] = { S500_MUX_I2S1,460 S500_MUX_NOR,461 S500_MUX_PCM0 };462/* mfp0_0 */463static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };464static unsigned int i2s_d1_mfp_funcs[] = { S500_MUX_I2S1,465 S500_MUX_NOR };466/* mfp1_31_29_ks_in0 */467static unsigned int ks_in0_mfp_pads[] = { KS_IN0 };468static unsigned int ks_in0_mfp_funcs[] = { S500_MUX_KS,469 S500_MUX_JTAG,470 S500_MUX_NOR,471 S500_MUX_PWM0,472 S500_MUX_PWM4,473 S500_MUX_SENS1,474 S500_MUX_PWM4,475 S500_MUX_P0 };476/* mfp1_31_29_ks_in1 */477static unsigned int ks_in1_mfp_pads[] = { KS_IN1 };478static unsigned int ks_in1_mfp_funcs[] = { S500_MUX_KS,479 S500_MUX_JTAG,480 S500_MUX_NOR,481 S500_MUX_PWM1,482 S500_MUX_PWM5,483 S500_MUX_SENS1,484 S500_MUX_PWM1,485 S500_MUX_USB30 };486/* mfp1_31_29_ks_in2 */487static unsigned int ks_in2_mfp_pads[] = { KS_IN2 };488static unsigned int ks_in2_mfp_funcs[] = { S500_MUX_KS,489 S500_MUX_JTAG,490 S500_MUX_NOR,491 S500_MUX_PWM0,492 S500_MUX_PWM0,493 S500_MUX_SENS1,494 S500_MUX_PWM0,495 S500_MUX_P0 };496/* mfp1_28_26_ks_in3 */497static unsigned int ks_in3_mfp_pads[] = { KS_IN3 };498static unsigned int ks_in3_mfp_funcs[] = { S500_MUX_KS,499 S500_MUX_JTAG,500 S500_MUX_NOR,501 S500_MUX_PWM1,502 S500_MUX_RESERVED,503 S500_MUX_SENS1 };504/* mfp1_28_26_ks_out0 */505static unsigned int ks_out0_mfp_pads[] = { KS_OUT0 };506static unsigned int ks_out0_mfp_funcs[] = { S500_MUX_KS,507 S500_MUX_UART5,508 S500_MUX_NOR,509 S500_MUX_PWM2,510 S500_MUX_RESERVED,511 S500_MUX_SENS1,512 S500_MUX_SD0 };513/* mfp1_28_26_ks_out1 */514static unsigned int ks_out1_mfp_pads[] = { KS_OUT1 };515static unsigned int ks_out1_mfp_funcs[] = { S500_MUX_KS,516 S500_MUX_JTAG,517 S500_MUX_NOR,518 S500_MUX_PWM3,519 S500_MUX_RESERVED,520 S500_MUX_SENS1,521 S500_MUX_SD0 };522/* mfp1_25_23 */523static unsigned int ks_out2_mfp_pads[] = { KS_OUT2 };524static unsigned int ks_out2_mfp_funcs[] = { S500_MUX_SD0,525 S500_MUX_KS,526 S500_MUX_NOR,527 S500_MUX_PWM2,528 S500_MUX_UART5,529 S500_MUX_SENS1 };530/* mfp1_22_21 */531static unsigned int lvds_o_pn_mfp_pads[] = { LVDS_OEP, LVDS_OEN,532 LVDS_ODP, LVDS_ODN,533 LVDS_OCP, LVDS_OCN,534 LVDS_OBP, LVDS_OBN,535 LVDS_OAP, LVDS_OAN };536static unsigned int lvds_o_pn_mfp_funcs[] = { S500_MUX_LVDS,537 S500_MUX_TS,538 S500_MUX_LCD0 };539/* mfp1_20_19 */540static unsigned int dsi_dn0_mfp_pads[] = { DSI_DN0 };541static unsigned int dsi_dn0_mfp_funcs[] = { S500_MUX_DSI,542 S500_MUX_UART2,543 S500_MUX_SPI0 };544/* mfp1_18_17 */545static unsigned int dsi_dp2_mfp_pads[] = { DSI_DP2 };546static unsigned int dsi_dp2_mfp_funcs[] = { S500_MUX_DSI,547 S500_MUX_UART2,548 S500_MUX_SPI0,549 S500_MUX_SD1 };550/* mfp1_16_14 */551static unsigned int lcd0_d17_mfp_pads[] = { LCD0_D17 };552static unsigned int lcd0_d17_mfp_funcs[] = { S500_MUX_NOR,553 S500_MUX_SD0,554 S500_MUX_SD1,555 S500_MUX_PWM3,556 S500_MUX_LCD0 };557/* mfp1_13_12 */558static unsigned int dsi_dp3_mfp_pads[] = { DSI_DP3 };559static unsigned int dsi_dp3_mfp_funcs[] = { S500_MUX_DSI,560 S500_MUX_SD0,561 S500_MUX_SD1,562 S500_MUX_LCD0 };563/* mfp1_11_10 */564static unsigned int dsi_dn3_mfp_pads[] = { DSI_DN3 };565static unsigned int dsi_dn3_mfp_funcs[] = { S500_MUX_DSI,566 S500_MUX_RESERVED,567 S500_MUX_SD1,568 S500_MUX_LCD0 };569/* mfp1_9_7 */570static unsigned int dsi_dp0_mfp_pads[] = { DSI_DP0 };571static unsigned int dsi_dp0_mfp_funcs[] = { S500_MUX_DSI,572 S500_MUX_RESERVED,573 S500_MUX_SD0,574 S500_MUX_UART2,575 S500_MUX_SPI0 };576/* mfp1_6_5 */577static unsigned int lvds_ee_pn_mfp_pads[] = { LVDS_EEP, LVDS_EEN };578static unsigned int lvds_ee_pn_mfp_funcs[] = { S500_MUX_LVDS,579 S500_MUX_NOR,580 S500_MUX_TS,581 S500_MUX_LCD0 };582/* mfp1_4_3 */583static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SCLK, SPI0_MOSI };584static unsigned int spi0_i2c_pcm_mfp_funcs[] = { S500_MUX_SPI0,585 S500_MUX_NOR,586 S500_MUX_I2C3,587 S500_MUX_PCM0 };588/* mfp1_2_0 */589static unsigned int spi0_i2s_pcm_mfp_pads[] = { SPI0_SS, SPI0_MISO };590static unsigned int spi0_i2s_pcm_mfp_funcs[] = { S500_MUX_SPI0,591 S500_MUX_NOR,592 S500_MUX_I2S1,593 S500_MUX_PCM1,594 S500_MUX_PCM0 };595/* mfp2_31 reserved */596/* mfp2_30_29 */597static unsigned int dsi_dnp1_cp_mfp_pads[] = { DSI_DP1, DSI_CP, DSI_CN };598static unsigned int dsi_dnp1_cp_mfp_funcs[] = { S500_MUX_DSI,599 S500_MUX_SD1,600 S500_MUX_LCD0 };601/* mfp2_28_27 */602static unsigned int lvds_e_pn_mfp_pads[] = { LVDS_EDP, LVDS_EDN,603 LVDS_ECP, LVDS_ECN,604 LVDS_EBP, LVDS_EBN,605 LVDS_EAP, LVDS_EAN };606static unsigned int lvds_e_pn_mfp_funcs[] = { S500_MUX_LVDS,607 S500_MUX_NOR,608 S500_MUX_LCD0 };609/* mfp2_26_24 */610static unsigned int dsi_dn2_mfp_pads[] = { DSI_DN2 };611static unsigned int dsi_dn2_mfp_funcs[] = { S500_MUX_DSI,612 S500_MUX_RESERVED,613 S500_MUX_SD1,614 S500_MUX_UART2,615 S500_MUX_SPI0 };616/* mfp2_23 */617static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };618static unsigned int uart2_rtsb_mfp_funcs[] = { S500_MUX_UART2,619 S500_MUX_UART0 };620/* mfp2_22 */621static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };622static unsigned int uart2_ctsb_mfp_funcs[] = { S500_MUX_UART2,623 S500_MUX_UART0 };624/* mfp2_21 */625static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };626static unsigned int uart3_rtsb_mfp_funcs[] = { S500_MUX_UART3,627 S500_MUX_UART5 };628/* mfp2_20 */629static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };630static unsigned int uart3_ctsb_mfp_funcs[] = { S500_MUX_UART3,631 S500_MUX_UART5 };632/* mfp2_19_17 */633static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };634static unsigned int sd0_d0_mfp_funcs[] = { S500_MUX_SD0,635 S500_MUX_NOR,636 S500_MUX_RESERVED,637 S500_MUX_JTAG,638 S500_MUX_UART2,639 S500_MUX_UART5 };640/* mfp2_16_14 */641static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };642static unsigned int sd0_d1_mfp_funcs[] = { S500_MUX_SD0,643 S500_MUX_NOR,644 S500_MUX_RESERVED,645 S500_MUX_RESERVED,646 S500_MUX_UART2,647 S500_MUX_UART5 };648/* mfp2_13_11 */649static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2, SD0_D3 };650static unsigned int sd0_d2_d3_mfp_funcs[] = { S500_MUX_SD0,651 S500_MUX_NOR,652 S500_MUX_RESERVED,653 S500_MUX_JTAG,654 S500_MUX_UART2,655 S500_MUX_UART1 };656/* mfp2_10_9 */657static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1,658 SD1_D2, SD1_D3 };659static unsigned int sd1_d0_d3_mfp_funcs[] = { S500_MUX_SD0,660 S500_MUX_NOR,661 S500_MUX_RESERVED,662 S500_MUX_SD1 };663/* mfp2_8_7 */664static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };665static unsigned int sd0_cmd_mfp_funcs[] = { S500_MUX_SD0,666 S500_MUX_NOR,667 S500_MUX_RESERVED,668 S500_MUX_JTAG };669/* mfp2_6_5 */670static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };671static unsigned int sd0_clk_mfp_funcs[] = { S500_MUX_SD0,672 S500_MUX_RESERVED,673 S500_MUX_JTAG };674/* mfp2_4_3 */675static unsigned int sd1_cmd_mfp_pads[] = { SD1_CMD };676static unsigned int sd1_cmd_mfp_funcs[] = { S500_MUX_SD1,677 S500_MUX_NOR };678/* mfp2_2_0 */679static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };680static unsigned int uart0_rx_mfp_funcs[] = { S500_MUX_UART0,681 S500_MUX_UART2,682 S500_MUX_SPI1,683 S500_MUX_I2C0,684 S500_MUX_PCM1,685 S500_MUX_I2S1 };686/* mfp3_31 reserved */687/* mfp3_30 */688static unsigned int clko_25m_mfp_pads[] = { CLKO_25M };689static unsigned int clko_25m_mfp_funcs[] = { S500_MUX_RESERVED,690 S500_MUX_CLKO_25M };691/* mfp3_29_28 */692static unsigned int csi_cn_cp_mfp_pads[] = { CSI_CN, CSI_CP };693static unsigned int csi_cn_cp_mfp_funcs[] = { S500_MUX_MIPI_CSI,694 S500_MUX_SENS0 };695/* mfp3_27_24 reserved */696/* mfp3_23_22 */697static unsigned int sens0_ckout_mfp_pads[] = { SENSOR0_CKOUT };698static unsigned int sens0_ckout_mfp_funcs[] = { S500_MUX_SENS0,699 S500_MUX_NOR,700 S500_MUX_SENS1,701 S500_MUX_PWM1 };702/* mfp3_21_19 */703static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };704static unsigned int uart0_tx_mfp_funcs[] = { S500_MUX_UART0,705 S500_MUX_UART2,706 S500_MUX_SPI1,707 S500_MUX_I2C0,708 S500_MUX_SPDIF,709 S500_MUX_PCM1,710 S500_MUX_I2S1 };711/* mfp3_18_16 */712static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK,713 I2C0_SDATA };714static unsigned int i2c0_mfp_funcs[] = { S500_MUX_I2C0,715 S500_MUX_UART2,716 S500_MUX_I2C1,717 S500_MUX_UART1,718 S500_MUX_SPI1 };719/* mfp3_15_14 */720static unsigned int csi_dn_dp_mfp_pads[] = { CSI_DN0, CSI_DN1,721 CSI_DN2, CSI_DN3,722 CSI_DP0, CSI_DP1,723 CSI_DP2, CSI_DP3 };724static unsigned int csi_dn_dp_mfp_funcs[] = { S500_MUX_MIPI_CSI,725 S500_MUX_SENS0 };726/* mfp3_13_12 */727static unsigned int sen0_pclk_mfp_pads[] = { SENSOR0_PCLK };728static unsigned int sen0_pclk_mfp_funcs[] = { S500_MUX_SENS0,729 S500_MUX_NOR,730 S500_MUX_PWM0 };731/* mfp3_11_10 */732static unsigned int pcm1_in_mfp_pads[] = { PCM1_IN };733static unsigned int pcm1_in_mfp_funcs[] = { S500_MUX_PCM1,734 S500_MUX_SENS1,735 S500_MUX_UART4,736 S500_MUX_PWM4 };737/* mfp3_9_8 */738static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };739static unsigned int pcm1_clk_mfp_funcs[] = { S500_MUX_PCM1,740 S500_MUX_SENS1,741 S500_MUX_UART4,742 S500_MUX_PWM5 };743/* mfp3_7_6 */744static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };745static unsigned int pcm1_sync_mfp_funcs[] = { S500_MUX_PCM1,746 S500_MUX_SENS1,747 S500_MUX_UART6,748 S500_MUX_I2C3 };749/* mfp3_5_4 */750static unsigned int pcm1_out_mfp_pads[] = { PCM1_OUT };751static unsigned int pcm1_out_mfp_funcs[] = { S500_MUX_PCM1,752 S500_MUX_SENS1,753 S500_MUX_UART6,754 S500_MUX_I2C3 };755/* mfp3_3 */756static unsigned int dnand_data_wr_mfp_pads[] = { DNAND_D0, DNAND_D1,757 DNAND_D2, DNAND_D3,758 DNAND_D4, DNAND_D5,759 DNAND_D6, DNAND_D7,760 DNAND_RDB, DNAND_RDBN };761static unsigned int dnand_data_wr_mfp_funcs[] = { S500_MUX_NAND,762 S500_MUX_SD2 };763/* mfp3_2 */764static unsigned int dnand_acle_ce0_mfp_pads[] = { DNAND_ALE,765 DNAND_CLE,766 DNAND_CEB0,767 DNAND_CEB1 };768static unsigned int dnand_acle_ce0_mfp_funcs[] = { S500_MUX_NAND,769 S500_MUX_SPI2 };770/* mfp3_1_0_nand_ceb2 */771static unsigned int nand_ceb2_mfp_pads[] = { DNAND_CEB2 };772static unsigned int nand_ceb2_mfp_funcs[] = { S500_MUX_NAND,773 S500_MUX_PWM5 };774/* mfp3_1_0_nand_ceb3 */775static unsigned int nand_ceb3_mfp_pads[] = { DNAND_CEB3 };776static unsigned int nand_ceb3_mfp_funcs[] = { S500_MUX_NAND,777 S500_MUX_PWM4 };778 779/* PADDRV group data */780/* paddrv0_29_28 */781static unsigned int sirq_drv_pads[] = { SIRQ0, SIRQ1, SIRQ2 };782/* paddrv0_23_22 */783static unsigned int rmii_txd01_txen_drv_pads[] = { ETH_TXD0, ETH_TXD1,784 ETH_TXEN };785/* paddrv0_21_20 */786static unsigned int rmii_rxer_drv_pads[] = { ETH_RXER };787/* paddrv0_19_18 */788static unsigned int rmii_crs_drv_pads[] = { ETH_CRS_DV };789/* paddrv0_17_16 */790static unsigned int rmii_rxd10_drv_pads[] = { ETH_RXD0, ETH_RXD1 };791/* paddrv0_15_14 */792static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK };793/* paddrv0_13_12 */794static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO };795/* paddrv0_11_10 */796static unsigned int i2s_d0_drv_pads[] = { I2S_D0 };797/* paddrv0_9_8 */798static unsigned int i2s_bclk0_drv_pads[] = { I2S_BCLK0 };799/* paddrv0_7_6 */800static unsigned int i2s3_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0,801 I2S_D1 };802/* paddrv0_5_4 */803static unsigned int i2s13_drv_pads[] = { I2S_BCLK1, I2S_LRCLK1,804 I2S_MCLK1 };805/* paddrv0_3_2 */806static unsigned int pcm1_drv_pads[] = { PCM1_IN, PCM1_CLK,807 PCM1_SYNC, PCM1_OUT };808/* paddrv0_1_0 */809static unsigned int ks_in_drv_pads[] = { KS_IN0, KS_IN1,810 KS_IN2, KS_IN3 };811/* paddrv1_31_30 */812static unsigned int ks_out_drv_pads[] = { KS_OUT0, KS_OUT1, KS_OUT2 };813/* paddrv1_29_28 */814static unsigned int lvds_all_drv_pads[] = { LVDS_OEP, LVDS_OEN,815 LVDS_ODP, LVDS_ODN,816 LVDS_OCP, LVDS_OCN,817 LVDS_OBP, LVDS_OBN,818 LVDS_OAP, LVDS_OAN,819 LVDS_EEP, LVDS_EEN,820 LVDS_EDP, LVDS_EDN,821 LVDS_ECP, LVDS_ECN,822 LVDS_EBP, LVDS_EBN,823 LVDS_EAP, LVDS_EAN };824/* paddrv1_27_26 */825static unsigned int lcd_dsi_drv_pads[] = { DSI_DP3, DSI_DN3, DSI_DP1,826 DSI_DN1, DSI_CP, DSI_CN };827/* paddrv1_25_24 */828static unsigned int dsi_drv_pads[] = { DSI_DP0, DSI_DN0,829 DSI_DP2, DSI_DN2 };830/* paddrv1_23_22 */831static unsigned int sd0_d0_d3_drv_pads[] = { SD0_D0, SD0_D1,832 SD0_D2, SD0_D3 };833/* paddrv1_21_20 */834static unsigned int sd1_d0_d3_drv_pads[] = { SD1_D0, SD1_D1,835 SD1_D2, SD1_D3 };836/* paddrv1_19_18 */837static unsigned int sd0_cmd_drv_pads[] = { SD0_CMD };838/* paddrv1_17_16 */839static unsigned int sd0_clk_drv_pads[] = { SD0_CLK };840/* paddrv1_15_14 */841static unsigned int sd1_cmd_drv_pads[] = { SD1_CMD };842/* paddrv1_13_12 */843static unsigned int sd1_clk_drv_pads[] = { SD1_CLK };844/* paddrv1_11_10 */845static unsigned int spi0_all_drv_pads[] = { SPI0_SCLK, SPI0_SS,846 SPI0_MISO, SPI0_MOSI };847/* paddrv2_31_30 */848static unsigned int uart0_rx_drv_pads[] = { UART0_RX };849/* paddrv2_29_28 */850static unsigned int uart0_tx_drv_pads[] = { UART0_TX };851/* paddrv2_27_26 */852static unsigned int uart2_all_drv_pads[] = { UART2_RX, UART2_TX,853 UART2_RTSB, UART2_CTSB };854/* paddrv2_24_23 */855static unsigned int i2c0_all_drv_pads[] = { I2C0_SCLK, I2C0_SDATA };856/* paddrv2_22_21 */857static unsigned int i2c12_all_drv_pads[] = { I2C1_SCLK, I2C1_SDATA,858 I2C2_SCLK, I2C2_SDATA };859/* paddrv2_19_18 */860static unsigned int sens0_pclk_drv_pads[] = { SENSOR0_PCLK };861/* paddrv2_13_12 */862static unsigned int sens0_ckout_drv_pads[] = { SENSOR0_CKOUT };863/* paddrv2_3_2 */864static unsigned int uart3_all_drv_pads[] = { UART3_RX, UART3_TX,865 UART3_RTSB, UART3_CTSB };866 867/* Pinctrl groups */868static const struct owl_pingroup s500_groups[] = {869 MUX_PG(lcd0_d18_mfp, 0, 23, 3),870 MUX_PG(rmii_crs_dv_mfp, 0, 20, 3),871 MUX_PG(rmii_txd0_mfp, 0, 16, 3),872 MUX_PG(rmii_txd1_mfp, 0, 16, 3),873 MUX_PG(rmii_txen_mfp, 0, 13, 3),874 MUX_PG(rmii_rxen_mfp, 0, 13, 3),875 MUX_PG(rmii_rxd1_mfp, 0, 8, 3),876 MUX_PG(rmii_rxd0_mfp, 0, 8, 3),877 MUX_PG(rmii_ref_clk_mfp, 0, 6, 2),878 MUX_PG(i2s_d0_mfp, 0, 5, 1),879 MUX_PG(i2s_pcm1_mfp, 0, 3, 2),880 MUX_PG(i2s0_pcm0_mfp, 0, 1, 2),881 MUX_PG(i2s1_pcm0_mfp, 0, 1, 2),882 MUX_PG(i2s_d1_mfp, 0, 0, 1),883 MUX_PG(ks_in2_mfp, 1, 29, 3),884 MUX_PG(ks_in1_mfp, 1, 29, 3),885 MUX_PG(ks_in0_mfp, 1, 29, 3),886 MUX_PG(ks_in3_mfp, 1, 26, 3),887 MUX_PG(ks_out0_mfp, 1, 26, 3),888 MUX_PG(ks_out1_mfp, 1, 26, 3),889 MUX_PG(ks_out2_mfp, 1, 23, 3),890 MUX_PG(lvds_o_pn_mfp, 1, 21, 2),891 MUX_PG(dsi_dn0_mfp, 1, 19, 2),892 MUX_PG(dsi_dp2_mfp, 1, 17, 2),893 MUX_PG(lcd0_d17_mfp, 1, 14, 3),894 MUX_PG(dsi_dp3_mfp, 1, 12, 2),895 MUX_PG(dsi_dn3_mfp, 1, 10, 2),896 MUX_PG(dsi_dp0_mfp, 1, 7, 3),897 MUX_PG(lvds_ee_pn_mfp, 1, 5, 2),898 MUX_PG(spi0_i2c_pcm_mfp, 1, 3, 2),899 MUX_PG(spi0_i2s_pcm_mfp, 1, 0, 3),900 MUX_PG(dsi_dnp1_cp_mfp, 2, 29, 2),901 MUX_PG(lvds_e_pn_mfp, 2, 27, 2),902 MUX_PG(dsi_dn2_mfp, 2, 24, 3),903 MUX_PG(uart2_rtsb_mfp, 2, 23, 1),904 MUX_PG(uart2_ctsb_mfp, 2, 22, 1),905 MUX_PG(uart3_rtsb_mfp, 2, 21, 1),906 MUX_PG(uart3_ctsb_mfp, 2, 20, 1),907 MUX_PG(sd0_d0_mfp, 2, 17, 3),908 MUX_PG(sd0_d1_mfp, 2, 14, 3),909 MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),910 MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),911 MUX_PG(sd0_cmd_mfp, 2, 7, 2),912 MUX_PG(sd0_clk_mfp, 2, 5, 2),913 MUX_PG(sd1_cmd_mfp, 2, 3, 2),914 MUX_PG(uart0_rx_mfp, 2, 0, 3),915 MUX_PG(clko_25m_mfp, 3, 30, 1),916 MUX_PG(csi_cn_cp_mfp, 3, 28, 2),917 MUX_PG(sens0_ckout_mfp, 3, 22, 2),918 MUX_PG(uart0_tx_mfp, 3, 19, 3),919 MUX_PG(i2c0_mfp, 3, 16, 3),920 MUX_PG(csi_dn_dp_mfp, 3, 14, 2),921 MUX_PG(sen0_pclk_mfp, 3, 12, 2),922 MUX_PG(pcm1_in_mfp, 3, 10, 2),923 MUX_PG(pcm1_clk_mfp, 3, 8, 2),924 MUX_PG(pcm1_sync_mfp, 3, 6, 2),925 MUX_PG(pcm1_out_mfp, 3, 4, 2),926 MUX_PG(dnand_data_wr_mfp, 3, 3, 1),927 MUX_PG(dnand_acle_ce0_mfp, 3, 2, 1),928 MUX_PG(nand_ceb2_mfp, 3, 0, 2),929 MUX_PG(nand_ceb3_mfp, 3, 0, 2),930 931 DRV_PG(sirq_drv, 0, 28, 2),932 DRV_PG(rmii_txd01_txen_drv, 0, 22, 2),933 DRV_PG(rmii_rxer_drv, 0, 20, 2),934 DRV_PG(rmii_crs_drv, 0, 18, 2),935 DRV_PG(rmii_rxd10_drv, 0, 16, 2),936 DRV_PG(rmii_ref_clk_drv, 0, 14, 2),937 DRV_PG(smi_mdc_mdio_drv, 0, 12, 2),938 DRV_PG(i2s_d0_drv, 0, 10, 2),939 DRV_PG(i2s_bclk0_drv, 0, 8, 2),940 DRV_PG(i2s3_drv, 0, 6, 2),941 DRV_PG(i2s13_drv, 0, 4, 2),942 DRV_PG(pcm1_drv, 0, 2, 2),943 DRV_PG(ks_in_drv, 0, 0, 2),944 DRV_PG(ks_out_drv, 1, 30, 2),945 DRV_PG(lvds_all_drv, 1, 28, 2),946 DRV_PG(lcd_dsi_drv, 1, 26, 2),947 DRV_PG(dsi_drv, 1, 24, 2),948 DRV_PG(sd0_d0_d3_drv, 1, 22, 2),949 DRV_PG(sd1_d0_d3_drv, 1, 20, 2),950 DRV_PG(sd0_cmd_drv, 1, 18, 2),951 DRV_PG(sd0_clk_drv, 1, 16, 2),952 DRV_PG(sd1_cmd_drv, 1, 14, 2),953 DRV_PG(sd1_clk_drv, 1, 12, 2),954 DRV_PG(spi0_all_drv, 1, 10, 2),955 DRV_PG(uart0_rx_drv, 2, 30, 2),956 DRV_PG(uart0_tx_drv, 2, 28, 2),957 DRV_PG(uart2_all_drv, 2, 26, 2),958 DRV_PG(i2c0_all_drv, 2, 23, 2),959 DRV_PG(i2c12_all_drv, 2, 21, 2),960 DRV_PG(sens0_pclk_drv, 2, 18, 2),961 DRV_PG(sens0_ckout_drv, 2, 12, 2),962 DRV_PG(uart3_all_drv, 2, 2, 2),963};964 965static const char * const nor_groups[] = {966 "lcd0_d18_mfp",967 "i2s_d0_mfp",968 "i2s0_pcm0_mfp",969 "i2s1_pcm0_mfp",970 "i2s_d1_mfp",971 "ks_in2_mfp",972 "ks_in1_mfp",973 "ks_in0_mfp",974 "ks_in3_mfp",975 "ks_out0_mfp",976 "ks_out1_mfp",977 "ks_out2_mfp",978 "lcd0_d17_mfp",979 "lvds_ee_pn_mfp",980 "spi0_i2c_pcm_mfp",981 "spi0_i2s_pcm_mfp",982 "lvds_e_pn_mfp",983 "sd0_d0_mfp",984 "sd0_d1_mfp",985 "sd0_d2_d3_mfp",986 "sd1_d0_d3_mfp",987 "sd0_cmd_mfp",988 "sd1_cmd_mfp",989 "sens0_ckout_mfp",990 "sen0_pclk_mfp",991};992 993static const char * const eth_rmii_groups[] = {994 "rmii_crs_dv_mfp",995 "rmii_txd0_mfp",996 "rmii_txd1_mfp",997 "rmii_txen_mfp",998 "rmii_rxen_mfp",999 "rmii_rxd1_mfp",1000 "rmii_rxd0_mfp",1001 "rmii_ref_clk_mfp",1002};1003 1004static const char * const eth_smii_groups[] = {1005 "rmii_crs_dv_mfp",1006 "rmii_txd0_mfp",1007 "rmii_txd1_mfp",1008 "rmii_ref_clk_mfp",1009};1010 1011static const char * const spi0_groups[] = {1012 "dsi_dn0_mfp",1013 "dsi_dp2_mfp",1014 "dsi_dp0_mfp",1015 "spi0_i2c_pcm_mfp",1016 "spi0_i2s_pcm_mfp",1017 "dsi_dn2_mfp",1018};1019 1020static const char * const spi1_groups[] = {1021 "uart0_rx_mfp",1022 "uart0_tx_mfp",1023 "i2c0_mfp",1024};1025 1026static const char * const spi2_groups[] = {1027 "rmii_crs_dv_mfp",1028 "rmii_txd0_mfp",1029 "rmii_txd1_mfp",1030 "rmii_ref_clk_mfp",1031 "dnand_acle_ce0_mfp",1032};1033 1034static const char * const spi3_groups[] = {1035 "rmii_txen_mfp",1036 "rmii_rxen_mfp",1037 "rmii_rxd1_mfp",1038 "rmii_rxd0_mfp",1039};1040 1041static const char * const sens0_groups[] = {1042 "csi_cn_cp_mfp",1043 "sens0_ckout_mfp",1044 "csi_dn_dp_mfp",1045 "sen0_pclk_mfp",1046};1047 1048static const char * const sens1_groups[] = {1049 "lcd0_d18_mfp",1050 "ks_in2_mfp",1051 "ks_in1_mfp",1052 "ks_in0_mfp",1053 "ks_in3_mfp",1054 "ks_out0_mfp",1055 "ks_out1_mfp",1056 "ks_out2_mfp",1057 "sens0_ckout_mfp",1058 "pcm1_in_mfp",1059 "pcm1_clk_mfp",1060 "pcm1_sync_mfp",1061 "pcm1_out_mfp",1062};1063 1064static const char * const uart0_groups[] = {1065 "uart2_rtsb_mfp",1066 "uart2_ctsb_mfp",1067 "uart0_rx_mfp",1068 "uart0_tx_mfp",1069};1070 1071static const char * const uart1_groups[] = {1072 "sd0_d2_d3_mfp",1073 "i2c0_mfp",1074};1075 1076static const char * const uart2_groups[] = {1077 "rmii_txen_mfp",1078 "rmii_rxen_mfp",1079 "rmii_rxd1_mfp",1080 "rmii_rxd0_mfp",1081 "dsi_dn0_mfp",1082 "dsi_dp2_mfp",1083 "dsi_dp0_mfp",1084 "dsi_dn2_mfp",1085 "uart2_rtsb_mfp",1086 "uart2_ctsb_mfp",1087 "sd0_d0_mfp",1088 "sd0_d1_mfp",1089 "sd0_d2_d3_mfp",1090 "uart0_rx_mfp",1091 "uart0_tx_mfp",1092 "i2c0_mfp",1093};1094 1095static const char * const uart3_groups[] = {1096 "uart3_rtsb_mfp",1097 "uart3_ctsb_mfp",1098};1099 1100static const char * const uart4_groups[] = {1101 "rmii_crs_dv_mfp",1102 "rmii_ref_clk_mfp",1103 "pcm1_in_mfp",1104 "pcm1_clk_mfp",1105};1106 1107static const char * const uart5_groups[] = {1108 "rmii_rxd1_mfp",1109 "rmii_rxd0_mfp",1110 "ks_out0_mfp",1111 "ks_out2_mfp",1112 "uart3_rtsb_mfp",1113 "uart3_ctsb_mfp",1114 "sd0_d0_mfp",1115 "sd0_d1_mfp",1116};1117 1118static const char * const uart6_groups[] = {1119 "rmii_txd0_mfp",1120 "rmii_txd1_mfp",1121 "pcm1_sync_mfp",1122 "pcm1_out_mfp",1123};1124 1125static const char * const i2s0_groups[] = {1126 "i2s_d0_mfp",1127 "i2s_pcm1_mfp",1128 "i2s0_pcm0_mfp",1129};1130 1131static const char * const i2s1_groups[] = {1132 "i2s1_pcm0_mfp",1133 "i2s_d1_mfp",1134 "spi0_i2s_pcm_mfp",1135 "uart0_rx_mfp",1136 "uart0_tx_mfp",1137};1138 1139static const char * const pcm1_groups[] = {1140 "i2s_pcm1_mfp",1141 "spi0_i2s_pcm_mfp",1142 "uart0_rx_mfp",1143 "uart0_tx_mfp",1144 "pcm1_in_mfp",1145 "pcm1_clk_mfp",1146 "pcm1_sync_mfp",1147 "pcm1_out_mfp",1148};1149 1150static const char * const pcm0_groups[] = {1151 "i2s0_pcm0_mfp",1152 "i2s1_pcm0_mfp",1153 "spi0_i2c_pcm_mfp",1154 "spi0_i2s_pcm_mfp",1155};1156 1157static const char * const ks_groups[] = {1158 "ks_in2_mfp",1159 "ks_in1_mfp",1160 "ks_in0_mfp",1161 "ks_in3_mfp",1162 "ks_out0_mfp",1163 "ks_out1_mfp",1164 "ks_out2_mfp",1165};1166 1167static const char * const jtag_groups[] = {1168 "ks_in2_mfp",1169 "ks_in1_mfp",1170 "ks_in0_mfp",1171 "ks_in3_mfp",1172 "ks_out1_mfp",1173 "sd0_d0_mfp",1174 "sd0_d2_d3_mfp",1175 "sd0_cmd_mfp",1176 "sd0_clk_mfp",1177};1178 1179static const char * const pwm0_groups[] = {1180 "ks_in2_mfp",1181 "ks_in0_mfp",1182 "rmii_txen_mfp",1183 "sen0_pclk_mfp",1184};1185 1186static const char * const pwm1_groups[] = {1187 "rmii_rxen_mfp",1188 "ks_in1_mfp",1189 "ks_in3_mfp",1190 "sens0_ckout_mfp",1191};1192 1193static const char * const pwm2_groups[] = {1194 "lcd0_d18_mfp",1195 "rmii_rxd1_mfp",1196 "ks_out0_mfp",1197 "ks_out2_mfp",1198};1199 1200static const char * const pwm3_groups[] = {1201 "rmii_rxd0_mfp",1202 "ks_out1_mfp",1203 "lcd0_d17_mfp",1204};1205 1206static const char * const pwm4_groups[] = {1207 "lcd0_d18_mfp",1208 "rmii_crs_dv_mfp",1209 "rmii_txd0_mfp",1210 "ks_in0_mfp",1211 "pcm1_in_mfp",1212 "nand_ceb3_mfp",1213};1214 1215static const char * const pwm5_groups[] = {1216 "rmii_txd1_mfp",1217 "ks_in1_mfp",1218 "pcm1_clk_mfp",1219 "nand_ceb2_mfp",1220};1221 1222static const char * const p0_groups[] = {1223 "ks_in2_mfp",1224 "ks_in0_mfp",1225};1226 1227static const char * const sd0_groups[] = {1228 "ks_out0_mfp",1229 "ks_out1_mfp",1230 "ks_out2_mfp",1231 "lcd0_d17_mfp",1232 "dsi_dp3_mfp",1233 "dsi_dp0_mfp",1234 "sd0_d0_mfp",1235 "sd0_d1_mfp",1236 "sd0_d2_d3_mfp",1237 "sd1_d0_d3_mfp",1238 "sd0_cmd_mfp",1239 "sd0_clk_mfp",1240};1241 1242static const char * const sd1_groups[] = {1243 "dsi_dp2_mfp",1244 "lcd0_d17_mfp",1245 "dsi_dp3_mfp",1246 "dsi_dn3_mfp",1247 "dsi_dnp1_cp_mfp",1248 "dsi_dn2_mfp",1249 "sd1_d0_d3_mfp",1250 "sd1_cmd_mfp",1251};1252 1253static const char * const sd2_groups[] = {1254 "dnand_data_wr_mfp",1255};1256 1257static const char * const i2c0_groups[] = {1258 "uart0_rx_mfp",1259 "uart0_tx_mfp",1260 "i2c0_mfp",1261};1262 1263static const char * const i2c1_groups[] = {1264 "i2c0_mfp",1265};1266 1267static const char * const i2c3_groups[] = {1268 "spi0_i2c_pcm_mfp",1269 "pcm1_sync_mfp",1270 "pcm1_out_mfp",1271};1272 1273static const char * const lvds_groups[] = {1274 "lvds_o_pn_mfp",1275 "lvds_ee_pn_mfp",1276 "lvds_e_pn_mfp",1277};1278 1279static const char * const ts_groups[] = {1280 "lvds_o_pn_mfp",1281 "lvds_ee_pn_mfp",1282};1283 1284static const char * const lcd0_groups[] = {1285 "lcd0_d18_mfp",1286 "lcd0_d17_mfp",1287 "lvds_o_pn_mfp",1288 "dsi_dp3_mfp",1289 "dsi_dn3_mfp",1290 "lvds_ee_pn_mfp",1291 "dsi_dnp1_cp_mfp",1292 "lvds_e_pn_mfp",1293};1294 1295static const char * const usb30_groups[] = {1296 "ks_in1_mfp",1297};1298 1299static const char * const clko_25m_groups[] = {1300 "clko_25m_mfp",1301};1302 1303static const char * const mipi_csi_groups[] = {1304 "csi_cn_cp_mfp",1305 "csi_dn_dp_mfp",1306};1307 1308static const char * const dsi_groups[] = {1309 "dsi_dn0_mfp",1310 "dsi_dp2_mfp",1311 "dsi_dp3_mfp",1312 "dsi_dn3_mfp",1313 "dsi_dp0_mfp",1314 "dsi_dnp1_cp_mfp",1315 "dsi_dn2_mfp",1316};1317 1318static const char * const nand_groups[] = {1319 "dnand_data_wr_mfp",1320 "dnand_acle_ce0_mfp",1321 "nand_ceb2_mfp",1322 "nand_ceb3_mfp",1323};1324 1325static const char * const spdif_groups[] = {1326 "uart0_tx_mfp",1327};1328 1329static const struct owl_pinmux_func s500_functions[] = {1330 [S500_MUX_NOR] = FUNCTION(nor),1331 [S500_MUX_ETH_RMII] = FUNCTION(eth_rmii),1332 [S500_MUX_ETH_SMII] = FUNCTION(eth_smii),1333 [S500_MUX_SPI0] = FUNCTION(spi0),1334 [S500_MUX_SPI1] = FUNCTION(spi1),1335 [S500_MUX_SPI2] = FUNCTION(spi2),1336 [S500_MUX_SPI3] = FUNCTION(spi3),1337 [S500_MUX_SENS0] = FUNCTION(sens0),1338 [S500_MUX_SENS1] = FUNCTION(sens1),1339 [S500_MUX_UART0] = FUNCTION(uart0),1340 [S500_MUX_UART1] = FUNCTION(uart1),1341 [S500_MUX_UART2] = FUNCTION(uart2),1342 [S500_MUX_UART3] = FUNCTION(uart3),1343 [S500_MUX_UART4] = FUNCTION(uart4),1344 [S500_MUX_UART5] = FUNCTION(uart5),1345 [S500_MUX_UART6] = FUNCTION(uart6),1346 [S500_MUX_I2S0] = FUNCTION(i2s0),1347 [S500_MUX_I2S1] = FUNCTION(i2s1),1348 [S500_MUX_PCM1] = FUNCTION(pcm1),1349 [S500_MUX_PCM0] = FUNCTION(pcm0),1350 [S500_MUX_KS] = FUNCTION(ks),1351 [S500_MUX_JTAG] = FUNCTION(jtag),1352 [S500_MUX_PWM0] = FUNCTION(pwm0),1353 [S500_MUX_PWM1] = FUNCTION(pwm1),1354 [S500_MUX_PWM2] = FUNCTION(pwm2),1355 [S500_MUX_PWM3] = FUNCTION(pwm3),1356 [S500_MUX_PWM4] = FUNCTION(pwm4),1357 [S500_MUX_PWM5] = FUNCTION(pwm5),1358 [S500_MUX_P0] = FUNCTION(p0),1359 [S500_MUX_SD0] = FUNCTION(sd0),1360 [S500_MUX_SD1] = FUNCTION(sd1),1361 [S500_MUX_SD2] = FUNCTION(sd2),1362 [S500_MUX_I2C0] = FUNCTION(i2c0),1363 [S500_MUX_I2C1] = FUNCTION(i2c1),1364 /*[S500_MUX_I2C2] = FUNCTION(i2c2),*/1365 [S500_MUX_I2C3] = FUNCTION(i2c3),1366 [S500_MUX_DSI] = FUNCTION(dsi),1367 [S500_MUX_LVDS] = FUNCTION(lvds),1368 [S500_MUX_USB30] = FUNCTION(usb30),1369 [S500_MUX_CLKO_25M] = FUNCTION(clko_25m),1370 [S500_MUX_MIPI_CSI] = FUNCTION(mipi_csi),1371 [S500_MUX_NAND] = FUNCTION(nand),1372 [S500_MUX_SPDIF] = FUNCTION(spdif),1373 /*[S500_MUX_SIRQ0] = FUNCTION(sirq0),*/1374 /*[S500_MUX_SIRQ1] = FUNCTION(sirq1),*/1375 /*[S500_MUX_SIRQ2] = FUNCTION(sirq2),*/1376 [S500_MUX_TS] = FUNCTION(ts),1377 [S500_MUX_LCD0] = FUNCTION(lcd0),1378};1379 1380/* PAD_ST0 */1381static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);1382static PAD_ST_CONF(UART0_RX, 0, 29, 1);1383static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);1384static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);1385static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);1386static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);1387static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);1388static PAD_ST_CONF(DSI_DP0, 0, 16, 1);1389static PAD_ST_CONF(DSI_DN0, 0, 15, 1);1390static PAD_ST_CONF(UART0_TX, 0, 14, 1);1391static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1);1392static PAD_ST_CONF(SD0_CLK, 0, 12, 1);1393static PAD_ST_CONF(KS_IN0, 0, 11, 1);1394static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1);1395static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);1396static PAD_ST_CONF(KS_OUT0, 0, 6, 1);1397static PAD_ST_CONF(KS_OUT1, 0, 5, 1);1398static PAD_ST_CONF(KS_OUT2, 0, 4, 1);1399 1400/* PAD_ST1 */1401static PAD_ST_CONF(DSI_DP2, 1, 31, 1);1402static PAD_ST_CONF(DSI_DN2, 1, 30, 1);1403static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);1404static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);1405static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);1406static PAD_ST_CONF(UART3_RX, 1, 25, 1);1407static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);1408static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);1409static PAD_ST_CONF(UART2_RX, 1, 22, 1);1410static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);1411static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);1412static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);1413static PAD_ST_CONF(ETH_RXER, 1, 18, 1);1414static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);1415static PAD_ST_CONF(LVDS_OAP, 1, 12, 1);1416static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);1417static PAD_ST_CONF(PCM1_IN, 1, 10, 1);1418static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);1419static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);1420static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);1421static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);1422static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);1423static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1);1424static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);1425static PAD_ST_CONF(SPI0_SS, 1, 2, 1);1426static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);1427static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);1428 1429/* PAD_PULLCTL0 */1430static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1);1431static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1);1432static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1);1433static PAD_PULLCTL_CONF(LCD0_D17, 0, 27, 1);1434static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1);1435static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1);1436static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2);1437static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2);1438static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2);1439static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1);1440static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1);1441static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1);1442static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1);1443static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1);1444static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1);1445static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1);1446static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1);1447static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1);1448 1449/* PAD_PULLCTL1 */1450static PAD_PULLCTL_CONF(DSI_CP, 1, 31, 1);1451static PAD_PULLCTL_CONF(DSI_CN, 1, 30, 1);1452static PAD_PULLCTL_CONF(DSI_DN2, 1, 28, 1);1453static PAD_PULLCTL_CONF(DNAND_RDBN, 1, 25, 1);1454static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1);1455static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1);1456static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1);1457static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1);1458static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1);1459static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1);1460static PAD_PULLCTL_CONF(SD1_CMD, 1, 11, 1);1461static PAD_PULLCTL_CONF(SD1_D0, 1, 6, 1);1462static PAD_PULLCTL_CONF(SD1_D1, 1, 5, 1);1463static PAD_PULLCTL_CONF(SD1_D2, 1, 4, 1);1464static PAD_PULLCTL_CONF(SD1_D3, 1, 3, 1);1465static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1);1466static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1);1467static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1);1468 1469/* PAD_PULLCTL2 */1470static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 12, 1);1471static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 11, 1);1472static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1);1473static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1);1474static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1);1475static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1);1476static PAD_PULLCTL_CONF(DNAND_DQSN, 2, 5, 2);1477static PAD_PULLCTL_CONF(DNAND_DQS, 2, 3, 2);1478static PAD_PULLCTL_CONF(DNAND_D0, 2, 2, 1);1479static PAD_PULLCTL_CONF(DNAND_D1, 2, 2, 1);1480static PAD_PULLCTL_CONF(DNAND_D2, 2, 2, 1);1481static PAD_PULLCTL_CONF(DNAND_D3, 2, 2, 1);1482static PAD_PULLCTL_CONF(DNAND_D4, 2, 2, 1);1483static PAD_PULLCTL_CONF(DNAND_D5, 2, 2, 1);1484static PAD_PULLCTL_CONF(DNAND_D6, 2, 2, 1);1485static PAD_PULLCTL_CONF(DNAND_D7, 2, 2, 1);1486 1487/* Pad info table */1488static const struct owl_padinfo s500_padinfo[NUM_PADS] = {1489 [DNAND_DQS] = PAD_INFO_PULLCTL(DNAND_DQS),1490 [DNAND_DQSN] = PAD_INFO_PULLCTL(DNAND_DQSN),1491 [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),1492 [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),1493 [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),1494 [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),1495 [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),1496 [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),1497 [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),1498 [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),1499 [ETH_MDC] = PAD_INFO(ETH_MDC),1500 [ETH_MDIO] = PAD_INFO(ETH_MDIO),1501 [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),1502 [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),1503 [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),1504 [I2S_D0] = PAD_INFO(I2S_D0),1505 [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),1506 [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),1507 [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),1508 [I2S_D1] = PAD_INFO(I2S_D1),1509 [I2S_BCLK1] = PAD_INFO(I2S_BCLK1),1510 [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),1511 [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),1512 [KS_IN0] = PAD_INFO_PULLCTL_ST(KS_IN0),1513 [KS_IN1] = PAD_INFO_PULLCTL(KS_IN1),1514 [KS_IN2] = PAD_INFO_PULLCTL(KS_IN2),1515 [KS_IN3] = PAD_INFO_PULLCTL(KS_IN3),1516 [KS_OUT0] = PAD_INFO_PULLCTL_ST(KS_OUT0),1517 [KS_OUT1] = PAD_INFO_PULLCTL_ST(KS_OUT1),1518 [KS_OUT2] = PAD_INFO_PULLCTL_ST(KS_OUT2),1519 [LVDS_OEP] = PAD_INFO(LVDS_OEP),1520 [LVDS_OEN] = PAD_INFO(LVDS_OEN),1521 [LVDS_ODP] = PAD_INFO(LVDS_ODP),1522 [LVDS_ODN] = PAD_INFO(LVDS_ODN),1523 [LVDS_OCP] = PAD_INFO(LVDS_OCP),1524 [LVDS_OCN] = PAD_INFO(LVDS_OCN),1525 [LVDS_OBP] = PAD_INFO(LVDS_OBP),1526 [LVDS_OBN] = PAD_INFO(LVDS_OBN),1527 [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),1528 [LVDS_OAN] = PAD_INFO(LVDS_OAN),1529 [LVDS_EEP] = PAD_INFO(LVDS_EEP),1530 [LVDS_EEN] = PAD_INFO(LVDS_EEN),1531 [LVDS_EDP] = PAD_INFO(LVDS_EDP),1532 [LVDS_EDN] = PAD_INFO(LVDS_EDN),1533 [LVDS_ECP] = PAD_INFO(LVDS_ECP),1534 [LVDS_ECN] = PAD_INFO(LVDS_ECN),1535 [LVDS_EBP] = PAD_INFO(LVDS_EBP),1536 [LVDS_EBN] = PAD_INFO(LVDS_EBN),1537 [LVDS_EAP] = PAD_INFO(LVDS_EAP),1538 [LVDS_EAN] = PAD_INFO(LVDS_EAN),1539 [LCD0_D18] = PAD_INFO(LCD0_D18),1540 [LCD0_D17] = PAD_INFO_PULLCTL(LCD0_D17),1541 [DSI_DP3] = PAD_INFO(DSI_DP3),1542 [DSI_DN3] = PAD_INFO_PULLCTL(DSI_DN3),1543 [DSI_DP1] = PAD_INFO_PULLCTL(DSI_DP1),1544 [DSI_DN1] = PAD_INFO(DSI_DN1),1545 [DSI_CP] = PAD_INFO_PULLCTL(DSI_CP),1546 [DSI_CN] = PAD_INFO_PULLCTL(DSI_CN),1547 [DSI_DP0] = PAD_INFO_ST(DSI_DP0),1548 [DSI_DN0] = PAD_INFO_ST(DSI_DN0),1549 [DSI_DP2] = PAD_INFO_ST(DSI_DP2),1550 [DSI_DN2] = PAD_INFO_PULLCTL_ST(DSI_DN2),1551 [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),1552 [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),1553 [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),1554 [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),1555 [SD1_D0] = PAD_INFO_PULLCTL(SD1_D0),1556 [SD1_D1] = PAD_INFO_PULLCTL(SD1_D1),1557 [SD1_D2] = PAD_INFO_PULLCTL(SD1_D2),1558 [SD1_D3] = PAD_INFO_PULLCTL(SD1_D3),1559 [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),1560 [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),1561 [SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD),1562 [SD1_CLK] = PAD_INFO(SD1_CLK),1563 [SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK),1564 [SPI0_SS] = PAD_INFO_ST(SPI0_SS),1565 [SPI0_MISO] = PAD_INFO_ST(SPI0_MISO),1566 [SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI),1567 [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),1568 [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),1569 [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),1570 [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),1571 [SENSOR0_PCLK] = PAD_INFO_ST(SENSOR0_PCLK),1572 [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),1573 [DNAND_ALE] = PAD_INFO(DNAND_ALE),1574 [DNAND_CLE] = PAD_INFO(DNAND_CLE),1575 [DNAND_CEB0] = PAD_INFO(DNAND_CEB0),1576 [DNAND_CEB1] = PAD_INFO(DNAND_CEB1),1577 [DNAND_CEB2] = PAD_INFO(DNAND_CEB2),1578 [DNAND_CEB3] = PAD_INFO(DNAND_CEB3),1579 [UART2_RX] = PAD_INFO_ST(UART2_RX),1580 [UART2_TX] = PAD_INFO(UART2_TX),1581 [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),1582 [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),1583 [UART3_RX] = PAD_INFO_ST(UART3_RX),1584 [UART3_TX] = PAD_INFO(UART3_TX),1585 [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),1586 [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),1587 [PCM1_IN] = PAD_INFO_ST(PCM1_IN),1588 [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),1589 [PCM1_SYNC] = PAD_INFO_PULLCTL_ST(PCM1_SYNC),1590 [PCM1_OUT] = PAD_INFO_PULLCTL(PCM1_OUT),1591 [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),1592 [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),1593 [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),1594 [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),1595 [CSI_DN0] = PAD_INFO(CSI_DN0),1596 [CSI_DP0] = PAD_INFO(CSI_DP0),1597 [CSI_DN1] = PAD_INFO(CSI_DN1),1598 [CSI_DP1] = PAD_INFO(CSI_DP1),1599 [CSI_CN] = PAD_INFO(CSI_CN),1600 [CSI_CP] = PAD_INFO(CSI_CP),1601 [CSI_DN2] = PAD_INFO(CSI_DN2),1602 [CSI_DP2] = PAD_INFO(CSI_DP2),1603 [CSI_DN3] = PAD_INFO(CSI_DN3),1604 [CSI_DP3] = PAD_INFO(CSI_DP3),1605 [DNAND_D0] = PAD_INFO_PULLCTL(DNAND_D0),1606 [DNAND_D1] = PAD_INFO_PULLCTL(DNAND_D1),1607 [DNAND_D2] = PAD_INFO_PULLCTL(DNAND_D2),1608 [DNAND_D3] = PAD_INFO_PULLCTL(DNAND_D3),1609 [DNAND_D4] = PAD_INFO_PULLCTL(DNAND_D4),1610 [DNAND_D5] = PAD_INFO_PULLCTL(DNAND_D5),1611 [DNAND_D6] = PAD_INFO_PULLCTL(DNAND_D6),1612 [DNAND_D7] = PAD_INFO_PULLCTL(DNAND_D7),1613 [DNAND_WRB] = PAD_INFO(DNAND_WRB),1614 [DNAND_RDB] = PAD_INFO(DNAND_RDB),1615 [DNAND_RDBN] = PAD_INFO_PULLCTL(DNAND_RDBN),1616 [DNAND_RB] = PAD_INFO(DNAND_RB),1617 [PORB] = PAD_INFO(PORB),1618 [CLKO_25M] = PAD_INFO_PULLCTL(CLKO_25M),1619 [BSEL] = PAD_INFO(BSEL),1620 [PKG0] = PAD_INFO(PKG0),1621 [PKG1] = PAD_INFO(PKG1),1622 [PKG2] = PAD_INFO(PKG2),1623 [PKG3] = PAD_INFO(PKG3),1624};1625 1626static const struct owl_gpio_port s500_gpio_ports[] = {1627 OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x230, 0),1628 OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x1F8, 0x204, 0x208, 0x22C, 1),1629 OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x1EC, 0x200, 0x204, 0x228, 2),1630 OWL_GPIO_PORT(D, 0x0024, 32, 0x0, 0x4, 0x8, 0x1E0, 0x1FC, 0x200, 0x224, 3),1631 OWL_GPIO_PORT(E, 0x0030, 4, 0x0, 0x4, 0x8, 0x1D4, 0x1F8, 0x1FC, 0x220, 4),1632};1633 1634enum s500_pinconf_pull {1635 OWL_PINCONF_PULL_DOWN,1636 OWL_PINCONF_PULL_UP,1637};1638 1639static int s500_pad_pinconf_arg2val(const struct owl_padinfo *info,1640 unsigned int param, u32 *arg)1641{1642 switch (param) {1643 case PIN_CONFIG_BIAS_PULL_DOWN:1644 *arg = OWL_PINCONF_PULL_DOWN;1645 break;1646 case PIN_CONFIG_BIAS_PULL_UP:1647 *arg = OWL_PINCONF_PULL_UP;1648 break;1649 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:1650 *arg = (*arg >= 1 ? 1 : 0);1651 break;1652 default:1653 return -EOPNOTSUPP;1654 }1655 1656 return 0;1657}1658 1659static int s500_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,1660 unsigned int param, u32 *arg)1661{1662 switch (param) {1663 case PIN_CONFIG_BIAS_PULL_DOWN:1664 *arg = *arg == OWL_PINCONF_PULL_DOWN;1665 break;1666 case PIN_CONFIG_BIAS_PULL_UP:1667 *arg = *arg == OWL_PINCONF_PULL_UP;1668 break;1669 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:1670 *arg = *arg == 1;1671 break;1672 default:1673 return -EOPNOTSUPP;1674 }1675 1676 return 0;1677}1678 1679static struct owl_pinctrl_soc_data s500_pinctrl_data = {1680 .padinfo = s500_padinfo,1681 .pins = (const struct pinctrl_pin_desc *)s500_pads,1682 .npins = ARRAY_SIZE(s500_pads),1683 .functions = s500_functions,1684 .nfunctions = ARRAY_SIZE(s500_functions),1685 .groups = s500_groups,1686 .ngroups = ARRAY_SIZE(s500_groups),1687 .ngpios = NUM_GPIOS,1688 .ports = s500_gpio_ports,1689 .nports = ARRAY_SIZE(s500_gpio_ports),1690 .padctl_arg2val = s500_pad_pinconf_arg2val,1691 .padctl_val2arg = s500_pad_pinconf_val2arg,1692};1693 1694static int s500_pinctrl_probe(struct platform_device *pdev)1695{1696 return owl_pinctrl_probe(pdev, &s500_pinctrl_data);1697}1698 1699static const struct of_device_id s500_pinctrl_of_match[] = {1700 { .compatible = "actions,s500-pinctrl", },1701 { }1702};1703 1704static struct platform_driver s500_pinctrl_driver = {1705 .driver = {1706 .name = "pinctrl-s500",1707 .of_match_table = of_match_ptr(s500_pinctrl_of_match),1708 },1709 .probe = s500_pinctrl_probe,1710};1711 1712static int __init s500_pinctrl_init(void)1713{1714 return platform_driver_register(&s500_pinctrl_driver);1715}1716arch_initcall(s500_pinctrl_init);1717 1718static void __exit s500_pinctrl_exit(void)1719{1720 platform_driver_unregister(&s500_pinctrl_driver);1721}1722module_exit(s500_pinctrl_exit);1723 1724MODULE_AUTHOR("Actions Semi Inc.");1725MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@gmail.com>");1726MODULE_DESCRIPTION("Actions Semi S500 SoC Pinctrl Driver");1727