1830 lines · c
1// SPDX-License-Identifier: GPL-2.0+2/*3 * OWL S900 Pinctrl driver4 *5 * Copyright (c) 2014 Actions Semi Inc.6 * Author: David Liu <liuwei@actions-semi.com>7 *8 * Copyright (c) 2018 Linaro Ltd.9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>10 */11 12#include <linux/module.h>13#include <linux/of.h>14#include <linux/platform_device.h>15#include <linux/pinctrl/pinctrl.h>16#include <linux/pinctrl/pinconf-generic.h>17#include "pinctrl-owl.h"18 19/* Pinctrl registers offset */20#define MFCTL0 (0x0040)21#define MFCTL1 (0x0044)22#define MFCTL2 (0x0048)23#define MFCTL3 (0x004C)24#define PAD_PULLCTL0 (0x0060)25#define PAD_PULLCTL1 (0x0064)26#define PAD_PULLCTL2 (0x0068)27#define PAD_ST0 (0x006C)28#define PAD_ST1 (0x0070)29#define PAD_CTL (0x0074)30#define PAD_DRV0 (0x0080)31#define PAD_DRV1 (0x0084)32#define PAD_DRV2 (0x0088)33#define PAD_SR0 (0x0270)34#define PAD_SR1 (0x0274)35#define PAD_SR2 (0x0278)36 37#define _GPIOA(offset) (offset)38#define _GPIOB(offset) (32 + (offset))39#define _GPIOC(offset) (64 + (offset))40#define _GPIOD(offset) (76 + (offset))41#define _GPIOE(offset) (106 + (offset))42#define _GPIOF(offset) (138 + (offset))43 44#define NUM_GPIOS (_GPIOF(7) + 1)45#define _PIN(offset) (NUM_GPIOS + (offset))46 47#define ETH_TXD0 _GPIOA(0)48#define ETH_TXD1 _GPIOA(1)49#define ETH_TXEN _GPIOA(2)50#define ETH_RXER _GPIOA(3)51#define ETH_CRS_DV _GPIOA(4)52#define ETH_RXD1 _GPIOA(5)53#define ETH_RXD0 _GPIOA(6)54#define ETH_REF_CLK _GPIOA(7)55#define ETH_MDC _GPIOA(8)56#define ETH_MDIO _GPIOA(9)57#define SIRQ0 _GPIOA(10)58#define SIRQ1 _GPIOA(11)59#define SIRQ2 _GPIOA(12)60#define I2S_D0 _GPIOA(13)61#define I2S_BCLK0 _GPIOA(14)62#define I2S_LRCLK0 _GPIOA(15)63#define I2S_MCLK0 _GPIOA(16)64#define I2S_D1 _GPIOA(17)65#define I2S_BCLK1 _GPIOA(18)66#define I2S_LRCLK1 _GPIOA(19)67#define I2S_MCLK1 _GPIOA(20)68#define ERAM_A5 _GPIOA(21)69#define ERAM_A6 _GPIOA(22)70#define ERAM_A7 _GPIOA(23)71#define ERAM_A8 _GPIOA(24)72#define ERAM_A9 _GPIOA(25)73#define ERAM_A10 _GPIOA(26)74#define ERAM_A11 _GPIOA(27)75#define SD0_D0 _GPIOA(28)76#define SD0_D1 _GPIOA(29)77#define SD0_D2 _GPIOA(30)78#define SD0_D3 _GPIOA(31)79 80#define SD1_D0 _GPIOB(0)81#define SD1_D1 _GPIOB(1)82#define SD1_D2 _GPIOB(2)83#define SD1_D3 _GPIOB(3)84#define SD0_CMD _GPIOB(4)85#define SD0_CLK _GPIOB(5)86#define SD1_CMD _GPIOB(6)87#define SD1_CLK _GPIOB(7)88#define SPI0_SCLK _GPIOB(8)89#define SPI0_SS _GPIOB(9)90#define SPI0_MISO _GPIOB(10)91#define SPI0_MOSI _GPIOB(11)92#define UART0_RX _GPIOB(12)93#define UART0_TX _GPIOB(13)94#define UART2_RX _GPIOB(14)95#define UART2_TX _GPIOB(15)96#define UART2_RTSB _GPIOB(16)97#define UART2_CTSB _GPIOB(17)98#define UART4_RX _GPIOB(18)99#define UART4_TX _GPIOB(19)100#define I2C0_SCLK _GPIOB(20)101#define I2C0_SDATA _GPIOB(21)102#define I2C1_SCLK _GPIOB(22)103#define I2C1_SDATA _GPIOB(23)104#define I2C2_SCLK _GPIOB(24)105#define I2C2_SDATA _GPIOB(25)106#define CSI0_DN0 _GPIOB(26)107#define CSI0_DP0 _GPIOB(27)108#define CSI0_DN1 _GPIOB(28)109#define CSI0_DP1 _GPIOB(29)110#define CSI0_CN _GPIOB(30)111#define CSI0_CP _GPIOB(31)112 113#define CSI0_DN2 _GPIOC(0)114#define CSI0_DP2 _GPIOC(1)115#define CSI0_DN3 _GPIOC(2)116#define CSI0_DP3 _GPIOC(3)117#define SENSOR0_PCLK _GPIOC(4)118#define CSI1_DN0 _GPIOC(5)119#define CSI1_DP0 _GPIOC(6)120#define CSI1_DN1 _GPIOC(7)121#define CSI1_DP1 _GPIOC(8)122#define CSI1_CN _GPIOC(9)123#define CSI1_CP _GPIOC(10)124#define SENSOR0_CKOUT _GPIOC(11)125 126#define LVDS_OEP _GPIOD(0)127#define LVDS_OEN _GPIOD(1)128#define LVDS_ODP _GPIOD(2)129#define LVDS_ODN _GPIOD(3)130#define LVDS_OCP _GPIOD(4)131#define LVDS_OCN _GPIOD(5)132#define LVDS_OBP _GPIOD(6)133#define LVDS_OBN _GPIOD(7)134#define LVDS_OAP _GPIOD(8)135#define LVDS_OAN _GPIOD(9)136#define LVDS_EEP _GPIOD(10)137#define LVDS_EEN _GPIOD(11)138#define LVDS_EDP _GPIOD(12)139#define LVDS_EDN _GPIOD(13)140#define LVDS_ECP _GPIOD(14)141#define LVDS_ECN _GPIOD(15)142#define LVDS_EBP _GPIOD(16)143#define LVDS_EBN _GPIOD(17)144#define LVDS_EAP _GPIOD(18)145#define LVDS_EAN _GPIOD(19)146#define DSI_DP3 _GPIOD(20)147#define DSI_DN3 _GPIOD(21)148#define DSI_DP1 _GPIOD(22)149#define DSI_DN1 _GPIOD(23)150#define DSI_CP _GPIOD(24)151#define DSI_CN _GPIOD(25)152#define DSI_DP0 _GPIOD(26)153#define DSI_DN0 _GPIOD(27)154#define DSI_DP2 _GPIOD(28)155#define DSI_DN2 _GPIOD(29)156 157#define NAND0_D0 _GPIOE(0)158#define NAND0_D1 _GPIOE(1)159#define NAND0_D2 _GPIOE(2)160#define NAND0_D3 _GPIOE(3)161#define NAND0_D4 _GPIOE(4)162#define NAND0_D5 _GPIOE(5)163#define NAND0_D6 _GPIOE(6)164#define NAND0_D7 _GPIOE(7)165#define NAND0_DQS _GPIOE(8)166#define NAND0_DQSN _GPIOE(9)167#define NAND0_ALE _GPIOE(10)168#define NAND0_CLE _GPIOE(11)169#define NAND0_CEB0 _GPIOE(12)170#define NAND0_CEB1 _GPIOE(13)171#define NAND0_CEB2 _GPIOE(14)172#define NAND0_CEB3 _GPIOE(15)173#define NAND1_D0 _GPIOE(16)174#define NAND1_D1 _GPIOE(17)175#define NAND1_D2 _GPIOE(18)176#define NAND1_D3 _GPIOE(19)177#define NAND1_D4 _GPIOE(20)178#define NAND1_D5 _GPIOE(21)179#define NAND1_D6 _GPIOE(22)180#define NAND1_D7 _GPIOE(23)181#define NAND1_DQS _GPIOE(24)182#define NAND1_DQSN _GPIOE(25)183#define NAND1_ALE _GPIOE(26)184#define NAND1_CLE _GPIOE(27)185#define NAND1_CEB0 _GPIOE(28)186#define NAND1_CEB1 _GPIOE(29)187#define NAND1_CEB2 _GPIOE(30)188#define NAND1_CEB3 _GPIOE(31)189 190#define PCM1_IN _GPIOF(0)191#define PCM1_CLK _GPIOF(1)192#define PCM1_SYNC _GPIOF(2)193#define PCM1_OUT _GPIOF(3)194#define UART3_RX _GPIOF(4)195#define UART3_TX _GPIOF(5)196#define UART3_RTSB _GPIOF(6)197#define UART3_CTSB _GPIOF(7)198 199/* System */200#define SGPIO0 _PIN(0)201#define SGPIO1 _PIN(1)202#define SGPIO2 _PIN(2)203#define SGPIO3 _PIN(3)204 205#define NUM_PADS (_PIN(3) + 1)206 207/* Pad names as specified in datasheet */208static const struct pinctrl_pin_desc s900_pads[] = {209 PINCTRL_PIN(ETH_TXD0, "eth_txd0"),210 PINCTRL_PIN(ETH_TXD1, "eth_txd1"),211 PINCTRL_PIN(ETH_TXEN, "eth_txen"),212 PINCTRL_PIN(ETH_RXER, "eth_rxer"),213 PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),214 PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),215 PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),216 PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),217 PINCTRL_PIN(ETH_MDC, "eth_mdc"),218 PINCTRL_PIN(ETH_MDIO, "eth_mdio"),219 PINCTRL_PIN(SIRQ0, "sirq0"),220 PINCTRL_PIN(SIRQ1, "sirq1"),221 PINCTRL_PIN(SIRQ2, "sirq2"),222 PINCTRL_PIN(I2S_D0, "i2s_d0"),223 PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),224 PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),225 PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),226 PINCTRL_PIN(I2S_D1, "i2s_d1"),227 PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),228 PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),229 PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),230 PINCTRL_PIN(PCM1_IN, "pcm1_in"),231 PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),232 PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),233 PINCTRL_PIN(PCM1_OUT, "pcm1_out"),234 PINCTRL_PIN(ERAM_A5, "eram_a5"),235 PINCTRL_PIN(ERAM_A6, "eram_a6"),236 PINCTRL_PIN(ERAM_A7, "eram_a7"),237 PINCTRL_PIN(ERAM_A8, "eram_a8"),238 PINCTRL_PIN(ERAM_A9, "eram_a9"),239 PINCTRL_PIN(ERAM_A10, "eram_a10"),240 PINCTRL_PIN(ERAM_A11, "eram_a11"),241 PINCTRL_PIN(LVDS_OEP, "lvds_oep"),242 PINCTRL_PIN(LVDS_OEN, "lvds_oen"),243 PINCTRL_PIN(LVDS_ODP, "lvds_odp"),244 PINCTRL_PIN(LVDS_ODN, "lvds_odn"),245 PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),246 PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),247 PINCTRL_PIN(LVDS_OBP, "lvds_obp"),248 PINCTRL_PIN(LVDS_OBN, "lvds_obn"),249 PINCTRL_PIN(LVDS_OAP, "lvds_oap"),250 PINCTRL_PIN(LVDS_OAN, "lvds_oan"),251 PINCTRL_PIN(LVDS_EEP, "lvds_eep"),252 PINCTRL_PIN(LVDS_EEN, "lvds_een"),253 PINCTRL_PIN(LVDS_EDP, "lvds_edp"),254 PINCTRL_PIN(LVDS_EDN, "lvds_edn"),255 PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),256 PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),257 PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),258 PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),259 PINCTRL_PIN(LVDS_EAP, "lvds_eap"),260 PINCTRL_PIN(LVDS_EAN, "lvds_ean"),261 PINCTRL_PIN(SD0_D0, "sd0_d0"),262 PINCTRL_PIN(SD0_D1, "sd0_d1"),263 PINCTRL_PIN(SD0_D2, "sd0_d2"),264 PINCTRL_PIN(SD0_D3, "sd0_d3"),265 PINCTRL_PIN(SD1_D0, "sd1_d0"),266 PINCTRL_PIN(SD1_D1, "sd1_d1"),267 PINCTRL_PIN(SD1_D2, "sd1_d2"),268 PINCTRL_PIN(SD1_D3, "sd1_d3"),269 PINCTRL_PIN(SD0_CMD, "sd0_cmd"),270 PINCTRL_PIN(SD0_CLK, "sd0_clk"),271 PINCTRL_PIN(SD1_CMD, "sd1_cmd"),272 PINCTRL_PIN(SD1_CLK, "sd1_clk"),273 PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"),274 PINCTRL_PIN(SPI0_SS, "spi0_ss"),275 PINCTRL_PIN(SPI0_MISO, "spi0_miso"),276 PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"),277 PINCTRL_PIN(UART0_RX, "uart0_rx"),278 PINCTRL_PIN(UART0_TX, "uart0_tx"),279 PINCTRL_PIN(UART2_RX, "uart2_rx"),280 PINCTRL_PIN(UART2_TX, "uart2_tx"),281 PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),282 PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),283 PINCTRL_PIN(UART3_RX, "uart3_rx"),284 PINCTRL_PIN(UART3_TX, "uart3_tx"),285 PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),286 PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),287 PINCTRL_PIN(UART4_RX, "uart4_rx"),288 PINCTRL_PIN(UART4_TX, "uart4_tx"),289 PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),290 PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),291 PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),292 PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),293 PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),294 PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),295 PINCTRL_PIN(CSI0_DN0, "csi0_dn0"),296 PINCTRL_PIN(CSI0_DP0, "csi0_dp0"),297 PINCTRL_PIN(CSI0_DN1, "csi0_dn1"),298 PINCTRL_PIN(CSI0_DP1, "csi0_dp1"),299 PINCTRL_PIN(CSI0_CN, "csi0_cn"),300 PINCTRL_PIN(CSI0_CP, "csi0_cp"),301 PINCTRL_PIN(CSI0_DN2, "csi0_dn2"),302 PINCTRL_PIN(CSI0_DP2, "csi0_dp2"),303 PINCTRL_PIN(CSI0_DN3, "csi0_dn3"),304 PINCTRL_PIN(CSI0_DP3, "csi0_dp3"),305 PINCTRL_PIN(DSI_DP3, "dsi_dp3"),306 PINCTRL_PIN(DSI_DN3, "dsi_dn3"),307 PINCTRL_PIN(DSI_DP1, "dsi_dp1"),308 PINCTRL_PIN(DSI_DN1, "dsi_dn1"),309 PINCTRL_PIN(DSI_CP, "dsi_cp"),310 PINCTRL_PIN(DSI_CN, "dsi_cn"),311 PINCTRL_PIN(DSI_DP0, "dsi_dp0"),312 PINCTRL_PIN(DSI_DN0, "dsi_dn0"),313 PINCTRL_PIN(DSI_DP2, "dsi_dp2"),314 PINCTRL_PIN(DSI_DN2, "dsi_dn2"),315 PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),316 PINCTRL_PIN(CSI1_DN0, "csi1_dn0"),317 PINCTRL_PIN(CSI1_DP0, "csi1_dp0"),318 PINCTRL_PIN(CSI1_DN1, "csi1_dn1"),319 PINCTRL_PIN(CSI1_DP1, "csi1_dp1"),320 PINCTRL_PIN(CSI1_CN, "csi1_cn"),321 PINCTRL_PIN(CSI1_CP, "csi1_cp"),322 PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),323 PINCTRL_PIN(NAND0_D0, "nand0_d0"),324 PINCTRL_PIN(NAND0_D1, "nand0_d1"),325 PINCTRL_PIN(NAND0_D2, "nand0_d2"),326 PINCTRL_PIN(NAND0_D3, "nand0_d3"),327 PINCTRL_PIN(NAND0_D4, "nand0_d4"),328 PINCTRL_PIN(NAND0_D5, "nand0_d5"),329 PINCTRL_PIN(NAND0_D6, "nand0_d6"),330 PINCTRL_PIN(NAND0_D7, "nand0_d7"),331 PINCTRL_PIN(NAND0_DQS, "nand0_dqs"),332 PINCTRL_PIN(NAND0_DQSN, "nand0_dqsn"),333 PINCTRL_PIN(NAND0_ALE, "nand0_ale"),334 PINCTRL_PIN(NAND0_CLE, "nand0_cle"),335 PINCTRL_PIN(NAND0_CEB0, "nand0_ceb0"),336 PINCTRL_PIN(NAND0_CEB1, "nand0_ceb1"),337 PINCTRL_PIN(NAND0_CEB2, "nand0_ceb2"),338 PINCTRL_PIN(NAND0_CEB3, "nand0_ceb3"),339 PINCTRL_PIN(NAND1_D0, "nand1_d0"),340 PINCTRL_PIN(NAND1_D1, "nand1_d1"),341 PINCTRL_PIN(NAND1_D2, "nand1_d2"),342 PINCTRL_PIN(NAND1_D3, "nand1_d3"),343 PINCTRL_PIN(NAND1_D4, "nand1_d4"),344 PINCTRL_PIN(NAND1_D5, "nand1_d5"),345 PINCTRL_PIN(NAND1_D6, "nand1_d6"),346 PINCTRL_PIN(NAND1_D7, "nand1_d7"),347 PINCTRL_PIN(NAND1_DQS, "nand1_dqs"),348 PINCTRL_PIN(NAND1_DQSN, "nand1_dqsn"),349 PINCTRL_PIN(NAND1_ALE, "nand1_ale"),350 PINCTRL_PIN(NAND1_CLE, "nand1_cle"),351 PINCTRL_PIN(NAND1_CEB0, "nand1_ceb0"),352 PINCTRL_PIN(NAND1_CEB1, "nand1_ceb1"),353 PINCTRL_PIN(NAND1_CEB2, "nand1_ceb2"),354 PINCTRL_PIN(NAND1_CEB3, "nand1_ceb3"),355 PINCTRL_PIN(SGPIO0, "sgpio0"),356 PINCTRL_PIN(SGPIO1, "sgpio1"),357 PINCTRL_PIN(SGPIO2, "sgpio2"),358 PINCTRL_PIN(SGPIO3, "sgpio3")359};360 361enum s900_pinmux_functions {362 S900_MUX_ERAM,363 S900_MUX_ETH_RMII,364 S900_MUX_ETH_SMII,365 S900_MUX_SPI0,366 S900_MUX_SPI1,367 S900_MUX_SPI2,368 S900_MUX_SPI3,369 S900_MUX_SENS0,370 S900_MUX_UART0,371 S900_MUX_UART1,372 S900_MUX_UART2,373 S900_MUX_UART3,374 S900_MUX_UART4,375 S900_MUX_UART5,376 S900_MUX_UART6,377 S900_MUX_I2S0,378 S900_MUX_I2S1,379 S900_MUX_PCM0,380 S900_MUX_PCM1,381 S900_MUX_JTAG,382 S900_MUX_PWM0,383 S900_MUX_PWM1,384 S900_MUX_PWM2,385 S900_MUX_PWM3,386 S900_MUX_PWM4,387 S900_MUX_PWM5,388 S900_MUX_SD0,389 S900_MUX_SD1,390 S900_MUX_SD2,391 S900_MUX_SD3,392 S900_MUX_I2C0,393 S900_MUX_I2C1,394 S900_MUX_I2C2,395 S900_MUX_I2C3,396 S900_MUX_I2C4,397 S900_MUX_I2C5,398 S900_MUX_LVDS,399 S900_MUX_USB20,400 S900_MUX_USB30,401 S900_MUX_GPU,402 S900_MUX_MIPI_CSI0,403 S900_MUX_MIPI_CSI1,404 S900_MUX_MIPI_DSI,405 S900_MUX_NAND0,406 S900_MUX_NAND1,407 S900_MUX_SPDIF,408 S900_MUX_SIRQ0,409 S900_MUX_SIRQ1,410 S900_MUX_SIRQ2,411 S900_MUX_AUX_START,412 S900_MUX_MAX,413 S900_MUX_RESERVED414};415 416/* mfp0_22 */417static unsigned int lvds_oxx_uart4_mfp_pads[] = { LVDS_OAP, LVDS_OAN };418static unsigned int lvds_oxx_uart4_mfp_funcs[] = { S900_MUX_ERAM,419 S900_MUX_UART4 };420/* mfp0_21_20 */421static unsigned int rmii_mdc_mfp_pads[] = { ETH_MDC };422static unsigned int rmii_mdc_mfp_funcs[] = { S900_MUX_ETH_RMII,423 S900_MUX_PWM2,424 S900_MUX_UART2,425 S900_MUX_RESERVED };426static unsigned int rmii_mdio_mfp_pads[] = { ETH_MDIO };427static unsigned int rmii_mdio_mfp_funcs[] = { S900_MUX_ETH_RMII,428 S900_MUX_PWM3,429 S900_MUX_UART2,430 S900_MUX_RESERVED };431/* mfp0_19 */432static unsigned int sirq0_mfp_pads[] = { SIRQ0 };433static unsigned int sirq0_mfp_funcs[] = { S900_MUX_SIRQ0,434 S900_MUX_PWM0 };435static unsigned int sirq1_mfp_pads[] = { SIRQ1 };436static unsigned int sirq1_mfp_funcs[] = { S900_MUX_SIRQ1,437 S900_MUX_PWM1 };438/* mfp0_18_16 */439static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 };440static unsigned int rmii_txd0_mfp_funcs[] = { S900_MUX_ETH_RMII,441 S900_MUX_ETH_SMII,442 S900_MUX_SPI2,443 S900_MUX_UART6,444 S900_MUX_SENS0,445 S900_MUX_PWM0 };446static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 };447static unsigned int rmii_txd1_mfp_funcs[] = { S900_MUX_ETH_RMII,448 S900_MUX_ETH_SMII,449 S900_MUX_SPI2,450 S900_MUX_UART6,451 S900_MUX_SENS0,452 S900_MUX_PWM1 };453/* mfp0_15_13 */454static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN };455static unsigned int rmii_txen_mfp_funcs[] = { S900_MUX_ETH_RMII,456 S900_MUX_UART2,457 S900_MUX_SPI3,458 S900_MUX_RESERVED,459 S900_MUX_RESERVED,460 S900_MUX_PWM2,461 S900_MUX_SENS0 };462 463static unsigned int rmii_rxer_mfp_pads[] = { ETH_RXER };464static unsigned int rmii_rxer_mfp_funcs[] = { S900_MUX_ETH_RMII,465 S900_MUX_UART2,466 S900_MUX_SPI3,467 S900_MUX_RESERVED,468 S900_MUX_RESERVED,469 S900_MUX_PWM3,470 S900_MUX_SENS0 };471/* mfp0_12_11 */472static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV };473static unsigned int rmii_crs_dv_mfp_funcs[] = { S900_MUX_ETH_RMII,474 S900_MUX_ETH_SMII,475 S900_MUX_SPI2,476 S900_MUX_UART4 };477/* mfp0_10_8 */478static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 };479static unsigned int rmii_rxd1_mfp_funcs[] = { S900_MUX_ETH_RMII,480 S900_MUX_UART2,481 S900_MUX_SPI3,482 S900_MUX_RESERVED,483 S900_MUX_UART5,484 S900_MUX_PWM0,485 S900_MUX_SENS0 };486static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 };487static unsigned int rmii_rxd0_mfp_funcs[] = { S900_MUX_ETH_RMII,488 S900_MUX_UART2,489 S900_MUX_SPI3,490 S900_MUX_RESERVED,491 S900_MUX_UART5,492 S900_MUX_PWM1,493 S900_MUX_SENS0 };494/* mfp0_7_6 */495static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };496static unsigned int rmii_ref_clk_mfp_funcs[] = { S900_MUX_ETH_RMII,497 S900_MUX_UART4,498 S900_MUX_SPI2,499 S900_MUX_RESERVED };500/* mfp0_5 */501static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };502static unsigned int i2s_d0_mfp_funcs[] = { S900_MUX_I2S0,503 S900_MUX_PCM0 };504static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };505static unsigned int i2s_d1_mfp_funcs[] = { S900_MUX_I2S1,506 S900_MUX_PCM0 };507 508/* mfp0_4_3 */509static unsigned int i2s_lr_m_clk0_mfp_pads[] = { I2S_LRCLK0,510 I2S_MCLK0 };511static unsigned int i2s_lr_m_clk0_mfp_funcs[] = { S900_MUX_I2S0,512 S900_MUX_PCM0,513 S900_MUX_PCM1,514 S900_MUX_RESERVED };515/* mfp0_2 */516static unsigned int i2s_bclk0_mfp_pads[] = { I2S_BCLK0 };517static unsigned int i2s_bclk0_mfp_funcs[] = { S900_MUX_I2S0,518 S900_MUX_PCM0 };519static unsigned int i2s_bclk1_mclk1_mfp_pads[] = { I2S_BCLK1,520 I2S_LRCLK1,521 I2S_MCLK1 };522static unsigned int i2s_bclk1_mclk1_mfp_funcs[] = { S900_MUX_I2S1,523 S900_MUX_PCM0 };524/* mfp0_1_0 */525static unsigned int pcm1_in_out_mfp_pads[] = { PCM1_IN,526 PCM1_OUT };527static unsigned int pcm1_in_out_mfp_funcs[] = { S900_MUX_PCM1,528 S900_MUX_SPI1,529 S900_MUX_I2C3,530 S900_MUX_UART4 };531static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };532static unsigned int pcm1_clk_mfp_funcs[] = { S900_MUX_PCM1,533 S900_MUX_SPI1,534 S900_MUX_PWM4,535 S900_MUX_UART4 };536static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };537static unsigned int pcm1_sync_mfp_funcs[] = { S900_MUX_PCM1,538 S900_MUX_SPI1,539 S900_MUX_PWM5,540 S900_MUX_UART4 };541/* mfp1_31_29 */542static unsigned int eram_a5_mfp_pads[] = { ERAM_A5 };543static unsigned int eram_a5_mfp_funcs[] = { S900_MUX_UART4,544 S900_MUX_JTAG,545 S900_MUX_ERAM,546 S900_MUX_PWM0,547 S900_MUX_RESERVED,548 S900_MUX_SENS0 };549static unsigned int eram_a6_mfp_pads[] = { ERAM_A6 };550static unsigned int eram_a6_mfp_funcs[] = { S900_MUX_UART4,551 S900_MUX_JTAG,552 S900_MUX_ERAM,553 S900_MUX_PWM1,554 S900_MUX_RESERVED,555 S900_MUX_SENS0,556};557static unsigned int eram_a7_mfp_pads[] = { ERAM_A7 };558static unsigned int eram_a7_mfp_funcs[] = { S900_MUX_RESERVED,559 S900_MUX_JTAG,560 S900_MUX_ERAM,561 S900_MUX_RESERVED,562 S900_MUX_RESERVED,563 S900_MUX_SENS0 };564/* mfp1_28_26 */565static unsigned int eram_a8_mfp_pads[] = { ERAM_A8 };566static unsigned int eram_a8_mfp_funcs[] = { S900_MUX_RESERVED,567 S900_MUX_JTAG,568 S900_MUX_ERAM,569 S900_MUX_PWM1,570 S900_MUX_RESERVED,571 S900_MUX_SENS0 };572static unsigned int eram_a9_mfp_pads[] = { ERAM_A9 };573static unsigned int eram_a9_mfp_funcs[] = { S900_MUX_USB20,574 S900_MUX_UART5,575 S900_MUX_ERAM,576 S900_MUX_PWM2,577 S900_MUX_RESERVED,578 S900_MUX_SENS0 };579static unsigned int eram_a10_mfp_pads[] = { ERAM_A10 };580static unsigned int eram_a10_mfp_funcs[] = { S900_MUX_USB30,581 S900_MUX_JTAG,582 S900_MUX_ERAM,583 S900_MUX_PWM3,584 S900_MUX_RESERVED,585 S900_MUX_SENS0,586 S900_MUX_RESERVED,587 S900_MUX_RESERVED };588/* mfp1_25_23 */589static unsigned int eram_a11_mfp_pads[] = { ERAM_A11 };590static unsigned int eram_a11_mfp_funcs[] = { S900_MUX_RESERVED,591 S900_MUX_RESERVED,592 S900_MUX_ERAM,593 S900_MUX_PWM2,594 S900_MUX_UART5,595 S900_MUX_RESERVED,596 S900_MUX_SENS0,597 S900_MUX_RESERVED };598/* mfp1_22 */599static unsigned int lvds_oep_odn_mfp_pads[] = { LVDS_OEP,600 LVDS_OEN,601 LVDS_ODP,602 LVDS_ODN };603static unsigned int lvds_oep_odn_mfp_funcs[] = { S900_MUX_LVDS,604 S900_MUX_UART2 };605static unsigned int lvds_ocp_obn_mfp_pads[] = { LVDS_OCP,606 LVDS_OCN,607 LVDS_OBP,608 LVDS_OBN };609static unsigned int lvds_ocp_obn_mfp_funcs[] = { S900_MUX_LVDS,610 S900_MUX_PCM1 };611static unsigned int lvds_oap_oan_mfp_pads[] = { LVDS_OAP,612 LVDS_OAN };613static unsigned int lvds_oap_oan_mfp_funcs[] = { S900_MUX_LVDS,614 S900_MUX_ERAM };615/* mfp1_21 */616static unsigned int lvds_e_mfp_pads[] = { LVDS_EEP,617 LVDS_EEN,618 LVDS_EDP,619 LVDS_EDN,620 LVDS_ECP,621 LVDS_ECN,622 LVDS_EBP,623 LVDS_EBN,624 LVDS_EAP,625 LVDS_EAN };626static unsigned int lvds_e_mfp_funcs[] = { S900_MUX_LVDS,627 S900_MUX_ERAM };628/* mfp1_5_4 */629static unsigned int spi0_sclk_mosi_mfp_pads[] = { SPI0_SCLK,630 SPI0_MOSI };631static unsigned int spi0_sclk_mosi_mfp_funcs[] = { S900_MUX_SPI0,632 S900_MUX_ERAM,633 S900_MUX_I2C3,634 S900_MUX_PCM0 };635/* mfp1_3_1 */636static unsigned int spi0_ss_mfp_pads[] = { SPI0_SS };637static unsigned int spi0_ss_mfp_funcs[] = { S900_MUX_SPI0,638 S900_MUX_ERAM,639 S900_MUX_I2S1,640 S900_MUX_PCM1,641 S900_MUX_PCM0,642 S900_MUX_PWM4 };643static unsigned int spi0_miso_mfp_pads[] = { SPI0_MISO };644static unsigned int spi0_miso_mfp_funcs[] = { S900_MUX_SPI0,645 S900_MUX_ERAM,646 S900_MUX_I2S1,647 S900_MUX_PCM1,648 S900_MUX_PCM0,649 S900_MUX_PWM5 };650/* mfp2_23 */651static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };652static unsigned int uart2_rtsb_mfp_funcs[] = { S900_MUX_UART2,653 S900_MUX_UART0 };654/* mfp2_22 */655static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };656static unsigned int uart2_ctsb_mfp_funcs[] = { S900_MUX_UART2,657 S900_MUX_UART0 };658/* mfp2_21 */659static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };660static unsigned int uart3_rtsb_mfp_funcs[] = { S900_MUX_UART3,661 S900_MUX_UART5 };662/* mfp2_20 */663static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };664static unsigned int uart3_ctsb_mfp_funcs[] = { S900_MUX_UART3,665 S900_MUX_UART5 };666/* mfp2_19_17 */667static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };668static unsigned int sd0_d0_mfp_funcs[] = { S900_MUX_SD0,669 S900_MUX_ERAM,670 S900_MUX_RESERVED,671 S900_MUX_JTAG,672 S900_MUX_UART2,673 S900_MUX_UART5,674 S900_MUX_GPU };675/* mfp2_16_14 */676static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };677static unsigned int sd0_d1_mfp_funcs[] = { S900_MUX_SD0,678 S900_MUX_ERAM,679 S900_MUX_GPU,680 S900_MUX_RESERVED,681 S900_MUX_UART2,682 S900_MUX_UART5 };683/* mfp_13_11 */684static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2,685 SD0_D3 };686static unsigned int sd0_d2_d3_mfp_funcs[] = { S900_MUX_SD0,687 S900_MUX_ERAM,688 S900_MUX_RESERVED,689 S900_MUX_JTAG,690 S900_MUX_UART2,691 S900_MUX_UART1,692 S900_MUX_GPU };693/* mfp2_10_9 */694static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1,695 SD1_D2, SD1_D3 };696static unsigned int sd1_d0_d3_mfp_funcs[] = { S900_MUX_SD1,697 S900_MUX_ERAM };698/* mfp2_8_7 */699static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };700static unsigned int sd0_cmd_mfp_funcs[] = { S900_MUX_SD0,701 S900_MUX_ERAM,702 S900_MUX_GPU,703 S900_MUX_JTAG };704/* mfp2_6_5 */705static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };706static unsigned int sd0_clk_mfp_funcs[] = { S900_MUX_SD0,707 S900_MUX_ERAM,708 S900_MUX_JTAG,709 S900_MUX_GPU };710/* mfp2_4_3 */711static unsigned int sd1_cmd_clk_mfp_pads[] = { SD1_CMD, SD1_CLK };712static unsigned int sd1_cmd_clk_mfp_funcs[] = { S900_MUX_SD1,713 S900_MUX_ERAM };714/* mfp2_2_0 */715static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };716static unsigned int uart0_rx_mfp_funcs[] = { S900_MUX_UART0,717 S900_MUX_UART2,718 S900_MUX_SPI1,719 S900_MUX_I2C5,720 S900_MUX_PCM1,721 S900_MUX_I2S1 };722/* mfp3_27 */723static unsigned int nand0_d0_ceb3_mfp_pads[] = { NAND0_D0, NAND0_D1,724 NAND0_D2, NAND0_D3,725 NAND0_D4, NAND0_D5,726 NAND0_D6, NAND0_D7,727 NAND0_DQSN, NAND0_CEB3 };728static unsigned int nand0_d0_ceb3_mfp_funcs[] = { S900_MUX_NAND0,729 S900_MUX_SD2 };730/* mfp3_21_19 */731static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };732static unsigned int uart0_tx_mfp_funcs[] = { S900_MUX_UART0,733 S900_MUX_UART2,734 S900_MUX_SPI1,735 S900_MUX_I2C5,736 S900_MUX_SPDIF,737 S900_MUX_PCM1,738 S900_MUX_I2S1 };739/* mfp3_18_16 */740static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK, I2C0_SDATA };741static unsigned int i2c0_mfp_funcs[] = { S900_MUX_I2C0,742 S900_MUX_UART2,743 S900_MUX_I2C1,744 S900_MUX_UART1,745 S900_MUX_SPI1 };746/* mfp3_15 */747static unsigned int csi0_cn_cp_mfp_pads[] = { CSI0_CN, CSI0_CP };748static unsigned int csi0_cn_cp_mfp_funcs[] = { S900_MUX_SENS0,749 S900_MUX_SENS0 };750/* mfp3_14 */751static unsigned int csi0_dn0_dp3_mfp_pads[] = { CSI0_DN0, CSI0_DP0,752 CSI0_DN1, CSI0_DP1,753 CSI0_CN, CSI0_CP,754 CSI0_DP2, CSI0_DN2,755 CSI0_DN3, CSI0_DP3 };756static unsigned int csi0_dn0_dp3_mfp_funcs[] = { S900_MUX_MIPI_CSI0,757 S900_MUX_SENS0 };758/* mfp3_13 */759static unsigned int csi1_dn0_cp_mfp_pads[] = { CSI1_DN0, CSI1_DP0,760 CSI1_DN1, CSI1_DP1,761 CSI1_CN, CSI1_CP };762static unsigned int csi1_dn0_cp_mfp_funcs[] = { S900_MUX_MIPI_CSI1,763 S900_MUX_SENS0 };764/* mfp3_12_dsi */765static unsigned int dsi_dp3_dn1_mfp_pads[] = { DSI_DP3, DSI_DN2,766 DSI_DP1, DSI_DN1 };767static unsigned int dsi_dp3_dn1_mfp_funcs[] = { S900_MUX_MIPI_DSI,768 S900_MUX_UART2 };769static unsigned int dsi_cp_dn0_mfp_pads[] = { DSI_CP, DSI_CN,770 DSI_DP0, DSI_DN0 };771static unsigned int dsi_cp_dn0_mfp_funcs[] = { S900_MUX_MIPI_DSI,772 S900_MUX_PCM1 };773static unsigned int dsi_dp2_dn2_mfp_pads[] = { DSI_DP2, DSI_DN2 };774static unsigned int dsi_dp2_dn2_mfp_funcs[] = { S900_MUX_MIPI_DSI,775 S900_MUX_UART4 };776/* mfp3_11 */777static unsigned int nand1_d0_ceb1_mfp_pads[] = { NAND1_D0, NAND1_D1,778 NAND1_D2, NAND1_D3,779 NAND1_D4, NAND1_D5,780 NAND1_D6, NAND1_D7,781 NAND1_DQSN, NAND1_CEB1 };782static unsigned int nand1_d0_ceb1_mfp_funcs[] = { S900_MUX_NAND1,783 S900_MUX_SD3 };784/* mfp3_10 */785static unsigned int nand1_ceb3_mfp_pads[] = { NAND1_CEB3 };786static unsigned int nand1_ceb3_mfp_funcs[] = { S900_MUX_NAND1,787 S900_MUX_PWM0 };788static unsigned int nand1_ceb0_mfp_pads[] = { NAND1_CEB0 };789static unsigned int nand1_ceb0_mfp_funcs[] = { S900_MUX_NAND1,790 S900_MUX_PWM1 };791/* mfp3_9 */792static unsigned int csi1_dn0_dp0_mfp_pads[] = { CSI1_DN0, CSI1_DP0 };793static unsigned int csi1_dn0_dp0_mfp_funcs[] = { S900_MUX_SENS0,794 S900_MUX_SENS0 };795/* mfp3_8 */796static unsigned int uart4_rx_tx_mfp_pads[] = { UART4_RX, UART4_TX };797static unsigned int uart4_rx_tx_mfp_funcs[] = { S900_MUX_UART4,798 S900_MUX_I2C4 };799/* PADDRV group data */800/* drv0 */801static unsigned int sgpio3_drv_pads[] = { SGPIO3 };802static unsigned int sgpio2_drv_pads[] = { SGPIO2 };803static unsigned int sgpio1_drv_pads[] = { SGPIO1 };804static unsigned int sgpio0_drv_pads[] = { SGPIO0 };805static unsigned int rmii_tx_d0_d1_drv_pads[] = { ETH_TXD0, ETH_TXD1 };806static unsigned int rmii_txen_rxer_drv_pads[] = { ETH_TXEN, ETH_RXER };807static unsigned int rmii_crs_dv_drv_pads[] = { ETH_CRS_DV };808static unsigned int rmii_rx_d1_d0_drv_pads[] = { ETH_RXD1, ETH_RXD0 };809static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK };810static unsigned int rmii_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO };811static unsigned int sirq_0_1_drv_pads[] = { SIRQ0, SIRQ1 };812static unsigned int sirq2_drv_pads[] = { SIRQ2 };813static unsigned int i2s_d0_d1_drv_pads[] = { I2S_D0, I2S_D1 };814static unsigned int i2s_lr_m_clk0_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0 };815static unsigned int i2s_blk1_mclk1_drv_pads[] = { I2S_BCLK0, I2S_BCLK1,816 I2S_LRCLK1, I2S_MCLK1 };817static unsigned int pcm1_in_out_drv_pads[] = { PCM1_IN, PCM1_CLK,818 PCM1_SYNC, PCM1_OUT };819/* drv1 */820static unsigned int lvds_oap_oan_drv_pads[] = { LVDS_OAP, LVDS_OAN };821static unsigned int lvds_oep_odn_drv_pads[] = { LVDS_OEP, LVDS_OEN,822 LVDS_ODP, LVDS_ODN };823static unsigned int lvds_ocp_obn_drv_pads[] = { LVDS_OCP, LVDS_OCN,824 LVDS_OBP, LVDS_OBN };825static unsigned int lvds_e_drv_pads[] = { LVDS_EEP, LVDS_EEN,826 LVDS_EDP, LVDS_EDN,827 LVDS_ECP, LVDS_ECN,828 LVDS_EBP, LVDS_EBN };829static unsigned int sd0_d3_d0_drv_pads[] = { SD0_D3, SD0_D2,830 SD0_D1, SD0_D0 };831static unsigned int sd1_d3_d0_drv_pads[] = { SD1_D3, SD1_D2,832 SD1_D1, SD1_D0 };833static unsigned int sd0_sd1_cmd_clk_drv_pads[] = { SD0_CLK, SD0_CMD,834 SD1_CLK, SD1_CMD };835static unsigned int spi0_sclk_mosi_drv_pads[] = { SPI0_SCLK, SPI0_MOSI };836static unsigned int spi0_ss_miso_drv_pads[] = { SPI0_SS, SPI0_MISO };837static unsigned int uart0_rx_tx_drv_pads[] = { UART0_RX, UART0_TX };838static unsigned int uart4_rx_tx_drv_pads[] = { UART4_RX, UART4_TX };839static unsigned int uart2_drv_pads[] = { UART2_RX, UART2_TX,840 UART2_RTSB, UART2_CTSB };841static unsigned int uart3_drv_pads[] = { UART3_RX, UART3_TX,842 UART3_RTSB, UART3_CTSB };843/* drv2 */844static unsigned int i2c0_drv_pads[] = { I2C0_SCLK, I2C0_SDATA };845static unsigned int i2c1_drv_pads[] = { I2C1_SCLK, I2C1_SDATA };846static unsigned int i2c2_drv_pads[] = { I2C2_SCLK, I2C2_SDATA };847static unsigned int sensor0_drv_pads[] = { SENSOR0_PCLK,848 SENSOR0_CKOUT };849/* SR group data */850/* sr0 */851static unsigned int sgpio3_sr_pads[] = { SGPIO3 };852static unsigned int sgpio2_sr_pads[] = { SGPIO2 };853static unsigned int sgpio1_sr_pads[] = { SGPIO1 };854static unsigned int sgpio0_sr_pads[] = { SGPIO0 };855static unsigned int rmii_tx_d0_d1_sr_pads[] = { ETH_TXD0, ETH_TXD1 };856static unsigned int rmii_txen_rxer_sr_pads[] = { ETH_TXEN, ETH_RXER };857static unsigned int rmii_crs_dv_sr_pads[] = { ETH_CRS_DV };858static unsigned int rmii_rx_d1_d0_sr_pads[] = { ETH_RXD1, ETH_RXD0 };859static unsigned int rmii_ref_clk_sr_pads[] = { ETH_REF_CLK };860static unsigned int rmii_mdc_mdio_sr_pads[] = { ETH_MDC, ETH_MDIO };861static unsigned int sirq_0_1_sr_pads[] = { SIRQ0, SIRQ1 };862static unsigned int sirq2_sr_pads[] = { SIRQ2 };863static unsigned int i2s_do_d1_sr_pads[] = { I2S_D0, I2S_D1 };864static unsigned int i2s_lr_m_clk0_sr_pads[] = { I2S_LRCLK0, I2S_MCLK0 };865static unsigned int i2s_bclk0_mclk1_sr_pads[] = { I2S_BCLK0, I2S_BCLK1,866 I2S_LRCLK1, I2S_MCLK1 };867static unsigned int pcm1_in_out_sr_pads[] = { PCM1_IN, PCM1_CLK,868 PCM1_SYNC, PCM1_OUT };869/* sr1 */870static unsigned int sd1_d3_d0_sr_pads[] = { SD1_D3, SD1_D2,871 SD1_D1, SD1_D0 };872static unsigned int sd0_sd1_clk_cmd_sr_pads[] = { SD0_CLK, SD0_CMD,873 SD1_CLK, SD1_CMD };874static unsigned int spi0_sclk_mosi_sr_pads[] = { SPI0_SCLK, SPI0_MOSI };875static unsigned int spi0_ss_miso_sr_pads[] = { SPI0_SS, SPI0_MISO };876static unsigned int uart0_rx_tx_sr_pads[] = { UART0_RX, UART0_TX };877static unsigned int uart4_rx_tx_sr_pads[] = { UART4_RX, UART4_TX };878static unsigned int uart2_sr_pads[] = { UART2_RX, UART2_TX,879 UART2_RTSB, UART2_CTSB };880static unsigned int uart3_sr_pads[] = { UART3_RX, UART3_TX,881 UART3_RTSB, UART3_CTSB };882/* sr2 */883static unsigned int i2c0_sr_pads[] = { I2C0_SCLK, I2C0_SDATA };884static unsigned int i2c1_sr_pads[] = { I2C1_SCLK, I2C1_SDATA };885static unsigned int i2c2_sr_pads[] = { I2C2_SCLK, I2C2_SDATA };886static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK,887 SENSOR0_CKOUT };888 889 890/* Pinctrl groups */891static const struct owl_pingroup s900_groups[] = {892 MUX_PG(lvds_oxx_uart4_mfp, 0, 22, 1),893 MUX_PG(rmii_mdc_mfp, 0, 20, 2),894 MUX_PG(rmii_mdio_mfp, 0, 20, 2),895 MUX_PG(sirq0_mfp, 0, 19, 1),896 MUX_PG(sirq1_mfp, 0, 19, 1),897 MUX_PG(rmii_txd0_mfp, 0, 16, 3),898 MUX_PG(rmii_txd1_mfp, 0, 16, 3),899 MUX_PG(rmii_txen_mfp, 0, 13, 3),900 MUX_PG(rmii_rxer_mfp, 0, 13, 3),901 MUX_PG(rmii_crs_dv_mfp, 0, 11, 2),902 MUX_PG(rmii_rxd1_mfp, 0, 8, 3),903 MUX_PG(rmii_rxd0_mfp, 0, 8, 3),904 MUX_PG(rmii_ref_clk_mfp, 0, 6, 2),905 MUX_PG(i2s_d0_mfp, 0, 5, 1),906 MUX_PG(i2s_d1_mfp, 0, 5, 1),907 MUX_PG(i2s_lr_m_clk0_mfp, 0, 3, 2),908 MUX_PG(i2s_bclk0_mfp, 0, 2, 1),909 MUX_PG(i2s_bclk1_mclk1_mfp, 0, 2, 1),910 MUX_PG(pcm1_in_out_mfp, 0, 0, 2),911 MUX_PG(pcm1_clk_mfp, 0, 0, 2),912 MUX_PG(pcm1_sync_mfp, 0, 0, 2),913 MUX_PG(eram_a5_mfp, 1, 29, 3),914 MUX_PG(eram_a6_mfp, 1, 29, 3),915 MUX_PG(eram_a7_mfp, 1, 29, 3),916 MUX_PG(eram_a8_mfp, 1, 26, 3),917 MUX_PG(eram_a9_mfp, 1, 26, 3),918 MUX_PG(eram_a10_mfp, 1, 26, 3),919 MUX_PG(eram_a11_mfp, 1, 23, 3),920 MUX_PG(lvds_oep_odn_mfp, 1, 22, 1),921 MUX_PG(lvds_ocp_obn_mfp, 1, 22, 1),922 MUX_PG(lvds_oap_oan_mfp, 1, 22, 1),923 MUX_PG(lvds_e_mfp, 1, 21, 1),924 MUX_PG(spi0_sclk_mosi_mfp, 1, 4, 2),925 MUX_PG(spi0_ss_mfp, 1, 1, 3),926 MUX_PG(spi0_miso_mfp, 1, 1, 3),927 MUX_PG(uart2_rtsb_mfp, 2, 23, 1),928 MUX_PG(uart2_ctsb_mfp, 2, 22, 1),929 MUX_PG(uart3_rtsb_mfp, 2, 21, 1),930 MUX_PG(uart3_ctsb_mfp, 2, 20, 1),931 MUX_PG(sd0_d0_mfp, 2, 17, 3),932 MUX_PG(sd0_d1_mfp, 2, 14, 3),933 MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),934 MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),935 MUX_PG(sd0_cmd_mfp, 2, 7, 2),936 MUX_PG(sd0_clk_mfp, 2, 5, 2),937 MUX_PG(sd1_cmd_clk_mfp, 2, 3, 2),938 MUX_PG(uart0_rx_mfp, 2, 0, 3),939 MUX_PG(nand0_d0_ceb3_mfp, 3, 27, 1),940 MUX_PG(uart0_tx_mfp, 3, 19, 3),941 MUX_PG(i2c0_mfp, 3, 16, 3),942 MUX_PG(csi0_cn_cp_mfp, 3, 15, 1),943 MUX_PG(csi0_dn0_dp3_mfp, 3, 14, 1),944 MUX_PG(csi1_dn0_cp_mfp, 3, 13, 1),945 MUX_PG(dsi_dp3_dn1_mfp, 3, 12, 1),946 MUX_PG(dsi_cp_dn0_mfp, 3, 12, 1),947 MUX_PG(dsi_dp2_dn2_mfp, 3, 12, 1),948 MUX_PG(nand1_d0_ceb1_mfp, 3, 11, 1),949 MUX_PG(nand1_ceb3_mfp, 3, 10, 1),950 MUX_PG(nand1_ceb0_mfp, 3, 10, 1),951 MUX_PG(csi1_dn0_dp0_mfp, 3, 9, 1),952 MUX_PG(uart4_rx_tx_mfp, 3, 8, 1),953 954 DRV_PG(sgpio3_drv, 0, 30, 2),955 DRV_PG(sgpio2_drv, 0, 28, 2),956 DRV_PG(sgpio1_drv, 0, 26, 2),957 DRV_PG(sgpio0_drv, 0, 24, 2),958 DRV_PG(rmii_tx_d0_d1_drv, 0, 22, 2),959 DRV_PG(rmii_txen_rxer_drv, 0, 20, 2),960 DRV_PG(rmii_crs_dv_drv, 0, 18, 2),961 DRV_PG(rmii_rx_d1_d0_drv, 0, 16, 2),962 DRV_PG(rmii_ref_clk_drv, 0, 14, 2),963 DRV_PG(rmii_mdc_mdio_drv, 0, 12, 2),964 DRV_PG(sirq_0_1_drv, 0, 10, 2),965 DRV_PG(sirq2_drv, 0, 8, 2),966 DRV_PG(i2s_d0_d1_drv, 0, 6, 2),967 DRV_PG(i2s_lr_m_clk0_drv, 0, 4, 2),968 DRV_PG(i2s_blk1_mclk1_drv, 0, 2, 2),969 DRV_PG(pcm1_in_out_drv, 0, 0, 2),970 DRV_PG(lvds_oap_oan_drv, 1, 28, 2),971 DRV_PG(lvds_oep_odn_drv, 1, 26, 2),972 DRV_PG(lvds_ocp_obn_drv, 1, 24, 2),973 DRV_PG(lvds_e_drv, 1, 22, 2),974 DRV_PG(sd0_d3_d0_drv, 1, 20, 2),975 DRV_PG(sd1_d3_d0_drv, 1, 18, 2),976 DRV_PG(sd0_sd1_cmd_clk_drv, 1, 16, 2),977 DRV_PG(spi0_sclk_mosi_drv, 1, 14, 2),978 DRV_PG(spi0_ss_miso_drv, 1, 12, 2),979 DRV_PG(uart0_rx_tx_drv, 1, 10, 2),980 DRV_PG(uart4_rx_tx_drv, 1, 8, 2),981 DRV_PG(uart2_drv, 1, 6, 2),982 DRV_PG(uart3_drv, 1, 4, 2),983 DRV_PG(i2c0_drv, 2, 30, 2),984 DRV_PG(i2c1_drv, 2, 28, 2),985 DRV_PG(i2c2_drv, 2, 26, 2),986 DRV_PG(sensor0_drv, 2, 20, 2),987 988 SR_PG(sgpio3_sr, 0, 15, 1),989 SR_PG(sgpio2_sr, 0, 14, 1),990 SR_PG(sgpio1_sr, 0, 13, 1),991 SR_PG(sgpio0_sr, 0, 12, 1),992 SR_PG(rmii_tx_d0_d1_sr, 0, 11, 1),993 SR_PG(rmii_txen_rxer_sr, 0, 10, 1),994 SR_PG(rmii_crs_dv_sr, 0, 9, 1),995 SR_PG(rmii_rx_d1_d0_sr, 0, 8, 1),996 SR_PG(rmii_ref_clk_sr, 0, 7, 1),997 SR_PG(rmii_mdc_mdio_sr, 0, 6, 1),998 SR_PG(sirq_0_1_sr, 0, 5, 1),999 SR_PG(sirq2_sr, 0, 4, 1),1000 SR_PG(i2s_do_d1_sr, 0, 3, 1),1001 SR_PG(i2s_lr_m_clk0_sr, 0, 2, 1),1002 SR_PG(i2s_bclk0_mclk1_sr, 0, 1, 1),1003 SR_PG(pcm1_in_out_sr, 0, 0, 1),1004 SR_PG(sd1_d3_d0_sr, 1, 25, 1),1005 SR_PG(sd0_sd1_clk_cmd_sr, 1, 24, 1),1006 SR_PG(spi0_sclk_mosi_sr, 1, 23, 1),1007 SR_PG(spi0_ss_miso_sr, 1, 22, 1),1008 SR_PG(uart0_rx_tx_sr, 1, 21, 1),1009 SR_PG(uart4_rx_tx_sr, 1, 20, 1),1010 SR_PG(uart2_sr, 1, 19, 1),1011 SR_PG(uart3_sr, 1, 18, 1),1012 SR_PG(i2c0_sr, 2, 31, 1),1013 SR_PG(i2c1_sr, 2, 30, 1),1014 SR_PG(i2c2_sr, 2, 29, 1),1015 SR_PG(sensor0_sr, 2, 25, 1)1016};1017 1018static const char * const eram_groups[] = {1019 "lvds_oxx_uart4_mfp",1020 "eram_a5_mfp",1021 "eram_a6_mfp",1022 "eram_a7_mfp",1023 "eram_a8_mfp",1024 "eram_a9_mfp",1025 "eram_a10_mfp",1026 "eram_a11_mfp",1027 "lvds_oap_oan_mfp",1028 "lvds_e_mfp",1029 "spi0_sclk_mosi_mfp",1030 "spi0_ss_mfp",1031 "spi0_miso_mfp",1032 "sd0_d0_mfp",1033 "sd0_d1_mfp",1034 "sd0_d2_d3_mfp",1035 "sd1_d0_d3_mfp",1036 "sd0_cmd_mfp",1037 "sd0_clk_mfp",1038 "sd1_cmd_clk_mfp",1039};1040 1041static const char * const eth_rmii_groups[] = {1042 "rmii_mdc_mfp",1043 "rmii_mdio_mfp",1044 "rmii_txd0_mfp",1045 "rmii_txd1_mfp",1046 "rmii_txen_mfp",1047 "rmii_rxer_mfp",1048 "rmii_crs_dv_mfp",1049 "rmii_rxd1_mfp",1050 "rmii_rxd0_mfp",1051 "rmii_ref_clk_mfp",1052 "eth_smi_dummy",1053};1054 1055static const char * const eth_smii_groups[] = {1056 "rmii_txd0_mfp",1057 "rmii_txd1_mfp",1058 "rmii_crs_dv_mfp",1059 "eth_smi_dummy",1060};1061 1062static const char * const spi0_groups[] = {1063 "spi0_sclk_mosi_mfp",1064 "spi0_ss_mfp",1065 "spi0_miso_mfp",1066 "spi0_sclk_mosi_mfp",1067 "spi0_ss_mfp",1068 "spi0_miso_mfp",1069};1070 1071static const char * const spi1_groups[] = {1072 "pcm1_in_out_mfp",1073 "pcm1_clk_mfp",1074 "pcm1_sync_mfp",1075 "uart0_rx_mfp",1076 "uart0_tx_mfp",1077 "i2c0_mfp",1078};1079 1080static const char * const spi2_groups[] = {1081 "rmii_txd0_mfp",1082 "rmii_txd1_mfp",1083 "rmii_crs_dv_mfp",1084 "rmii_ref_clk_mfp",1085};1086 1087static const char * const spi3_groups[] = {1088 "rmii_txen_mfp",1089 "rmii_rxer_mfp",1090};1091 1092static const char * const sens0_groups[] = {1093 "rmii_txd0_mfp",1094 "rmii_txd1_mfp",1095 "rmii_txen_mfp",1096 "rmii_rxer_mfp",1097 "rmii_rxd1_mfp",1098 "rmii_rxd0_mfp",1099 "eram_a5_mfp",1100 "eram_a6_mfp",1101 "eram_a7_mfp",1102 "eram_a8_mfp",1103 "eram_a9_mfp",1104 "csi0_cn_cp_mfp",1105 "csi0_dn0_dp3_mfp",1106 "csi1_dn0_cp_mfp",1107 "csi1_dn0_dp0_mfp",1108};1109 1110static const char * const uart0_groups[] = {1111 "uart2_rtsb_mfp",1112 "uart2_ctsb_mfp",1113 "uart0_rx_mfp",1114 "uart0_tx_mfp",1115};1116 1117static const char * const uart1_groups[] = {1118 "sd0_d2_d3_mfp",1119 "i2c0_mfp",1120};1121 1122static const char * const uart2_groups[] = {1123 "rmii_mdc_mfp",1124 "rmii_mdio_mfp",1125 "rmii_txen_mfp",1126 "rmii_rxer_mfp",1127 "rmii_rxd1_mfp",1128 "rmii_rxd0_mfp",1129 "lvds_oep_odn_mfp",1130 "uart2_rtsb_mfp",1131 "uart2_ctsb_mfp",1132 "sd0_d0_mfp",1133 "sd0_d1_mfp",1134 "sd0_d2_d3_mfp",1135 "uart0_rx_mfp",1136 "uart0_tx_mfp_pads",1137 "i2c0_mfp_pads",1138 "dsi_dp3_dn1_mfp",1139 "uart2_dummy"1140};1141 1142static const char * const uart3_groups[] = {1143 "uart3_rtsb_mfp",1144 "uart3_ctsb_mfp",1145 "uart3_dummy"1146};1147 1148static const char * const uart4_groups[] = {1149 "lvds_oxx_uart4_mfp",1150 "rmii_crs_dv_mfp",1151 "rmii_ref_clk_mfp",1152 "pcm1_in_out_mfp",1153 "pcm1_clk_mfp",1154 "pcm1_sync_mfp",1155 "eram_a5_mfp",1156 "eram_a6_mfp",1157 "dsi_dp2_dn2_mfp",1158 "uart4_rx_tx_mfp_pads",1159 "uart4_dummy"1160};1161 1162static const char * const uart5_groups[] = {1163 "rmii_rxd1_mfp",1164 "rmii_rxd0_mfp",1165 "eram_a9_mfp",1166 "eram_a11_mfp",1167 "uart3_rtsb_mfp",1168 "uart3_ctsb_mfp",1169 "sd0_d0_mfp",1170 "sd0_d1_mfp",1171};1172 1173static const char * const uart6_groups[] = {1174 "rmii_txd0_mfp",1175 "rmii_txd1_mfp",1176};1177 1178static const char * const i2s0_groups[] = {1179 "i2s_d0_mfp",1180 "i2s_lr_m_clk0_mfp",1181 "i2s_bclk0_mfp",1182 "i2s0_dummy",1183};1184 1185static const char * const i2s1_groups[] = {1186 "i2s_d1_mfp",1187 "i2s_bclk1_mclk1_mfp",1188 "spi0_ss_mfp",1189 "spi0_miso_mfp",1190 "uart0_rx_mfp",1191 "uart0_tx_mfp",1192 "i2s1_dummy",1193};1194 1195static const char * const pcm0_groups[] = {1196 "i2s_d0_mfp",1197 "i2s_d1_mfp",1198 "i2s_lr_m_clk0_mfp",1199 "i2s_bclk0_mfp",1200 "i2s_bclk1_mclk1_mfp",1201 "spi0_sclk_mosi_mfp",1202 "spi0_ss_mfp",1203 "spi0_miso_mfp",1204};1205 1206static const char * const pcm1_groups[] = {1207 "i2s_lr_m_clk0_mfp",1208 "pcm1_in_out_mfp",1209 "pcm1_clk_mfp",1210 "pcm1_sync_mfp",1211 "lvds_oep_odn_mfp",1212 "spi0_ss_mfp",1213 "spi0_miso_mfp",1214 "uart0_rx_mfp",1215 "uart0_tx_mfp",1216 "dsi_cp_dn0_mfp",1217 "pcm1_dummy",1218};1219 1220static const char * const jtag_groups[] = {1221 "eram_a5_mfp",1222 "eram_a6_mfp",1223 "eram_a7_mfp",1224 "eram_a8_mfp",1225 "eram_a10_mfp",1226 "eram_a10_mfp",1227 "sd0_d2_d3_mfp",1228 "sd0_cmd_mfp",1229 "sd0_clk_mfp",1230};1231 1232static const char * const pwm0_groups[] = {1233 "sirq0_mfp",1234 "rmii_txd0_mfp",1235 "rmii_rxd1_mfp",1236 "eram_a5_mfp",1237 "nand1_ceb3_mfp",1238};1239 1240static const char * const pwm1_groups[] = {1241 "sirq1_mfp",1242 "rmii_txd1_mfp",1243 "rmii_rxd0_mfp",1244 "eram_a6_mfp",1245 "eram_a8_mfp",1246 "nand1_ceb0_mfp",1247};1248 1249static const char * const pwm2_groups[] = {1250 "rmii_mdc_mfp",1251 "rmii_txen_mfp",1252 "eram_a9_mfp",1253 "eram_a11_mfp",1254};1255 1256static const char * const pwm3_groups[] = {1257 "rmii_mdio_mfp",1258 "rmii_rxer_mfp",1259 "eram_a10_mfp",1260};1261 1262static const char * const pwm4_groups[] = {1263 "pcm1_clk_mfp",1264 "spi0_ss_mfp",1265};1266 1267static const char * const pwm5_groups[] = {1268 "pcm1_sync_mfp",1269 "spi0_miso_mfp",1270};1271 1272static const char * const sd0_groups[] = {1273 "sd0_d0_mfp",1274 "sd0_d1_mfp",1275 "sd0_d2_d3_mfp",1276 "sd0_cmd_mfp",1277 "sd0_clk_mfp",1278};1279 1280static const char * const sd1_groups[] = {1281 "sd1_d0_d3_mfp",1282 "sd1_cmd_clk_mfp",1283 "sd1_dummy",1284};1285 1286static const char * const sd2_groups[] = {1287 "nand0_d0_ceb3_mfp",1288};1289 1290static const char * const sd3_groups[] = {1291 "nand1_d0_ceb1_mfp",1292};1293 1294static const char * const i2c0_groups[] = {1295 "i2c0_mfp",1296};1297 1298static const char * const i2c1_groups[] = {1299 "i2c0_mfp",1300 "i2c1_dummy"1301};1302 1303static const char * const i2c2_groups[] = {1304 "i2c2_dummy"1305};1306 1307static const char * const i2c3_groups[] = {1308 "pcm1_in_out_mfp",1309 "spi0_sclk_mosi_mfp",1310};1311 1312static const char * const i2c4_groups[] = {1313 "uart4_rx_tx_mfp",1314};1315 1316static const char * const i2c5_groups[] = {1317 "uart0_rx_mfp",1318 "uart0_tx_mfp",1319};1320 1321 1322static const char * const lvds_groups[] = {1323 "lvds_oep_odn_mfp",1324 "lvds_ocp_obn_mfp",1325 "lvds_oap_oan_mfp",1326 "lvds_e_mfp",1327};1328 1329static const char * const usb20_groups[] = {1330 "eram_a9_mfp",1331};1332 1333static const char * const usb30_groups[] = {1334 "eram_a10_mfp",1335};1336 1337static const char * const gpu_groups[] = {1338 "sd0_d0_mfp",1339 "sd0_d1_mfp",1340 "sd0_d2_d3_mfp",1341 "sd0_cmd_mfp",1342 "sd0_clk_mfp",1343};1344 1345static const char * const mipi_csi0_groups[] = {1346 "csi0_dn0_dp3_mfp",1347};1348 1349static const char * const mipi_csi1_groups[] = {1350 "csi1_dn0_cp_mfp",1351};1352 1353static const char * const mipi_dsi_groups[] = {1354 "dsi_dp3_dn1_mfp",1355 "dsi_cp_dn0_mfp",1356 "dsi_dp2_dn2_mfp",1357 "mipi_dsi_dummy",1358};1359 1360static const char * const nand0_groups[] = {1361 "nand0_d0_ceb3_mfp",1362 "nand0_dummy",1363};1364 1365static const char * const nand1_groups[] = {1366 "nand1_d0_ceb1_mfp",1367 "nand1_ceb3_mfp",1368 "nand1_ceb0_mfp",1369 "nand1_dummy",1370};1371 1372static const char * const spdif_groups[] = {1373 "uart0_tx_mfp",1374};1375 1376static const char * const sirq0_groups[] = {1377 "sirq0_mfp",1378 "sirq0_dummy",1379};1380 1381static const char * const sirq1_groups[] = {1382 "sirq1_mfp",1383 "sirq1_dummy",1384};1385 1386static const char * const sirq2_groups[] = {1387 "sirq2_dummy",1388};1389 1390static const struct owl_pinmux_func s900_functions[] = {1391 [S900_MUX_ERAM] = FUNCTION(eram),1392 [S900_MUX_ETH_RMII] = FUNCTION(eth_rmii),1393 [S900_MUX_ETH_SMII] = FUNCTION(eth_smii),1394 [S900_MUX_SPI0] = FUNCTION(spi0),1395 [S900_MUX_SPI1] = FUNCTION(spi1),1396 [S900_MUX_SPI2] = FUNCTION(spi2),1397 [S900_MUX_SPI3] = FUNCTION(spi3),1398 [S900_MUX_SENS0] = FUNCTION(sens0),1399 [S900_MUX_UART0] = FUNCTION(uart0),1400 [S900_MUX_UART1] = FUNCTION(uart1),1401 [S900_MUX_UART2] = FUNCTION(uart2),1402 [S900_MUX_UART3] = FUNCTION(uart3),1403 [S900_MUX_UART4] = FUNCTION(uart4),1404 [S900_MUX_UART5] = FUNCTION(uart5),1405 [S900_MUX_UART6] = FUNCTION(uart6),1406 [S900_MUX_I2S0] = FUNCTION(i2s0),1407 [S900_MUX_I2S1] = FUNCTION(i2s1),1408 [S900_MUX_PCM0] = FUNCTION(pcm0),1409 [S900_MUX_PCM1] = FUNCTION(pcm1),1410 [S900_MUX_JTAG] = FUNCTION(jtag),1411 [S900_MUX_PWM0] = FUNCTION(pwm0),1412 [S900_MUX_PWM1] = FUNCTION(pwm1),1413 [S900_MUX_PWM2] = FUNCTION(pwm2),1414 [S900_MUX_PWM3] = FUNCTION(pwm3),1415 [S900_MUX_PWM4] = FUNCTION(pwm4),1416 [S900_MUX_PWM5] = FUNCTION(pwm5),1417 [S900_MUX_SD0] = FUNCTION(sd0),1418 [S900_MUX_SD1] = FUNCTION(sd1),1419 [S900_MUX_SD2] = FUNCTION(sd2),1420 [S900_MUX_SD3] = FUNCTION(sd3),1421 [S900_MUX_I2C0] = FUNCTION(i2c0),1422 [S900_MUX_I2C1] = FUNCTION(i2c1),1423 [S900_MUX_I2C2] = FUNCTION(i2c2),1424 [S900_MUX_I2C3] = FUNCTION(i2c3),1425 [S900_MUX_I2C4] = FUNCTION(i2c4),1426 [S900_MUX_I2C5] = FUNCTION(i2c5),1427 [S900_MUX_LVDS] = FUNCTION(lvds),1428 [S900_MUX_USB30] = FUNCTION(usb30),1429 [S900_MUX_USB20] = FUNCTION(usb20),1430 [S900_MUX_GPU] = FUNCTION(gpu),1431 [S900_MUX_MIPI_CSI0] = FUNCTION(mipi_csi0),1432 [S900_MUX_MIPI_CSI1] = FUNCTION(mipi_csi1),1433 [S900_MUX_MIPI_DSI] = FUNCTION(mipi_dsi),1434 [S900_MUX_NAND0] = FUNCTION(nand0),1435 [S900_MUX_NAND1] = FUNCTION(nand1),1436 [S900_MUX_SPDIF] = FUNCTION(spdif),1437 [S900_MUX_SIRQ0] = FUNCTION(sirq0),1438 [S900_MUX_SIRQ1] = FUNCTION(sirq1),1439 [S900_MUX_SIRQ2] = FUNCTION(sirq2)1440};1441 1442/* PAD_PULLCTL0 */1443static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2);1444static PAD_PULLCTL_CONF(SIRQ0, 0, 16, 2);1445static PAD_PULLCTL_CONF(SIRQ1, 0, 14, 2);1446static PAD_PULLCTL_CONF(SIRQ2, 0, 12, 2);1447static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 10, 2);1448static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 2);1449static PAD_PULLCTL_CONF(ERAM_A5, 0, 6, 2);1450static PAD_PULLCTL_CONF(ERAM_A6, 0, 4, 2);1451static PAD_PULLCTL_CONF(ERAM_A7, 0, 2, 2);1452static PAD_PULLCTL_CONF(ERAM_A10, 0, 0, 2);1453 1454/* PAD_PULLCTL1 */1455static PAD_PULLCTL_CONF(PCM1_IN, 1, 30, 2);1456static PAD_PULLCTL_CONF(PCM1_OUT, 1, 28, 2);1457static PAD_PULLCTL_CONF(SD0_D0, 1, 26, 2);1458static PAD_PULLCTL_CONF(SD0_D1, 1, 24, 2);1459static PAD_PULLCTL_CONF(SD0_D2, 1, 22, 2);1460static PAD_PULLCTL_CONF(SD0_D3, 1, 20, 2);1461static PAD_PULLCTL_CONF(SD0_CMD, 1, 18, 2);1462static PAD_PULLCTL_CONF(SD0_CLK, 1, 16, 2);1463static PAD_PULLCTL_CONF(SD1_CMD, 1, 14, 2);1464static PAD_PULLCTL_CONF(SD1_D0, 1, 12, 2);1465static PAD_PULLCTL_CONF(SD1_D1, 1, 10, 2);1466static PAD_PULLCTL_CONF(SD1_D2, 1, 8, 2);1467static PAD_PULLCTL_CONF(SD1_D3, 1, 6, 2);1468static PAD_PULLCTL_CONF(UART0_RX, 1, 4, 2);1469static PAD_PULLCTL_CONF(UART0_TX, 1, 2, 2);1470 1471/* PAD_PULLCTL2 */1472static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 26, 2);1473static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 24, 2);1474static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 22, 2);1475static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 20, 2);1476static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 18, 2);1477static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 16, 2);1478static PAD_PULLCTL_CONF(NAND0_D0, 2, 15, 1);1479static PAD_PULLCTL_CONF(NAND0_D1, 2, 15, 1);1480static PAD_PULLCTL_CONF(NAND0_D2, 2, 15, 1);1481static PAD_PULLCTL_CONF(NAND0_D3, 2, 15, 1);1482static PAD_PULLCTL_CONF(NAND0_D4, 2, 15, 1);1483static PAD_PULLCTL_CONF(NAND0_D5, 2, 15, 1);1484static PAD_PULLCTL_CONF(NAND0_D6, 2, 15, 1);1485static PAD_PULLCTL_CONF(NAND0_D7, 2, 15, 1);1486static PAD_PULLCTL_CONF(NAND0_DQSN, 2, 14, 1);1487static PAD_PULLCTL_CONF(NAND0_DQS, 2, 13, 1);1488static PAD_PULLCTL_CONF(NAND1_D0, 2, 12, 1);1489static PAD_PULLCTL_CONF(NAND1_D1, 2, 12, 1);1490static PAD_PULLCTL_CONF(NAND1_D2, 2, 12, 1);1491static PAD_PULLCTL_CONF(NAND1_D3, 2, 12, 1);1492static PAD_PULLCTL_CONF(NAND1_D4, 2, 12, 1);1493static PAD_PULLCTL_CONF(NAND1_D5, 2, 12, 1);1494static PAD_PULLCTL_CONF(NAND1_D6, 2, 12, 1);1495static PAD_PULLCTL_CONF(NAND1_D7, 2, 12, 1);1496static PAD_PULLCTL_CONF(NAND1_DQSN, 2, 11, 1);1497static PAD_PULLCTL_CONF(NAND1_DQS, 2, 10, 1);1498static PAD_PULLCTL_CONF(SGPIO2, 2, 8, 2);1499static PAD_PULLCTL_CONF(SGPIO3, 2, 6, 2);1500static PAD_PULLCTL_CONF(UART4_RX, 2, 4, 2);1501static PAD_PULLCTL_CONF(UART4_TX, 2, 2, 2);1502 1503/* PAD_ST0 */1504static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);1505static PAD_ST_CONF(UART0_RX, 0, 29, 1);1506static PAD_ST_CONF(ETH_MDC, 0, 28, 1);1507static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);1508static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);1509static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);1510static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);1511static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);1512static PAD_ST_CONF(SGPIO2, 0, 18, 1);1513static PAD_ST_CONF(SGPIO3, 0, 17, 1);1514static PAD_ST_CONF(UART4_TX, 0, 16, 1);1515static PAD_ST_CONF(I2S_D1, 0, 15, 1);1516static PAD_ST_CONF(UART0_TX, 0, 14, 1);1517static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1);1518static PAD_ST_CONF(SD0_CLK, 0, 12, 1);1519static PAD_ST_CONF(ERAM_A5, 0, 11, 1);1520static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);1521static PAD_ST_CONF(ERAM_A9, 0, 6, 1);1522static PAD_ST_CONF(LVDS_OEP, 0, 5, 1);1523static PAD_ST_CONF(LVDS_ODN, 0, 4, 1);1524static PAD_ST_CONF(LVDS_OAP, 0, 3, 1);1525static PAD_ST_CONF(I2S_BCLK1, 0, 2, 1);1526 1527/* PAD_ST1 */1528static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);1529static PAD_ST_CONF(UART4_RX, 1, 28, 1);1530static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);1531static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);1532static PAD_ST_CONF(UART3_RX, 1, 25, 1);1533static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);1534static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);1535static PAD_ST_CONF(UART2_RX, 1, 22, 1);1536static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);1537static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);1538static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);1539static PAD_ST_CONF(ETH_RXER, 1, 18, 1);1540static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);1541static PAD_ST_CONF(LVDS_OCP, 1, 16, 1);1542static PAD_ST_CONF(LVDS_OBP, 1, 15, 1);1543static PAD_ST_CONF(LVDS_OBN, 1, 14, 1);1544static PAD_ST_CONF(PCM1_OUT, 1, 12, 1);1545static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);1546static PAD_ST_CONF(PCM1_IN, 1, 10, 1);1547static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);1548static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);1549static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);1550static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);1551static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);1552static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1);1553static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);1554static PAD_ST_CONF(SPI0_SS, 1, 2, 1);1555static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);1556static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);1557 1558/* Pad info table */1559static const struct owl_padinfo s900_padinfo[NUM_PADS] = {1560 [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),1561 [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),1562 [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),1563 [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),1564 [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),1565 [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),1566 [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),1567 [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),1568 [ETH_MDC] = PAD_INFO_ST(ETH_MDC),1569 [ETH_MDIO] = PAD_INFO(ETH_MDIO),1570 [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),1571 [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),1572 [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),1573 [I2S_D0] = PAD_INFO(I2S_D0),1574 [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),1575 [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),1576 [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),1577 [I2S_D1] = PAD_INFO_ST(I2S_D1),1578 [I2S_BCLK1] = PAD_INFO_ST(I2S_BCLK1),1579 [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),1580 [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),1581 [PCM1_IN] = PAD_INFO_PULLCTL_ST(PCM1_IN),1582 [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),1583 [PCM1_SYNC] = PAD_INFO_ST(PCM1_SYNC),1584 [PCM1_OUT] = PAD_INFO_PULLCTL_ST(PCM1_OUT),1585 [ERAM_A5] = PAD_INFO_PULLCTL_ST(ERAM_A5),1586 [ERAM_A6] = PAD_INFO_PULLCTL(ERAM_A6),1587 [ERAM_A7] = PAD_INFO_PULLCTL(ERAM_A7),1588 [ERAM_A8] = PAD_INFO(ERAM_A8),1589 [ERAM_A9] = PAD_INFO_ST(ERAM_A9),1590 [ERAM_A10] = PAD_INFO_PULLCTL(ERAM_A10),1591 [ERAM_A11] = PAD_INFO(ERAM_A11),1592 [LVDS_OEP] = PAD_INFO_ST(LVDS_OEP),1593 [LVDS_OEN] = PAD_INFO(LVDS_OEN),1594 [LVDS_ODP] = PAD_INFO(LVDS_ODP),1595 [LVDS_ODN] = PAD_INFO_ST(LVDS_ODN),1596 [LVDS_OCP] = PAD_INFO_ST(LVDS_OCP),1597 [LVDS_OCN] = PAD_INFO(LVDS_OCN),1598 [LVDS_OBP] = PAD_INFO_ST(LVDS_OBP),1599 [LVDS_OBN] = PAD_INFO_ST(LVDS_OBN),1600 [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),1601 [LVDS_OAN] = PAD_INFO(LVDS_OAN),1602 [LVDS_EEP] = PAD_INFO(LVDS_EEP),1603 [LVDS_EEN] = PAD_INFO(LVDS_EEN),1604 [LVDS_EDP] = PAD_INFO(LVDS_EDP),1605 [LVDS_EDN] = PAD_INFO(LVDS_EDN),1606 [LVDS_ECP] = PAD_INFO(LVDS_ECP),1607 [LVDS_ECN] = PAD_INFO(LVDS_ECN),1608 [LVDS_EBP] = PAD_INFO(LVDS_EBP),1609 [LVDS_EBN] = PAD_INFO(LVDS_EBN),1610 [LVDS_EAP] = PAD_INFO(LVDS_EAP),1611 [LVDS_EAN] = PAD_INFO(LVDS_EAN),1612 [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),1613 [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),1614 [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),1615 [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),1616 [SD1_D0] = PAD_INFO_PULLCTL(SD1_D0),1617 [SD1_D1] = PAD_INFO_PULLCTL(SD1_D1),1618 [SD1_D2] = PAD_INFO_PULLCTL(SD1_D2),1619 [SD1_D3] = PAD_INFO_PULLCTL(SD1_D3),1620 [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),1621 [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),1622 [SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD),1623 [SD1_CLK] = PAD_INFO(SD1_CLK),1624 [SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK),1625 [SPI0_SS] = PAD_INFO_ST(SPI0_SS),1626 [SPI0_MISO] = PAD_INFO_ST(SPI0_MISO),1627 [SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI),1628 [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),1629 [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),1630 [UART2_RX] = PAD_INFO_ST(UART2_RX),1631 [UART2_TX] = PAD_INFO(UART2_TX),1632 [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),1633 [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),1634 [UART3_RX] = PAD_INFO_ST(UART3_RX),1635 [UART3_TX] = PAD_INFO(UART3_TX),1636 [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),1637 [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),1638 [UART4_RX] = PAD_INFO_PULLCTL_ST(UART4_RX),1639 [UART4_TX] = PAD_INFO_PULLCTL_ST(UART4_TX),1640 [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),1641 [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),1642 [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),1643 [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),1644 [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),1645 [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),1646 [CSI0_DN0] = PAD_INFO(CSI0_DN0),1647 [CSI0_DP0] = PAD_INFO(CSI0_DP0),1648 [CSI0_DN1] = PAD_INFO(CSI0_DN1),1649 [CSI0_DP1] = PAD_INFO(CSI0_DP1),1650 [CSI0_CN] = PAD_INFO(CSI0_CN),1651 [CSI0_CP] = PAD_INFO(CSI0_CP),1652 [CSI0_DN2] = PAD_INFO(CSI0_DN2),1653 [CSI0_DP2] = PAD_INFO(CSI0_DP2),1654 [CSI0_DN3] = PAD_INFO(CSI0_DN3),1655 [CSI0_DP3] = PAD_INFO(CSI0_DP3),1656 [DSI_DP3] = PAD_INFO(DSI_DP3),1657 [DSI_DN3] = PAD_INFO(DSI_DN3),1658 [DSI_DP1] = PAD_INFO(DSI_DP1),1659 [DSI_DN1] = PAD_INFO(DSI_DN1),1660 [DSI_CP] = PAD_INFO(DSI_CP),1661 [DSI_CN] = PAD_INFO(DSI_CN),1662 [DSI_DP0] = PAD_INFO(DSI_DP0),1663 [DSI_DN0] = PAD_INFO(DSI_DN0),1664 [DSI_DP2] = PAD_INFO(DSI_DP2),1665 [DSI_DN2] = PAD_INFO(DSI_DN2),1666 [SENSOR0_PCLK] = PAD_INFO(SENSOR0_PCLK),1667 [CSI1_DN0] = PAD_INFO(CSI1_DN0),1668 [CSI1_DP0] = PAD_INFO(CSI1_DP0),1669 [CSI1_DN1] = PAD_INFO(CSI1_DN1),1670 [CSI1_DP1] = PAD_INFO(CSI1_DP1),1671 [CSI1_CN] = PAD_INFO(CSI1_CN),1672 [CSI1_CP] = PAD_INFO(CSI1_CP),1673 [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),1674 [NAND0_D0] = PAD_INFO_PULLCTL(NAND0_D0),1675 [NAND0_D1] = PAD_INFO_PULLCTL(NAND0_D1),1676 [NAND0_D2] = PAD_INFO_PULLCTL(NAND0_D2),1677 [NAND0_D3] = PAD_INFO_PULLCTL(NAND0_D3),1678 [NAND0_D4] = PAD_INFO_PULLCTL(NAND0_D4),1679 [NAND0_D5] = PAD_INFO_PULLCTL(NAND0_D5),1680 [NAND0_D6] = PAD_INFO_PULLCTL(NAND0_D6),1681 [NAND0_D7] = PAD_INFO_PULLCTL(NAND0_D7),1682 [NAND0_DQS] = PAD_INFO_PULLCTL(NAND0_DQS),1683 [NAND0_DQSN] = PAD_INFO_PULLCTL(NAND0_DQSN),1684 [NAND0_ALE] = PAD_INFO(NAND0_ALE),1685 [NAND0_CLE] = PAD_INFO(NAND0_CLE),1686 [NAND0_CEB0] = PAD_INFO(NAND0_CEB0),1687 [NAND0_CEB1] = PAD_INFO(NAND0_CEB1),1688 [NAND0_CEB2] = PAD_INFO(NAND0_CEB2),1689 [NAND0_CEB3] = PAD_INFO(NAND0_CEB3),1690 [NAND1_D0] = PAD_INFO_PULLCTL(NAND1_D0),1691 [NAND1_D1] = PAD_INFO_PULLCTL(NAND1_D1),1692 [NAND1_D2] = PAD_INFO_PULLCTL(NAND1_D2),1693 [NAND1_D3] = PAD_INFO_PULLCTL(NAND1_D3),1694 [NAND1_D4] = PAD_INFO_PULLCTL(NAND1_D4),1695 [NAND1_D5] = PAD_INFO_PULLCTL(NAND1_D5),1696 [NAND1_D6] = PAD_INFO_PULLCTL(NAND1_D6),1697 [NAND1_D7] = PAD_INFO_PULLCTL(NAND1_D7),1698 [NAND1_DQS] = PAD_INFO_PULLCTL(NAND1_DQS),1699 [NAND1_DQSN] = PAD_INFO_PULLCTL(NAND1_DQSN),1700 [NAND1_ALE] = PAD_INFO(NAND1_ALE),1701 [NAND1_CLE] = PAD_INFO(NAND1_CLE),1702 [NAND1_CEB0] = PAD_INFO(NAND1_CEB0),1703 [NAND1_CEB1] = PAD_INFO(NAND1_CEB1),1704 [NAND1_CEB2] = PAD_INFO(NAND1_CEB2),1705 [NAND1_CEB3] = PAD_INFO(NAND1_CEB3),1706 [SGPIO0] = PAD_INFO(SGPIO0),1707 [SGPIO1] = PAD_INFO(SGPIO1),1708 [SGPIO2] = PAD_INFO_PULLCTL_ST(SGPIO2),1709 [SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)1710};1711 1712static const struct owl_gpio_port s900_gpio_ports[] = {1713 OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240, 0),1714 OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C, 0),1715 OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0),1716 OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234, 0),1717 OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230, 0),1718 OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178, 0)1719};1720 1721enum s900_pinconf_pull {1722 OWL_PINCONF_PULL_HIZ,1723 OWL_PINCONF_PULL_DOWN,1724 OWL_PINCONF_PULL_UP,1725 OWL_PINCONF_PULL_HOLD,1726};1727 1728static int s900_pad_pinconf_arg2val(const struct owl_padinfo *info,1729 unsigned int param,1730 u32 *arg)1731{1732 switch (param) {1733 case PIN_CONFIG_BIAS_BUS_HOLD:1734 *arg = OWL_PINCONF_PULL_HOLD;1735 break;1736 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:1737 *arg = OWL_PINCONF_PULL_HIZ;1738 break;1739 case PIN_CONFIG_BIAS_PULL_DOWN:1740 *arg = OWL_PINCONF_PULL_DOWN;1741 break;1742 case PIN_CONFIG_BIAS_PULL_UP:1743 *arg = OWL_PINCONF_PULL_UP;1744 break;1745 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:1746 *arg = (*arg >= 1 ? 1 : 0);1747 break;1748 default:1749 return -ENOTSUPP;1750 }1751 1752 return 0;1753}1754 1755static int s900_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,1756 unsigned int param,1757 u32 *arg)1758{1759 switch (param) {1760 case PIN_CONFIG_BIAS_BUS_HOLD:1761 *arg = *arg == OWL_PINCONF_PULL_HOLD;1762 break;1763 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:1764 *arg = *arg == OWL_PINCONF_PULL_HIZ;1765 break;1766 case PIN_CONFIG_BIAS_PULL_DOWN:1767 *arg = *arg == OWL_PINCONF_PULL_DOWN;1768 break;1769 case PIN_CONFIG_BIAS_PULL_UP:1770 *arg = *arg == OWL_PINCONF_PULL_UP;1771 break;1772 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:1773 *arg = *arg == 1;1774 break;1775 default:1776 return -ENOTSUPP;1777 }1778 1779 return 0;1780}1781 1782static struct owl_pinctrl_soc_data s900_pinctrl_data = {1783 .padinfo = s900_padinfo,1784 .pins = (const struct pinctrl_pin_desc *)s900_pads,1785 .npins = ARRAY_SIZE(s900_pads),1786 .functions = s900_functions,1787 .nfunctions = ARRAY_SIZE(s900_functions),1788 .groups = s900_groups,1789 .ngroups = ARRAY_SIZE(s900_groups),1790 .ngpios = NUM_GPIOS,1791 .ports = s900_gpio_ports,1792 .nports = ARRAY_SIZE(s900_gpio_ports),1793 .padctl_arg2val = s900_pad_pinconf_arg2val,1794 .padctl_val2arg = s900_pad_pinconf_val2arg,1795};1796 1797static int s900_pinctrl_probe(struct platform_device *pdev)1798{1799 return owl_pinctrl_probe(pdev, &s900_pinctrl_data);1800}1801 1802static const struct of_device_id s900_pinctrl_of_match[] = {1803 { .compatible = "actions,s900-pinctrl", },1804 { }1805};1806 1807static struct platform_driver s900_pinctrl_driver = {1808 .driver = {1809 .name = "pinctrl-s900",1810 .of_match_table = of_match_ptr(s900_pinctrl_of_match),1811 },1812 .probe = s900_pinctrl_probe,1813};1814 1815static int __init s900_pinctrl_init(void)1816{1817 return platform_driver_register(&s900_pinctrl_driver);1818}1819arch_initcall(s900_pinctrl_init);1820 1821static void __exit s900_pinctrl_exit(void)1822{1823 platform_driver_unregister(&s900_pinctrl_driver);1824}1825module_exit(s900_pinctrl_exit);1826 1827MODULE_AUTHOR("Actions Semi Inc.");1828MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");1829MODULE_DESCRIPTION("Actions Semi S900 SoC Pinctrl Driver");1830