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1// SPDX-License-Identifier: GPL-2.0-only2// Copyright (C) 2014-2017 Broadcom3 4/*5 * Broadcom Cygnus IOMUX driver6 *7 * This file contains the Cygnus IOMUX driver that supports group based PINMUX8 * configuration. Although PINMUX configuration is mainly group based, the9 * Cygnus IOMUX controller allows certain pins to be individually muxed to GPIO10 * function, and therefore be controlled by the Cygnus ASIU GPIO controller11 */12 13#include <linux/err.h>14#include <linux/io.h>15#include <linux/of.h>16#include <linux/platform_device.h>17#include <linux/seq_file.h>18#include <linux/slab.h>19 20#include <linux/pinctrl/pinconf-generic.h>21#include <linux/pinctrl/pinconf.h>22#include <linux/pinctrl/pinctrl.h>23#include <linux/pinctrl/pinmux.h>24 25#include "../core.h"26#include "../pinctrl-utils.h"27 28#define CYGNUS_NUM_IOMUX_REGS 829#define CYGNUS_NUM_MUX_PER_REG 830#define CYGNUS_NUM_IOMUX (CYGNUS_NUM_IOMUX_REGS * \31 CYGNUS_NUM_MUX_PER_REG)32 33/*34 * Cygnus IOMUX register description35 *36 * @offset: register offset for mux configuration of a group37 * @shift: bit shift for mux configuration of a group38 * @alt: alternate function to set to39 */40struct cygnus_mux {41 unsigned int offset;42 unsigned int shift;43 unsigned int alt;44};45 46/*47 * Keep track of Cygnus IOMUX configuration and prevent double configuration48 *49 * @cygnus_mux: Cygnus IOMUX register description50 * @is_configured: flag to indicate whether a mux setting has already been51 * configured52 */53struct cygnus_mux_log {54 struct cygnus_mux mux;55 bool is_configured;56};57 58/*59 * Group based IOMUX configuration60 *61 * @name: name of the group62 * @pins: array of pins used by this group63 * @num_pins: total number of pins used by this group64 * @mux: Cygnus group based IOMUX configuration65 */66struct cygnus_pin_group {67 const char *name;68 const unsigned *pins;69 unsigned num_pins;70 struct cygnus_mux mux;71};72 73/*74 * Cygnus mux function and supported pin groups75 *76 * @name: name of the function77 * @groups: array of groups that can be supported by this function78 * @num_groups: total number of groups that can be supported by this function79 */80struct cygnus_pin_function {81 const char *name;82 const char * const *groups;83 unsigned num_groups;84};85 86/*87 * Cygnus IOMUX pinctrl core88 *89 * @pctl: pointer to pinctrl_dev90 * @dev: pointer to device91 * @base0: first I/O register base of the Cygnus IOMUX controller92 * @base1: second I/O register base93 * @groups: pointer to array of groups94 * @num_groups: total number of groups95 * @functions: pointer to array of functions96 * @num_functions: total number of functions97 * @mux_log: pointer to the array of mux logs98 * @lock: lock to protect register access99 */100struct cygnus_pinctrl {101 struct pinctrl_dev *pctl;102 struct device *dev;103 void __iomem *base0;104 void __iomem *base1;105 106 const struct cygnus_pin_group *groups;107 unsigned num_groups;108 109 const struct cygnus_pin_function *functions;110 unsigned num_functions;111 112 struct cygnus_mux_log *mux_log;113 114 spinlock_t lock;115};116 117/*118 * Certain pins can be individually muxed to GPIO function119 *120 * @is_supported: flag to indicate GPIO mux is supported for this pin121 * @offset: register offset for GPIO mux override of a pin122 * @shift: bit shift for GPIO mux override of a pin123 */124struct cygnus_gpio_mux {125 int is_supported;126 unsigned int offset;127 unsigned int shift;128};129 130/*131 * Description of a pin in Cygnus132 *133 * @pin: pin number134 * @name: pin name135 * @gpio_mux: GPIO override related information136 */137struct cygnus_pin {138 unsigned pin;139 char *name;140 struct cygnus_gpio_mux gpio_mux;141};142 143#define CYGNUS_PIN_DESC(p, n, i, o, s) \144{ \145 .pin = p, \146 .name = n, \147 .gpio_mux = { \148 .is_supported = i, \149 .offset = o, \150 .shift = s, \151 }, \152}153 154/*155 * List of pins in Cygnus156 */157static struct cygnus_pin cygnus_pins[] = {158 CYGNUS_PIN_DESC(0, "ext_device_reset_n", 0, 0, 0),159 CYGNUS_PIN_DESC(1, "chip_mode0", 0, 0, 0),160 CYGNUS_PIN_DESC(2, "chip_mode1", 0, 0, 0),161 CYGNUS_PIN_DESC(3, "chip_mode2", 0, 0, 0),162 CYGNUS_PIN_DESC(4, "chip_mode3", 0, 0, 0),163 CYGNUS_PIN_DESC(5, "chip_mode4", 0, 0, 0),164 CYGNUS_PIN_DESC(6, "bsc0_scl", 0, 0, 0),165 CYGNUS_PIN_DESC(7, "bsc0_sda", 0, 0, 0),166 CYGNUS_PIN_DESC(8, "bsc1_scl", 0, 0, 0),167 CYGNUS_PIN_DESC(9, "bsc1_sda", 0, 0, 0),168 CYGNUS_PIN_DESC(10, "d1w_dq", 1, 0x28, 0),169 CYGNUS_PIN_DESC(11, "d1wowstz_l", 1, 0x4, 28),170 CYGNUS_PIN_DESC(12, "gpio0", 0, 0, 0),171 CYGNUS_PIN_DESC(13, "gpio1", 0, 0, 0),172 CYGNUS_PIN_DESC(14, "gpio2", 0, 0, 0),173 CYGNUS_PIN_DESC(15, "gpio3", 0, 0, 0),174 CYGNUS_PIN_DESC(16, "gpio4", 0, 0, 0),175 CYGNUS_PIN_DESC(17, "gpio5", 0, 0, 0),176 CYGNUS_PIN_DESC(18, "gpio6", 0, 0, 0),177 CYGNUS_PIN_DESC(19, "gpio7", 0, 0, 0),178 CYGNUS_PIN_DESC(20, "gpio8", 0, 0, 0),179 CYGNUS_PIN_DESC(21, "gpio9", 0, 0, 0),180 CYGNUS_PIN_DESC(22, "gpio10", 0, 0, 0),181 CYGNUS_PIN_DESC(23, "gpio11", 0, 0, 0),182 CYGNUS_PIN_DESC(24, "gpio12", 0, 0, 0),183 CYGNUS_PIN_DESC(25, "gpio13", 0, 0, 0),184 CYGNUS_PIN_DESC(26, "gpio14", 0, 0, 0),185 CYGNUS_PIN_DESC(27, "gpio15", 0, 0, 0),186 CYGNUS_PIN_DESC(28, "gpio16", 0, 0, 0),187 CYGNUS_PIN_DESC(29, "gpio17", 0, 0, 0),188 CYGNUS_PIN_DESC(30, "gpio18", 0, 0, 0),189 CYGNUS_PIN_DESC(31, "gpio19", 0, 0, 0),190 CYGNUS_PIN_DESC(32, "gpio20", 0, 0, 0),191 CYGNUS_PIN_DESC(33, "gpio21", 0, 0, 0),192 CYGNUS_PIN_DESC(34, "gpio22", 0, 0, 0),193 CYGNUS_PIN_DESC(35, "gpio23", 0, 0, 0),194 CYGNUS_PIN_DESC(36, "mdc", 0, 0, 0),195 CYGNUS_PIN_DESC(37, "mdio", 0, 0, 0),196 CYGNUS_PIN_DESC(38, "pwm0", 1, 0x10, 30),197 CYGNUS_PIN_DESC(39, "pwm1", 1, 0x10, 28),198 CYGNUS_PIN_DESC(40, "pwm2", 1, 0x10, 26),199 CYGNUS_PIN_DESC(41, "pwm3", 1, 0x10, 24),200 CYGNUS_PIN_DESC(42, "sc0_clk", 1, 0x10, 22),201 CYGNUS_PIN_DESC(43, "sc0_cmdvcc_l", 1, 0x10, 20),202 CYGNUS_PIN_DESC(44, "sc0_detect", 1, 0x10, 18),203 CYGNUS_PIN_DESC(45, "sc0_fcb", 1, 0x10, 16),204 CYGNUS_PIN_DESC(46, "sc0_io", 1, 0x10, 14),205 CYGNUS_PIN_DESC(47, "sc0_rst_l", 1, 0x10, 12),206 CYGNUS_PIN_DESC(48, "sc1_clk", 1, 0x10, 10),207 CYGNUS_PIN_DESC(49, "sc1_cmdvcc_l", 1, 0x10, 8),208 CYGNUS_PIN_DESC(50, "sc1_detect", 1, 0x10, 6),209 CYGNUS_PIN_DESC(51, "sc1_fcb", 1, 0x10, 4),210 CYGNUS_PIN_DESC(52, "sc1_io", 1, 0x10, 2),211 CYGNUS_PIN_DESC(53, "sc1_rst_l", 1, 0x10, 0),212 CYGNUS_PIN_DESC(54, "spi0_clk", 1, 0x18, 10),213 CYGNUS_PIN_DESC(55, "spi0_mosi", 1, 0x18, 6),214 CYGNUS_PIN_DESC(56, "spi0_miso", 1, 0x18, 8),215 CYGNUS_PIN_DESC(57, "spi0_ss", 1, 0x18, 4),216 CYGNUS_PIN_DESC(58, "spi1_clk", 1, 0x18, 2),217 CYGNUS_PIN_DESC(59, "spi1_mosi", 1, 0x1c, 30),218 CYGNUS_PIN_DESC(60, "spi1_miso", 1, 0x18, 0),219 CYGNUS_PIN_DESC(61, "spi1_ss", 1, 0x1c, 28),220 CYGNUS_PIN_DESC(62, "spi2_clk", 1, 0x1c, 26),221 CYGNUS_PIN_DESC(63, "spi2_mosi", 1, 0x1c, 22),222 CYGNUS_PIN_DESC(64, "spi2_miso", 1, 0x1c, 24),223 CYGNUS_PIN_DESC(65, "spi2_ss", 1, 0x1c, 20),224 CYGNUS_PIN_DESC(66, "spi3_clk", 1, 0x1c, 18),225 CYGNUS_PIN_DESC(67, "spi3_mosi", 1, 0x1c, 14),226 CYGNUS_PIN_DESC(68, "spi3_miso", 1, 0x1c, 16),227 CYGNUS_PIN_DESC(69, "spi3_ss", 1, 0x1c, 12),228 CYGNUS_PIN_DESC(70, "uart0_cts", 1, 0x1c, 10),229 CYGNUS_PIN_DESC(71, "uart0_rts", 1, 0x1c, 8),230 CYGNUS_PIN_DESC(72, "uart0_rx", 1, 0x1c, 6),231 CYGNUS_PIN_DESC(73, "uart0_tx", 1, 0x1c, 4),232 CYGNUS_PIN_DESC(74, "uart1_cts", 1, 0x1c, 2),233 CYGNUS_PIN_DESC(75, "uart1_dcd", 1, 0x1c, 0),234 CYGNUS_PIN_DESC(76, "uart1_dsr", 1, 0x20, 14),235 CYGNUS_PIN_DESC(77, "uart1_dtr", 1, 0x20, 12),236 CYGNUS_PIN_DESC(78, "uart1_ri", 1, 0x20, 10),237 CYGNUS_PIN_DESC(79, "uart1_rts", 1, 0x20, 8),238 CYGNUS_PIN_DESC(80, "uart1_rx", 1, 0x20, 6),239 CYGNUS_PIN_DESC(81, "uart1_tx", 1, 0x20, 4),240 CYGNUS_PIN_DESC(82, "uart3_rx", 1, 0x20, 2),241 CYGNUS_PIN_DESC(83, "uart3_tx", 1, 0x20, 0),242 CYGNUS_PIN_DESC(84, "sdio1_clk_sdcard", 1, 0x14, 6),243 CYGNUS_PIN_DESC(85, "sdio1_cmd", 1, 0x14, 4),244 CYGNUS_PIN_DESC(86, "sdio1_data0", 1, 0x14, 2),245 CYGNUS_PIN_DESC(87, "sdio1_data1", 1, 0x14, 0),246 CYGNUS_PIN_DESC(88, "sdio1_data2", 1, 0x18, 30),247 CYGNUS_PIN_DESC(89, "sdio1_data3", 1, 0x18, 28),248 CYGNUS_PIN_DESC(90, "sdio1_wp_n", 1, 0x18, 24),249 CYGNUS_PIN_DESC(91, "sdio1_card_rst", 1, 0x14, 10),250 CYGNUS_PIN_DESC(92, "sdio1_led_on", 1, 0x18, 26),251 CYGNUS_PIN_DESC(93, "sdio1_cd", 1, 0x14, 8),252 CYGNUS_PIN_DESC(94, "sdio0_clk_sdcard", 1, 0x14, 26),253 CYGNUS_PIN_DESC(95, "sdio0_cmd", 1, 0x14, 24),254 CYGNUS_PIN_DESC(96, "sdio0_data0", 1, 0x14, 22),255 CYGNUS_PIN_DESC(97, "sdio0_data1", 1, 0x14, 20),256 CYGNUS_PIN_DESC(98, "sdio0_data2", 1, 0x14, 18),257 CYGNUS_PIN_DESC(99, "sdio0_data3", 1, 0x14, 16),258 CYGNUS_PIN_DESC(100, "sdio0_wp_n", 1, 0x14, 12),259 CYGNUS_PIN_DESC(101, "sdio0_card_rst", 1, 0x14, 30),260 CYGNUS_PIN_DESC(102, "sdio0_led_on", 1, 0x14, 14),261 CYGNUS_PIN_DESC(103, "sdio0_cd", 1, 0x14, 28),262 CYGNUS_PIN_DESC(104, "sflash_clk", 1, 0x18, 22),263 CYGNUS_PIN_DESC(105, "sflash_cs_l", 1, 0x18, 20),264 CYGNUS_PIN_DESC(106, "sflash_mosi", 1, 0x18, 14),265 CYGNUS_PIN_DESC(107, "sflash_miso", 1, 0x18, 16),266 CYGNUS_PIN_DESC(108, "sflash_wp_n", 1, 0x18, 12),267 CYGNUS_PIN_DESC(109, "sflash_hold_n", 1, 0x18, 18),268 CYGNUS_PIN_DESC(110, "nand_ale", 1, 0xc, 30),269 CYGNUS_PIN_DESC(111, "nand_ce0_l", 1, 0xc, 28),270 CYGNUS_PIN_DESC(112, "nand_ce1_l", 1, 0xc, 26),271 CYGNUS_PIN_DESC(113, "nand_cle", 1, 0xc, 24),272 CYGNUS_PIN_DESC(114, "nand_dq0", 1, 0xc, 22),273 CYGNUS_PIN_DESC(115, "nand_dq1", 1, 0xc, 20),274 CYGNUS_PIN_DESC(116, "nand_dq2", 1, 0xc, 18),275 CYGNUS_PIN_DESC(117, "nand_dq3", 1, 0xc, 16),276 CYGNUS_PIN_DESC(118, "nand_dq4", 1, 0xc, 14),277 CYGNUS_PIN_DESC(119, "nand_dq5", 1, 0xc, 12),278 CYGNUS_PIN_DESC(120, "nand_dq6", 1, 0xc, 10),279 CYGNUS_PIN_DESC(121, "nand_dq7", 1, 0xc, 8),280 CYGNUS_PIN_DESC(122, "nand_rb_l", 1, 0xc, 6),281 CYGNUS_PIN_DESC(123, "nand_re_l", 1, 0xc, 4),282 CYGNUS_PIN_DESC(124, "nand_we_l", 1, 0xc, 2),283 CYGNUS_PIN_DESC(125, "nand_wp_l", 1, 0xc, 0),284 CYGNUS_PIN_DESC(126, "lcd_clac", 1, 0x4, 26),285 CYGNUS_PIN_DESC(127, "lcd_clcp", 1, 0x4, 24),286 CYGNUS_PIN_DESC(128, "lcd_cld0", 1, 0x4, 22),287 CYGNUS_PIN_DESC(129, "lcd_cld1", 1, 0x4, 0),288 CYGNUS_PIN_DESC(130, "lcd_cld10", 1, 0x4, 20),289 CYGNUS_PIN_DESC(131, "lcd_cld11", 1, 0x4, 18),290 CYGNUS_PIN_DESC(132, "lcd_cld12", 1, 0x4, 16),291 CYGNUS_PIN_DESC(133, "lcd_cld13", 1, 0x4, 14),292 CYGNUS_PIN_DESC(134, "lcd_cld14", 1, 0x4, 12),293 CYGNUS_PIN_DESC(135, "lcd_cld15", 1, 0x4, 10),294 CYGNUS_PIN_DESC(136, "lcd_cld16", 1, 0x4, 8),295 CYGNUS_PIN_DESC(137, "lcd_cld17", 1, 0x4, 6),296 CYGNUS_PIN_DESC(138, "lcd_cld18", 1, 0x4, 4),297 CYGNUS_PIN_DESC(139, "lcd_cld19", 1, 0x4, 2),298 CYGNUS_PIN_DESC(140, "lcd_cld2", 1, 0x8, 22),299 CYGNUS_PIN_DESC(141, "lcd_cld20", 1, 0x8, 30),300 CYGNUS_PIN_DESC(142, "lcd_cld21", 1, 0x8, 28),301 CYGNUS_PIN_DESC(143, "lcd_cld22", 1, 0x8, 26),302 CYGNUS_PIN_DESC(144, "lcd_cld23", 1, 0x8, 24),303 CYGNUS_PIN_DESC(145, "lcd_cld3", 1, 0x8, 20),304 CYGNUS_PIN_DESC(146, "lcd_cld4", 1, 0x8, 18),305 CYGNUS_PIN_DESC(147, "lcd_cld5", 1, 0x8, 16),306 CYGNUS_PIN_DESC(148, "lcd_cld6", 1, 0x8, 14),307 CYGNUS_PIN_DESC(149, "lcd_cld7", 1, 0x8, 12),308 CYGNUS_PIN_DESC(150, "lcd_cld8", 1, 0x8, 10),309 CYGNUS_PIN_DESC(151, "lcd_cld9", 1, 0x8, 8),310 CYGNUS_PIN_DESC(152, "lcd_clfp", 1, 0x8, 6),311 CYGNUS_PIN_DESC(153, "lcd_clle", 1, 0x8, 4),312 CYGNUS_PIN_DESC(154, "lcd_cllp", 1, 0x8, 2),313 CYGNUS_PIN_DESC(155, "lcd_clpower", 1, 0x8, 0),314 CYGNUS_PIN_DESC(156, "camera_vsync", 1, 0x4, 30),315 CYGNUS_PIN_DESC(157, "camera_trigger", 1, 0x0, 0),316 CYGNUS_PIN_DESC(158, "camera_strobe", 1, 0x0, 2),317 CYGNUS_PIN_DESC(159, "camera_standby", 1, 0x0, 4),318 CYGNUS_PIN_DESC(160, "camera_reset_n", 1, 0x0, 6),319 CYGNUS_PIN_DESC(161, "camera_pixdata9", 1, 0x0, 8),320 CYGNUS_PIN_DESC(162, "camera_pixdata8", 1, 0x0, 10),321 CYGNUS_PIN_DESC(163, "camera_pixdata7", 1, 0x0, 12),322 CYGNUS_PIN_DESC(164, "camera_pixdata6", 1, 0x0, 14),323 CYGNUS_PIN_DESC(165, "camera_pixdata5", 1, 0x0, 16),324 CYGNUS_PIN_DESC(166, "camera_pixdata4", 1, 0x0, 18),325 CYGNUS_PIN_DESC(167, "camera_pixdata3", 1, 0x0, 20),326 CYGNUS_PIN_DESC(168, "camera_pixdata2", 1, 0x0, 22),327 CYGNUS_PIN_DESC(169, "camera_pixdata1", 1, 0x0, 24),328 CYGNUS_PIN_DESC(170, "camera_pixdata0", 1, 0x0, 26),329 CYGNUS_PIN_DESC(171, "camera_pixclk", 1, 0x0, 28),330 CYGNUS_PIN_DESC(172, "camera_hsync", 1, 0x0, 30),331 CYGNUS_PIN_DESC(173, "camera_pll_ref_clk", 0, 0, 0),332 CYGNUS_PIN_DESC(174, "usb_id_indication", 0, 0, 0),333 CYGNUS_PIN_DESC(175, "usb_vbus_indication", 0, 0, 0),334 CYGNUS_PIN_DESC(176, "gpio0_3p3", 0, 0, 0),335 CYGNUS_PIN_DESC(177, "gpio1_3p3", 0, 0, 0),336 CYGNUS_PIN_DESC(178, "gpio2_3p3", 0, 0, 0),337 CYGNUS_PIN_DESC(179, "gpio3_3p3", 0, 0, 0),338};339 340/*341 * List of groups of pins342 */343static const unsigned bsc1_pins[] = { 8, 9 };344static const unsigned pcie_clkreq_pins[] = { 8, 9 };345 346static const unsigned i2s2_0_pins[] = { 12 };347static const unsigned i2s2_1_pins[] = { 13 };348static const unsigned i2s2_2_pins[] = { 14 };349static const unsigned i2s2_3_pins[] = { 15 };350static const unsigned i2s2_4_pins[] = { 16 };351 352static const unsigned pwm4_pins[] = { 17 };353static const unsigned pwm5_pins[] = { 18 };354 355static const unsigned key0_pins[] = { 20 };356static const unsigned key1_pins[] = { 21 };357static const unsigned key2_pins[] = { 22 };358static const unsigned key3_pins[] = { 23 };359static const unsigned key4_pins[] = { 24 };360static const unsigned key5_pins[] = { 25 };361 362static const unsigned key6_pins[] = { 26 };363static const unsigned audio_dte0_pins[] = { 26 };364 365static const unsigned key7_pins[] = { 27 };366static const unsigned audio_dte1_pins[] = { 27 };367 368static const unsigned key8_pins[] = { 28 };369static const unsigned key9_pins[] = { 29 };370static const unsigned key10_pins[] = { 30 };371static const unsigned key11_pins[] = { 31 };372static const unsigned key12_pins[] = { 32 };373static const unsigned key13_pins[] = { 33 };374 375static const unsigned key14_pins[] = { 34 };376static const unsigned audio_dte2_pins[] = { 34 };377 378static const unsigned key15_pins[] = { 35 };379static const unsigned audio_dte3_pins[] = { 35 };380 381static const unsigned pwm0_pins[] = { 38 };382static const unsigned pwm1_pins[] = { 39 };383static const unsigned pwm2_pins[] = { 40 };384static const unsigned pwm3_pins[] = { 41 };385 386static const unsigned sdio0_pins[] = { 94, 95, 96, 97, 98, 99 };387 388static const unsigned smart_card0_pins[] = { 42, 43, 44, 46, 47 };389static const unsigned i2s0_0_pins[] = { 42, 43, 44, 46 };390static const unsigned spdif_pins[] = { 47 };391 392static const unsigned smart_card1_pins[] = { 48, 49, 50, 52, 53 };393static const unsigned i2s1_0_pins[] = { 48, 49, 50, 52 };394 395static const unsigned spi0_pins[] = { 54, 55, 56, 57 };396 397static const unsigned spi1_pins[] = { 58, 59, 60, 61 };398 399static const unsigned spi2_pins[] = { 62, 63, 64, 65 };400 401static const unsigned spi3_pins[] = { 66, 67, 68, 69 };402static const unsigned sw_led0_0_pins[] = { 66, 67, 68, 69 };403 404static const unsigned d1w_pins[] = { 10, 11 };405static const unsigned uart4_pins[] = { 10, 11 };406static const unsigned sw_led2_0_pins[] = { 10, 11 };407 408static const unsigned lcd_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,409 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,410 148, 149, 150, 151, 152, 153, 154, 155 };411static const unsigned sram_0_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,412 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,413 148, 149, 150, 151, 152, 153, 154, 155 };414static const unsigned spi5_pins[] = { 141, 142, 143, 144 };415 416static const unsigned uart0_pins[] = { 70, 71, 72, 73 };417static const unsigned sw_led0_1_pins[] = { 70, 71, 72, 73 };418 419static const unsigned uart1_dte_pins[] = { 75, 76, 77, 78 };420static const unsigned uart2_pins[] = { 75, 76, 77, 78 };421 422static const unsigned uart1_pins[] = { 74, 79, 80, 81 };423 424static const unsigned uart3_pins[] = { 82, 83 };425 426static const unsigned qspi_0_pins[] = { 104, 105, 106, 107 };427 428static const unsigned nand_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117,429 118, 119, 120, 121, 122, 123, 124, 125 };430 431static const unsigned sdio0_cd_pins[] = { 103 };432 433static const unsigned sdio0_mmc_pins[] = { 100, 101, 102 };434 435static const unsigned sdio1_data_0_pins[] = { 86, 87 };436static const unsigned can0_pins[] = { 86, 87 };437static const unsigned spi4_0_pins[] = { 86, 87 };438 439static const unsigned sdio1_data_1_pins[] = { 88, 89 };440static const unsigned can1_pins[] = { 88, 89 };441static const unsigned spi4_1_pins[] = { 88, 89 };442 443static const unsigned sdio1_cd_pins[] = { 93 };444 445static const unsigned sdio1_led_pins[] = { 84, 85 };446static const unsigned sw_led2_1_pins[] = { 84, 85 };447 448static const unsigned sdio1_mmc_pins[] = { 90, 91, 92 };449 450static const unsigned cam_led_pins[] = { 156, 157, 158, 159, 160 };451static const unsigned sw_led1_pins[] = { 156, 157, 158, 159 };452 453static const unsigned cam_0_pins[] = { 169, 170, 171, 169, 170 };454 455static const unsigned cam_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,456 168 };457static const unsigned sram_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,458 168 };459 460static const unsigned qspi_1_pins[] = { 108, 109 };461 462static const unsigned smart_card0_fcb_pins[] = { 45 };463static const unsigned i2s0_1_pins[] = { 45 };464 465static const unsigned smart_card1_fcb_pins[] = { 51 };466static const unsigned i2s1_1_pins[] = { 51 };467 468static const unsigned gpio0_3p3_pins[] = { 176 };469static const unsigned usb0_oc_pins[] = { 176 };470 471static const unsigned gpio1_3p3_pins[] = { 177 };472static const unsigned usb1_oc_pins[] = { 177 };473 474static const unsigned gpio2_3p3_pins[] = { 178 };475static const unsigned usb2_oc_pins[] = { 178 };476 477#define CYGNUS_PIN_GROUP(group_name, off, sh, al) \478{ \479 .name = __stringify(group_name) "_grp", \480 .pins = group_name ## _pins, \481 .num_pins = ARRAY_SIZE(group_name ## _pins), \482 .mux = { \483 .offset = off, \484 .shift = sh, \485 .alt = al, \486 } \487}488 489/*490 * List of Cygnus pin groups491 */492static const struct cygnus_pin_group cygnus_pin_groups[] = {493 CYGNUS_PIN_GROUP(i2s2_0, 0x0, 0, 2),494 CYGNUS_PIN_GROUP(i2s2_1, 0x0, 4, 2),495 CYGNUS_PIN_GROUP(i2s2_2, 0x0, 8, 2),496 CYGNUS_PIN_GROUP(i2s2_3, 0x0, 12, 2),497 CYGNUS_PIN_GROUP(i2s2_4, 0x0, 16, 2),498 CYGNUS_PIN_GROUP(pwm4, 0x0, 20, 0),499 CYGNUS_PIN_GROUP(pwm5, 0x0, 24, 2),500 CYGNUS_PIN_GROUP(key0, 0x4, 0, 1),501 CYGNUS_PIN_GROUP(key1, 0x4, 4, 1),502 CYGNUS_PIN_GROUP(key2, 0x4, 8, 1),503 CYGNUS_PIN_GROUP(key3, 0x4, 12, 1),504 CYGNUS_PIN_GROUP(key4, 0x4, 16, 1),505 CYGNUS_PIN_GROUP(key5, 0x4, 20, 1),506 CYGNUS_PIN_GROUP(key6, 0x4, 24, 1),507 CYGNUS_PIN_GROUP(audio_dte0, 0x4, 24, 2),508 CYGNUS_PIN_GROUP(key7, 0x4, 28, 1),509 CYGNUS_PIN_GROUP(audio_dte1, 0x4, 28, 2),510 CYGNUS_PIN_GROUP(key8, 0x8, 0, 1),511 CYGNUS_PIN_GROUP(key9, 0x8, 4, 1),512 CYGNUS_PIN_GROUP(key10, 0x8, 8, 1),513 CYGNUS_PIN_GROUP(key11, 0x8, 12, 1),514 CYGNUS_PIN_GROUP(key12, 0x8, 16, 1),515 CYGNUS_PIN_GROUP(key13, 0x8, 20, 1),516 CYGNUS_PIN_GROUP(key14, 0x8, 24, 1),517 CYGNUS_PIN_GROUP(audio_dte2, 0x8, 24, 2),518 CYGNUS_PIN_GROUP(key15, 0x8, 28, 1),519 CYGNUS_PIN_GROUP(audio_dte3, 0x8, 28, 2),520 CYGNUS_PIN_GROUP(pwm0, 0xc, 0, 0),521 CYGNUS_PIN_GROUP(pwm1, 0xc, 4, 0),522 CYGNUS_PIN_GROUP(pwm2, 0xc, 8, 0),523 CYGNUS_PIN_GROUP(pwm3, 0xc, 12, 0),524 CYGNUS_PIN_GROUP(sdio0, 0xc, 16, 0),525 CYGNUS_PIN_GROUP(smart_card0, 0xc, 20, 0),526 CYGNUS_PIN_GROUP(i2s0_0, 0xc, 20, 1),527 CYGNUS_PIN_GROUP(spdif, 0xc, 20, 1),528 CYGNUS_PIN_GROUP(smart_card1, 0xc, 24, 0),529 CYGNUS_PIN_GROUP(i2s1_0, 0xc, 24, 1),530 CYGNUS_PIN_GROUP(spi0, 0x10, 0, 0),531 CYGNUS_PIN_GROUP(spi1, 0x10, 4, 0),532 CYGNUS_PIN_GROUP(spi2, 0x10, 8, 0),533 CYGNUS_PIN_GROUP(spi3, 0x10, 12, 0),534 CYGNUS_PIN_GROUP(sw_led0_0, 0x10, 12, 2),535 CYGNUS_PIN_GROUP(d1w, 0x10, 16, 0),536 CYGNUS_PIN_GROUP(uart4, 0x10, 16, 1),537 CYGNUS_PIN_GROUP(sw_led2_0, 0x10, 16, 2),538 CYGNUS_PIN_GROUP(lcd, 0x10, 20, 0),539 CYGNUS_PIN_GROUP(sram_0, 0x10, 20, 1),540 CYGNUS_PIN_GROUP(spi5, 0x10, 20, 2),541 CYGNUS_PIN_GROUP(uart0, 0x14, 0, 0),542 CYGNUS_PIN_GROUP(sw_led0_1, 0x14, 0, 2),543 CYGNUS_PIN_GROUP(uart1_dte, 0x14, 4, 0),544 CYGNUS_PIN_GROUP(uart2, 0x14, 4, 1),545 CYGNUS_PIN_GROUP(uart1, 0x14, 8, 0),546 CYGNUS_PIN_GROUP(uart3, 0x14, 12, 0),547 CYGNUS_PIN_GROUP(qspi_0, 0x14, 16, 0),548 CYGNUS_PIN_GROUP(nand, 0x14, 20, 0),549 CYGNUS_PIN_GROUP(sdio0_cd, 0x18, 0, 0),550 CYGNUS_PIN_GROUP(sdio0_mmc, 0x18, 4, 0),551 CYGNUS_PIN_GROUP(sdio1_data_0, 0x18, 8, 0),552 CYGNUS_PIN_GROUP(can0, 0x18, 8, 1),553 CYGNUS_PIN_GROUP(spi4_0, 0x18, 8, 2),554 CYGNUS_PIN_GROUP(sdio1_data_1, 0x18, 12, 0),555 CYGNUS_PIN_GROUP(can1, 0x18, 12, 1),556 CYGNUS_PIN_GROUP(spi4_1, 0x18, 12, 2),557 CYGNUS_PIN_GROUP(sdio1_cd, 0x18, 16, 0),558 CYGNUS_PIN_GROUP(sdio1_led, 0x18, 20, 0),559 CYGNUS_PIN_GROUP(sw_led2_1, 0x18, 20, 2),560 CYGNUS_PIN_GROUP(sdio1_mmc, 0x18, 24, 0),561 CYGNUS_PIN_GROUP(cam_led, 0x1c, 0, 0),562 CYGNUS_PIN_GROUP(sw_led1, 0x1c, 0, 1),563 CYGNUS_PIN_GROUP(cam_0, 0x1c, 4, 0),564 CYGNUS_PIN_GROUP(cam_1, 0x1c, 8, 0),565 CYGNUS_PIN_GROUP(sram_1, 0x1c, 8, 1),566 CYGNUS_PIN_GROUP(qspi_1, 0x1c, 12, 0),567 CYGNUS_PIN_GROUP(bsc1, 0x1c, 16, 0),568 CYGNUS_PIN_GROUP(pcie_clkreq, 0x1c, 16, 1),569 CYGNUS_PIN_GROUP(smart_card0_fcb, 0x20, 0, 0),570 CYGNUS_PIN_GROUP(i2s0_1, 0x20, 0, 1),571 CYGNUS_PIN_GROUP(smart_card1_fcb, 0x20, 4, 0),572 CYGNUS_PIN_GROUP(i2s1_1, 0x20, 4, 1),573 CYGNUS_PIN_GROUP(gpio0_3p3, 0x28, 0, 0),574 CYGNUS_PIN_GROUP(usb0_oc, 0x28, 0, 1),575 CYGNUS_PIN_GROUP(gpio1_3p3, 0x28, 4, 0),576 CYGNUS_PIN_GROUP(usb1_oc, 0x28, 4, 1),577 CYGNUS_PIN_GROUP(gpio2_3p3, 0x28, 8, 0),578 CYGNUS_PIN_GROUP(usb2_oc, 0x28, 8, 1),579};580 581/*582 * List of groups supported by functions583 */584static const char * const i2s0_grps[] = { "i2s0_0_grp", "i2s0_1_grp" };585static const char * const i2s1_grps[] = { "i2s1_0_grp", "i2s1_1_grp" };586static const char * const i2s2_grps[] = { "i2s2_0_grp", "i2s2_1_grp",587 "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" };588static const char * const spdif_grps[] = { "spdif_grp" };589static const char * const pwm0_grps[] = { "pwm0_grp" };590static const char * const pwm1_grps[] = { "pwm1_grp" };591static const char * const pwm2_grps[] = { "pwm2_grp" };592static const char * const pwm3_grps[] = { "pwm3_grp" };593static const char * const pwm4_grps[] = { "pwm4_grp" };594static const char * const pwm5_grps[] = { "pwm5_grp" };595static const char * const key_grps[] = { "key0_grp", "key1_grp", "key2_grp",596 "key3_grp", "key4_grp", "key5_grp", "key6_grp", "key7_grp", "key8_grp",597 "key9_grp", "key10_grp", "key11_grp", "key12_grp", "key13_grp",598 "key14_grp", "key15_grp" };599static const char * const audio_dte_grps[] = { "audio_dte0_grp",600 "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" };601static const char * const smart_card0_grps[] = { "smart_card0_grp",602 "smart_card0_fcb_grp" };603static const char * const smart_card1_grps[] = { "smart_card1_grp",604 "smart_card1_fcb_grp" };605static const char * const spi0_grps[] = { "spi0_grp" };606static const char * const spi1_grps[] = { "spi1_grp" };607static const char * const spi2_grps[] = { "spi2_grp" };608static const char * const spi3_grps[] = { "spi3_grp" };609static const char * const spi4_grps[] = { "spi4_0_grp", "spi4_1_grp" };610static const char * const spi5_grps[] = { "spi5_grp" };611 612static const char * const sw_led0_grps[] = { "sw_led0_0_grp",613 "sw_led0_1_grp" };614static const char * const sw_led1_grps[] = { "sw_led1_grp" };615static const char * const sw_led2_grps[] = { "sw_led2_0_grp",616 "sw_led2_1_grp" };617static const char * const d1w_grps[] = { "d1w_grp" };618static const char * const lcd_grps[] = { "lcd_grp" };619static const char * const sram_grps[] = { "sram_0_grp", "sram_1_grp" };620 621static const char * const uart0_grps[] = { "uart0_grp" };622static const char * const uart1_grps[] = { "uart1_grp", "uart1_dte_grp" };623static const char * const uart2_grps[] = { "uart2_grp" };624static const char * const uart3_grps[] = { "uart3_grp" };625static const char * const uart4_grps[] = { "uart4_grp" };626static const char * const qspi_grps[] = { "qspi_0_grp", "qspi_1_grp" };627static const char * const nand_grps[] = { "nand_grp" };628static const char * const sdio0_grps[] = { "sdio0_grp", "sdio0_cd_grp",629 "sdio0_mmc_grp" };630static const char * const sdio1_grps[] = { "sdio1_data_0_grp",631 "sdio1_data_1_grp", "sdio1_cd_grp", "sdio1_led_grp", "sdio1_mmc_grp" };632static const char * const can0_grps[] = { "can0_grp" };633static const char * const can1_grps[] = { "can1_grp" };634static const char * const cam_grps[] = { "cam_led_grp", "cam_0_grp",635 "cam_1_grp" };636static const char * const bsc1_grps[] = { "bsc1_grp" };637static const char * const pcie_clkreq_grps[] = { "pcie_clkreq_grp" };638static const char * const usb0_oc_grps[] = { "usb0_oc_grp" };639static const char * const usb1_oc_grps[] = { "usb1_oc_grp" };640static const char * const usb2_oc_grps[] = { "usb2_oc_grp" };641 642#define CYGNUS_PIN_FUNCTION(func) \643{ \644 .name = #func, \645 .groups = func ## _grps, \646 .num_groups = ARRAY_SIZE(func ## _grps), \647}648 649/*650 * List of supported functions in Cygnus651 */652static const struct cygnus_pin_function cygnus_pin_functions[] = {653 CYGNUS_PIN_FUNCTION(i2s0),654 CYGNUS_PIN_FUNCTION(i2s1),655 CYGNUS_PIN_FUNCTION(i2s2),656 CYGNUS_PIN_FUNCTION(spdif),657 CYGNUS_PIN_FUNCTION(pwm0),658 CYGNUS_PIN_FUNCTION(pwm1),659 CYGNUS_PIN_FUNCTION(pwm2),660 CYGNUS_PIN_FUNCTION(pwm3),661 CYGNUS_PIN_FUNCTION(pwm4),662 CYGNUS_PIN_FUNCTION(pwm5),663 CYGNUS_PIN_FUNCTION(key),664 CYGNUS_PIN_FUNCTION(audio_dte),665 CYGNUS_PIN_FUNCTION(smart_card0),666 CYGNUS_PIN_FUNCTION(smart_card1),667 CYGNUS_PIN_FUNCTION(spi0),668 CYGNUS_PIN_FUNCTION(spi1),669 CYGNUS_PIN_FUNCTION(spi2),670 CYGNUS_PIN_FUNCTION(spi3),671 CYGNUS_PIN_FUNCTION(spi4),672 CYGNUS_PIN_FUNCTION(spi5),673 CYGNUS_PIN_FUNCTION(sw_led0),674 CYGNUS_PIN_FUNCTION(sw_led1),675 CYGNUS_PIN_FUNCTION(sw_led2),676 CYGNUS_PIN_FUNCTION(d1w),677 CYGNUS_PIN_FUNCTION(lcd),678 CYGNUS_PIN_FUNCTION(sram),679 CYGNUS_PIN_FUNCTION(uart0),680 CYGNUS_PIN_FUNCTION(uart1),681 CYGNUS_PIN_FUNCTION(uart2),682 CYGNUS_PIN_FUNCTION(uart3),683 CYGNUS_PIN_FUNCTION(uart4),684 CYGNUS_PIN_FUNCTION(qspi),685 CYGNUS_PIN_FUNCTION(nand),686 CYGNUS_PIN_FUNCTION(sdio0),687 CYGNUS_PIN_FUNCTION(sdio1),688 CYGNUS_PIN_FUNCTION(can0),689 CYGNUS_PIN_FUNCTION(can1),690 CYGNUS_PIN_FUNCTION(cam),691 CYGNUS_PIN_FUNCTION(bsc1),692 CYGNUS_PIN_FUNCTION(pcie_clkreq),693 CYGNUS_PIN_FUNCTION(usb0_oc),694 CYGNUS_PIN_FUNCTION(usb1_oc),695 CYGNUS_PIN_FUNCTION(usb2_oc),696};697 698static int cygnus_get_groups_count(struct pinctrl_dev *pctrl_dev)699{700 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);701 702 return pinctrl->num_groups;703}704 705static const char *cygnus_get_group_name(struct pinctrl_dev *pctrl_dev,706 unsigned selector)707{708 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);709 710 return pinctrl->groups[selector].name;711}712 713static int cygnus_get_group_pins(struct pinctrl_dev *pctrl_dev,714 unsigned selector, const unsigned **pins,715 unsigned *num_pins)716{717 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);718 719 *pins = pinctrl->groups[selector].pins;720 *num_pins = pinctrl->groups[selector].num_pins;721 722 return 0;723}724 725static void cygnus_pin_dbg_show(struct pinctrl_dev *pctrl_dev,726 struct seq_file *s, unsigned offset)727{728 seq_printf(s, " %s", dev_name(pctrl_dev->dev));729}730 731static const struct pinctrl_ops cygnus_pinctrl_ops = {732 .get_groups_count = cygnus_get_groups_count,733 .get_group_name = cygnus_get_group_name,734 .get_group_pins = cygnus_get_group_pins,735 .pin_dbg_show = cygnus_pin_dbg_show,736 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,737 .dt_free_map = pinctrl_utils_free_map,738};739 740static int cygnus_get_functions_count(struct pinctrl_dev *pctrl_dev)741{742 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);743 744 return pinctrl->num_functions;745}746 747static const char *cygnus_get_function_name(struct pinctrl_dev *pctrl_dev,748 unsigned selector)749{750 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);751 752 return pinctrl->functions[selector].name;753}754 755static int cygnus_get_function_groups(struct pinctrl_dev *pctrl_dev,756 unsigned selector,757 const char * const **groups,758 unsigned * const num_groups)759{760 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);761 762 *groups = pinctrl->functions[selector].groups;763 *num_groups = pinctrl->functions[selector].num_groups;764 765 return 0;766}767 768static int cygnus_pinmux_set(struct cygnus_pinctrl *pinctrl,769 const struct cygnus_pin_function *func,770 const struct cygnus_pin_group *grp,771 struct cygnus_mux_log *mux_log)772{773 const struct cygnus_mux *mux = &grp->mux;774 int i;775 u32 val, mask = 0x7;776 unsigned long flags;777 778 for (i = 0; i < CYGNUS_NUM_IOMUX; i++) {779 if (mux->offset != mux_log[i].mux.offset ||780 mux->shift != mux_log[i].mux.shift)781 continue;782 783 /* match found if we reach here */784 785 /* if this is a new configuration, just do it! */786 if (!mux_log[i].is_configured)787 break;788 789 /*790 * IOMUX has been configured previously and one is trying to791 * configure it to a different function792 */793 if (mux_log[i].mux.alt != mux->alt) {794 dev_err(pinctrl->dev,795 "double configuration error detected!\n");796 dev_err(pinctrl->dev, "func:%s grp:%s\n",797 func->name, grp->name);798 return -EINVAL;799 } else {800 /*801 * One tries to configure it to the same function.802 * Just quit and don't bother803 */804 return 0;805 }806 }807 808 mux_log[i].mux.alt = mux->alt;809 mux_log[i].is_configured = true;810 811 spin_lock_irqsave(&pinctrl->lock, flags);812 813 val = readl(pinctrl->base0 + grp->mux.offset);814 val &= ~(mask << grp->mux.shift);815 val |= grp->mux.alt << grp->mux.shift;816 writel(val, pinctrl->base0 + grp->mux.offset);817 818 spin_unlock_irqrestore(&pinctrl->lock, flags);819 820 return 0;821}822 823static int cygnus_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,824 unsigned func_select, unsigned grp_select)825{826 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);827 const struct cygnus_pin_function *func =828 &pinctrl->functions[func_select];829 const struct cygnus_pin_group *grp = &pinctrl->groups[grp_select];830 831 dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",832 func_select, func->name, grp_select, grp->name);833 834 dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",835 grp->mux.offset, grp->mux.shift, grp->mux.alt);836 837 return cygnus_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);838}839 840static int cygnus_gpio_request_enable(struct pinctrl_dev *pctrl_dev,841 struct pinctrl_gpio_range *range,842 unsigned pin)843{844 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);845 const struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;846 u32 val;847 unsigned long flags;848 849 /* not all pins support GPIO pinmux override */850 if (!mux->is_supported)851 return -ENOTSUPP;852 853 spin_lock_irqsave(&pinctrl->lock, flags);854 855 val = readl(pinctrl->base1 + mux->offset);856 val |= 0x3 << mux->shift;857 writel(val, pinctrl->base1 + mux->offset);858 859 spin_unlock_irqrestore(&pinctrl->lock, flags);860 861 dev_dbg(pctrl_dev->dev,862 "gpio request enable pin=%u offset=0x%x shift=%u\n",863 pin, mux->offset, mux->shift);864 865 return 0;866}867 868static void cygnus_gpio_disable_free(struct pinctrl_dev *pctrl_dev,869 struct pinctrl_gpio_range *range,870 unsigned pin)871{872 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);873 struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;874 u32 val;875 unsigned long flags;876 877 if (!mux->is_supported)878 return;879 880 spin_lock_irqsave(&pinctrl->lock, flags);881 882 val = readl(pinctrl->base1 + mux->offset);883 val &= ~(0x3 << mux->shift);884 writel(val, pinctrl->base1 + mux->offset);885 886 spin_unlock_irqrestore(&pinctrl->lock, flags);887 888 dev_err(pctrl_dev->dev,889 "gpio disable free pin=%u offset=0x%x shift=%u\n",890 pin, mux->offset, mux->shift);891}892 893static const struct pinmux_ops cygnus_pinmux_ops = {894 .get_functions_count = cygnus_get_functions_count,895 .get_function_name = cygnus_get_function_name,896 .get_function_groups = cygnus_get_function_groups,897 .set_mux = cygnus_pinmux_set_mux,898 .gpio_request_enable = cygnus_gpio_request_enable,899 .gpio_disable_free = cygnus_gpio_disable_free,900};901 902static struct pinctrl_desc cygnus_pinctrl_desc = {903 .name = "cygnus-pinmux",904 .pctlops = &cygnus_pinctrl_ops,905 .pmxops = &cygnus_pinmux_ops,906};907 908static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)909{910 struct cygnus_mux_log *log;911 unsigned int i, j;912 913 pinctrl->mux_log = devm_kcalloc(pinctrl->dev, CYGNUS_NUM_IOMUX,914 sizeof(struct cygnus_mux_log),915 GFP_KERNEL);916 if (!pinctrl->mux_log)917 return -ENOMEM;918 919 for (i = 0; i < CYGNUS_NUM_IOMUX_REGS; i++) {920 for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) {921 log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG922 + j];923 log->mux.offset = i * 4;924 log->mux.shift = j * 4;925 log->mux.alt = 0;926 log->is_configured = false;927 }928 }929 930 return 0;931}932 933static int cygnus_pinmux_probe(struct platform_device *pdev)934{935 struct cygnus_pinctrl *pinctrl;936 int i, ret;937 struct pinctrl_pin_desc *pins;938 unsigned num_pins = ARRAY_SIZE(cygnus_pins);939 940 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);941 if (!pinctrl)942 return -ENOMEM;943 944 pinctrl->dev = &pdev->dev;945 platform_set_drvdata(pdev, pinctrl);946 spin_lock_init(&pinctrl->lock);947 948 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);949 if (IS_ERR(pinctrl->base0)) {950 dev_err(&pdev->dev, "unable to map I/O space\n");951 return PTR_ERR(pinctrl->base0);952 }953 954 pinctrl->base1 = devm_platform_ioremap_resource(pdev, 1);955 if (IS_ERR(pinctrl->base1)) {956 dev_err(&pdev->dev, "unable to map I/O space\n");957 return PTR_ERR(pinctrl->base1);958 }959 960 ret = cygnus_mux_log_init(pinctrl);961 if (ret) {962 dev_err(&pdev->dev, "unable to initialize IOMUX log\n");963 return ret;964 }965 966 pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);967 if (!pins)968 return -ENOMEM;969 970 for (i = 0; i < num_pins; i++) {971 pins[i].number = cygnus_pins[i].pin;972 pins[i].name = cygnus_pins[i].name;973 pins[i].drv_data = &cygnus_pins[i].gpio_mux;974 }975 976 pinctrl->groups = cygnus_pin_groups;977 pinctrl->num_groups = ARRAY_SIZE(cygnus_pin_groups);978 pinctrl->functions = cygnus_pin_functions;979 pinctrl->num_functions = ARRAY_SIZE(cygnus_pin_functions);980 cygnus_pinctrl_desc.pins = pins;981 cygnus_pinctrl_desc.npins = num_pins;982 983 pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &cygnus_pinctrl_desc,984 pinctrl);985 if (IS_ERR(pinctrl->pctl)) {986 dev_err(&pdev->dev, "unable to register Cygnus IOMUX pinctrl\n");987 return PTR_ERR(pinctrl->pctl);988 }989 990 return 0;991}992 993static const struct of_device_id cygnus_pinmux_of_match[] = {994 { .compatible = "brcm,cygnus-pinmux" },995 { }996};997 998static struct platform_driver cygnus_pinmux_driver = {999 .driver = {1000 .name = "cygnus-pinmux",1001 .of_match_table = cygnus_pinmux_of_match,1002 .suppress_bind_attrs = true,1003 },1004 .probe = cygnus_pinmux_probe,1005};1006 1007static int __init cygnus_pinmux_init(void)1008{1009 return platform_driver_register(&cygnus_pinmux_driver);1010}1011arch_initcall(cygnus_pinmux_init);1012