339 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>5 */6 7#include <linux/init.h>8#include <linux/platform_device.h>9#include <linux/of.h>10#include <linux/pinctrl/pinctrl.h>11#include <linux/regmap.h>12#include <dt-bindings/pinctrl/mt65xx.h>13 14#include "pinctrl-mtk-common.h"15#include "pinctrl-mtk-mt8135.h"16 17#define DRV_BASE1 0x50018#define DRV_BASE2 0x51019#define PUPD_BASE1 0x40020#define PUPD_BASE2 0x45021#define R0_BASE1 0x4d022#define R1_BASE1 0x20023#define R1_BASE2 0x25024 25struct mtk_spec_pull_set {26 unsigned char pin;27 unsigned char pupd_bit;28 unsigned short pupd_offset;29 unsigned short r0_offset;30 unsigned short r1_offset;31 unsigned char r0_bit;32 unsigned char r1_bit;33};34 35#define SPEC_PULL(_pin, _pupd_offset, _pupd_bit, _r0_offset, \36 _r0_bit, _r1_offset, _r1_bit) \37 { \38 .pin = _pin, \39 .pupd_offset = _pupd_offset, \40 .pupd_bit = _pupd_bit, \41 .r0_offset = _r0_offset, \42 .r0_bit = _r0_bit, \43 .r1_offset = _r1_offset, \44 .r1_bit = _r1_bit, \45 }46 47static const struct mtk_drv_group_desc mt8135_drv_grp[] = {48 /* E8E4E2 2/4/6/8/10/12/14/16 */49 MTK_DRV_GRP(2, 16, 0, 2, 2),50 /* E8E4 4/8/12/16 */51 MTK_DRV_GRP(4, 16, 1, 2, 4),52 /* E4E2 2/4/6/8 */53 MTK_DRV_GRP(2, 8, 0, 1, 2),54 /* E16E8E4 4/8/12/16/20/24/28/32 */55 MTK_DRV_GRP(4, 32, 0, 2, 4)56};57 58static const struct mtk_pin_drv_grp mt8135_pin_drv[] = {59 MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),60 MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),61 MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),62 MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),63 MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),64 MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),65 MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),66 MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),67 MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),68 MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),69 70 MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1),71 MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1),72 MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1),73 MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1),74 MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1),75 MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1),76 MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1),77 MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1),78 MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1),79 MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1),80 MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1),81 MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1),82 MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1),83 MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1),84 MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1),85 MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1),86 MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2),87 MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1),88 MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1),89 MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1),90 MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1),91 MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1),92 MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1),93 MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1),94 MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1),95 MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1),96 MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1),97 MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1),98 99 MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),100 MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),101 MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),102 MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),103 MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),104 MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),105 MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),106 MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),107 108 MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),109 MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),110 MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),111 MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),112 MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),113 MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),114 MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),115 MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1),116 MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1),117 MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1),118 MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1),119 MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1),120 MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1),121 122 MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1),123 MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1),124 MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1),125 MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1),126 MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1),127 MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1),128 MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1),129 MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3),130 MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3),131 132 MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3),133 MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3),134 135 MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3),136 MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3),137 138 MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3),139 MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3),140 MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3),141 MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3),142 MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3),143 MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3),144 145 MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),146 MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),147 MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),148 MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),149 MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),150 MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),151 MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),152 153 MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0),154 155 MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),156 MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),157 MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1),158 MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1),159 MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1),160 161 162 MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1),163 MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1),164 MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1),165 MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1),166 MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1),167 MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2),168 MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2),169 MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2),170 MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2),171 MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2),172 MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2),173 174 MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2),175 MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2),176 MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2),177 MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2),178 MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2),179 MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2),180 181 MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1),182 MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1),183 MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1),184 MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1),185 MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1),186 187 MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2),188 MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2),189 MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2),190 MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2),191 MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1),192 MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1),193 MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1),194 195 MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0),196 MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0),197 MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0),198 MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0),199 MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0),200 MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0)201};202 203static const struct mtk_spec_pull_set spec_pupd[] = {204 SPEC_PULL(0, PUPD_BASE1, 0, R0_BASE1, 9, R1_BASE1, 0),205 SPEC_PULL(1, PUPD_BASE1, 1, R0_BASE1, 8, R1_BASE1, 1),206 SPEC_PULL(2, PUPD_BASE1, 2, R0_BASE1, 7, R1_BASE1, 2),207 SPEC_PULL(3, PUPD_BASE1, 3, R0_BASE1, 6, R1_BASE1, 3),208 SPEC_PULL(4, PUPD_BASE1, 4, R0_BASE1, 1, R1_BASE1, 4),209 SPEC_PULL(5, PUPD_BASE1, 5, R0_BASE1, 0, R1_BASE1, 5),210 SPEC_PULL(6, PUPD_BASE1, 6, R0_BASE1, 5, R1_BASE1, 6),211 SPEC_PULL(7, PUPD_BASE1, 7, R0_BASE1, 4, R1_BASE1, 7),212 SPEC_PULL(8, PUPD_BASE1, 8, R0_BASE1, 3, R1_BASE1, 8),213 SPEC_PULL(9, PUPD_BASE1, 9, R0_BASE1, 2, R1_BASE1, 9),214 SPEC_PULL(89, PUPD_BASE2, 9, R0_BASE1, 18, R1_BASE2, 9),215 SPEC_PULL(90, PUPD_BASE2, 10, R0_BASE1, 19, R1_BASE2, 10),216 SPEC_PULL(91, PUPD_BASE2, 11, R0_BASE1, 23, R1_BASE2, 11),217 SPEC_PULL(92, PUPD_BASE2, 12, R0_BASE1, 24, R1_BASE2, 12),218 SPEC_PULL(93, PUPD_BASE2, 13, R0_BASE1, 25, R1_BASE2, 13),219 SPEC_PULL(94, PUPD_BASE2, 14, R0_BASE1, 22, R1_BASE2, 14),220 SPEC_PULL(95, PUPD_BASE2, 15, R0_BASE1, 20, R1_BASE2, 15),221 SPEC_PULL(96, PUPD_BASE2+0x10, 0, R0_BASE1, 16, R1_BASE2+0x10, 0),222 SPEC_PULL(97, PUPD_BASE2+0x10, 1, R0_BASE1, 21, R1_BASE2+0x10, 1),223 SPEC_PULL(98, PUPD_BASE2+0x10, 2, R0_BASE1, 17, R1_BASE2+0x10, 2),224 SPEC_PULL(197, PUPD_BASE1+0xc0, 5, R0_BASE1, 13, R1_BASE2+0xc0, 5),225 SPEC_PULL(198, PUPD_BASE2+0xc0, 6, R0_BASE1, 14, R1_BASE2+0xc0, 6),226 SPEC_PULL(199, PUPD_BASE2+0xc0, 7, R0_BASE1, 11, R1_BASE2+0xc0, 7),227 SPEC_PULL(200, PUPD_BASE2+0xc0, 8, R0_BASE1, 10, R1_BASE2+0xc0, 8),228 SPEC_PULL(201, PUPD_BASE2+0xc0, 9, R0_BASE1, 13, R1_BASE2+0xc0, 9),229 SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)230};231 232static int spec_pull_set(struct regmap *regmap,233 const struct mtk_pinctrl_devdata *devdata,234 unsigned int pin, bool isup, unsigned int r1r0)235{236 unsigned int i;237 unsigned int reg_pupd, reg_set_r0, reg_set_r1;238 unsigned int reg_rst_r0, reg_rst_r1;239 unsigned char align = devdata->port_align;240 bool find = false;241 242 for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {243 if (pin == spec_pupd[i].pin) {244 find = true;245 break;246 }247 }248 249 if (!find)250 return -EINVAL;251 252 if (isup)253 reg_pupd = spec_pupd[i].pupd_offset + align;254 else255 reg_pupd = spec_pupd[i].pupd_offset + (align << 1);256 257 regmap_write(regmap, reg_pupd, spec_pupd[i].pupd_bit);258 259 reg_set_r0 = spec_pupd[i].r0_offset + align;260 reg_rst_r0 = spec_pupd[i].r0_offset + (align << 1);261 reg_set_r1 = spec_pupd[i].r1_offset + align;262 reg_rst_r1 = spec_pupd[i].r1_offset + (align << 1);263 264 switch (r1r0) {265 case MTK_PUPD_SET_R1R0_00:266 regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);267 regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);268 break;269 case MTK_PUPD_SET_R1R0_01:270 regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);271 regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);272 break;273 case MTK_PUPD_SET_R1R0_10:274 regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);275 regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);276 break;277 case MTK_PUPD_SET_R1R0_11:278 regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);279 regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);280 break;281 default:282 return -EINVAL;283 }284 285 return 0;286}287 288static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {289 .pins = mtk_pins_mt8135,290 .npins = ARRAY_SIZE(mtk_pins_mt8135),291 .grp_desc = mt8135_drv_grp,292 .n_grp_cls = ARRAY_SIZE(mt8135_drv_grp),293 .pin_drv_grp = mt8135_pin_drv,294 .n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv),295 .spec_pull_set = spec_pull_set,296 .dir_offset = 0x0000,297 .ies_offset = 0x0100,298 .pullen_offset = 0x0200,299 .smt_offset = 0x0300,300 .pullsel_offset = 0x0400,301 .dout_offset = 0x0800,302 .din_offset = 0x0A00,303 .pinmux_offset = 0x0C00,304 .type1_start = 34,305 .type1_end = 149,306 .port_shf = 4,307 .port_mask = 0xf,308 .port_align = 4,309 .mode_mask = 0xf,310 .mode_per_reg = 5,311 .mode_shf = 4,312 .eint_hw = {313 .port_mask = 7,314 .ports = 6,315 .ap_num = 192,316 .db_cnt = 16,317 .db_time = debounce_time_mt2701,318 },319};320 321static const struct of_device_id mt8135_pctrl_match[] = {322 { .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data },323 { }324};325 326static struct platform_driver mtk_pinctrl_driver = {327 .probe = mtk_pctrl_common_probe,328 .driver = {329 .name = "mediatek-mt8135-pinctrl",330 .of_match_table = mt8135_pctrl_match,331 },332};333 334static int __init mtk_pinctrl_init(void)335{336 return platform_driver_register(&mtk_pinctrl_driver);337}338arch_initcall(mtk_pinctrl_init);339