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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Pinmux & pinconf driver for the IP block found in the Nomadik SoC. This4 * depends on gpio-nomadik and some handling is intertwined; see nmk_gpio_chips5 * which is used by this driver to access the GPIO banks array.6 *7 * Copyright (C) 2008,2009 STMicroelectronics8 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>9 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>10 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>11 */12 13#include <linux/bitops.h>14#include <linux/cleanup.h>15#include <linux/clk.h>16#include <linux/device.h>17#include <linux/err.h>18#include <linux/gpio/driver.h>19#include <linux/init.h>20#include <linux/interrupt.h>21#include <linux/io.h>22#include <linux/kernel.h>23#include <linux/of.h>24#include <linux/of_address.h>25#include <linux/of_platform.h>26#include <linux/platform_device.h>27#include <linux/property.h>28#include <linux/seq_file.h>29#include <linux/slab.h>30#include <linux/spinlock.h>31#include <linux/types.h>32 33/* Since we request GPIOs from ourself */34#include <linux/pinctrl/consumer.h>35#include <linux/pinctrl/machine.h>36#include <linux/pinctrl/pinconf.h>37#include <linux/pinctrl/pinctrl.h>38#include <linux/pinctrl/pinmux.h>39 40#include "../core.h"41#include "../pinctrl-utils.h"42 43#include <linux/gpio/gpio-nomadik.h>44 45/*46 * pin configurations are represented by 32-bit integers:47 *48 * bit 0.. 8 - Pin Number (512 Pins Maximum)49 * bit 9..10 - Alternate Function Selection50 * bit 11..12 - Pull up/down state51 * bit 13 - Sleep mode behaviour52 * bit 14 - Direction53 * bit 15 - Value (if output)54 * bit 16..18 - SLPM pull up/down state55 * bit 19..20 - SLPM direction56 * bit 21..22 - SLPM Value (if output)57 * bit 23..25 - PDIS value (if input)58 * bit 26 - Gpio mode59 * bit 27 - Sleep mode60 *61 * to facilitate the definition, the following macros are provided62 *63 * PIN_CFG_DEFAULT - default config (0):64 * pull up/down = disabled65 * sleep mode = input/wakeup66 * direction = input67 * value = low68 * SLPM direction = same as normal69 * SLPM pull = same as normal70 * SLPM value = same as normal71 *72 * PIN_CFG - default config with alternate function73 */74 75#define PIN_NUM_MASK 0x1ff76#define PIN_NUM(x) ((x) & PIN_NUM_MASK)77 78#define PIN_ALT_SHIFT 979#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)80#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)81#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)82#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)83#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)84#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)85 86#define PIN_PULL_SHIFT 1187#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)88#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)89#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)90#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)91#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)92 93#define PIN_SLPM_SHIFT 1394#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)95#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)96#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)97#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)98/* These two replace the above in DB8500v2+ */99#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)100#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)101#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE102 103#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */104#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */105 106#define PIN_DIR_SHIFT 14107#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)108#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)109#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)110#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)111 112#define PIN_VAL_SHIFT 15113#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)114#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)115#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)116#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)117 118#define PIN_SLPM_PULL_SHIFT 16119#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)120#define PIN_SLPM_PULL(x) \121 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)122#define PIN_SLPM_PULL_NONE \123 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)124#define PIN_SLPM_PULL_UP \125 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)126#define PIN_SLPM_PULL_DOWN \127 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)128 129#define PIN_SLPM_DIR_SHIFT 19130#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)131#define PIN_SLPM_DIR(x) \132 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)133#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)134#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)135 136#define PIN_SLPM_VAL_SHIFT 21137#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)138#define PIN_SLPM_VAL(x) \139 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)140#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)141#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)142 143#define PIN_SLPM_PDIS_SHIFT 23144#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)145#define PIN_SLPM_PDIS(x) \146 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)147#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)148#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)149#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)150 151#define PIN_LOWEMI_SHIFT 25152#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)153#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)154#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)155#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)156 157#define PIN_GPIOMODE_SHIFT 26158#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)159#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)160#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)161#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)162 163#define PIN_SLEEPMODE_SHIFT 27164#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)165#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)166#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)167#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)168 169/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */170#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)171#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)172#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)173#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)174#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)175 176#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)177#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)178#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)179#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)180#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)181 182#define PIN_CFG_DEFAULT (0)183 184#define PIN_CFG(num, alt) \185 (PIN_CFG_DEFAULT |\186 (PIN_NUM(num) | PIN_##alt))187 188#define PIN_CFG_INPUT(num, alt, pull) \189 (PIN_CFG_DEFAULT |\190 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))191 192#define PIN_CFG_OUTPUT(num, alt, val) \193 (PIN_CFG_DEFAULT |\194 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))195 196/**197 * struct nmk_pinctrl - state container for the Nomadik pin controller198 * @dev: containing device pointer199 * @pctl: corresponding pin controller device200 * @soc: SoC data for this specific chip201 * @prcm_base: PRCM register range virtual base202 */203struct nmk_pinctrl {204 struct device *dev;205 struct pinctrl_dev *pctl;206 const struct nmk_pinctrl_soc_data *soc;207 void __iomem *prcm_base;208};209 210/* See nmk_gpio_populate_chip() that fills this array. */211struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];212 213DEFINE_SPINLOCK(nmk_gpio_slpm_lock);214 215static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,216 unsigned int offset, int gpio_mode)217{218 u32 afunc, bfunc;219 220 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);221 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);222 if (gpio_mode & NMK_GPIO_ALT_A)223 afunc |= BIT(offset);224 if (gpio_mode & NMK_GPIO_ALT_B)225 bfunc |= BIT(offset);226 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);227 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);228}229 230static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,231 unsigned int offset, enum nmk_gpio_pull pull)232{233 u32 pdis;234 235 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);236 if (pull == NMK_GPIO_PULL_NONE) {237 pdis |= BIT(offset);238 nmk_chip->pull_up &= ~BIT(offset);239 } else {240 pdis &= ~BIT(offset);241 }242 243 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);244 245 if (pull == NMK_GPIO_PULL_UP) {246 nmk_chip->pull_up |= BIT(offset);247 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);248 } else if (pull == NMK_GPIO_PULL_DOWN) {249 nmk_chip->pull_up &= ~BIT(offset);250 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);251 }252}253 254static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,255 unsigned int offset, bool lowemi)256{257 bool enabled = nmk_chip->lowemi & BIT(offset);258 259 if (lowemi == enabled)260 return;261 262 if (lowemi)263 nmk_chip->lowemi |= BIT(offset);264 else265 nmk_chip->lowemi &= ~BIT(offset);266 267 writel_relaxed(nmk_chip->lowemi,268 nmk_chip->addr + NMK_GPIO_LOWEMI);269}270 271static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,272 unsigned int offset)273{274 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);275}276 277static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,278 unsigned int offset, int gpio_mode,279 bool glitch)280{281 u32 rwimsc = nmk_chip->rwimsc;282 u32 fwimsc = nmk_chip->fwimsc;283 284 if (glitch && nmk_chip->set_ioforce) {285 u32 bit = BIT(offset);286 287 /* Prevent spurious wakeups */288 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);289 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);290 291 nmk_chip->set_ioforce(true);292 }293 294 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);295 296 if (glitch && nmk_chip->set_ioforce) {297 nmk_chip->set_ioforce(false);298 299 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);300 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);301 }302}303 304static void305nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned int offset)306{307 u32 falling = nmk_chip->fimsc & BIT(offset);308 u32 rising = nmk_chip->rimsc & BIT(offset);309 int gpio = nmk_chip->chip.base + offset;310 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);311 struct irq_data *d = irq_get_irq_data(irq);312 313 if (!rising && !falling)314 return;315 316 if (!d || !irqd_irq_disabled(d))317 return;318 319 if (rising) {320 nmk_chip->rimsc &= ~BIT(offset);321 writel_relaxed(nmk_chip->rimsc,322 nmk_chip->addr + NMK_GPIO_RIMSC);323 }324 325 if (falling) {326 nmk_chip->fimsc &= ~BIT(offset);327 writel_relaxed(nmk_chip->fimsc,328 nmk_chip->addr + NMK_GPIO_FIMSC);329 }330 331 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);332}333 334static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)335{336 u32 val;337 338 val = readl(reg);339 val = ((val & ~mask) | (value & mask));340 writel(val, reg);341}342 343static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,344 unsigned int offset, unsigned int alt_num)345{346 int i;347 u16 reg;348 u8 bit;349 u8 alt_index;350 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;351 const u16 *gpiocr_regs;352 353 if (!npct->prcm_base)354 return;355 356 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {357 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",358 alt_num);359 return;360 }361 362 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {363 if (npct->soc->altcx_pins[i].pin == offset)364 break;365 }366 if (i == npct->soc->npins_altcx) {367 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",368 offset);369 return;370 }371 372 pin_desc = npct->soc->altcx_pins + i;373 gpiocr_regs = npct->soc->prcm_gpiocr_registers;374 375 /*376 * If alt_num is NULL, just clear current ALTCx selection377 * to make sure we come back to a pure ALTC selection378 */379 if (!alt_num) {380 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {381 if (pin_desc->altcx[i].used) {382 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];383 bit = pin_desc->altcx[i].control_bit;384 if (readl(npct->prcm_base + reg) & BIT(bit)) {385 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);386 dev_dbg(npct->dev,387 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",388 offset, i + 1);389 }390 }391 }392 return;393 }394 395 alt_index = alt_num - 1;396 if (!pin_desc->altcx[alt_index].used) {397 dev_warn(npct->dev,398 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",399 offset, alt_num);400 return;401 }402 403 /*404 * Check if any other ALTCx functions are activated on this pin405 * and disable it first.406 */407 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {408 if (i == alt_index)409 continue;410 if (pin_desc->altcx[i].used) {411 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];412 bit = pin_desc->altcx[i].control_bit;413 if (readl(npct->prcm_base + reg) & BIT(bit)) {414 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);415 dev_dbg(npct->dev,416 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",417 offset, i + 1);418 }419 }420 }421 422 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];423 bit = pin_desc->altcx[alt_index].control_bit;424 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",425 offset, alt_index + 1);426 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));427}428 429/*430 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:431 * - Save SLPM registers432 * - Set SLPM=0 for the IOs you want to switch and others to 1433 * - Configure the GPIO registers for the IOs that are being switched434 * - Set IOFORCE=1435 * - Modify the AFLSA/B registers for the IOs that are being switched436 * - Set IOFORCE=0437 * - Restore SLPM registers438 * - Any spurious wake up event during switch sequence to be ignored and439 * cleared440 */441static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)442{443 int i;444 445 for (i = 0; i < NMK_MAX_BANKS; i++) {446 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];447 unsigned int temp = slpm[i];448 449 if (!chip)450 break;451 452 clk_enable(chip->clk);453 454 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);455 writel(temp, chip->addr + NMK_GPIO_SLPC);456 }457}458 459static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)460{461 int i;462 463 for (i = 0; i < NMK_MAX_BANKS; i++) {464 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];465 466 if (!chip)467 break;468 469 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);470 471 clk_disable(chip->clk);472 }473}474 475/* Only called by gpio-nomadik but requires knowledge of struct nmk_pinctrl. */476int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)477{478 int i;479 u16 reg;480 u8 bit;481 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);482 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;483 const u16 *gpiocr_regs;484 485 if (!npct->prcm_base)486 return NMK_GPIO_ALT_C;487 488 for (i = 0; i < npct->soc->npins_altcx; i++) {489 if (npct->soc->altcx_pins[i].pin == gpio)490 break;491 }492 if (i == npct->soc->npins_altcx)493 return NMK_GPIO_ALT_C;494 495 pin_desc = npct->soc->altcx_pins + i;496 gpiocr_regs = npct->soc->prcm_gpiocr_registers;497 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {498 if (pin_desc->altcx[i].used) {499 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];500 bit = pin_desc->altcx[i].control_bit;501 if (readl(npct->prcm_base + reg) & BIT(bit))502 return NMK_GPIO_ALT_C + i + 1;503 }504 }505 return NMK_GPIO_ALT_C;506}507 508static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)509{510 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);511 512 return npct->soc->ngroups;513}514 515static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,516 unsigned int selector)517{518 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);519 520 return npct->soc->groups[selector].grp.name;521}522 523static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,524 const unsigned int **pins,525 unsigned int *num_pins)526{527 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);528 529 *pins = npct->soc->groups[selector].grp.pins;530 *num_pins = npct->soc->groups[selector].grp.npins;531 return 0;532}533 534/* This makes the mapping from pin number to a GPIO chip. We also return the pin535 * offset in the GPIO chip for convenience (and to avoid a second loop).536 */537static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned int pin,538 unsigned int *offset)539{540 int i, j = 0;541 struct nmk_gpio_chip *nmk_gpio;542 543 /* We assume that pins are allocated in bank order. */544 for (i = 0; i < NMK_MAX_BANKS; i++) {545 nmk_gpio = nmk_gpio_chips[i];546 if (!nmk_gpio)547 continue;548 if (pin >= j && pin < j + nmk_gpio->chip.ngpio) {549 if (offset)550 *offset = pin - j;551 return nmk_gpio;552 }553 j += nmk_gpio->chip.ngpio;554 }555 return NULL;556}557 558static struct gpio_chip *find_gc_from_pin(unsigned int pin)559{560 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin, NULL);561 562 if (nmk_gpio)563 return &nmk_gpio->chip;564 return NULL;565}566 567static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,568 unsigned int offset)569{570 struct gpio_chip *chip = find_gc_from_pin(offset);571 572 if (!chip) {573 seq_printf(s, "invalid pin offset");574 return;575 }576 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);577}578 579static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,580 unsigned int *num_maps, const char *group,581 const char *function)582{583 if (*num_maps == *reserved_maps)584 return -ENOSPC;585 586 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;587 (*map)[*num_maps].data.mux.group = group;588 (*map)[*num_maps].data.mux.function = function;589 (*num_maps)++;590 591 return 0;592}593 594static int nmk_dt_add_map_configs(struct pinctrl_map **map,595 unsigned int *reserved_maps,596 unsigned int *num_maps, const char *group,597 unsigned long *configs, unsigned int num_configs)598{599 unsigned long *dup_configs;600 601 if (*num_maps == *reserved_maps)602 return -ENOSPC;603 604 dup_configs = kmemdup_array(configs, num_configs, sizeof(*dup_configs), GFP_KERNEL);605 if (!dup_configs)606 return -ENOMEM;607 608 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;609 610 (*map)[*num_maps].data.configs.group_or_pin = group;611 (*map)[*num_maps].data.configs.configs = dup_configs;612 (*map)[*num_maps].data.configs.num_configs = num_configs;613 (*num_maps)++;614 615 return 0;616}617 618#define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }619#define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \620 .size = ARRAY_SIZE(y), }621 622static const unsigned long nmk_pin_input_modes[] = {623 PIN_INPUT_NOPULL,624 PIN_INPUT_PULLUP,625 PIN_INPUT_PULLDOWN,626};627 628static const unsigned long nmk_pin_output_modes[] = {629 PIN_OUTPUT_LOW,630 PIN_OUTPUT_HIGH,631 PIN_DIR_OUTPUT,632};633 634static const unsigned long nmk_pin_sleep_modes[] = {635 PIN_SLEEPMODE_DISABLED,636 PIN_SLEEPMODE_ENABLED,637};638 639static const unsigned long nmk_pin_sleep_input_modes[] = {640 PIN_SLPM_INPUT_NOPULL,641 PIN_SLPM_INPUT_PULLUP,642 PIN_SLPM_INPUT_PULLDOWN,643 PIN_SLPM_DIR_INPUT,644};645 646static const unsigned long nmk_pin_sleep_output_modes[] = {647 PIN_SLPM_OUTPUT_LOW,648 PIN_SLPM_OUTPUT_HIGH,649 PIN_SLPM_DIR_OUTPUT,650};651 652static const unsigned long nmk_pin_sleep_wakeup_modes[] = {653 PIN_SLPM_WAKEUP_DISABLE,654 PIN_SLPM_WAKEUP_ENABLE,655};656 657static const unsigned long nmk_pin_gpio_modes[] = {658 PIN_GPIOMODE_DISABLED,659 PIN_GPIOMODE_ENABLED,660};661 662static const unsigned long nmk_pin_sleep_pdis_modes[] = {663 PIN_SLPM_PDIS_DISABLED,664 PIN_SLPM_PDIS_ENABLED,665};666 667struct nmk_cfg_param {668 const char *property;669 unsigned long config;670 const unsigned long *choice;671 int size;672};673 674static const struct nmk_cfg_param nmk_cfg_params[] = {675 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),676 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),677 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),678 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),679 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),680 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),681 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),682 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),683};684 685static int nmk_dt_pin_config(int index, int val, unsigned long *config)686{687 if (!nmk_cfg_params[index].choice) {688 *config = nmk_cfg_params[index].config;689 } else {690 /* test if out of range */691 if (val < nmk_cfg_params[index].size) {692 *config = nmk_cfg_params[index].config |693 nmk_cfg_params[index].choice[val];694 }695 }696 return 0;697}698 699static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)700{701 int i, pin_number;702 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);703 704 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)705 for (i = 0; i < npct->soc->npins; i++)706 if (npct->soc->pins[i].number == pin_number)707 return npct->soc->pins[i].name;708 return NULL;709}710 711static bool nmk_pinctrl_dt_get_config(struct device_node *np,712 unsigned long *configs)713{714 bool has_config = 0;715 unsigned long cfg = 0;716 int i, val, ret;717 718 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {719 ret = of_property_read_u32(np, nmk_cfg_params[i].property, &val);720 if (ret != -EINVAL) {721 if (nmk_dt_pin_config(i, val, &cfg) == 0) {722 *configs |= cfg;723 has_config = 1;724 }725 }726 }727 728 return has_config;729}730 731static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,732 struct device_node *np,733 struct pinctrl_map **map,734 unsigned int *reserved_maps,735 unsigned int *num_maps)736{737 int ret;738 const char *function = NULL;739 unsigned long configs = 0;740 bool has_config = 0;741 struct property *prop;742 struct device_node *np_config;743 744 ret = of_property_read_string(np, "function", &function);745 if (ret >= 0) {746 const char *group;747 748 ret = of_property_count_strings(np, "groups");749 if (ret < 0)750 goto exit;751 752 ret = pinctrl_utils_reserve_map(pctldev, map,753 reserved_maps,754 num_maps, ret);755 if (ret < 0)756 goto exit;757 758 of_property_for_each_string(np, "groups", prop, group) {759 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,760 group, function);761 if (ret < 0)762 goto exit;763 }764 }765 766 has_config = nmk_pinctrl_dt_get_config(np, &configs);767 np_config = of_parse_phandle(np, "ste,config", 0);768 if (np_config) {769 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);770 of_node_put(np_config);771 }772 if (has_config) {773 const char *gpio_name;774 const char *pin;775 776 ret = of_property_count_strings(np, "pins");777 if (ret < 0)778 goto exit;779 ret = pinctrl_utils_reserve_map(pctldev, map,780 reserved_maps,781 num_maps, ret);782 if (ret < 0)783 goto exit;784 785 of_property_for_each_string(np, "pins", prop, pin) {786 gpio_name = nmk_find_pin_name(pctldev, pin);787 788 ret = nmk_dt_add_map_configs(map, reserved_maps,789 num_maps,790 gpio_name, &configs, 1);791 if (ret < 0)792 goto exit;793 }794 }795 796exit:797 return ret;798}799 800static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,801 struct device_node *np_config,802 struct pinctrl_map **map,803 unsigned int *num_maps)804{805 unsigned int reserved_maps;806 int ret;807 808 reserved_maps = 0;809 *map = NULL;810 *num_maps = 0;811 812 for_each_child_of_node_scoped(np_config, np) {813 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,814 &reserved_maps, num_maps);815 if (ret < 0) {816 pinctrl_utils_free_map(pctldev, *map, *num_maps);817 return ret;818 }819 }820 821 return 0;822}823 824static const struct pinctrl_ops nmk_pinctrl_ops = {825 .get_groups_count = nmk_get_groups_cnt,826 .get_group_name = nmk_get_group_name,827 .get_group_pins = nmk_get_group_pins,828 .pin_dbg_show = nmk_pin_dbg_show,829 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,830 .dt_free_map = pinctrl_utils_free_map,831};832 833static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)834{835 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);836 837 return npct->soc->nfunctions;838}839 840static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,841 unsigned int function)842{843 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);844 845 return npct->soc->functions[function].name;846}847 848static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,849 unsigned int function,850 const char * const **groups,851 unsigned * const num_groups)852{853 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);854 855 *groups = npct->soc->functions[function].groups;856 *num_groups = npct->soc->functions[function].ngroups;857 858 return 0;859}860 861static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned int function,862 unsigned int group)863{864 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);865 const struct nmk_pingroup *g;866 static unsigned int slpm[NMK_MAX_BANKS];867 unsigned long flags = 0;868 bool glitch;869 int ret = -EINVAL;870 int i;871 872 g = &npct->soc->groups[group];873 874 if (g->altsetting < 0)875 return -EINVAL;876 877 dev_dbg(npct->dev, "enable group %s, %zu pins\n", g->grp.name, g->grp.npins);878 879 /*880 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,881 * we may pass through an undesired state. In this case we take882 * some extra care.883 *884 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:885 * - Save SLPM registers (since we have a shadow register in the886 * nmk_chip we're using that as backup)887 * - Set SLPM=0 for the IOs you want to switch and others to 1888 * - Configure the GPIO registers for the IOs that are being switched889 * - Set IOFORCE=1890 * - Modify the AFLSA/B registers for the IOs that are being switched891 * - Set IOFORCE=0892 * - Restore SLPM registers893 * - Any spurious wake up event during switch sequence to be ignored894 * and cleared895 *896 * We REALLY need to save ALL slpm registers, because the external897 * IOFORCE will switch *all* ports to their sleepmode setting to as898 * to avoid glitches. (Not just one port!)899 */900 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);901 902 if (glitch) {903 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);904 905 /* Initially don't put any pins to sleep when switching */906 memset(slpm, 0xff, sizeof(slpm));907 908 /*909 * Then mask the pins that need to be sleeping now when we're910 * switching to the ALT C function.911 */912 for (i = 0; i < g->grp.npins; i++) {913 struct nmk_gpio_chip *nmk_chip;914 unsigned int bit;915 916 nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i], &bit);917 if (!nmk_chip) {918 dev_err(npct->dev,919 "invalid pin offset %d in group %s at index %d\n",920 g->grp.pins[i], g->grp.name, i);921 goto out_pre_slpm_init;922 }923 924 slpm[nmk_chip->bank] &= ~BIT(bit);925 }926 nmk_gpio_glitch_slpm_init(slpm);927 }928 929 for (i = 0; i < g->grp.npins; i++) {930 struct nmk_gpio_chip *nmk_chip;931 unsigned int bit;932 933 nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i], &bit);934 if (!nmk_chip) {935 dev_err(npct->dev,936 "invalid pin offset %d in group %s at index %d\n",937 g->grp.pins[i], g->grp.name, i);938 goto out_glitch;939 }940 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n",941 g->grp.pins[i], g->altsetting);942 943 clk_enable(nmk_chip->clk);944 /*945 * If the pin is switching to altfunc, and there was an946 * interrupt installed on it which has been lazy disabled,947 * actually mask the interrupt to prevent spurious interrupts948 * that would occur while the pin is under control of the949 * peripheral. Only SKE does this.950 */951 nmk_gpio_disable_lazy_irq(nmk_chip, bit);952 953 __nmk_gpio_set_mode_safe(nmk_chip, bit,954 (g->altsetting & NMK_GPIO_ALT_C), glitch);955 clk_disable(nmk_chip->clk);956 957 /*958 * Call PRCM GPIOCR config function in case ALTC959 * has been selected:960 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers961 * must be set.962 * - If selection is pure ALTC and previous selection was ALTCx,963 * then some bits in PRCM GPIOCR registers must be cleared.964 */965 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)966 nmk_prcm_altcx_set_mode(npct, g->grp.pins[i],967 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);968 }969 970 /* When all pins are successfully reconfigured we get here */971 ret = 0;972 973out_glitch:974 if (glitch)975 nmk_gpio_glitch_slpm_restore(slpm);976out_pre_slpm_init:977 if (glitch)978 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);979 980 return ret;981}982 983static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,984 struct pinctrl_gpio_range *range,985 unsigned int pin)986{987 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);988 struct nmk_gpio_chip *nmk_chip;989 struct gpio_chip *chip;990 unsigned int bit;991 992 if (!range) {993 dev_err(npct->dev, "invalid range\n");994 return -EINVAL;995 }996 if (!range->gc) {997 dev_err(npct->dev, "missing GPIO chip in range\n");998 return -EINVAL;999 }1000 chip = range->gc;1001 nmk_chip = gpiochip_get_data(chip);1002 1003 dev_dbg(npct->dev, "enable pin %u as GPIO\n", pin);1004 1005 find_nmk_gpio_from_pin(pin, &bit);1006 1007 clk_enable(nmk_chip->clk);1008 /* There is no glitch when converting any pin to GPIO */1009 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);1010 clk_disable(nmk_chip->clk);1011 1012 return 0;1013}1014 1015static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,1016 struct pinctrl_gpio_range *range,1017 unsigned int pin)1018{1019 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);1020 1021 dev_dbg(npct->dev, "disable pin %u as GPIO\n", pin);1022 /* Set the pin to some default state, GPIO is usually default */1023}1024 1025static const struct pinmux_ops nmk_pinmux_ops = {1026 .get_functions_count = nmk_pmx_get_funcs_cnt,1027 .get_function_name = nmk_pmx_get_func_name,1028 .get_function_groups = nmk_pmx_get_func_groups,1029 .set_mux = nmk_pmx_set,1030 .gpio_request_enable = nmk_gpio_request_enable,1031 .gpio_disable_free = nmk_gpio_disable_free,1032 .strict = true,1033};1034 1035static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,1036 unsigned long *config)1037{1038 /* Not implemented */1039 return -EINVAL;1040}1041 1042static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,1043 unsigned long *configs, unsigned int num_configs)1044{1045 static const char * const pullnames[] = {1046 [NMK_GPIO_PULL_NONE] = "none",1047 [NMK_GPIO_PULL_UP] = "up",1048 [NMK_GPIO_PULL_DOWN] = "down",1049 [3] /* illegal */ = "??"1050 };1051 static const char * const slpmnames[] = {1052 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",1053 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",1054 };1055 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);1056 struct nmk_gpio_chip *nmk_chip;1057 unsigned int bit;1058 unsigned long cfg;1059 int pull, slpm, output, val, i;1060 bool lowemi, gpiomode, sleep;1061 1062 nmk_chip = find_nmk_gpio_from_pin(pin, &bit);1063 if (!nmk_chip) {1064 dev_err(npct->dev,1065 "invalid pin offset %d\n", pin);1066 return -EINVAL;1067 }1068 1069 for (i = 0; i < num_configs; i++) {1070 /*1071 * The pin config contains pin number and altfunction fields,1072 * here we just ignore that part. It's being handled by the1073 * framework and pinmux callback respectively.1074 */1075 cfg = configs[i];1076 pull = PIN_PULL(cfg);1077 slpm = PIN_SLPM(cfg);1078 output = PIN_DIR(cfg);1079 val = PIN_VAL(cfg);1080 lowemi = PIN_LOWEMI(cfg);1081 gpiomode = PIN_GPIOMODE(cfg);1082 sleep = PIN_SLEEPMODE(cfg);1083 1084 if (sleep) {1085 int slpm_pull = PIN_SLPM_PULL(cfg);1086 int slpm_output = PIN_SLPM_DIR(cfg);1087 int slpm_val = PIN_SLPM_VAL(cfg);1088 1089 /* All pins go into GPIO mode at sleep */1090 gpiomode = true;1091 1092 /*1093 * The SLPM_* values are normal values + 1 to allow zero1094 * to mean "same as normal".1095 */1096 if (slpm_pull)1097 pull = slpm_pull - 1;1098 if (slpm_output)1099 output = slpm_output - 1;1100 if (slpm_val)1101 val = slpm_val - 1;1102 1103 dev_dbg(nmk_chip->chip.parent,1104 "pin %d: sleep pull %s, dir %s, val %s\n",1105 pin,1106 slpm_pull ? pullnames[pull] : "same",1107 slpm_output ? (output ? "output" : "input")1108 : "same",1109 slpm_val ? (val ? "high" : "low") : "same");1110 }1111 1112 dev_dbg(nmk_chip->chip.parent,1113 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",1114 pin, cfg, pullnames[pull], slpmnames[slpm],1115 output ? "output " : "input",1116 output ? (val ? "high" : "low") : "",1117 lowemi ? "on" : "off");1118 1119 clk_enable(nmk_chip->clk);1120 if (gpiomode)1121 /* No glitch when going to GPIO mode */1122 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);1123 if (output) {1124 __nmk_gpio_make_output(nmk_chip, bit, val);1125 } else {1126 __nmk_gpio_make_input(nmk_chip, bit);1127 __nmk_gpio_set_pull(nmk_chip, bit, pull);1128 }1129 /* TODO: isn't this only applicable on output pins? */1130 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);1131 1132 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);1133 clk_disable(nmk_chip->clk);1134 } /* for each config */1135 1136 return 0;1137}1138 1139static const struct pinconf_ops nmk_pinconf_ops = {1140 .pin_config_get = nmk_pin_config_get,1141 .pin_config_set = nmk_pin_config_set,1142};1143 1144static struct pinctrl_desc nmk_pinctrl_desc = {1145 .name = "pinctrl-nomadik",1146 .pctlops = &nmk_pinctrl_ops,1147 .pmxops = &nmk_pinmux_ops,1148 .confops = &nmk_pinconf_ops,1149 .owner = THIS_MODULE,1150};1151 1152static const struct of_device_id nmk_pinctrl_match[] = {1153 {1154 .compatible = "stericsson,stn8815-pinctrl",1155 .data = (void *)PINCTRL_NMK_STN8815,1156 },1157 {1158 .compatible = "stericsson,db8500-pinctrl",1159 .data = (void *)PINCTRL_NMK_DB8500,1160 },1161 {},1162};1163 1164#ifdef CONFIG_PM_SLEEP1165static int nmk_pinctrl_suspend(struct device *dev)1166{1167 struct nmk_pinctrl *npct;1168 1169 npct = dev_get_drvdata(dev);1170 if (!npct)1171 return -EINVAL;1172 1173 return pinctrl_force_sleep(npct->pctl);1174}1175 1176static int nmk_pinctrl_resume(struct device *dev)1177{1178 struct nmk_pinctrl *npct;1179 1180 npct = dev_get_drvdata(dev);1181 if (!npct)1182 return -EINVAL;1183 1184 return pinctrl_force_default(npct->pctl);1185}1186#endif1187 1188static int nmk_pinctrl_probe(struct platform_device *pdev)1189{1190 struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev);1191 struct fwnode_handle *prcm_fwnode;1192 struct nmk_pinctrl *npct;1193 uintptr_t version = 0;1194 int i;1195 1196 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);1197 if (!npct)1198 return -ENOMEM;1199 1200 version = (uintptr_t)device_get_match_data(&pdev->dev);1201 1202 /* Poke in other ASIC variants here */1203 if (version == PINCTRL_NMK_STN8815)1204 nmk_pinctrl_stn8815_init(&npct->soc);1205 if (version == PINCTRL_NMK_DB8500)1206 nmk_pinctrl_db8500_init(&npct->soc);1207 1208 /*1209 * Since we depend on the GPIO chips to provide clock and register base1210 * for the pin control operations, make sure that we have these1211 * populated before we continue. Follow the phandles to instantiate1212 * them. The GPIO portion of the actual hardware may be probed before1213 * or after this point: it shouldn't matter as the APIs are orthogonal.1214 */1215 for (i = 0; i < NMK_MAX_BANKS; i++) {1216 struct fwnode_handle *gpio_fwnode;1217 struct nmk_gpio_chip *nmk_chip;1218 1219 gpio_fwnode = fwnode_find_reference(fwnode, "nomadik-gpio-chips", i);1220 if (IS_ERR(gpio_fwnode))1221 continue;1222 1223 dev_info(&pdev->dev, "populate NMK GPIO %d \"%pfwP\"\n", i, gpio_fwnode);1224 nmk_chip = nmk_gpio_populate_chip(gpio_fwnode, pdev);1225 if (IS_ERR(nmk_chip))1226 dev_err(&pdev->dev,1227 "could not populate nmk chip struct - continue anyway\n");1228 else1229 /* We are NOT compatible with mobileye,eyeq5-gpio. */1230 BUG_ON(nmk_chip->is_mobileye_soc);1231 fwnode_handle_put(gpio_fwnode);1232 }1233 1234 prcm_fwnode = fwnode_find_reference(fwnode, "prcm", 0);1235 if (!IS_ERR(prcm_fwnode)) {1236 npct->prcm_base = fwnode_iomap(prcm_fwnode, 0);1237 fwnode_handle_put(prcm_fwnode);1238 }1239 if (!npct->prcm_base) {1240 if (version == PINCTRL_NMK_STN8815) {1241 dev_info(&pdev->dev,1242 "No PRCM base, assuming no ALT-Cx control is available\n");1243 } else {1244 dev_err(&pdev->dev, "missing PRCM base address\n");1245 return -EINVAL;1246 }1247 }1248 1249 nmk_pinctrl_desc.pins = npct->soc->pins;1250 nmk_pinctrl_desc.npins = npct->soc->npins;1251 npct->dev = &pdev->dev;1252 1253 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);1254 if (IS_ERR(npct->pctl)) {1255 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");1256 return PTR_ERR(npct->pctl);1257 }1258 1259 platform_set_drvdata(pdev, npct);1260 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");1261 1262 return 0;1263}1264 1265static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,1266 nmk_pinctrl_suspend,1267 nmk_pinctrl_resume);1268 1269static struct platform_driver nmk_pinctrl_driver = {1270 .driver = {1271 .name = "pinctrl-nomadik",1272 .of_match_table = nmk_pinctrl_match,1273 .pm = &nmk_pinctrl_pm_ops,1274 },1275 .probe = nmk_pinctrl_probe,1276};1277 1278static int __init nmk_pinctrl_init(void)1279{1280 return platform_driver_register(&nmk_pinctrl_driver);1281}1282core_initcall(nmk_pinctrl_init);1283