2037 lines · c
1// SPDX-License-Identifier: GPL-2.02// Copyright (c) 2016-2018 Nuvoton Technology corporation.3// Copyright (c) 2016, Dell Inc4 5#include <linux/device.h>6#include <linux/gpio/driver.h>7#include <linux/interrupt.h>8#include <linux/irq.h>9#include <linux/mfd/syscon.h>10#include <linux/module.h>11#include <linux/of.h>12#include <linux/of_address.h>13#include <linux/of_irq.h>14#include <linux/platform_device.h>15#include <linux/property.h>16#include <linux/regmap.h>17#include <linux/seq_file.h>18 19#include <linux/pinctrl/consumer.h>20#include <linux/pinctrl/machine.h>21#include <linux/pinctrl/pinconf-generic.h>22#include <linux/pinctrl/pinconf.h>23#include <linux/pinctrl/pinctrl.h>24#include <linux/pinctrl/pinmux.h>25 26/* GCR registers */27#define NPCM7XX_GCR_PDID 0x0028#define NPCM7XX_GCR_MFSEL1 0x0C29#define NPCM7XX_GCR_MFSEL2 0x1030#define NPCM7XX_GCR_MFSEL3 0x6431#define NPCM7XX_GCR_MFSEL4 0xb032#define NPCM7XX_GCR_CPCTL 0xD033#define NPCM7XX_GCR_CP2BST 0xD434#define NPCM7XX_GCR_B2CPNT 0xD835#define NPCM7XX_GCR_I2CSEGSEL 0xE036#define NPCM7XX_GCR_I2CSEGCTL 0xE437#define NPCM7XX_GCR_SRCNT 0x6838#define NPCM7XX_GCR_FLOCKR1 0x7439#define NPCM7XX_GCR_DSCNT 0x7840 41#define SRCNT_ESPI BIT(3)42 43/* GPIO registers */44#define NPCM7XX_GP_N_TLOCK1 0x0045#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */46#define NPCM7XX_GP_N_POL 0x08 /* Polarity */47#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */48#define NPCM7XX_GP_N_OE 0x10 /* Output Enable */49#define NPCM7XX_GP_N_OTYP 0x1450#define NPCM7XX_GP_N_MP 0x1851#define NPCM7XX_GP_N_PU 0x1c /* Pull-up */52#define NPCM7XX_GP_N_PD 0x20 /* Pull-down */53#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */54#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */55#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */56#define NPCM7XX_GP_N_OBL0 0x3057#define NPCM7XX_GP_N_OBL1 0x3458#define NPCM7XX_GP_N_OBL2 0x3859#define NPCM7XX_GP_N_OBL3 0x3c60#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */61#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */62#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */63#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */64#define NPCM7XX_GP_N_SPLCK 0x5065#define NPCM7XX_GP_N_MPLCK 0x5466#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */67#define NPCM7XX_GP_N_OSRC 0x5c68#define NPCM7XX_GP_N_ODSC 0x6069#define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */70#define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */71#define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */72#define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */73#define NPCM7XX_GP_N_TLOCK2 0x7c74 75#define NPCM7XX_GPIO_PER_BANK 3276#define NPCM7XX_GPIO_BANK_NUM 877#define NPCM7XX_GCR_NONE 078 79/* Structure for register banks */80struct npcm7xx_gpio {81 void __iomem *base;82 struct gpio_chip gc;83 int irqbase;84 int irq;85 u32 pinctrl_id;86 int (*direction_input)(struct gpio_chip *chip, unsigned int offset);87 int (*direction_output)(struct gpio_chip *chip, unsigned int offset,88 int value);89 int (*request)(struct gpio_chip *chip, unsigned int offset);90 void (*free)(struct gpio_chip *chip, unsigned int offset);91};92 93struct npcm7xx_pinctrl {94 struct pinctrl_dev *pctldev;95 struct device *dev;96 struct npcm7xx_gpio gpio_bank[NPCM7XX_GPIO_BANK_NUM];97 struct irq_domain *domain;98 struct regmap *gcr_regmap;99 void __iomem *regs;100 u32 bank_num;101};102 103/* GPIO handling in the pinctrl driver */104static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,105 unsigned int pinmask)106{107 unsigned long flags;108 unsigned long val;109 110 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);111 112 val = ioread32(reg) | pinmask;113 iowrite32(val, reg);114 115 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);116}117 118static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,119 unsigned int pinmask)120{121 unsigned long flags;122 unsigned long val;123 124 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);125 126 val = ioread32(reg) & ~pinmask;127 iowrite32(val, reg);128 129 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);130}131 132static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)133{134 struct npcm7xx_gpio *bank = gpiochip_get_data(chip);135 136 seq_printf(s, "-- module %d [gpio%d - %d]\n",137 bank->gc.base / bank->gc.ngpio,138 bank->gc.base,139 bank->gc.base + bank->gc.ngpio);140 seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n",141 ioread32(bank->base + NPCM7XX_GP_N_DIN),142 ioread32(bank->base + NPCM7XX_GP_N_DOUT),143 ioread32(bank->base + NPCM7XX_GP_N_IEM),144 ioread32(bank->base + NPCM7XX_GP_N_OE));145 seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n",146 ioread32(bank->base + NPCM7XX_GP_N_PU),147 ioread32(bank->base + NPCM7XX_GP_N_PD),148 ioread32(bank->base + NPCM7XX_GP_N_DBNC),149 ioread32(bank->base + NPCM7XX_GP_N_POL));150 seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",151 ioread32(bank->base + NPCM7XX_GP_N_EVTYP),152 ioread32(bank->base + NPCM7XX_GP_N_EVBE),153 ioread32(bank->base + NPCM7XX_GP_N_EVEN),154 ioread32(bank->base + NPCM7XX_GP_N_EVST));155 seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",156 ioread32(bank->base + NPCM7XX_GP_N_OTYP),157 ioread32(bank->base + NPCM7XX_GP_N_OSRC),158 ioread32(bank->base + NPCM7XX_GP_N_ODSC));159 seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",160 ioread32(bank->base + NPCM7XX_GP_N_OBL0),161 ioread32(bank->base + NPCM7XX_GP_N_OBL1),162 ioread32(bank->base + NPCM7XX_GP_N_OBL2),163 ioread32(bank->base + NPCM7XX_GP_N_OBL3));164 seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",165 ioread32(bank->base + NPCM7XX_GP_N_SPLCK),166 ioread32(bank->base + NPCM7XX_GP_N_MPLCK));167}168 169static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)170{171 struct npcm7xx_gpio *bank = gpiochip_get_data(chip);172 int ret;173 174 ret = pinctrl_gpio_direction_input(chip, offset);175 if (ret)176 return ret;177 178 return bank->direction_input(chip, offset);179}180 181/* Set GPIO to Output with initial value */182static int npcmgpio_direction_output(struct gpio_chip *chip,183 unsigned int offset, int value)184{185 struct npcm7xx_gpio *bank = gpiochip_get_data(chip);186 int ret;187 188 dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset,189 value);190 191 ret = pinctrl_gpio_direction_output(chip, offset);192 if (ret)193 return ret;194 195 return bank->direction_output(chip, offset, value);196}197 198static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)199{200 struct npcm7xx_gpio *bank = gpiochip_get_data(chip);201 int ret;202 203 dev_dbg(chip->parent, "gpio_request: offset%d\n", offset);204 ret = pinctrl_gpio_request(chip, offset);205 if (ret)206 return ret;207 208 return bank->request(chip, offset);209}210 211static void npcmgpio_irq_handler(struct irq_desc *desc)212{213 struct gpio_chip *gc;214 struct irq_chip *chip;215 struct npcm7xx_gpio *bank;216 unsigned long sts, en, bit;217 218 gc = irq_desc_get_handler_data(desc);219 bank = gpiochip_get_data(gc);220 chip = irq_desc_get_chip(desc);221 222 chained_irq_enter(chip, desc);223 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);224 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN);225 dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts,226 en);227 228 sts &= en;229 for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK)230 generic_handle_domain_irq(gc->irq.domain, bit);231 chained_irq_exit(chip, desc);232}233 234static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)235{236 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);237 struct npcm7xx_gpio *bank = gpiochip_get_data(gc);238 unsigned int gpio = BIT(irqd_to_hwirq(d));239 240 dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio,241 d->irq, type);242 switch (type) {243 case IRQ_TYPE_EDGE_RISING:244 dev_dbg(bank->gc.parent, "edge.rising\n");245 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);246 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);247 break;248 case IRQ_TYPE_EDGE_FALLING:249 dev_dbg(bank->gc.parent, "edge.falling\n");250 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);251 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);252 break;253 case IRQ_TYPE_EDGE_BOTH:254 dev_dbg(bank->gc.parent, "edge.both\n");255 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);256 break;257 case IRQ_TYPE_LEVEL_LOW:258 dev_dbg(bank->gc.parent, "level.low\n");259 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);260 break;261 case IRQ_TYPE_LEVEL_HIGH:262 dev_dbg(bank->gc.parent, "level.high\n");263 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);264 break;265 default:266 dev_dbg(bank->gc.parent, "invalid irq type\n");267 return -EINVAL;268 }269 270 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {271 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);272 irq_set_handler_locked(d, handle_level_irq);273 } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING274 | IRQ_TYPE_EDGE_FALLING)) {275 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);276 irq_set_handler_locked(d, handle_edge_irq);277 }278 279 return 0;280}281 282static void npcmgpio_irq_ack(struct irq_data *d)283{284 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);285 struct npcm7xx_gpio *bank = gpiochip_get_data(gc);286 unsigned int gpio = irqd_to_hwirq(d);287 288 dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq);289 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST);290}291 292/* Disable GPIO interrupt */293static void npcmgpio_irq_mask(struct irq_data *d)294{295 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);296 struct npcm7xx_gpio *bank = gpiochip_get_data(gc);297 unsigned int gpio = irqd_to_hwirq(d);298 299 /* Clear events */300 dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq);301 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC);302 gpiochip_disable_irq(gc, gpio);303}304 305/* Enable GPIO interrupt */306static void npcmgpio_irq_unmask(struct irq_data *d)307{308 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);309 struct npcm7xx_gpio *bank = gpiochip_get_data(gc);310 unsigned int gpio = irqd_to_hwirq(d);311 312 /* Enable events */313 gpiochip_enable_irq(gc, gpio);314 dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq);315 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS);316}317 318static unsigned int npcmgpio_irq_startup(struct irq_data *d)319{320 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);321 unsigned int gpio = irqd_to_hwirq(d);322 323 /* active-high, input, clear interrupt, enable interrupt */324 dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq);325 npcmgpio_direction_input(gc, gpio);326 npcmgpio_irq_ack(d);327 npcmgpio_irq_unmask(d);328 329 return 0;330}331 332static const struct irq_chip npcmgpio_irqchip = {333 .name = "NPCM7XX-GPIO-IRQ",334 .irq_ack = npcmgpio_irq_ack,335 .irq_unmask = npcmgpio_irq_unmask,336 .irq_mask = npcmgpio_irq_mask,337 .irq_set_type = npcmgpio_set_irq_type,338 .irq_startup = npcmgpio_irq_startup,339 .flags = IRQCHIP_IMMUTABLE,340 GPIOCHIP_IRQ_RESOURCE_HELPERS,341};342 343/* pinmux handing in the pinctrl driver*/344static const int smb0_pins[] = { 115, 114 };345static const int smb0b_pins[] = { 195, 194 };346static const int smb0c_pins[] = { 202, 196 };347static const int smb0d_pins[] = { 198, 199 };348static const int smb0den_pins[] = { 197 };349 350static const int smb1_pins[] = { 117, 116 };351static const int smb1b_pins[] = { 126, 127 };352static const int smb1c_pins[] = { 124, 125 };353static const int smb1d_pins[] = { 4, 5 };354 355static const int smb2_pins[] = { 119, 118 };356static const int smb2b_pins[] = { 122, 123 };357static const int smb2c_pins[] = { 120, 121 };358static const int smb2d_pins[] = { 6, 7 };359 360static const int smb3_pins[] = { 30, 31 };361static const int smb3b_pins[] = { 39, 40 };362static const int smb3c_pins[] = { 37, 38 };363static const int smb3d_pins[] = { 59, 60 };364 365static const int smb4_pins[] = { 28, 29 };366static const int smb4b_pins[] = { 18, 19 };367static const int smb4c_pins[] = { 20, 21 };368static const int smb4d_pins[] = { 22, 23 };369static const int smb4den_pins[] = { 17 };370 371static const int smb5_pins[] = { 26, 27 };372static const int smb5b_pins[] = { 13, 12 };373static const int smb5c_pins[] = { 15, 14 };374static const int smb5d_pins[] = { 94, 93 };375static const int ga20kbc_pins[] = { 94, 93 };376 377static const int smb6_pins[] = { 172, 171 };378static const int smb7_pins[] = { 174, 173 };379static const int smb8_pins[] = { 129, 128 };380static const int smb9_pins[] = { 131, 130 };381static const int smb10_pins[] = { 133, 132 };382static const int smb11_pins[] = { 135, 134 };383static const int smb12_pins[] = { 221, 220 };384static const int smb13_pins[] = { 223, 222 };385static const int smb14_pins[] = { 22, 23 };386static const int smb15_pins[] = { 20, 21 };387 388static const int fanin0_pins[] = { 64 };389static const int fanin1_pins[] = { 65 };390static const int fanin2_pins[] = { 66 };391static const int fanin3_pins[] = { 67 };392static const int fanin4_pins[] = { 68 };393static const int fanin5_pins[] = { 69 };394static const int fanin6_pins[] = { 70 };395static const int fanin7_pins[] = { 71 };396static const int fanin8_pins[] = { 72 };397static const int fanin9_pins[] = { 73 };398static const int fanin10_pins[] = { 74 };399static const int fanin11_pins[] = { 75 };400static const int fanin12_pins[] = { 76 };401static const int fanin13_pins[] = { 77 };402static const int fanin14_pins[] = { 78 };403static const int fanin15_pins[] = { 79 };404static const int faninx_pins[] = { 175, 176, 177, 203 };405 406static const int pwm0_pins[] = { 80 };407static const int pwm1_pins[] = { 81 };408static const int pwm2_pins[] = { 82 };409static const int pwm3_pins[] = { 83 };410static const int pwm4_pins[] = { 144 };411static const int pwm5_pins[] = { 145 };412static const int pwm6_pins[] = { 146 };413static const int pwm7_pins[] = { 147 };414 415static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };416static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };417 418/* RGMII 1 pin group */419static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,420 106, 107 };421/* RGMII 1 MD interface pin group */422static const int rg1mdio_pins[] = { 108, 109 };423 424/* RGMII 2 pin group */425static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,426 213, 214, 215 };427/* RGMII 2 MD interface pin group */428static const int rg2mdio_pins[] = { 216, 217 };429 430static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,431 213, 214, 215, 216, 217 };432/* Serial I/O Expander 1 */433static const int iox1_pins[] = { 0, 1, 2, 3 };434/* Serial I/O Expander 2 */435static const int iox2_pins[] = { 4, 5, 6, 7 };436/* Host Serial I/O Expander 2 */437static const int ioxh_pins[] = { 10, 11, 24, 25 };438 439static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };440static const int mmcwp_pins[] = { 153 };441static const int mmccd_pins[] = { 155 };442static const int mmcrst_pins[] = { 155 };443static const int mmc8_pins[] = { 148, 149, 150, 151 };444 445/* RMII 1 pin groups */446static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };447static const int r1err_pins[] = { 56 };448static const int r1md_pins[] = { 57, 58 };449 450/* RMII 2 pin groups */451static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };452static const int r2err_pins[] = { 90 };453static const int r2md_pins[] = { 91, 92 };454 455static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };456static const int sd1pwr_pins[] = { 143 };457 458static const int wdog1_pins[] = { 218 };459static const int wdog2_pins[] = { 219 };460 461/* BMC serial port 0 */462static const int bmcuart0a_pins[] = { 41, 42 };463static const int bmcuart0b_pins[] = { 48, 49 };464 465static const int bmcuart1_pins[] = { 43, 44, 62, 63 };466 467/* System Control Interrupt and Power Management Event pin group */468static const int scipme_pins[] = { 169 };469/* System Management Interrupt pin group */470static const int sci_pins[] = { 170 };471/* Serial Interrupt Line pin group */472static const int serirq_pins[] = { 162 };473 474static const int clkout_pins[] = { 160 };475static const int clkreq_pins[] = { 231 };476 477static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };478/* Graphics SPI Clock pin group */479static const int gspi_pins[] = { 12, 13, 14, 15 };480 481static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };482static const int spixcs1_pins[] = { 228 };483 484static const int pspi1_pins[] = { 175, 176, 177 };485static const int pspi2_pins[] = { 17, 18, 19 };486 487static const int spi0cs1_pins[] = { 32 };488 489static const int spi3_pins[] = { 183, 184, 185, 186 };490static const int spi3cs1_pins[] = { 187 };491static const int spi3quad_pins[] = { 188, 189 };492static const int spi3cs2_pins[] = { 188 };493static const int spi3cs3_pins[] = { 189 };494 495static const int ddc_pins[] = { 204, 205, 206, 207 };496 497static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };498static const int lpcclk_pins[] = { 168 };499static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };500 501static const int lkgpo0_pins[] = { 16 };502static const int lkgpo1_pins[] = { 8 };503static const int lkgpo2_pins[] = { 9 };504 505static const int nprd_smi_pins[] = { 190 };506 507/*508 * pin: name, number509 * group: name, npins, pins510 * function: name, ngroups, groups511 */512struct npcm7xx_group {513 const char *name;514 const unsigned int *pins;515 int npins;516};517 518#define NPCM7XX_GRPS \519 NPCM7XX_GRP(smb0), \520 NPCM7XX_GRP(smb0b), \521 NPCM7XX_GRP(smb0c), \522 NPCM7XX_GRP(smb0d), \523 NPCM7XX_GRP(smb0den), \524 NPCM7XX_GRP(smb1), \525 NPCM7XX_GRP(smb1b), \526 NPCM7XX_GRP(smb1c), \527 NPCM7XX_GRP(smb1d), \528 NPCM7XX_GRP(smb2), \529 NPCM7XX_GRP(smb2b), \530 NPCM7XX_GRP(smb2c), \531 NPCM7XX_GRP(smb2d), \532 NPCM7XX_GRP(smb3), \533 NPCM7XX_GRP(smb3b), \534 NPCM7XX_GRP(smb3c), \535 NPCM7XX_GRP(smb3d), \536 NPCM7XX_GRP(smb4), \537 NPCM7XX_GRP(smb4b), \538 NPCM7XX_GRP(smb4c), \539 NPCM7XX_GRP(smb4d), \540 NPCM7XX_GRP(smb4den), \541 NPCM7XX_GRP(smb5), \542 NPCM7XX_GRP(smb5b), \543 NPCM7XX_GRP(smb5c), \544 NPCM7XX_GRP(smb5d), \545 NPCM7XX_GRP(ga20kbc), \546 NPCM7XX_GRP(smb6), \547 NPCM7XX_GRP(smb7), \548 NPCM7XX_GRP(smb8), \549 NPCM7XX_GRP(smb9), \550 NPCM7XX_GRP(smb10), \551 NPCM7XX_GRP(smb11), \552 NPCM7XX_GRP(smb12), \553 NPCM7XX_GRP(smb13), \554 NPCM7XX_GRP(smb14), \555 NPCM7XX_GRP(smb15), \556 NPCM7XX_GRP(fanin0), \557 NPCM7XX_GRP(fanin1), \558 NPCM7XX_GRP(fanin2), \559 NPCM7XX_GRP(fanin3), \560 NPCM7XX_GRP(fanin4), \561 NPCM7XX_GRP(fanin5), \562 NPCM7XX_GRP(fanin6), \563 NPCM7XX_GRP(fanin7), \564 NPCM7XX_GRP(fanin8), \565 NPCM7XX_GRP(fanin9), \566 NPCM7XX_GRP(fanin10), \567 NPCM7XX_GRP(fanin11), \568 NPCM7XX_GRP(fanin12), \569 NPCM7XX_GRP(fanin13), \570 NPCM7XX_GRP(fanin14), \571 NPCM7XX_GRP(fanin15), \572 NPCM7XX_GRP(faninx), \573 NPCM7XX_GRP(pwm0), \574 NPCM7XX_GRP(pwm1), \575 NPCM7XX_GRP(pwm2), \576 NPCM7XX_GRP(pwm3), \577 NPCM7XX_GRP(pwm4), \578 NPCM7XX_GRP(pwm5), \579 NPCM7XX_GRP(pwm6), \580 NPCM7XX_GRP(pwm7), \581 NPCM7XX_GRP(rg1), \582 NPCM7XX_GRP(rg1mdio), \583 NPCM7XX_GRP(rg2), \584 NPCM7XX_GRP(rg2mdio), \585 NPCM7XX_GRP(ddr), \586 NPCM7XX_GRP(uart1), \587 NPCM7XX_GRP(uart2), \588 NPCM7XX_GRP(bmcuart0a), \589 NPCM7XX_GRP(bmcuart0b), \590 NPCM7XX_GRP(bmcuart1), \591 NPCM7XX_GRP(iox1), \592 NPCM7XX_GRP(iox2), \593 NPCM7XX_GRP(ioxh), \594 NPCM7XX_GRP(gspi), \595 NPCM7XX_GRP(mmc), \596 NPCM7XX_GRP(mmcwp), \597 NPCM7XX_GRP(mmccd), \598 NPCM7XX_GRP(mmcrst), \599 NPCM7XX_GRP(mmc8), \600 NPCM7XX_GRP(r1), \601 NPCM7XX_GRP(r1err), \602 NPCM7XX_GRP(r1md), \603 NPCM7XX_GRP(r2), \604 NPCM7XX_GRP(r2err), \605 NPCM7XX_GRP(r2md), \606 NPCM7XX_GRP(sd1), \607 NPCM7XX_GRP(sd1pwr), \608 NPCM7XX_GRP(wdog1), \609 NPCM7XX_GRP(wdog2), \610 NPCM7XX_GRP(scipme), \611 NPCM7XX_GRP(sci), \612 NPCM7XX_GRP(serirq), \613 NPCM7XX_GRP(jtag2), \614 NPCM7XX_GRP(spix), \615 NPCM7XX_GRP(spixcs1), \616 NPCM7XX_GRP(pspi1), \617 NPCM7XX_GRP(pspi2), \618 NPCM7XX_GRP(ddc), \619 NPCM7XX_GRP(clkreq), \620 NPCM7XX_GRP(clkout), \621 NPCM7XX_GRP(spi3), \622 NPCM7XX_GRP(spi3cs1), \623 NPCM7XX_GRP(spi3quad), \624 NPCM7XX_GRP(spi3cs2), \625 NPCM7XX_GRP(spi3cs3), \626 NPCM7XX_GRP(spi0cs1), \627 NPCM7XX_GRP(lpc), \628 NPCM7XX_GRP(lpcclk), \629 NPCM7XX_GRP(espi), \630 NPCM7XX_GRP(lkgpo0), \631 NPCM7XX_GRP(lkgpo1), \632 NPCM7XX_GRP(lkgpo2), \633 NPCM7XX_GRP(nprd_smi), \634 \635 636enum {637#define NPCM7XX_GRP(x) fn_ ## x638 NPCM7XX_GRPS639 /* add placeholder for none/gpio */640 NPCM7XX_GRP(none),641 NPCM7XX_GRP(gpio),642#undef NPCM7XX_GRP643};644 645static struct npcm7xx_group npcm7xx_groups[] = {646#define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \647 .npins = ARRAY_SIZE(x ## _pins) }648 NPCM7XX_GRPS649#undef NPCM7XX_GRP650};651 652#define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a)653#define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b }654#define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \655 .groups = nm ## _grp }656struct npcm7xx_func {657 const char *name;658 const unsigned int ngroups;659 const char *const *groups;660};661 662NPCM7XX_SFUNC(smb0);663NPCM7XX_SFUNC(smb0b);664NPCM7XX_SFUNC(smb0c);665NPCM7XX_SFUNC(smb0d);666NPCM7XX_SFUNC(smb0den);667NPCM7XX_SFUNC(smb1);668NPCM7XX_SFUNC(smb1b);669NPCM7XX_SFUNC(smb1c);670NPCM7XX_SFUNC(smb1d);671NPCM7XX_SFUNC(smb2);672NPCM7XX_SFUNC(smb2b);673NPCM7XX_SFUNC(smb2c);674NPCM7XX_SFUNC(smb2d);675NPCM7XX_SFUNC(smb3);676NPCM7XX_SFUNC(smb3b);677NPCM7XX_SFUNC(smb3c);678NPCM7XX_SFUNC(smb3d);679NPCM7XX_SFUNC(smb4);680NPCM7XX_SFUNC(smb4b);681NPCM7XX_SFUNC(smb4c);682NPCM7XX_SFUNC(smb4d);683NPCM7XX_SFUNC(smb4den);684NPCM7XX_SFUNC(smb5);685NPCM7XX_SFUNC(smb5b);686NPCM7XX_SFUNC(smb5c);687NPCM7XX_SFUNC(smb5d);688NPCM7XX_SFUNC(ga20kbc);689NPCM7XX_SFUNC(smb6);690NPCM7XX_SFUNC(smb7);691NPCM7XX_SFUNC(smb8);692NPCM7XX_SFUNC(smb9);693NPCM7XX_SFUNC(smb10);694NPCM7XX_SFUNC(smb11);695NPCM7XX_SFUNC(smb12);696NPCM7XX_SFUNC(smb13);697NPCM7XX_SFUNC(smb14);698NPCM7XX_SFUNC(smb15);699NPCM7XX_SFUNC(fanin0);700NPCM7XX_SFUNC(fanin1);701NPCM7XX_SFUNC(fanin2);702NPCM7XX_SFUNC(fanin3);703NPCM7XX_SFUNC(fanin4);704NPCM7XX_SFUNC(fanin5);705NPCM7XX_SFUNC(fanin6);706NPCM7XX_SFUNC(fanin7);707NPCM7XX_SFUNC(fanin8);708NPCM7XX_SFUNC(fanin9);709NPCM7XX_SFUNC(fanin10);710NPCM7XX_SFUNC(fanin11);711NPCM7XX_SFUNC(fanin12);712NPCM7XX_SFUNC(fanin13);713NPCM7XX_SFUNC(fanin14);714NPCM7XX_SFUNC(fanin15);715NPCM7XX_SFUNC(faninx);716NPCM7XX_SFUNC(pwm0);717NPCM7XX_SFUNC(pwm1);718NPCM7XX_SFUNC(pwm2);719NPCM7XX_SFUNC(pwm3);720NPCM7XX_SFUNC(pwm4);721NPCM7XX_SFUNC(pwm5);722NPCM7XX_SFUNC(pwm6);723NPCM7XX_SFUNC(pwm7);724NPCM7XX_SFUNC(rg1);725NPCM7XX_SFUNC(rg1mdio);726NPCM7XX_SFUNC(rg2);727NPCM7XX_SFUNC(rg2mdio);728NPCM7XX_SFUNC(ddr);729NPCM7XX_SFUNC(uart1);730NPCM7XX_SFUNC(uart2);731NPCM7XX_SFUNC(bmcuart0a);732NPCM7XX_SFUNC(bmcuart0b);733NPCM7XX_SFUNC(bmcuart1);734NPCM7XX_SFUNC(iox1);735NPCM7XX_SFUNC(iox2);736NPCM7XX_SFUNC(ioxh);737NPCM7XX_SFUNC(gspi);738NPCM7XX_SFUNC(mmc);739NPCM7XX_SFUNC(mmcwp);740NPCM7XX_SFUNC(mmccd);741NPCM7XX_SFUNC(mmcrst);742NPCM7XX_SFUNC(mmc8);743NPCM7XX_SFUNC(r1);744NPCM7XX_SFUNC(r1err);745NPCM7XX_SFUNC(r1md);746NPCM7XX_SFUNC(r2);747NPCM7XX_SFUNC(r2err);748NPCM7XX_SFUNC(r2md);749NPCM7XX_SFUNC(sd1);750NPCM7XX_SFUNC(sd1pwr);751NPCM7XX_SFUNC(wdog1);752NPCM7XX_SFUNC(wdog2);753NPCM7XX_SFUNC(scipme);754NPCM7XX_SFUNC(sci);755NPCM7XX_SFUNC(serirq);756NPCM7XX_SFUNC(jtag2);757NPCM7XX_SFUNC(spix);758NPCM7XX_SFUNC(spixcs1);759NPCM7XX_SFUNC(pspi1);760NPCM7XX_SFUNC(pspi2);761NPCM7XX_SFUNC(ddc);762NPCM7XX_SFUNC(clkreq);763NPCM7XX_SFUNC(clkout);764NPCM7XX_SFUNC(spi3);765NPCM7XX_SFUNC(spi3cs1);766NPCM7XX_SFUNC(spi3quad);767NPCM7XX_SFUNC(spi3cs2);768NPCM7XX_SFUNC(spi3cs3);769NPCM7XX_SFUNC(spi0cs1);770NPCM7XX_SFUNC(lpc);771NPCM7XX_SFUNC(lpcclk);772NPCM7XX_SFUNC(espi);773NPCM7XX_SFUNC(lkgpo0);774NPCM7XX_SFUNC(lkgpo1);775NPCM7XX_SFUNC(lkgpo2);776NPCM7XX_SFUNC(nprd_smi);777 778/* Function names */779static struct npcm7xx_func npcm7xx_funcs[] = {780 NPCM7XX_MKFUNC(smb0),781 NPCM7XX_MKFUNC(smb0b),782 NPCM7XX_MKFUNC(smb0c),783 NPCM7XX_MKFUNC(smb0d),784 NPCM7XX_MKFUNC(smb0den),785 NPCM7XX_MKFUNC(smb1),786 NPCM7XX_MKFUNC(smb1b),787 NPCM7XX_MKFUNC(smb1c),788 NPCM7XX_MKFUNC(smb1d),789 NPCM7XX_MKFUNC(smb2),790 NPCM7XX_MKFUNC(smb2b),791 NPCM7XX_MKFUNC(smb2c),792 NPCM7XX_MKFUNC(smb2d),793 NPCM7XX_MKFUNC(smb3),794 NPCM7XX_MKFUNC(smb3b),795 NPCM7XX_MKFUNC(smb3c),796 NPCM7XX_MKFUNC(smb3d),797 NPCM7XX_MKFUNC(smb4),798 NPCM7XX_MKFUNC(smb4b),799 NPCM7XX_MKFUNC(smb4c),800 NPCM7XX_MKFUNC(smb4d),801 NPCM7XX_MKFUNC(smb4den),802 NPCM7XX_MKFUNC(smb5),803 NPCM7XX_MKFUNC(smb5b),804 NPCM7XX_MKFUNC(smb5c),805 NPCM7XX_MKFUNC(smb5d),806 NPCM7XX_MKFUNC(ga20kbc),807 NPCM7XX_MKFUNC(smb6),808 NPCM7XX_MKFUNC(smb7),809 NPCM7XX_MKFUNC(smb8),810 NPCM7XX_MKFUNC(smb9),811 NPCM7XX_MKFUNC(smb10),812 NPCM7XX_MKFUNC(smb11),813 NPCM7XX_MKFUNC(smb12),814 NPCM7XX_MKFUNC(smb13),815 NPCM7XX_MKFUNC(smb14),816 NPCM7XX_MKFUNC(smb15),817 NPCM7XX_MKFUNC(fanin0),818 NPCM7XX_MKFUNC(fanin1),819 NPCM7XX_MKFUNC(fanin2),820 NPCM7XX_MKFUNC(fanin3),821 NPCM7XX_MKFUNC(fanin4),822 NPCM7XX_MKFUNC(fanin5),823 NPCM7XX_MKFUNC(fanin6),824 NPCM7XX_MKFUNC(fanin7),825 NPCM7XX_MKFUNC(fanin8),826 NPCM7XX_MKFUNC(fanin9),827 NPCM7XX_MKFUNC(fanin10),828 NPCM7XX_MKFUNC(fanin11),829 NPCM7XX_MKFUNC(fanin12),830 NPCM7XX_MKFUNC(fanin13),831 NPCM7XX_MKFUNC(fanin14),832 NPCM7XX_MKFUNC(fanin15),833 NPCM7XX_MKFUNC(faninx),834 NPCM7XX_MKFUNC(pwm0),835 NPCM7XX_MKFUNC(pwm1),836 NPCM7XX_MKFUNC(pwm2),837 NPCM7XX_MKFUNC(pwm3),838 NPCM7XX_MKFUNC(pwm4),839 NPCM7XX_MKFUNC(pwm5),840 NPCM7XX_MKFUNC(pwm6),841 NPCM7XX_MKFUNC(pwm7),842 NPCM7XX_MKFUNC(rg1),843 NPCM7XX_MKFUNC(rg1mdio),844 NPCM7XX_MKFUNC(rg2),845 NPCM7XX_MKFUNC(rg2mdio),846 NPCM7XX_MKFUNC(ddr),847 NPCM7XX_MKFUNC(uart1),848 NPCM7XX_MKFUNC(uart2),849 NPCM7XX_MKFUNC(bmcuart0a),850 NPCM7XX_MKFUNC(bmcuart0b),851 NPCM7XX_MKFUNC(bmcuart1),852 NPCM7XX_MKFUNC(iox1),853 NPCM7XX_MKFUNC(iox2),854 NPCM7XX_MKFUNC(ioxh),855 NPCM7XX_MKFUNC(gspi),856 NPCM7XX_MKFUNC(mmc),857 NPCM7XX_MKFUNC(mmcwp),858 NPCM7XX_MKFUNC(mmccd),859 NPCM7XX_MKFUNC(mmcrst),860 NPCM7XX_MKFUNC(mmc8),861 NPCM7XX_MKFUNC(r1),862 NPCM7XX_MKFUNC(r1err),863 NPCM7XX_MKFUNC(r1md),864 NPCM7XX_MKFUNC(r2),865 NPCM7XX_MKFUNC(r2err),866 NPCM7XX_MKFUNC(r2md),867 NPCM7XX_MKFUNC(sd1),868 NPCM7XX_MKFUNC(sd1pwr),869 NPCM7XX_MKFUNC(wdog1),870 NPCM7XX_MKFUNC(wdog2),871 NPCM7XX_MKFUNC(scipme),872 NPCM7XX_MKFUNC(sci),873 NPCM7XX_MKFUNC(serirq),874 NPCM7XX_MKFUNC(jtag2),875 NPCM7XX_MKFUNC(spix),876 NPCM7XX_MKFUNC(spixcs1),877 NPCM7XX_MKFUNC(pspi1),878 NPCM7XX_MKFUNC(pspi2),879 NPCM7XX_MKFUNC(ddc),880 NPCM7XX_MKFUNC(clkreq),881 NPCM7XX_MKFUNC(clkout),882 NPCM7XX_MKFUNC(spi3),883 NPCM7XX_MKFUNC(spi3cs1),884 NPCM7XX_MKFUNC(spi3quad),885 NPCM7XX_MKFUNC(spi3cs2),886 NPCM7XX_MKFUNC(spi3cs3),887 NPCM7XX_MKFUNC(spi0cs1),888 NPCM7XX_MKFUNC(lpc),889 NPCM7XX_MKFUNC(lpcclk),890 NPCM7XX_MKFUNC(espi),891 NPCM7XX_MKFUNC(lkgpo0),892 NPCM7XX_MKFUNC(lkgpo1),893 NPCM7XX_MKFUNC(lkgpo2),894 NPCM7XX_MKFUNC(nprd_smi),895};896 897#define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \898 [a] = { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \899 .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \900 .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \901 .flag = k }902 903/* Drive strength controlled by NPCM7XX_GP_N_ODSC */904#define DRIVE_STRENGTH_LO_SHIFT 8905#define DRIVE_STRENGTH_HI_SHIFT 12906#define DRIVE_STRENGTH_MASK 0x0000FF00907 908#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \909 ((hi) << DRIVE_STRENGTH_HI_SHIFT))910#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)911#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)912 913#define GPI 0x1 /* Not GPO */914#define GPO 0x2 /* Not GPI */915#define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */916#define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */917 918struct npcm7xx_pincfg {919 int flag;920 int fn0, reg0, bit0;921 int fn1, reg1, bit1;922 int fn2, reg2, bit2;923};924 925static const struct npcm7xx_pincfg pincfg[] = {926 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */927 NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),928 NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),929 NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),930 NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),931 NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),932 NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),933 NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),934 NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),935 NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),936 NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),937 NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),938 NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),939 NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),940 NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),941 NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),942 NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),943 NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),944 NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)),945 NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),946 NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),947 NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),948 NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),949 NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),950 NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),951 NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),952 NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),953 NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),954 NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),955 NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),956 NPCM7XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),957 NPCM7XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),958 NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),959 960 NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0),961 NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),962 NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),963 NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),964 NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),965 NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),966 NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),967 NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0),968 NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),969 NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),970 NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),971 NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0),972 NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),973 NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),974 NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO),975 NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0),976 NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),977 NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),978 NPCM7XX_PINCFG(52, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),979 NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),980 NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),981 NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),982 NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0),983 NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),984 NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),985 NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),986 NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),987 NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO),988 NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),989 NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),990 991 NPCM7XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, 0),992 NPCM7XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, 0),993 NPCM7XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, 0),994 NPCM7XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, 0),995 NPCM7XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, 0),996 NPCM7XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, 0),997 NPCM7XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, 0),998 NPCM7XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, 0),999 NPCM7XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, 0),1000 NPCM7XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, 0),1001 NPCM7XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, 0),1002 NPCM7XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, 0),1003 NPCM7XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, 0),1004 NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0),1005 NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0),1006 NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0),1007 NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),1008 NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),1009 NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),1010 NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),1011 NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1012 NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1013 NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1014 NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),1015 NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),1016 NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),1017 NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0),1018 NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),1019 NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),1020 NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),1021 NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),1022 NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),1023 1024 NPCM7XX_PINCFG(96, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1025 NPCM7XX_PINCFG(97, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1026 NPCM7XX_PINCFG(98, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1027 NPCM7XX_PINCFG(99, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1028 NPCM7XX_PINCFG(100, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1029 NPCM7XX_PINCFG(101, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1030 NPCM7XX_PINCFG(102, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1031 NPCM7XX_PINCFG(103, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1032 NPCM7XX_PINCFG(104, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1033 NPCM7XX_PINCFG(105, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1034 NPCM7XX_PINCFG(106, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1035 NPCM7XX_PINCFG(107, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),1036 NPCM7XX_PINCFG(108, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),1037 NPCM7XX_PINCFG(109, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),1038 NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1039 NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1040 NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1041 NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1042 NPCM7XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),1043 NPCM7XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),1044 NPCM7XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),1045 NPCM7XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),1046 NPCM7XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),1047 NPCM7XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),1048 NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),1049 NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),1050 NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),1051 NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),1052 NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),1053 NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),1054 NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),1055 NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),1056 1057 NPCM7XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),1058 NPCM7XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),1059 NPCM7XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),1060 NPCM7XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),1061 NPCM7XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),1062 NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),1063 NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),1064 NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),1065 NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1066 NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1067 NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1068 NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1069 NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1070 NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0),1071 NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1072 NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0),1073 NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),1074 NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),1075 NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),1076 NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),1077 NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1078 NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1079 NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1080 NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1081 NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1082 NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */1083 NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1084 NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */1085 NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1086 NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1087 NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1088 NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1089 1090 NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1091 NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)),1092 NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)),1093 NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),1094 NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),1095 NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),1096 NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),1097 NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),1098 NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0),1099 NPCM7XX_PINCFG(169, scipme, MFSEL3, 0, none, NONE, 0, none, NONE, 0, 0),1100 NPCM7XX_PINCFG(170, sci, MFSEL1, 22, none, NONE, 0, none, NONE, 0, 0),1101 NPCM7XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),1102 NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),1103 NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),1104 NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),1105 NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),1106 NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),1107 NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),1108 NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1109 NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1110 NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1111 NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),1112 NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),1113 NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1114 NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),1115 NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),1116 NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),1117 NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),1118 NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW),1119 NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW),1120 NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)),1121 NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */1122 1123 NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */1124 NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),1125 NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),1126 NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),1127 NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),1128 NPCM7XX_PINCFG(197, smb0den, I2CSEGSEL, 22, none, NONE, 0, none, NONE, 0, SLEW),1129 NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),1130 NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),1131 NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),1132 NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),1133 NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),1134 NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),1135 NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),1136 NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),1137 NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),1138 NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),1139 NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1140 NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1141 NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1142 NPCM7XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1143 NPCM7XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1144 NPCM7XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1145 NPCM7XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1146 NPCM7XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),1147 NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),1148 NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),1149 NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0),1150 NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),1151 NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),1152 NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),1153 NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),1154 NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),1155 1156 NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW),1157 NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),1158 NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),1159 NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1160 NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1161 NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1162 NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),1163 NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),1164 NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */1165 NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */1166 NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */1167};1168 1169/* number, name, drv_data */1170static const struct pinctrl_pin_desc npcm7xx_pins[] = {1171 PINCTRL_PIN(0, "GPIO0/IOX1DI"),1172 PINCTRL_PIN(1, "GPIO1/IOX1LD"),1173 PINCTRL_PIN(2, "GPIO2/IOX1CK"),1174 PINCTRL_PIN(3, "GPIO3/IOX1D0"),1175 PINCTRL_PIN(4, "GPIO4/IOX2DI/SMB1DSDA"),1176 PINCTRL_PIN(5, "GPIO5/IOX2LD/SMB1DSCL"),1177 PINCTRL_PIN(6, "GPIO6/IOX2CK/SMB2DSDA"),1178 PINCTRL_PIN(7, "GPIO7/IOX2D0/SMB2DSCL"),1179 PINCTRL_PIN(8, "GPIO8/LKGPO1"),1180 PINCTRL_PIN(9, "GPIO9/LKGPO2"),1181 PINCTRL_PIN(10, "GPIO10/IOXHLD"),1182 PINCTRL_PIN(11, "GPIO11/IOXHCK"),1183 PINCTRL_PIN(12, "GPIO12/GSPICK/SMB5BSCL"),1184 PINCTRL_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"),1185 PINCTRL_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"),1186 PINCTRL_PIN(15, "GPIO15/GSPICS/SMB5CSDA"),1187 PINCTRL_PIN(16, "GPIO16/LKGPO0"),1188 PINCTRL_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"),1189 PINCTRL_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"),1190 PINCTRL_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"),1191 PINCTRL_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"),1192 PINCTRL_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"),1193 PINCTRL_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"),1194 PINCTRL_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"),1195 PINCTRL_PIN(24, "GPIO24/IOXHDO"),1196 PINCTRL_PIN(25, "GPIO25/IOXHDI"),1197 PINCTRL_PIN(26, "GPIO26/SMB5SDA"),1198 PINCTRL_PIN(27, "GPIO27/SMB5SCL"),1199 PINCTRL_PIN(28, "GPIO28/SMB4SDA"),1200 PINCTRL_PIN(29, "GPIO29/SMB4SCL"),1201 PINCTRL_PIN(30, "GPIO30/SMB3SDA"),1202 PINCTRL_PIN(31, "GPIO31/SMB3SCL"),1203 1204 PINCTRL_PIN(32, "GPIO32/nSPI0CS1"),1205 PINCTRL_PIN(33, "SPI0D2"),1206 PINCTRL_PIN(34, "SPI0D3"),1207 PINCTRL_PIN(37, "GPIO37/SMB3CSDA"),1208 PINCTRL_PIN(38, "GPIO38/SMB3CSCL"),1209 PINCTRL_PIN(39, "GPIO39/SMB3BSDA"),1210 PINCTRL_PIN(40, "GPIO40/SMB3BSCL"),1211 PINCTRL_PIN(41, "GPIO41/BSPRXD"),1212 PINCTRL_PIN(42, "GPO42/BSPTXD/STRAP11"),1213 PINCTRL_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"),1214 PINCTRL_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"),1215 PINCTRL_PIN(45, "GPIO45/nDCD1/JTDO2"),1216 PINCTRL_PIN(46, "GPIO46/nDSR1/JTCK2"),1217 PINCTRL_PIN(47, "GPIO47/nRI1/JCP_RDY2"),1218 PINCTRL_PIN(48, "GPIO48/TXD2/BSPTXD"),1219 PINCTRL_PIN(49, "GPIO49/RXD2/BSPRXD"),1220 PINCTRL_PIN(50, "GPIO50/nCTS2"),1221 PINCTRL_PIN(51, "GPO51/nRTS2/STRAP2"),1222 PINCTRL_PIN(52, "GPIO52/nDCD2"),1223 PINCTRL_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"),1224 PINCTRL_PIN(54, "GPIO54/nDSR2"),1225 PINCTRL_PIN(55, "GPIO55/nRI2"),1226 PINCTRL_PIN(56, "GPIO56/R1RXERR"),1227 PINCTRL_PIN(57, "GPIO57/R1MDC"),1228 PINCTRL_PIN(58, "GPIO58/R1MDIO"),1229 PINCTRL_PIN(59, "GPIO59/SMB3DSDA"),1230 PINCTRL_PIN(60, "GPIO60/SMB3DSCL"),1231 PINCTRL_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"),1232 PINCTRL_PIN(62, "GPO62/nRTST1/STRAP5"),1233 PINCTRL_PIN(63, "GPO63/TXD1/STRAP4"),1234 1235 PINCTRL_PIN(64, "GPIO64/FANIN0"),1236 PINCTRL_PIN(65, "GPIO65/FANIN1"),1237 PINCTRL_PIN(66, "GPIO66/FANIN2"),1238 PINCTRL_PIN(67, "GPIO67/FANIN3"),1239 PINCTRL_PIN(68, "GPIO68/FANIN4"),1240 PINCTRL_PIN(69, "GPIO69/FANIN5"),1241 PINCTRL_PIN(70, "GPIO70/FANIN6"),1242 PINCTRL_PIN(71, "GPIO71/FANIN7"),1243 PINCTRL_PIN(72, "GPIO72/FANIN8"),1244 PINCTRL_PIN(73, "GPIO73/FANIN9"),1245 PINCTRL_PIN(74, "GPIO74/FANIN10"),1246 PINCTRL_PIN(75, "GPIO75/FANIN11"),1247 PINCTRL_PIN(76, "GPIO76/FANIN12"),1248 PINCTRL_PIN(77, "GPIO77/FANIN13"),1249 PINCTRL_PIN(78, "GPIO78/FANIN14"),1250 PINCTRL_PIN(79, "GPIO79/FANIN15"),1251 PINCTRL_PIN(80, "GPIO80/PWM0"),1252 PINCTRL_PIN(81, "GPIO81/PWM1"),1253 PINCTRL_PIN(82, "GPIO82/PWM2"),1254 PINCTRL_PIN(83, "GPIO83/PWM3"),1255 PINCTRL_PIN(84, "GPIO84/R2TXD0"),1256 PINCTRL_PIN(85, "GPIO85/R2TXD1"),1257 PINCTRL_PIN(86, "GPIO86/R2TXEN"),1258 PINCTRL_PIN(87, "GPIO87/R2RXD0"),1259 PINCTRL_PIN(88, "GPIO88/R2RXD1"),1260 PINCTRL_PIN(89, "GPIO89/R2CRSDV"),1261 PINCTRL_PIN(90, "GPIO90/R2RXERR"),1262 PINCTRL_PIN(91, "GPIO91/R2MDC"),1263 PINCTRL_PIN(92, "GPIO92/R2MDIO"),1264 PINCTRL_PIN(93, "GPIO93/GA20/SMB5DSCL"),1265 PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5DSDA"),1266 PINCTRL_PIN(95, "GPIO95/nLRESET/nESPIRST"),1267 1268 PINCTRL_PIN(96, "GPIO96/RG1TXD0"),1269 PINCTRL_PIN(97, "GPIO97/RG1TXD1"),1270 PINCTRL_PIN(98, "GPIO98/RG1TXD2"),1271 PINCTRL_PIN(99, "GPIO99/RG1TXD3"),1272 PINCTRL_PIN(100, "GPIO100/RG1TXC"),1273 PINCTRL_PIN(101, "GPIO101/RG1TXCTL"),1274 PINCTRL_PIN(102, "GPIO102/RG1RXD0"),1275 PINCTRL_PIN(103, "GPIO103/RG1RXD1"),1276 PINCTRL_PIN(104, "GPIO104/RG1RXD2"),1277 PINCTRL_PIN(105, "GPIO105/RG1RXD3"),1278 PINCTRL_PIN(106, "GPIO106/RG1RXC"),1279 PINCTRL_PIN(107, "GPIO107/RG1RXCTL"),1280 PINCTRL_PIN(108, "GPIO108/RG1MDC"),1281 PINCTRL_PIN(109, "GPIO109/RG1MDIO"),1282 PINCTRL_PIN(110, "GPIO110/RG2TXD0/DDRV0"),1283 PINCTRL_PIN(111, "GPIO111/RG2TXD1/DDRV1"),1284 PINCTRL_PIN(112, "GPIO112/RG2TXD2/DDRV2"),1285 PINCTRL_PIN(113, "GPIO113/RG2TXD3/DDRV3"),1286 PINCTRL_PIN(114, "GPIO114/SMB0SCL"),1287 PINCTRL_PIN(115, "GPIO115/SMB0SDA"),1288 PINCTRL_PIN(116, "GPIO116/SMB1SCL"),1289 PINCTRL_PIN(117, "GPIO117/SMB1SDA"),1290 PINCTRL_PIN(118, "GPIO118/SMB2SCL"),1291 PINCTRL_PIN(119, "GPIO119/SMB2SDA"),1292 PINCTRL_PIN(120, "GPIO120/SMB2CSDA"),1293 PINCTRL_PIN(121, "GPIO121/SMB2CSCL"),1294 PINCTRL_PIN(122, "GPIO122/SMB2BSDA"),1295 PINCTRL_PIN(123, "GPIO123/SMB2BSCL"),1296 PINCTRL_PIN(124, "GPIO124/SMB1CSDA"),1297 PINCTRL_PIN(125, "GPIO125/SMB1CSCL"),1298 PINCTRL_PIN(126, "GPIO126/SMB1BSDA"),1299 PINCTRL_PIN(127, "GPIO127/SMB1BSCL"),1300 1301 PINCTRL_PIN(128, "GPIO128/SMB8SCL"),1302 PINCTRL_PIN(129, "GPIO129/SMB8SDA"),1303 PINCTRL_PIN(130, "GPIO130/SMB9SCL"),1304 PINCTRL_PIN(131, "GPIO131/SMB9SDA"),1305 PINCTRL_PIN(132, "GPIO132/SMB10SCL"),1306 PINCTRL_PIN(133, "GPIO133/SMB10SDA"),1307 PINCTRL_PIN(134, "GPIO134/SMB11SCL"),1308 PINCTRL_PIN(135, "GPIO135/SMB11SDA"),1309 PINCTRL_PIN(136, "GPIO136/SD1DT0"),1310 PINCTRL_PIN(137, "GPIO137/SD1DT1"),1311 PINCTRL_PIN(138, "GPIO138/SD1DT2"),1312 PINCTRL_PIN(139, "GPIO139/SD1DT3"),1313 PINCTRL_PIN(140, "GPIO140/SD1CLK"),1314 PINCTRL_PIN(141, "GPIO141/SD1WP"),1315 PINCTRL_PIN(142, "GPIO142/SD1CMD"),1316 PINCTRL_PIN(143, "GPIO143/SD1CD/SD1PWR"),1317 PINCTRL_PIN(144, "GPIO144/PWM4"),1318 PINCTRL_PIN(145, "GPIO145/PWM5"),1319 PINCTRL_PIN(146, "GPIO146/PWM6"),1320 PINCTRL_PIN(147, "GPIO147/PWM7"),1321 PINCTRL_PIN(148, "GPIO148/MMCDT4"),1322 PINCTRL_PIN(149, "GPIO149/MMCDT5"),1323 PINCTRL_PIN(150, "GPIO150/MMCDT6"),1324 PINCTRL_PIN(151, "GPIO151/MMCDT7"),1325 PINCTRL_PIN(152, "GPIO152/MMCCLK"),1326 PINCTRL_PIN(153, "GPIO153/MMCWP"),1327 PINCTRL_PIN(154, "GPIO154/MMCCMD"),1328 PINCTRL_PIN(155, "GPIO155/nMMCCD/nMMCRST"),1329 PINCTRL_PIN(156, "GPIO156/MMCDT0"),1330 PINCTRL_PIN(157, "GPIO157/MMCDT1"),1331 PINCTRL_PIN(158, "GPIO158/MMCDT2"),1332 PINCTRL_PIN(159, "GPIO159/MMCDT3"),1333 1334 PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"),1335 PINCTRL_PIN(161, "GPIO161/nLFRAME/nESPICS"),1336 PINCTRL_PIN(162, "GPIO162/SERIRQ"),1337 PINCTRL_PIN(163, "GPIO163/LCLK/ESPICLK"),1338 PINCTRL_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/),1339 PINCTRL_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/),1340 PINCTRL_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/),1341 PINCTRL_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/),1342 PINCTRL_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"),1343 PINCTRL_PIN(169, "GPIO169/nSCIPME"),1344 PINCTRL_PIN(170, "GPIO170/nSMI"),1345 PINCTRL_PIN(171, "GPIO171/SMB6SCL"),1346 PINCTRL_PIN(172, "GPIO172/SMB6SDA"),1347 PINCTRL_PIN(173, "GPIO173/SMB7SCL"),1348 PINCTRL_PIN(174, "GPIO174/SMB7SDA"),1349 PINCTRL_PIN(175, "GPIO175/PSPI1CK/FANIN19"),1350 PINCTRL_PIN(176, "GPIO176/PSPI1DO/FANIN18"),1351 PINCTRL_PIN(177, "GPIO177/PSPI1DI/FANIN17"),1352 PINCTRL_PIN(178, "GPIO178/R1TXD0"),1353 PINCTRL_PIN(179, "GPIO179/R1TXD1"),1354 PINCTRL_PIN(180, "GPIO180/R1TXEN"),1355 PINCTRL_PIN(181, "GPIO181/R1RXD0"),1356 PINCTRL_PIN(182, "GPIO182/R1RXD1"),1357 PINCTRL_PIN(183, "GPIO183/SPI3CK"),1358 PINCTRL_PIN(184, "GPO184/SPI3D0/STRAP9"),1359 PINCTRL_PIN(185, "GPO185/SPI3D1/STRAP10"),1360 PINCTRL_PIN(186, "GPIO186/nSPI3CS0"),1361 PINCTRL_PIN(187, "GPIO187/nSPI3CS1"),1362 PINCTRL_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"),1363 PINCTRL_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"),1364 PINCTRL_PIN(190, "GPIO190/nPRD_SMI"),1365 PINCTRL_PIN(191, "GPIO191"),1366 1367 PINCTRL_PIN(192, "GPIO192"),1368 PINCTRL_PIN(193, "GPIO193/R1CRSDV"),1369 PINCTRL_PIN(194, "GPIO194/SMB0BSCL"),1370 PINCTRL_PIN(195, "GPIO195/SMB0BSDA"),1371 PINCTRL_PIN(196, "GPIO196/SMB0CSCL"),1372 PINCTRL_PIN(197, "GPIO197/SMB0DEN"),1373 PINCTRL_PIN(198, "GPIO198/SMB0DSDA"),1374 PINCTRL_PIN(199, "GPIO199/SMB0DSCL"),1375 PINCTRL_PIN(200, "GPIO200/R2CK"),1376 PINCTRL_PIN(201, "GPIO201/R1CK"),1377 PINCTRL_PIN(202, "GPIO202/SMB0CSDA"),1378 PINCTRL_PIN(203, "GPIO203/FANIN16"),1379 PINCTRL_PIN(204, "GPIO204/DDC2SCL"),1380 PINCTRL_PIN(205, "GPIO205/DDC2SDA"),1381 PINCTRL_PIN(206, "GPIO206/HSYNC2"),1382 PINCTRL_PIN(207, "GPIO207/VSYNC2"),1383 PINCTRL_PIN(208, "GPIO208/RG2TXC/DVCK"),1384 PINCTRL_PIN(209, "GPIO209/RG2TXCTL/DDRV4"),1385 PINCTRL_PIN(210, "GPIO210/RG2RXD0/DDRV5"),1386 PINCTRL_PIN(211, "GPIO211/RG2RXD1/DDRV6"),1387 PINCTRL_PIN(212, "GPIO212/RG2RXD2/DDRV7"),1388 PINCTRL_PIN(213, "GPIO213/RG2RXD3/DDRV8"),1389 PINCTRL_PIN(214, "GPIO214/RG2RXC/DDRV9"),1390 PINCTRL_PIN(215, "GPIO215/RG2RXCTL/DDRV10"),1391 PINCTRL_PIN(216, "GPIO216/RG2MDC/DDRV11"),1392 PINCTRL_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"),1393 PINCTRL_PIN(218, "GPIO218/nWDO1"),1394 PINCTRL_PIN(219, "GPIO219/nWDO2"),1395 PINCTRL_PIN(220, "GPIO220/SMB12SCL"),1396 PINCTRL_PIN(221, "GPIO221/SMB12SDA"),1397 PINCTRL_PIN(222, "GPIO222/SMB13SCL"),1398 PINCTRL_PIN(223, "GPIO223/SMB13SDA"),1399 1400 PINCTRL_PIN(224, "GPIO224/SPIXCK"),1401 PINCTRL_PIN(225, "GPO225/SPIXD0/STRAP12"),1402 PINCTRL_PIN(226, "GPO226/SPIXD1/STRAP13"),1403 PINCTRL_PIN(227, "GPIO227/nSPIXCS0"),1404 PINCTRL_PIN(228, "GPIO228/nSPIXCS1"),1405 PINCTRL_PIN(229, "GPO229/SPIXD2/STRAP3"),1406 PINCTRL_PIN(230, "GPIO230/SPIXD3"),1407 PINCTRL_PIN(231, "GPIO231/nCLKREQ"),1408 PINCTRL_PIN(255, "GPI255/DACOSEL"),1409};1410 1411/* Enable mode in pin group */1412static void npcm7xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,1413 int pin_number, int mode)1414{1415 const struct npcm7xx_pincfg *cfg;1416 int i;1417 1418 for (i = 0 ; i < pin_number ; i++) {1419 cfg = &pincfg[pin[i]];1420 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {1421 if (cfg->reg0)1422 regmap_update_bits(gcr_regmap, cfg->reg0,1423 BIT(cfg->bit0),1424 !!(cfg->fn0 == mode) ?1425 BIT(cfg->bit0) : 0);1426 if (cfg->reg1)1427 regmap_update_bits(gcr_regmap, cfg->reg1,1428 BIT(cfg->bit1),1429 !!(cfg->fn1 == mode) ?1430 BIT(cfg->bit1) : 0);1431 if (cfg->reg2)1432 regmap_update_bits(gcr_regmap, cfg->reg2,1433 BIT(cfg->bit2),1434 !!(cfg->fn2 == mode) ?1435 BIT(cfg->bit2) : 0);1436 }1437 }1438}1439 1440/* Get slew rate of pin (high/low) */1441static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank,1442 struct regmap *gcr_regmap, unsigned int pin)1443{1444 u32 val;1445 int gpio = (pin % bank->gc.ngpio);1446 unsigned long pinmask = BIT(gpio);1447 1448 if (pincfg[pin].flag & SLEW)1449 return ioread32(bank->base + NPCM7XX_GP_N_OSRC)1450 & pinmask;1451 /* LPC Slew rate in SRCNT register */1452 if (pincfg[pin].flag & SLEWLPC) {1453 regmap_read(gcr_regmap, NPCM7XX_GCR_SRCNT, &val);1454 return !!(val & SRCNT_ESPI);1455 }1456 1457 return -EINVAL;1458}1459 1460/* Set slew rate of pin (high/low) */1461static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank,1462 struct regmap *gcr_regmap, unsigned int pin,1463 int arg)1464{1465 int gpio = BIT(pin % bank->gc.ngpio);1466 1467 if (pincfg[pin].flag & SLEW) {1468 switch (arg) {1469 case 0:1470 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,1471 gpio);1472 return 0;1473 case 1:1474 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,1475 gpio);1476 return 0;1477 default:1478 return -EINVAL;1479 }1480 }1481 /* LPC Slew rate in SRCNT register */1482 if (pincfg[pin].flag & SLEWLPC) {1483 switch (arg) {1484 case 0:1485 regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,1486 SRCNT_ESPI, 0);1487 return 0;1488 case 1:1489 regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,1490 SRCNT_ESPI, SRCNT_ESPI);1491 return 0;1492 default:1493 return -EINVAL;1494 }1495 }1496 1497 return -EINVAL;1498}1499 1500/* Get drive strength for a pin, if supported */1501static int npcm7xx_get_drive_strength(struct pinctrl_dev *pctldev,1502 unsigned int pin)1503{1504 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);1505 struct npcm7xx_gpio *bank =1506 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];1507 int gpio = (pin % bank->gc.ngpio);1508 unsigned long pinmask = BIT(gpio);1509 u32 ds = 0;1510 int flg, val;1511 1512 flg = pincfg[pin].flag;1513 if (flg & DRIVE_STRENGTH_MASK) {1514 /* Get standard reading */1515 val = ioread32(bank->base + NPCM7XX_GP_N_ODSC)1516 & pinmask;1517 ds = val ? DSHI(flg) : DSLO(flg);1518 dev_dbg(bank->gc.parent,1519 "pin %d strength %d = %d\n", pin, val, ds);1520 return ds;1521 }1522 1523 return -EINVAL;1524}1525 1526/* Set drive strength for a pin, if supported */1527static int npcm7xx_set_drive_strength(struct npcm7xx_pinctrl *npcm,1528 unsigned int pin, int nval)1529{1530 int v;1531 struct npcm7xx_gpio *bank =1532 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];1533 int gpio = BIT(pin % bank->gc.ngpio);1534 1535 v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK);1536 if (!nval || !v)1537 return -ENOTSUPP;1538 if (DSLO(v) == nval) {1539 dev_dbg(bank->gc.parent,1540 "setting pin %d to low strength [%d]\n", pin, nval);1541 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);1542 return 0;1543 } else if (DSHI(v) == nval) {1544 dev_dbg(bank->gc.parent,1545 "setting pin %d to high strength [%d]\n", pin, nval);1546 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);1547 return 0;1548 }1549 1550 return -ENOTSUPP;1551}1552 1553/* pinctrl_ops */1554static void npcm7xx_pin_dbg_show(struct pinctrl_dev *pctldev,1555 struct seq_file *s, unsigned int offset)1556{1557 seq_printf(s, "pinctrl_ops.dbg: %d", offset);1558}1559 1560static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev)1561{1562 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);1563 1564 dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups));1565 return ARRAY_SIZE(npcm7xx_groups);1566}1567 1568static const char *npcm7xx_get_group_name(struct pinctrl_dev *pctldev,1569 unsigned int selector)1570{1571 return npcm7xx_groups[selector].name;1572}1573 1574static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev,1575 unsigned int selector,1576 const unsigned int **pins,1577 unsigned int *npins)1578{1579 *npins = npcm7xx_groups[selector].npins;1580 *pins = npcm7xx_groups[selector].pins;1581 1582 return 0;1583}1584 1585static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev,1586 struct pinctrl_map *map, u32 num_maps)1587{1588 kfree(map);1589}1590 1591static const struct pinctrl_ops npcm7xx_pinctrl_ops = {1592 .get_groups_count = npcm7xx_get_groups_count,1593 .get_group_name = npcm7xx_get_group_name,1594 .get_group_pins = npcm7xx_get_group_pins,1595 .pin_dbg_show = npcm7xx_pin_dbg_show,1596 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,1597 .dt_free_map = npcm7xx_dt_free_map,1598};1599 1600/* pinmux_ops */1601static int npcm7xx_get_functions_count(struct pinctrl_dev *pctldev)1602{1603 return ARRAY_SIZE(npcm7xx_funcs);1604}1605 1606static const char *npcm7xx_get_function_name(struct pinctrl_dev *pctldev,1607 unsigned int function)1608{1609 return npcm7xx_funcs[function].name;1610}1611 1612static int npcm7xx_get_function_groups(struct pinctrl_dev *pctldev,1613 unsigned int function,1614 const char * const **groups,1615 unsigned int * const ngroups)1616{1617 *ngroups = npcm7xx_funcs[function].ngroups;1618 *groups = npcm7xx_funcs[function].groups;1619 1620 return 0;1621}1622 1623static int npcm7xx_pinmux_set_mux(struct pinctrl_dev *pctldev,1624 unsigned int function,1625 unsigned int group)1626{1627 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);1628 1629 dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group,1630 npcm7xx_groups[group].name);1631 1632 npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins,1633 npcm7xx_groups[group].npins, group);1634 1635 return 0;1636}1637 1638static int npcm7xx_gpio_request_enable(struct pinctrl_dev *pctldev,1639 struct pinctrl_gpio_range *range,1640 unsigned int offset)1641{1642 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);1643 1644 if (!range) {1645 dev_err(npcm->dev, "invalid range\n");1646 return -EINVAL;1647 }1648 if (!range->gc) {1649 dev_err(npcm->dev, "invalid gpiochip\n");1650 return -EINVAL;1651 }1652 1653 npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio);1654 1655 return 0;1656}1657 1658/* Release GPIO back to pinctrl mode */1659static void npcm7xx_gpio_request_free(struct pinctrl_dev *pctldev,1660 struct pinctrl_gpio_range *range,1661 unsigned int offset)1662{1663 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);1664 int virq;1665 1666 virq = irq_find_mapping(npcm->domain, offset);1667 if (virq)1668 irq_dispose_mapping(virq);1669}1670 1671/* Set GPIO direction */1672static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,1673 struct pinctrl_gpio_range *range,1674 unsigned int offset, bool input)1675{1676 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);1677 struct npcm7xx_gpio *bank =1678 &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK];1679 int gpio = BIT(offset % bank->gc.ngpio);1680 1681 dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset,1682 input);1683 if (input)1684 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);1685 else1686 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);1687 1688 return 0;1689}1690 1691static const struct pinmux_ops npcm7xx_pinmux_ops = {1692 .get_functions_count = npcm7xx_get_functions_count,1693 .get_function_name = npcm7xx_get_function_name,1694 .get_function_groups = npcm7xx_get_function_groups,1695 .set_mux = npcm7xx_pinmux_set_mux,1696 .gpio_request_enable = npcm7xx_gpio_request_enable,1697 .gpio_disable_free = npcm7xx_gpio_request_free,1698 .gpio_set_direction = npcm_gpio_set_direction,1699};1700 1701/* pinconf_ops */1702static int npcm7xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,1703 unsigned long *config)1704{1705 enum pin_config_param param = pinconf_to_config_param(*config);1706 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);1707 struct npcm7xx_gpio *bank =1708 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];1709 int gpio = (pin % bank->gc.ngpio);1710 unsigned long pinmask = BIT(gpio);1711 u32 ie, oe, pu, pd;1712 int rc = 0;1713 1714 switch (param) {1715 case PIN_CONFIG_BIAS_DISABLE:1716 case PIN_CONFIG_BIAS_PULL_UP:1717 case PIN_CONFIG_BIAS_PULL_DOWN:1718 pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask;1719 pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask;1720 if (param == PIN_CONFIG_BIAS_DISABLE)1721 rc = (!pu && !pd);1722 else if (param == PIN_CONFIG_BIAS_PULL_UP)1723 rc = (pu && !pd);1724 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)1725 rc = (!pu && pd);1726 break;1727 case PIN_CONFIG_OUTPUT:1728 case PIN_CONFIG_INPUT_ENABLE:1729 ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;1730 oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;1731 if (param == PIN_CONFIG_INPUT_ENABLE)1732 rc = (ie && !oe);1733 else if (param == PIN_CONFIG_OUTPUT)1734 rc = (!ie && oe);1735 break;1736 case PIN_CONFIG_DRIVE_PUSH_PULL:1737 rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask);1738 break;1739 case PIN_CONFIG_DRIVE_OPEN_DRAIN:1740 rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask;1741 break;1742 case PIN_CONFIG_INPUT_DEBOUNCE:1743 rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask;1744 break;1745 case PIN_CONFIG_DRIVE_STRENGTH:1746 rc = npcm7xx_get_drive_strength(pctldev, pin);1747 if (rc)1748 *config = pinconf_to_config_packed(param, rc);1749 break;1750 case PIN_CONFIG_SLEW_RATE:1751 rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin);1752 if (rc >= 0)1753 *config = pinconf_to_config_packed(param, rc);1754 break;1755 default:1756 return -ENOTSUPP;1757 }1758 1759 if (!rc)1760 return -EINVAL;1761 1762 return 0;1763}1764 1765static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm,1766 unsigned int pin, unsigned long config)1767{1768 enum pin_config_param param = pinconf_to_config_param(config);1769 u16 arg = pinconf_to_config_argument(config);1770 struct npcm7xx_gpio *bank =1771 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];1772 int gpio = BIT(pin % bank->gc.ngpio);1773 1774 dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin);1775 switch (param) {1776 case PIN_CONFIG_BIAS_DISABLE:1777 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);1778 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);1779 break;1780 case PIN_CONFIG_BIAS_PULL_DOWN:1781 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);1782 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);1783 break;1784 case PIN_CONFIG_BIAS_PULL_UP:1785 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);1786 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);1787 break;1788 case PIN_CONFIG_INPUT_ENABLE:1789 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);1790 bank->direction_input(&bank->gc, pin % bank->gc.ngpio);1791 break;1792 case PIN_CONFIG_OUTPUT:1793 bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);1794 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);1795 break;1796 case PIN_CONFIG_DRIVE_PUSH_PULL:1797 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);1798 break;1799 case PIN_CONFIG_DRIVE_OPEN_DRAIN:1800 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);1801 break;1802 case PIN_CONFIG_INPUT_DEBOUNCE:1803 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio);1804 break;1805 case PIN_CONFIG_SLEW_RATE:1806 return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);1807 case PIN_CONFIG_DRIVE_STRENGTH:1808 return npcm7xx_set_drive_strength(npcm, pin, arg);1809 default:1810 return -ENOTSUPP;1811 }1812 1813 return 0;1814}1815 1816/* Set multiple configuration settings for a pin */1817static int npcm7xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,1818 unsigned long *configs, unsigned int num_configs)1819{1820 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);1821 int rc;1822 1823 while (num_configs--) {1824 rc = npcm7xx_config_set_one(npcm, pin, *configs++);1825 if (rc)1826 return rc;1827 }1828 1829 return 0;1830}1831 1832static const struct pinconf_ops npcm7xx_pinconf_ops = {1833 .is_generic = true,1834 .pin_config_get = npcm7xx_config_get,1835 .pin_config_set = npcm7xx_config_set,1836};1837 1838/* pinctrl_desc */1839static struct pinctrl_desc npcm7xx_pinctrl_desc = {1840 .name = "npcm7xx-pinctrl",1841 .pins = npcm7xx_pins,1842 .npins = ARRAY_SIZE(npcm7xx_pins),1843 .pctlops = &npcm7xx_pinctrl_ops,1844 .pmxops = &npcm7xx_pinmux_ops,1845 .confops = &npcm7xx_pinconf_ops,1846 .owner = THIS_MODULE,1847};1848 1849static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl)1850{1851 int ret = -ENXIO;1852 struct resource res;1853 struct device *dev = pctrl->dev;1854 struct fwnode_reference_args args;1855 struct fwnode_handle *child;1856 int id = 0;1857 1858 for_each_gpiochip_node(dev, child) {1859 struct device_node *np = to_of_node(child);1860 1861 ret = of_address_to_resource(np, 0, &res);1862 if (ret < 0) {1863 dev_err(dev, "Resource fail for GPIO bank %u\n", id);1864 return ret;1865 }1866 1867 pctrl->gpio_bank[id].base = ioremap(res.start, resource_size(&res));1868 if (!pctrl->gpio_bank[id].base)1869 return -EINVAL;1870 1871 ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4,1872 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN,1873 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT,1874 NULL,1875 NULL,1876 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM,1877 BGPIOF_READ_OUTPUT_REG_SET);1878 if (ret) {1879 dev_err(dev, "bgpio_init() failed\n");1880 return ret;1881 }1882 1883 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);1884 if (ret < 0) {1885 dev_err(dev, "gpio-ranges fail for GPIO bank %u\n", id);1886 return ret;1887 }1888 1889 ret = irq_of_parse_and_map(np, 0);1890 if (!ret) {1891 dev_err(dev, "No IRQ for GPIO bank %u\n", id);1892 return -EINVAL;1893 }1894 pctrl->gpio_bank[id].irq = ret;1895 pctrl->gpio_bank[id].irqbase = id * NPCM7XX_GPIO_PER_BANK;1896 pctrl->gpio_bank[id].pinctrl_id = args.args[0];1897 pctrl->gpio_bank[id].gc.base = args.args[1];1898 pctrl->gpio_bank[id].gc.ngpio = args.args[2];1899 pctrl->gpio_bank[id].gc.owner = THIS_MODULE;1900 pctrl->gpio_bank[id].gc.parent = dev;1901 pctrl->gpio_bank[id].gc.fwnode = child;1902 pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);1903 if (pctrl->gpio_bank[id].gc.label == NULL)1904 return -ENOMEM;1905 1906 pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;1907 pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input;1908 pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input;1909 pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output;1910 pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;1911 pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;1912 pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;1913 pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free;1914 id++;1915 }1916 1917 pctrl->bank_num = id;1918 return ret;1919}1920 1921static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl)1922{1923 int ret, id;1924 1925 for (id = 0 ; id < pctrl->bank_num ; id++) {1926 struct gpio_irq_chip *girq;1927 1928 girq = &pctrl->gpio_bank[id].gc.irq;1929 gpio_irq_chip_set_chip(girq, &npcmgpio_irqchip);1930 girq->parent_handler = npcmgpio_irq_handler;1931 girq->num_parents = 1;1932 girq->parents = devm_kcalloc(pctrl->dev, 1,1933 sizeof(*girq->parents),1934 GFP_KERNEL);1935 if (!girq->parents) {1936 ret = -ENOMEM;1937 goto err_register;1938 }1939 girq->parents[0] = pctrl->gpio_bank[id].irq;1940 girq->default_type = IRQ_TYPE_NONE;1941 girq->handler = handle_level_irq;1942 ret = devm_gpiochip_add_data(pctrl->dev,1943 &pctrl->gpio_bank[id].gc,1944 &pctrl->gpio_bank[id]);1945 if (ret) {1946 dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id);1947 goto err_register;1948 }1949 1950 ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc,1951 dev_name(pctrl->dev),1952 pctrl->gpio_bank[id].pinctrl_id,1953 pctrl->gpio_bank[id].gc.base,1954 pctrl->gpio_bank[id].gc.ngpio);1955 if (ret < 0) {1956 dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id);1957 gpiochip_remove(&pctrl->gpio_bank[id].gc);1958 goto err_register;1959 }1960 }1961 1962 return 0;1963 1964err_register:1965 for (; id > 0; id--)1966 gpiochip_remove(&pctrl->gpio_bank[id - 1].gc);1967 1968 return ret;1969}1970 1971static int npcm7xx_pinctrl_probe(struct platform_device *pdev)1972{1973 struct npcm7xx_pinctrl *pctrl;1974 int ret;1975 1976 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);1977 if (!pctrl)1978 return -ENOMEM;1979 1980 pctrl->dev = &pdev->dev;1981 dev_set_drvdata(&pdev->dev, pctrl);1982 1983 pctrl->gcr_regmap =1984 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");1985 if (IS_ERR(pctrl->gcr_regmap)) {1986 dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n");1987 return PTR_ERR(pctrl->gcr_regmap);1988 }1989 1990 ret = npcm7xx_gpio_of(pctrl);1991 if (ret < 0) {1992 dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret);1993 return ret;1994 }1995 1996 pctrl->pctldev = devm_pinctrl_register(&pdev->dev,1997 &npcm7xx_pinctrl_desc, pctrl);1998 if (IS_ERR(pctrl->pctldev)) {1999 dev_err(&pdev->dev, "Failed to register pinctrl device\n");2000 return PTR_ERR(pctrl->pctldev);2001 }2002 2003 ret = npcm7xx_gpio_register(pctrl);2004 if (ret < 0) {2005 dev_err(pctrl->dev, "Failed to register gpio %u\n", ret);2006 return ret;2007 }2008 2009 pr_info("NPCM7xx Pinctrl driver probed\n");2010 return 0;2011}2012 2013static const struct of_device_id npcm7xx_pinctrl_match[] = {2014 { .compatible = "nuvoton,npcm750-pinctrl" },2015 { },2016};2017MODULE_DEVICE_TABLE(of, npcm7xx_pinctrl_match);2018 2019static struct platform_driver npcm7xx_pinctrl_driver = {2020 .probe = npcm7xx_pinctrl_probe,2021 .driver = {2022 .name = "npcm7xx-pinctrl",2023 .of_match_table = npcm7xx_pinctrl_match,2024 .suppress_bind_attrs = true,2025 },2026};2027 2028static int __init npcm7xx_pinctrl_register(void)2029{2030 return platform_driver_register(&npcm7xx_pinctrl_driver);2031}2032arch_initcall(npcm7xx_pinctrl_register);2033 2034MODULE_AUTHOR("jordan_hargrave@dell.com");2035MODULE_AUTHOR("tomer.maimon@nuvoton.com");2036MODULE_DESCRIPTION("Nuvoton NPCM7XX Pinctrl and GPIO driver");2037