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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Core driver for the S32 CC (Common Chassis) pin controller4 *5 * Copyright 2017-2022,2024 NXP6 * Copyright (C) 2022 SUSE LLC7 * Copyright 2015-2016 Freescale Semiconductor, Inc.8 */9 10#include <linux/bitops.h>11#include <linux/err.h>12#include <linux/gpio/driver.h>13#include <linux/init.h>14#include <linux/io.h>15#include <linux/module.h>16#include <linux/of.h>17#include <linux/platform_device.h>18#include <linux/pinctrl/machine.h>19#include <linux/pinctrl/pinconf.h>20#include <linux/pinctrl/pinctrl.h>21#include <linux/pinctrl/pinmux.h>22#include <linux/regmap.h>23#include <linux/seq_file.h>24#include <linux/slab.h>25 26#include "../core.h"27#include "../pinconf.h"28#include "../pinctrl-utils.h"29#include "pinctrl-s32.h"30 31#define S32_PIN_ID_SHIFT 432#define S32_PIN_ID_MASK GENMASK(31, S32_PIN_ID_SHIFT)33 34#define S32_MSCR_SSS_MASK GENMASK(2, 0)35#define S32_MSCR_PUS BIT(12)36#define S32_MSCR_PUE BIT(13)37#define S32_MSCR_SRE(X) (((X) & GENMASK(3, 0)) << 14)38#define S32_MSCR_IBE BIT(19)39#define S32_MSCR_ODE BIT(20)40#define S32_MSCR_OBE BIT(21)41 42enum s32_write_type {43 S32_PINCONF_UPDATE_ONLY,44 S32_PINCONF_OVERWRITE,45};46 47static struct regmap_config s32_regmap_config = {48 .reg_bits = 32,49 .val_bits = 32,50 .reg_stride = 4,51};52 53static u32 get_pin_no(u32 pinmux)54{55 return (pinmux & S32_PIN_ID_MASK) >> S32_PIN_ID_SHIFT;56}57 58static u32 get_pin_func(u32 pinmux)59{60 return pinmux & GENMASK(3, 0);61}62 63struct s32_pinctrl_mem_region {64 struct regmap *map;65 const struct s32_pin_range *pin_range;66 char name[8];67};68 69/*70 * Holds pin configuration for GPIO's.71 * @pin_id: Pin ID for this GPIO72 * @config: Pin settings73 * @list: Linked list entry for each gpio pin74 */75struct gpio_pin_config {76 unsigned int pin_id;77 unsigned int config;78 struct list_head list;79};80 81/*82 * Pad config save/restore for power suspend/resume.83 */84struct s32_pinctrl_context {85 unsigned int *pads;86};87 88/*89 * @dev: a pointer back to containing device90 * @pctl: a pointer to the pinctrl device structure91 * @regions: reserved memory regions with start/end pin92 * @info: structure containing information about the pin93 * @gpio_configs: Saved configurations for GPIO pins94 * @gpiop_configs_lock: lock for the `gpio_configs` list95 * @s32_pinctrl_context: Configuration saved over system sleep96 */97struct s32_pinctrl {98 struct device *dev;99 struct pinctrl_dev *pctl;100 struct s32_pinctrl_mem_region *regions;101 struct s32_pinctrl_soc_info *info;102 struct list_head gpio_configs;103 spinlock_t gpio_configs_lock;104#ifdef CONFIG_PM_SLEEP105 struct s32_pinctrl_context saved_context;106#endif107};108 109static struct s32_pinctrl_mem_region *110s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin)111{112 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);113 const struct s32_pin_range *pin_range;114 unsigned int mem_regions = ipctl->info->soc_data->mem_regions;115 unsigned int i;116 117 for (i = 0; i < mem_regions; i++) {118 pin_range = ipctl->regions[i].pin_range;119 if (pin >= pin_range->start && pin <= pin_range->end)120 return &ipctl->regions[i];121 }122 123 return NULL;124}125 126static inline int s32_check_pin(struct pinctrl_dev *pctldev,127 unsigned int pin)128{129 return s32_get_region(pctldev, pin) ? 0 : -EINVAL;130}131 132static inline int s32_regmap_read(struct pinctrl_dev *pctldev,133 unsigned int pin, unsigned int *val)134{135 struct s32_pinctrl_mem_region *region;136 unsigned int offset;137 138 region = s32_get_region(pctldev, pin);139 if (!region)140 return -EINVAL;141 142 offset = (pin - region->pin_range->start) *143 regmap_get_reg_stride(region->map);144 145 return regmap_read(region->map, offset, val);146}147 148static inline int s32_regmap_write(struct pinctrl_dev *pctldev,149 unsigned int pin,150 unsigned int val)151{152 struct s32_pinctrl_mem_region *region;153 unsigned int offset;154 155 region = s32_get_region(pctldev, pin);156 if (!region)157 return -EINVAL;158 159 offset = (pin - region->pin_range->start) *160 regmap_get_reg_stride(region->map);161 162 return regmap_write(region->map, offset, val);163 164}165 166static inline int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin,167 unsigned int mask, unsigned int val)168{169 struct s32_pinctrl_mem_region *region;170 unsigned int offset;171 172 region = s32_get_region(pctldev, pin);173 if (!region)174 return -EINVAL;175 176 offset = (pin - region->pin_range->start) *177 regmap_get_reg_stride(region->map);178 179 return regmap_update_bits(region->map, offset, mask, val);180}181 182static int s32_get_groups_count(struct pinctrl_dev *pctldev)183{184 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);185 const struct s32_pinctrl_soc_info *info = ipctl->info;186 187 return info->ngroups;188}189 190static const char *s32_get_group_name(struct pinctrl_dev *pctldev,191 unsigned int selector)192{193 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);194 const struct s32_pinctrl_soc_info *info = ipctl->info;195 196 return info->groups[selector].data.name;197}198 199static int s32_get_group_pins(struct pinctrl_dev *pctldev,200 unsigned int selector, const unsigned int **pins,201 unsigned int *npins)202{203 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);204 const struct s32_pinctrl_soc_info *info = ipctl->info;205 206 *pins = info->groups[selector].data.pins;207 *npins = info->groups[selector].data.npins;208 209 return 0;210}211 212static void s32_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,213 unsigned int offset)214{215 seq_printf(s, "%s", dev_name(pctldev->dev));216}217 218static int s32_dt_group_node_to_map(struct pinctrl_dev *pctldev,219 struct device_node *np,220 struct pinctrl_map **map,221 unsigned int *reserved_maps,222 unsigned int *num_maps,223 const char *func_name)224{225 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);226 struct device *dev = ipctl->dev;227 unsigned long *cfgs = NULL;228 unsigned int n_cfgs, reserve = 1;229 int n_pins, ret;230 231 n_pins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32));232 if (n_pins < 0) {233 dev_warn(dev, "Can't find 'pinmux' property in node %pOFn\n", np);234 } else if (!n_pins) {235 return -EINVAL;236 }237 238 ret = pinconf_generic_parse_dt_config(np, pctldev, &cfgs, &n_cfgs);239 if (ret) {240 dev_err(dev, "%pOF: could not parse node property\n", np);241 return ret;242 }243 244 if (n_cfgs)245 reserve++;246 247 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,248 reserve);249 if (ret < 0)250 goto free_cfgs;251 252 ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,253 np->name, func_name);254 if (ret < 0)255 goto free_cfgs;256 257 if (n_cfgs) {258 ret = pinctrl_utils_add_map_configs(pctldev, map, reserved_maps,259 num_maps, np->name, cfgs, n_cfgs,260 PIN_MAP_TYPE_CONFIGS_GROUP);261 if (ret < 0)262 goto free_cfgs;263 }264 265free_cfgs:266 kfree(cfgs);267 return ret;268}269 270static int s32_dt_node_to_map(struct pinctrl_dev *pctldev,271 struct device_node *np_config,272 struct pinctrl_map **map,273 unsigned int *num_maps)274{275 unsigned int reserved_maps;276 int ret;277 278 reserved_maps = 0;279 *map = NULL;280 *num_maps = 0;281 282 for_each_available_child_of_node_scoped(np_config, np) {283 ret = s32_dt_group_node_to_map(pctldev, np, map,284 &reserved_maps, num_maps,285 np_config->name);286 if (ret < 0) {287 pinctrl_utils_free_map(pctldev, *map, *num_maps);288 return ret;289 }290 }291 292 return 0;293}294 295static const struct pinctrl_ops s32_pctrl_ops = {296 .get_groups_count = s32_get_groups_count,297 .get_group_name = s32_get_group_name,298 .get_group_pins = s32_get_group_pins,299 .pin_dbg_show = s32_pin_dbg_show,300 .dt_node_to_map = s32_dt_node_to_map,301 .dt_free_map = pinctrl_utils_free_map,302};303 304static int s32_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector,305 unsigned int group)306{307 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);308 const struct s32_pinctrl_soc_info *info = ipctl->info;309 int i, ret;310 struct s32_pin_group *grp;311 312 /*313 * Configure the mux mode for each pin in the group for a specific314 * function.315 */316 grp = &info->groups[group];317 318 dev_dbg(ipctl->dev, "set mux for function %s group %s\n",319 info->functions[selector].name, grp->data.name);320 321 /* Check beforehand so we don't have a partial config. */322 for (i = 0; i < grp->data.npins; i++) {323 if (s32_check_pin(pctldev, grp->data.pins[i]) != 0) {324 dev_err(info->dev, "invalid pin: %u in group: %u\n",325 grp->data.pins[i], group);326 return -EINVAL;327 }328 }329 330 for (i = 0, ret = 0; i < grp->data.npins && !ret; i++) {331 ret = s32_regmap_update(pctldev, grp->data.pins[i],332 S32_MSCR_SSS_MASK, grp->pin_sss[i]);333 if (ret) {334 dev_err(info->dev, "Failed to set pin %u\n",335 grp->data.pins[i]);336 return ret;337 }338 }339 340 return 0;341}342 343static int s32_pmx_get_funcs_count(struct pinctrl_dev *pctldev)344{345 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);346 const struct s32_pinctrl_soc_info *info = ipctl->info;347 348 return info->nfunctions;349}350 351static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev,352 unsigned int selector)353{354 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);355 const struct s32_pinctrl_soc_info *info = ipctl->info;356 357 return info->functions[selector].name;358}359 360static int s32_pmx_get_groups(struct pinctrl_dev *pctldev,361 unsigned int selector,362 const char * const **groups,363 unsigned int * const num_groups)364{365 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);366 const struct s32_pinctrl_soc_info *info = ipctl->info;367 368 *groups = info->functions[selector].groups;369 *num_groups = info->functions[selector].ngroups;370 371 return 0;372}373 374static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,375 struct pinctrl_gpio_range *range,376 unsigned int offset)377{378 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);379 struct gpio_pin_config *gpio_pin;380 unsigned int config;381 unsigned long flags;382 int ret;383 384 ret = s32_regmap_read(pctldev, offset, &config);385 if (ret)386 return ret;387 388 /* Save current configuration */389 gpio_pin = kmalloc(sizeof(*gpio_pin), GFP_KERNEL);390 if (!gpio_pin)391 return -ENOMEM;392 393 gpio_pin->pin_id = offset;394 gpio_pin->config = config;395 396 spin_lock_irqsave(&ipctl->gpio_configs_lock, flags);397 list_add(&gpio_pin->list, &ipctl->gpio_configs);398 spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags);399 400 /* GPIO pin means SSS = 0 */401 config &= ~S32_MSCR_SSS_MASK;402 403 return s32_regmap_write(pctldev, offset, config);404}405 406static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,407 struct pinctrl_gpio_range *range,408 unsigned int offset)409{410 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);411 struct gpio_pin_config *gpio_pin, *tmp;412 unsigned long flags;413 int ret;414 415 spin_lock_irqsave(&ipctl->gpio_configs_lock, flags);416 417 list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) {418 if (gpio_pin->pin_id == offset) {419 ret = s32_regmap_write(pctldev, gpio_pin->pin_id,420 gpio_pin->config);421 if (ret != 0)422 goto unlock;423 424 list_del(&gpio_pin->list);425 kfree(gpio_pin);426 break;427 }428 }429 430unlock:431 spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags);432}433 434static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,435 struct pinctrl_gpio_range *range,436 unsigned int offset,437 bool input)438{439 /* Always enable IBE for GPIOs. This allows us to read the440 * actual line value and compare it with the one set.441 */442 unsigned int config = S32_MSCR_IBE;443 unsigned int mask = S32_MSCR_IBE | S32_MSCR_OBE;444 445 /* Enable output buffer */446 if (!input)447 config |= S32_MSCR_OBE;448 449 return s32_regmap_update(pctldev, offset, mask, config);450}451 452static const struct pinmux_ops s32_pmx_ops = {453 .get_functions_count = s32_pmx_get_funcs_count,454 .get_function_name = s32_pmx_get_func_name,455 .get_function_groups = s32_pmx_get_groups,456 .set_mux = s32_pmx_set,457 .gpio_request_enable = s32_pmx_gpio_request_enable,458 .gpio_disable_free = s32_pmx_gpio_disable_free,459 .gpio_set_direction = s32_pmx_gpio_set_direction,460};461 462/* Set the reserved elements as -1 */463static const int support_slew[] = {208, -1, -1, -1, 166, 150, 133, 83};464 465static int s32_get_slew_regval(int arg)466{467 unsigned int i;468 469 /* Translate a real slew rate (MHz) to a register value */470 for (i = 0; i < ARRAY_SIZE(support_slew); i++) {471 if (arg == support_slew[i])472 return i;473 }474 475 return -EINVAL;476}477 478static inline void s32_pin_set_pull(enum pin_config_param param,479 unsigned int *mask, unsigned int *config)480{481 switch (param) {482 case PIN_CONFIG_BIAS_DISABLE:483 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:484 *config &= ~(S32_MSCR_PUS | S32_MSCR_PUE);485 break;486 case PIN_CONFIG_BIAS_PULL_UP:487 *config |= S32_MSCR_PUS | S32_MSCR_PUE;488 break;489 case PIN_CONFIG_BIAS_PULL_DOWN:490 *config &= ~S32_MSCR_PUS;491 *config |= S32_MSCR_PUE;492 break;493 default:494 return;495 }496 497 *mask |= S32_MSCR_PUS | S32_MSCR_PUE;498}499 500static int s32_parse_pincfg(unsigned long pincfg, unsigned int *mask,501 unsigned int *config)502{503 enum pin_config_param param;504 u32 arg;505 int ret;506 507 param = pinconf_to_config_param(pincfg);508 arg = pinconf_to_config_argument(pincfg);509 510 switch (param) {511 /* All pins are persistent over suspend */512 case PIN_CONFIG_PERSIST_STATE:513 return 0;514 case PIN_CONFIG_DRIVE_OPEN_DRAIN:515 *config |= S32_MSCR_ODE;516 *mask |= S32_MSCR_ODE;517 break;518 case PIN_CONFIG_DRIVE_PUSH_PULL:519 *config &= ~S32_MSCR_ODE;520 *mask |= S32_MSCR_ODE;521 break;522 case PIN_CONFIG_OUTPUT_ENABLE:523 if (arg)524 *config |= S32_MSCR_OBE;525 else526 *config &= ~S32_MSCR_OBE;527 *mask |= S32_MSCR_OBE;528 break;529 case PIN_CONFIG_INPUT_ENABLE:530 if (arg)531 *config |= S32_MSCR_IBE;532 else533 *config &= ~S32_MSCR_IBE;534 *mask |= S32_MSCR_IBE;535 break;536 case PIN_CONFIG_SLEW_RATE:537 ret = s32_get_slew_regval(arg);538 if (ret < 0)539 return ret;540 *config |= S32_MSCR_SRE((u32)ret);541 *mask |= S32_MSCR_SRE(~0);542 break;543 case PIN_CONFIG_BIAS_DISABLE:544 case PIN_CONFIG_BIAS_PULL_UP:545 case PIN_CONFIG_BIAS_PULL_DOWN:546 s32_pin_set_pull(param, mask, config);547 break;548 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:549 *config &= ~(S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE);550 *mask |= S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE;551 s32_pin_set_pull(param, mask, config);552 break;553 default:554 return -EOPNOTSUPP;555 }556 557 return 0;558}559 560static int s32_pinconf_mscr_write(struct pinctrl_dev *pctldev,561 unsigned int pin_id,562 unsigned long *configs,563 unsigned int num_configs,564 enum s32_write_type write_type)565{566 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);567 unsigned int config = 0, mask = 0;568 int i, ret;569 570 ret = s32_check_pin(pctldev, pin_id);571 if (ret)572 return ret;573 574 dev_dbg(ipctl->dev, "pinconf set pin %s with %u configs\n",575 pin_get_name(pctldev, pin_id), num_configs);576 577 for (i = 0; i < num_configs; i++) {578 ret = s32_parse_pincfg(configs[i], &mask, &config);579 if (ret)580 return ret;581 }582 583 /* If the MSCR configuration has to be written,584 * the SSS field should not be touched.585 */586 if (write_type == S32_PINCONF_OVERWRITE)587 mask = (unsigned int)~S32_MSCR_SSS_MASK;588 589 if (!config && !mask)590 return 0;591 592 if (write_type == S32_PINCONF_OVERWRITE)593 dev_dbg(ipctl->dev, "set: pin %u cfg 0x%x\n", pin_id, config);594 else595 dev_dbg(ipctl->dev, "update: pin %u cfg 0x%x\n", pin_id,596 config);597 598 return s32_regmap_update(pctldev, pin_id, mask, config);599}600 601static int s32_pinconf_get(struct pinctrl_dev *pctldev,602 unsigned int pin_id,603 unsigned long *config)604{605 return s32_regmap_read(pctldev, pin_id, (unsigned int *)config);606}607 608static int s32_pinconf_set(struct pinctrl_dev *pctldev,609 unsigned int pin_id, unsigned long *configs,610 unsigned int num_configs)611{612 return s32_pinconf_mscr_write(pctldev, pin_id, configs,613 num_configs, S32_PINCONF_UPDATE_ONLY);614}615 616static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int selector,617 unsigned long *configs, unsigned int num_configs)618{619 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);620 const struct s32_pinctrl_soc_info *info = ipctl->info;621 struct s32_pin_group *grp;622 int i, ret;623 624 grp = &info->groups[selector];625 for (i = 0; i < grp->data.npins; i++) {626 ret = s32_pinconf_mscr_write(pctldev, grp->data.pins[i],627 configs, num_configs, S32_PINCONF_OVERWRITE);628 if (ret)629 return ret;630 }631 632 return 0;633}634 635static void s32_pinconf_dbg_show(struct pinctrl_dev *pctldev,636 struct seq_file *s, unsigned int pin_id)637{638 unsigned int config;639 int ret;640 641 ret = s32_regmap_read(pctldev, pin_id, &config);642 if (ret)643 return;644 645 seq_printf(s, "0x%x", config);646}647 648static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,649 struct seq_file *s, unsigned int selector)650{651 struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);652 const struct s32_pinctrl_soc_info *info = ipctl->info;653 struct s32_pin_group *grp;654 unsigned int config;655 const char *name;656 int i, ret;657 658 seq_puts(s, "\n");659 grp = &info->groups[selector];660 for (i = 0; i < grp->data.npins; i++) {661 name = pin_get_name(pctldev, grp->data.pins[i]);662 ret = s32_regmap_read(pctldev, grp->data.pins[i], &config);663 if (ret)664 return;665 seq_printf(s, "%s: 0x%x\n", name, config);666 }667}668 669static const struct pinconf_ops s32_pinconf_ops = {670 .pin_config_get = s32_pinconf_get,671 .pin_config_set = s32_pinconf_set,672 .pin_config_group_set = s32_pconf_group_set,673 .pin_config_dbg_show = s32_pinconf_dbg_show,674 .pin_config_group_dbg_show = s32_pinconf_group_dbg_show,675};676 677#ifdef CONFIG_PM_SLEEP678static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl,679 unsigned int pin)680{681 const struct pin_desc *pd = pin_desc_get(ipctl->pctl, pin);682 683 if (!pd)684 return false;685 686 /*687 * Only restore the pin if it is actually in use by the kernel (or688 * by userspace).689 */690 if (pd->mux_owner || pd->gpio_owner)691 return true;692 693 return false;694}695 696int s32_pinctrl_suspend(struct device *dev)697{698 struct platform_device *pdev = to_platform_device(dev);699 struct s32_pinctrl *ipctl = platform_get_drvdata(pdev);700 const struct pinctrl_pin_desc *pin;701 const struct s32_pinctrl_soc_info *info = ipctl->info;702 struct s32_pinctrl_context *saved_context = &ipctl->saved_context;703 int i;704 int ret;705 unsigned int config;706 707 for (i = 0; i < info->soc_data->npins; i++) {708 pin = &info->soc_data->pins[i];709 710 if (!s32_pinctrl_should_save(ipctl, pin->number))711 continue;712 713 ret = s32_regmap_read(ipctl->pctl, pin->number, &config);714 if (ret)715 return -EINVAL;716 717 saved_context->pads[i] = config;718 }719 720 return 0;721}722 723int s32_pinctrl_resume(struct device *dev)724{725 struct platform_device *pdev = to_platform_device(dev);726 struct s32_pinctrl *ipctl = platform_get_drvdata(pdev);727 const struct s32_pinctrl_soc_info *info = ipctl->info;728 const struct pinctrl_pin_desc *pin;729 struct s32_pinctrl_context *saved_context = &ipctl->saved_context;730 int ret, i;731 732 for (i = 0; i < info->soc_data->npins; i++) {733 pin = &info->soc_data->pins[i];734 735 if (!s32_pinctrl_should_save(ipctl, pin->number))736 continue;737 738 ret = s32_regmap_write(ipctl->pctl, pin->number,739 saved_context->pads[i]);740 if (ret)741 return ret;742 }743 744 return 0;745}746#endif747 748static int s32_pinctrl_parse_groups(struct device_node *np,749 struct s32_pin_group *grp,750 struct s32_pinctrl_soc_info *info)751{752 struct device *dev;753 unsigned int *pins, *sss;754 int i, npins;755 u32 pinmux;756 757 dev = info->dev;758 759 dev_dbg(dev, "group: %pOFn\n", np);760 761 /* Initialise group */762 grp->data.name = np->name;763 764 npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32));765 if (npins < 0) {766 dev_err(dev, "Failed to read 'pinmux' property in node %s.\n",767 grp->data.name);768 return -EINVAL;769 }770 if (!npins) {771 dev_err(dev, "The group %s has no pins.\n", grp->data.name);772 return -EINVAL;773 }774 775 grp->data.npins = npins;776 777 pins = devm_kcalloc(info->dev, npins, sizeof(*pins), GFP_KERNEL);778 sss = devm_kcalloc(info->dev, npins, sizeof(*sss), GFP_KERNEL);779 if (!pins || !sss)780 return -ENOMEM;781 782 i = 0;783 of_property_for_each_u32(np, "pinmux", pinmux) {784 pins[i] = get_pin_no(pinmux);785 sss[i] = get_pin_func(pinmux);786 787 dev_dbg(info->dev, "pin: 0x%x, sss: 0x%x", pins[i], sss[i]);788 i++;789 }790 791 grp->data.pins = pins;792 grp->pin_sss = sss;793 794 return 0;795}796 797static int s32_pinctrl_parse_functions(struct device_node *np,798 struct s32_pinctrl_soc_info *info,799 u32 index)800{801 struct pinfunction *func;802 struct s32_pin_group *grp;803 const char **groups;804 u32 i = 0;805 int ret = 0;806 807 dev_dbg(info->dev, "parse function(%u): %pOFn\n", index, np);808 809 func = &info->functions[index];810 811 /* Initialise function */812 func->name = np->name;813 func->ngroups = of_get_child_count(np);814 if (func->ngroups == 0) {815 dev_err(info->dev, "no groups defined in %pOF\n", np);816 return -EINVAL;817 }818 819 groups = devm_kcalloc(info->dev, func->ngroups,820 sizeof(*func->groups), GFP_KERNEL);821 if (!groups)822 return -ENOMEM;823 824 for_each_child_of_node_scoped(np, child) {825 groups[i] = child->name;826 grp = &info->groups[info->grp_index++];827 ret = s32_pinctrl_parse_groups(child, grp, info);828 if (ret)829 return ret;830 i++;831 }832 833 func->groups = groups;834 835 return 0;836}837 838static int s32_pinctrl_probe_dt(struct platform_device *pdev,839 struct s32_pinctrl *ipctl)840{841 struct s32_pinctrl_soc_info *info = ipctl->info;842 struct device_node *np = pdev->dev.of_node;843 struct resource *res;844 struct regmap *map;845 void __iomem *base;846 unsigned int mem_regions = info->soc_data->mem_regions;847 int ret;848 u32 nfuncs = 0;849 u32 i = 0;850 851 if (!np)852 return -ENODEV;853 854 if (mem_regions == 0 || mem_regions >= 10000) {855 dev_err(&pdev->dev, "mem_regions is invalid: %u\n", mem_regions);856 return -EINVAL;857 }858 859 ipctl->regions = devm_kcalloc(&pdev->dev, mem_regions,860 sizeof(*ipctl->regions), GFP_KERNEL);861 if (!ipctl->regions)862 return -ENOMEM;863 864 for (i = 0; i < mem_regions; i++) {865 base = devm_platform_get_and_ioremap_resource(pdev, i, &res);866 if (IS_ERR(base))867 return PTR_ERR(base);868 869 snprintf(ipctl->regions[i].name,870 sizeof(ipctl->regions[i].name), "map%u", i);871 872 s32_regmap_config.name = ipctl->regions[i].name;873 s32_regmap_config.max_register = resource_size(res) -874 s32_regmap_config.reg_stride;875 876 map = devm_regmap_init_mmio(&pdev->dev, base,877 &s32_regmap_config);878 if (IS_ERR(map)) {879 dev_err(&pdev->dev, "Failed to init regmap[%u]\n", i);880 return PTR_ERR(map);881 }882 883 ipctl->regions[i].map = map;884 ipctl->regions[i].pin_range = &info->soc_data->mem_pin_ranges[i];885 }886 887 nfuncs = of_get_child_count(np);888 if (nfuncs <= 0) {889 dev_err(&pdev->dev, "no functions defined\n");890 return -EINVAL;891 }892 893 info->nfunctions = nfuncs;894 info->functions = devm_kcalloc(&pdev->dev, nfuncs,895 sizeof(*info->functions), GFP_KERNEL);896 if (!info->functions)897 return -ENOMEM;898 899 info->ngroups = 0;900 for_each_child_of_node_scoped(np, child)901 info->ngroups += of_get_child_count(child);902 903 info->groups = devm_kcalloc(&pdev->dev, info->ngroups,904 sizeof(*info->groups), GFP_KERNEL);905 if (!info->groups)906 return -ENOMEM;907 908 i = 0;909 for_each_child_of_node_scoped(np, child) {910 ret = s32_pinctrl_parse_functions(child, info, i++);911 if (ret)912 return ret;913 }914 915 return 0;916}917 918int s32_pinctrl_probe(struct platform_device *pdev,919 const struct s32_pinctrl_soc_data *soc_data)920{921 struct s32_pinctrl *ipctl;922 int ret;923 struct pinctrl_desc *s32_pinctrl_desc;924 struct s32_pinctrl_soc_info *info;925#ifdef CONFIG_PM_SLEEP926 struct s32_pinctrl_context *saved_context;927#endif928 929 if (!soc_data || !soc_data->pins || !soc_data->npins) {930 dev_err(&pdev->dev, "wrong pinctrl info\n");931 return -EINVAL;932 }933 934 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);935 if (!info)936 return -ENOMEM;937 938 info->soc_data = soc_data;939 info->dev = &pdev->dev;940 941 /* Create state holders etc for this driver */942 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);943 if (!ipctl)944 return -ENOMEM;945 946 ipctl->info = info;947 ipctl->dev = info->dev;948 platform_set_drvdata(pdev, ipctl);949 950 INIT_LIST_HEAD(&ipctl->gpio_configs);951 spin_lock_init(&ipctl->gpio_configs_lock);952 953 s32_pinctrl_desc =954 devm_kmalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL);955 if (!s32_pinctrl_desc)956 return -ENOMEM;957 958 s32_pinctrl_desc->name = dev_name(&pdev->dev);959 s32_pinctrl_desc->pins = info->soc_data->pins;960 s32_pinctrl_desc->npins = info->soc_data->npins;961 s32_pinctrl_desc->pctlops = &s32_pctrl_ops;962 s32_pinctrl_desc->pmxops = &s32_pmx_ops;963 s32_pinctrl_desc->confops = &s32_pinconf_ops;964 s32_pinctrl_desc->owner = THIS_MODULE;965 966 ret = s32_pinctrl_probe_dt(pdev, ipctl);967 if (ret) {968 dev_err(&pdev->dev, "fail to probe dt properties\n");969 return ret;970 }971 972 ipctl->pctl = devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc,973 ipctl);974 if (IS_ERR(ipctl->pctl))975 return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl),976 "could not register s32 pinctrl driver\n");977 978#ifdef CONFIG_PM_SLEEP979 saved_context = &ipctl->saved_context;980 saved_context->pads =981 devm_kcalloc(&pdev->dev, info->soc_data->npins,982 sizeof(*saved_context->pads),983 GFP_KERNEL);984 if (!saved_context->pads)985 return -ENOMEM;986#endif987 988 dev_info(&pdev->dev, "initialized s32 pinctrl driver\n");989 990 return 0;991}992