1272 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Driver for the Atmel PIO4 controller4 *5 * Copyright (C) 2015 Atmel,6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>7 */8 9#include <dt-bindings/pinctrl/at91.h>10 11#include <linux/clk.h>12#include <linux/gpio/driver.h>13#include <linux/init.h>14#include <linux/interrupt.h>15#include <linux/io.h>16#include <linux/of.h>17#include <linux/platform_device.h>18#include <linux/seq_file.h>19#include <linux/slab.h>20 21#include <linux/pinctrl/pinconf-generic.h>22#include <linux/pinctrl/pinconf.h>23#include <linux/pinctrl/pinctrl.h>24#include <linux/pinctrl/pinmux.h>25 26#include "core.h"27#include "pinconf.h"28#include "pinctrl-utils.h"29 30/*31 * Warning:32 * In order to not introduce confusion between Atmel PIO groups and pinctrl33 * framework groups, Atmel PIO groups will be called banks, line is kept to34 * designed the pin id into this bank.35 */36 37#define ATMEL_PIO_MSKR 0x000038#define ATMEL_PIO_CFGR 0x000439#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)40#define ATMEL_PIO_DIR_MASK BIT(8)41#define ATMEL_PIO_PUEN_MASK BIT(9)42#define ATMEL_PIO_PDEN_MASK BIT(10)43#define ATMEL_PIO_SR_MASK BIT(11)44#define ATMEL_PIO_IFEN_MASK BIT(12)45#define ATMEL_PIO_IFSCEN_MASK BIT(13)46#define ATMEL_PIO_OPD_MASK BIT(14)47#define ATMEL_PIO_SCHMITT_MASK BIT(15)48#define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)49#define ATMEL_PIO_DRVSTR_OFFSET 1650#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)51#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)52#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)53#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)54#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)55#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)56#define ATMEL_PIO_PDSR 0x000857#define ATMEL_PIO_LOCKSR 0x000C58#define ATMEL_PIO_SODR 0x001059#define ATMEL_PIO_CODR 0x001460#define ATMEL_PIO_ODSR 0x001861#define ATMEL_PIO_IER 0x002062#define ATMEL_PIO_IDR 0x002463#define ATMEL_PIO_IMR 0x002864#define ATMEL_PIO_ISR 0x002C65#define ATMEL_PIO_IOFR 0x003C66 67#define ATMEL_PIO_NPINS_PER_BANK 3268#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)69#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)70#define ATMEL_PIO_BANK_OFFSET 0x4071 72#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)73#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)74#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)75 76/* Custom pinconf parameters */77#define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)78 79/**80 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct81 * @nbanks: number of PIO banks82 * @last_bank_count: number of lines in the last bank (can be less than83 * the rest of the banks).84 * @slew_rate_support: slew rate support85 */86struct atmel_pioctrl_data {87 unsigned int nbanks;88 unsigned int last_bank_count;89 unsigned int slew_rate_support;90};91 92struct atmel_group {93 const char *name;94 u32 pin;95};96 97struct atmel_pin {98 unsigned int pin_id;99 unsigned int mux;100 unsigned int ioset;101 unsigned int bank;102 unsigned int line;103 const char *device;104};105 106/**107 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)108 * @reg_base: base address of the controller.109 * @clk: clock of the controller.110 * @nbanks: number of PIO groups, it can vary depending on the SoC.111 * @pinctrl_dev: pinctrl device registered.112 * @groups: groups table to provide group name and pin in the group to pinctrl.113 * @group_names: group names table to provide all the group/pin names to114 * pinctrl or gpio.115 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line116 * fields are set at probe time. Other ones are set when parsing dt117 * pinctrl.118 * @npins: number of pins.119 * @gpio_chip: gpio chip registered.120 * @irq_domain: irq domain for the gpio controller.121 * @irqs: table containing the hw irq number of the bank. The index of the122 * table is the bank id.123 * @pm_wakeup_sources: bitmap of wakeup sources (lines)124 * @pm_suspend_backup: backup/restore register values on suspend/resume125 * @dev: device entry for the Atmel PIO controller.126 * @node: node of the Atmel PIO controller.127 * @slew_rate_support: slew rate support128 */129struct atmel_pioctrl {130 void __iomem *reg_base;131 struct clk *clk;132 unsigned int nbanks;133 struct pinctrl_dev *pinctrl_dev;134 struct atmel_group *groups;135 const char * const *group_names;136 struct atmel_pin **pins;137 unsigned int npins;138 struct gpio_chip *gpio_chip;139 struct irq_domain *irq_domain;140 int *irqs;141 unsigned int *pm_wakeup_sources;142 struct {143 u32 imr;144 u32 odsr;145 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];146 } *pm_suspend_backup;147 struct device *dev;148 struct device_node *node;149 unsigned int slew_rate_support;150};151 152static const char * const atmel_functions[] = {153 "GPIO", "A", "B", "C", "D", "E", "F", "G"154};155 156static const struct pinconf_generic_params atmel_custom_bindings[] = {157 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},158};159 160/* --- GPIO --- */161static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,162 unsigned int bank, unsigned int reg)163{164 return readl_relaxed(atmel_pioctrl->reg_base165 + ATMEL_PIO_BANK_OFFSET * bank + reg);166}167 168static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,169 unsigned int bank, unsigned int reg,170 unsigned int val)171{172 writel_relaxed(val, atmel_pioctrl->reg_base173 + ATMEL_PIO_BANK_OFFSET * bank + reg);174}175 176static void atmel_gpio_irq_ack(struct irq_data *d)177{178 /*179 * Nothing to do, interrupt is cleared when reading the status180 * register.181 */182}183 184static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type)185{186 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);187 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];188 unsigned int reg;189 190 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,191 BIT(pin->line));192 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);193 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);194 195 switch (type) {196 case IRQ_TYPE_EDGE_RISING:197 irq_set_handler_locked(d, handle_edge_irq);198 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;199 break;200 case IRQ_TYPE_EDGE_FALLING:201 irq_set_handler_locked(d, handle_edge_irq);202 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;203 break;204 case IRQ_TYPE_EDGE_BOTH:205 irq_set_handler_locked(d, handle_edge_irq);206 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;207 break;208 case IRQ_TYPE_LEVEL_LOW:209 irq_set_handler_locked(d, handle_level_irq);210 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;211 break;212 case IRQ_TYPE_LEVEL_HIGH:213 irq_set_handler_locked(d, handle_level_irq);214 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;215 break;216 case IRQ_TYPE_NONE:217 default:218 return -EINVAL;219 }220 221 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);222 223 return 0;224}225 226static void atmel_gpio_irq_mask(struct irq_data *d)227{228 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);229 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];230 231 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,232 BIT(pin->line));233}234 235static void atmel_gpio_irq_unmask(struct irq_data *d)236{237 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);238 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];239 240 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,241 BIT(pin->line));242}243 244static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)245{246 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);247 int bank = ATMEL_PIO_BANK(d->hwirq);248 int line = ATMEL_PIO_LINE(d->hwirq);249 250 /* The gpio controller has one interrupt line per bank. */251 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);252 253 if (on)254 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);255 else256 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));257 258 return 0;259}260 261static struct irq_chip atmel_gpio_irq_chip = {262 .name = "GPIO",263 .irq_ack = atmel_gpio_irq_ack,264 .irq_mask = atmel_gpio_irq_mask,265 .irq_unmask = atmel_gpio_irq_unmask,266 .irq_set_type = atmel_gpio_irq_set_type,267 .irq_set_wake = pm_sleep_ptr(atmel_gpio_irq_set_wake),268};269 270static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)271{272 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);273 274 return irq_find_mapping(atmel_pioctrl->irq_domain, offset);275}276 277static void atmel_gpio_irq_handler(struct irq_desc *desc)278{279 unsigned int irq = irq_desc_get_irq(desc);280 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);281 struct irq_chip *chip = irq_desc_get_chip(desc);282 unsigned long isr;283 int n, bank = -1;284 285 /* Find from which bank is the irq received. */286 for (n = 0; n < atmel_pioctrl->nbanks; n++) {287 if (atmel_pioctrl->irqs[n] == irq) {288 bank = n;289 break;290 }291 }292 293 if (bank < 0) {294 dev_err(atmel_pioctrl->dev,295 "no bank associated to irq %u\n", irq);296 return;297 }298 299 chained_irq_enter(chip, desc);300 301 for (;;) {302 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,303 ATMEL_PIO_ISR);304 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,305 ATMEL_PIO_IMR);306 if (!isr)307 break;308 309 for_each_set_bit(n, &isr, BITS_PER_LONG)310 generic_handle_irq(atmel_gpio_to_irq(311 atmel_pioctrl->gpio_chip,312 bank * ATMEL_PIO_NPINS_PER_BANK + n));313 }314 315 chained_irq_exit(chip, desc);316}317 318static int atmel_gpio_direction_input(struct gpio_chip *chip,319 unsigned int offset)320{321 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);322 struct atmel_pin *pin = atmel_pioctrl->pins[offset];323 unsigned int reg;324 325 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,326 BIT(pin->line));327 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);328 reg &= ~ATMEL_PIO_DIR_MASK;329 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);330 331 return 0;332}333 334static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset)335{336 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);337 struct atmel_pin *pin = atmel_pioctrl->pins[offset];338 unsigned int reg;339 340 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);341 342 return !!(reg & BIT(pin->line));343}344 345static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,346 unsigned long *bits)347{348 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);349 unsigned int bank;350 351 bitmap_zero(bits, atmel_pioctrl->npins);352 353 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {354 unsigned int word = bank;355 unsigned int offset = 0;356 unsigned int reg;357 358#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG359 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);360 offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;361#endif362 if (!mask[word])363 continue;364 365 reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);366 bits[word] |= mask[word] & (reg << offset);367 }368 369 return 0;370}371 372static int atmel_gpio_direction_output(struct gpio_chip *chip,373 unsigned int offset,374 int value)375{376 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);377 struct atmel_pin *pin = atmel_pioctrl->pins[offset];378 unsigned int reg;379 380 atmel_gpio_write(atmel_pioctrl, pin->bank,381 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,382 BIT(pin->line));383 384 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,385 BIT(pin->line));386 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);387 reg |= ATMEL_PIO_DIR_MASK;388 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);389 390 return 0;391}392 393static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)394{395 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);396 struct atmel_pin *pin = atmel_pioctrl->pins[offset];397 398 atmel_gpio_write(atmel_pioctrl, pin->bank,399 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,400 BIT(pin->line));401}402 403static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,404 unsigned long *bits)405{406 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);407 unsigned int bank;408 409 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {410 unsigned int bitmask;411 unsigned int word = bank;412 413/*414 * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over415 * two 32bit words to handle the whole bitmask416 */417#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG418 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);419#endif420 if (!mask[word])421 continue;422 423 bitmask = mask[word] & bits[word];424 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);425 426 bitmask = mask[word] & ~bits[word];427 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);428 429#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG430 mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;431 bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;432#endif433 }434}435 436static struct gpio_chip atmel_gpio_chip = {437 .direction_input = atmel_gpio_direction_input,438 .get = atmel_gpio_get,439 .get_multiple = atmel_gpio_get_multiple,440 .direction_output = atmel_gpio_direction_output,441 .set = atmel_gpio_set,442 .set_multiple = atmel_gpio_set_multiple,443 .to_irq = atmel_gpio_to_irq,444 .base = 0,445};446 447/* --- PINCTRL --- */448static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,449 unsigned int pin_id)450{451 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);452 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;453 unsigned int line = atmel_pioctrl->pins[pin_id]->line;454 void __iomem *addr = atmel_pioctrl->reg_base455 + bank * ATMEL_PIO_BANK_OFFSET;456 457 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);458 /* Have to set MSKR first, to access the right pin CFGR. */459 wmb();460 461 return readl_relaxed(addr + ATMEL_PIO_CFGR);462}463 464static void atmel_pin_config_write(struct pinctrl_dev *pctldev,465 unsigned int pin_id, u32 conf)466{467 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);468 unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;469 unsigned int line = atmel_pioctrl->pins[pin_id]->line;470 void __iomem *addr = atmel_pioctrl->reg_base471 + bank * ATMEL_PIO_BANK_OFFSET;472 473 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);474 /* Have to set MSKR first, to access the right pin CFGR. */475 wmb();476 writel_relaxed(conf, addr + ATMEL_PIO_CFGR);477}478 479static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)480{481 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);482 483 return atmel_pioctrl->npins;484}485 486static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,487 unsigned int selector)488{489 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);490 491 return atmel_pioctrl->groups[selector].name;492}493 494static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,495 unsigned int selector,496 const unsigned int **pins,497 unsigned int *num_pins)498{499 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);500 501 *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin;502 *num_pins = 1;503 504 return 0;505}506 507static struct atmel_group *508atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin)509{510 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);511 int i;512 513 for (i = 0; i < atmel_pioctrl->npins; i++) {514 struct atmel_group *grp = atmel_pioctrl->groups + i;515 516 if (grp->pin == pin)517 return grp;518 }519 520 return NULL;521}522 523static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,524 struct device_node *np,525 u32 pinfunc, const char **grp_name,526 const char **func_name)527{528 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);529 unsigned int pin_id, func_id;530 struct atmel_group *grp;531 532 pin_id = ATMEL_GET_PIN_NO(pinfunc);533 func_id = ATMEL_GET_PIN_FUNC(pinfunc);534 535 if (func_id >= ARRAY_SIZE(atmel_functions))536 return -EINVAL;537 538 *func_name = atmel_functions[func_id];539 540 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);541 if (!grp)542 return -EINVAL;543 *grp_name = grp->name;544 545 atmel_pioctrl->pins[pin_id]->mux = func_id;546 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);547 /* Want the device name not the group one. */548 if (np->parent == atmel_pioctrl->node)549 atmel_pioctrl->pins[pin_id]->device = np->name;550 else551 atmel_pioctrl->pins[pin_id]->device = np->parent->name;552 553 return 0;554}555 556static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,557 struct device_node *np,558 struct pinctrl_map **map,559 unsigned int *reserved_maps,560 unsigned int *num_maps)561{562 unsigned int num_pins, num_configs, reserve;563 unsigned long *configs;564 struct property *pins;565 u32 pinfunc;566 int ret, i;567 568 pins = of_find_property(np, "pinmux", NULL);569 if (!pins)570 return -EINVAL;571 572 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,573 &num_configs);574 if (ret < 0) {575 dev_err(pctldev->dev, "%pOF: could not parse node property\n",576 np);577 return ret;578 }579 580 num_pins = pins->length / sizeof(u32);581 if (!num_pins) {582 dev_err(pctldev->dev, "no pins found in node %pOF\n", np);583 ret = -EINVAL;584 goto exit;585 }586 587 /*588 * Reserve maps, at least there is a mux map and an optional conf589 * map for each pin.590 */591 reserve = 1;592 if (num_configs)593 reserve++;594 reserve *= num_pins;595 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,596 reserve);597 if (ret < 0)598 goto exit;599 600 for (i = 0; i < num_pins; i++) {601 const char *group, *func;602 603 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);604 if (ret)605 goto exit;606 607 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,608 &func);609 if (ret)610 goto exit;611 612 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,613 group, func);614 615 if (num_configs) {616 ret = pinctrl_utils_add_map_configs(pctldev, map,617 reserved_maps, num_maps, group,618 configs, num_configs,619 PIN_MAP_TYPE_CONFIGS_GROUP);620 if (ret < 0)621 goto exit;622 }623 }624 625exit:626 kfree(configs);627 return ret;628}629 630static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,631 struct device_node *np_config,632 struct pinctrl_map **map,633 unsigned int *num_maps)634{635 unsigned int reserved_maps;636 int ret;637 638 *map = NULL;639 *num_maps = 0;640 reserved_maps = 0;641 642 /*643 * If all the pins of a device have the same configuration (or no one),644 * it is useless to add a subnode, so directly parse node referenced by645 * phandle.646 */647 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,648 &reserved_maps, num_maps);649 if (ret) {650 for_each_child_of_node_scoped(np_config, np) {651 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,652 &reserved_maps, num_maps);653 if (ret < 0)654 break;655 }656 }657 658 if (ret < 0) {659 pinctrl_utils_free_map(pctldev, *map, *num_maps);660 dev_err(pctldev->dev, "can't create maps for node %pOF\n",661 np_config);662 }663 664 return ret;665}666 667static const struct pinctrl_ops atmel_pctlops = {668 .get_groups_count = atmel_pctl_get_groups_count,669 .get_group_name = atmel_pctl_get_group_name,670 .get_group_pins = atmel_pctl_get_group_pins,671 .dt_node_to_map = atmel_pctl_dt_node_to_map,672 .dt_free_map = pinctrl_utils_free_map,673};674 675static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)676{677 return ARRAY_SIZE(atmel_functions);678}679 680static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,681 unsigned int selector)682{683 return atmel_functions[selector];684}685 686static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,687 unsigned int selector,688 const char * const **groups,689 unsigned * const num_groups)690{691 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);692 693 *groups = atmel_pioctrl->group_names;694 *num_groups = atmel_pioctrl->npins;695 696 return 0;697}698 699static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,700 unsigned int function,701 unsigned int group)702{703 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);704 unsigned int pin;705 u32 conf;706 707 dev_dbg(pctldev->dev, "enable function %s group %s\n",708 atmel_functions[function], atmel_pioctrl->groups[group].name);709 710 pin = atmel_pioctrl->groups[group].pin;711 conf = atmel_pin_config_read(pctldev, pin);712 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);713 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);714 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);715 atmel_pin_config_write(pctldev, pin, conf);716 717 return 0;718}719 720static const struct pinmux_ops atmel_pmxops = {721 .get_functions_count = atmel_pmx_get_functions_count,722 .get_function_name = atmel_pmx_get_function_name,723 .get_function_groups = atmel_pmx_get_function_groups,724 .set_mux = atmel_pmx_set_mux,725};726 727static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,728 unsigned int group,729 unsigned long *config)730{731 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);732 unsigned int param = pinconf_to_config_param(*config), arg = 0;733 struct atmel_group *grp = atmel_pioctrl->groups + group;734 unsigned int pin_id = grp->pin;735 u32 res;736 737 res = atmel_pin_config_read(pctldev, pin_id);738 739 switch (param) {740 case PIN_CONFIG_BIAS_PULL_UP:741 if (!(res & ATMEL_PIO_PUEN_MASK))742 return -EINVAL;743 arg = 1;744 break;745 case PIN_CONFIG_BIAS_PULL_DOWN:746 if ((res & ATMEL_PIO_PUEN_MASK) ||747 (!(res & ATMEL_PIO_PDEN_MASK)))748 return -EINVAL;749 arg = 1;750 break;751 case PIN_CONFIG_BIAS_DISABLE:752 if ((res & ATMEL_PIO_PUEN_MASK) ||753 ((res & ATMEL_PIO_PDEN_MASK)))754 return -EINVAL;755 arg = 1;756 break;757 case PIN_CONFIG_DRIVE_OPEN_DRAIN:758 if (!(res & ATMEL_PIO_OPD_MASK))759 return -EINVAL;760 arg = 1;761 break;762 case PIN_CONFIG_DRIVE_PUSH_PULL:763 if (res & ATMEL_PIO_OPD_MASK)764 return -EINVAL;765 arg = 1;766 break;767 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:768 if (!(res & ATMEL_PIO_SCHMITT_MASK))769 return -EINVAL;770 arg = 1;771 break;772 case PIN_CONFIG_SLEW_RATE:773 if (!atmel_pioctrl->slew_rate_support)774 return -EOPNOTSUPP;775 if (!(res & ATMEL_PIO_SR_MASK))776 return -EINVAL;777 arg = 1;778 break;779 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:780 if (!(res & ATMEL_PIO_DRVSTR_MASK))781 return -EINVAL;782 arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;783 break;784 case PIN_CONFIG_PERSIST_STATE:785 return -ENOTSUPP;786 default:787 return -ENOTSUPP;788 }789 790 *config = pinconf_to_config_packed(param, arg);791 return 0;792}793 794static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,795 unsigned int group,796 unsigned long *configs,797 unsigned int num_configs)798{799 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);800 struct atmel_group *grp = atmel_pioctrl->groups + group;801 unsigned int bank, pin, pin_id = grp->pin;802 u32 mask, conf = 0;803 int i;804 805 conf = atmel_pin_config_read(pctldev, pin_id);806 807 /* Keep slew rate enabled by default. */808 if (atmel_pioctrl->slew_rate_support)809 conf |= ATMEL_PIO_SR_MASK;810 811 for (i = 0; i < num_configs; i++) {812 unsigned int param = pinconf_to_config_param(configs[i]);813 unsigned int arg = pinconf_to_config_argument(configs[i]);814 815 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",816 __func__, pin_id, configs[i]);817 818 switch (param) {819 case PIN_CONFIG_BIAS_DISABLE:820 conf &= (~ATMEL_PIO_PUEN_MASK);821 conf &= (~ATMEL_PIO_PDEN_MASK);822 break;823 case PIN_CONFIG_BIAS_PULL_UP:824 conf |= ATMEL_PIO_PUEN_MASK;825 conf &= (~ATMEL_PIO_PDEN_MASK);826 break;827 case PIN_CONFIG_BIAS_PULL_DOWN:828 conf |= ATMEL_PIO_PDEN_MASK;829 conf &= (~ATMEL_PIO_PUEN_MASK);830 break;831 case PIN_CONFIG_DRIVE_OPEN_DRAIN:832 conf |= ATMEL_PIO_OPD_MASK;833 break;834 case PIN_CONFIG_DRIVE_PUSH_PULL:835 conf &= ~ATMEL_PIO_OPD_MASK;836 break;837 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:838 if (arg == 0)839 conf |= ATMEL_PIO_SCHMITT_MASK;840 else841 conf &= (~ATMEL_PIO_SCHMITT_MASK);842 break;843 case PIN_CONFIG_INPUT_DEBOUNCE:844 if (arg == 0) {845 conf &= (~ATMEL_PIO_IFEN_MASK);846 conf &= (~ATMEL_PIO_IFSCEN_MASK);847 } else {848 /*849 * We don't care about the debounce value for several reasons:850 * - can't have different debounce periods inside a same group,851 * - the register to configure this period is a secure register.852 * The debouncing filter can filter a pulse with a duration of less853 * than 1/2 slow clock period.854 */855 conf |= ATMEL_PIO_IFEN_MASK;856 conf |= ATMEL_PIO_IFSCEN_MASK;857 }858 break;859 case PIN_CONFIG_OUTPUT:860 conf |= ATMEL_PIO_DIR_MASK;861 bank = ATMEL_PIO_BANK(pin_id);862 pin = ATMEL_PIO_LINE(pin_id);863 mask = 1 << pin;864 865 if (arg == 0) {866 writel_relaxed(mask, atmel_pioctrl->reg_base +867 bank * ATMEL_PIO_BANK_OFFSET +868 ATMEL_PIO_CODR);869 } else {870 writel_relaxed(mask, atmel_pioctrl->reg_base +871 bank * ATMEL_PIO_BANK_OFFSET +872 ATMEL_PIO_SODR);873 }874 break;875 case PIN_CONFIG_SLEW_RATE:876 if (!atmel_pioctrl->slew_rate_support)877 break;878 /* And remove it if explicitly requested. */879 if (arg == 0)880 conf &= ~ATMEL_PIO_SR_MASK;881 break;882 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:883 switch (arg) {884 case ATMEL_PIO_DRVSTR_LO:885 case ATMEL_PIO_DRVSTR_ME:886 case ATMEL_PIO_DRVSTR_HI:887 conf &= (~ATMEL_PIO_DRVSTR_MASK);888 conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;889 break;890 default:891 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");892 }893 break;894 case PIN_CONFIG_PERSIST_STATE:895 return -ENOTSUPP;896 default:897 dev_warn(pctldev->dev,898 "unsupported configuration parameter: %u\n",899 param);900 continue;901 }902 }903 904 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);905 atmel_pin_config_write(pctldev, pin_id, conf);906 907 return 0;908}909 910static int atmel_conf_pin_config_set(struct pinctrl_dev *pctldev,911 unsigned pin,912 unsigned long *configs,913 unsigned num_configs)914{915 struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin);916 917 return atmel_conf_pin_config_group_set(pctldev, grp->pin, configs, num_configs);918}919 920static int atmel_conf_pin_config_get(struct pinctrl_dev *pctldev,921 unsigned pin,922 unsigned long *configs)923{924 struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin);925 926 return atmel_conf_pin_config_group_get(pctldev, grp->pin, configs);927}928 929static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,930 struct seq_file *s,931 unsigned int pin_id)932{933 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);934 u32 conf;935 936 if (!atmel_pioctrl->pins[pin_id]->device)937 return;938 939 seq_printf(s, " (%s, ioset %u) ",940 atmel_pioctrl->pins[pin_id]->device,941 atmel_pioctrl->pins[pin_id]->ioset);942 943 conf = atmel_pin_config_read(pctldev, pin_id);944 if (conf & ATMEL_PIO_PUEN_MASK)945 seq_printf(s, "%s ", "pull-up");946 if (conf & ATMEL_PIO_PDEN_MASK)947 seq_printf(s, "%s ", "pull-down");948 if (conf & ATMEL_PIO_IFEN_MASK)949 seq_printf(s, "%s ", "debounce");950 if (conf & ATMEL_PIO_OPD_MASK)951 seq_printf(s, "%s ", "open-drain");952 else953 seq_printf(s, "%s ", "push-pull");954 if (conf & ATMEL_PIO_SCHMITT_MASK)955 seq_printf(s, "%s ", "schmitt");956 if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))957 seq_printf(s, "%s ", "slew-rate");958 if (conf & ATMEL_PIO_DRVSTR_MASK) {959 switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {960 case ATMEL_PIO_DRVSTR_ME:961 seq_printf(s, "%s ", "medium-drive");962 break;963 case ATMEL_PIO_DRVSTR_HI:964 seq_printf(s, "%s ", "high-drive");965 break;966 /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */967 default:968 seq_printf(s, "%s ", "low-drive");969 }970 }971}972 973static const struct pinconf_ops atmel_confops = {974 .pin_config_group_get = atmel_conf_pin_config_group_get,975 .pin_config_group_set = atmel_conf_pin_config_group_set,976 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,977 .pin_config_set = atmel_conf_pin_config_set,978 .pin_config_get = atmel_conf_pin_config_get,979};980 981static struct pinctrl_desc atmel_pinctrl_desc = {982 .name = "atmel_pinctrl",983 .confops = &atmel_confops,984 .pctlops = &atmel_pctlops,985 .pmxops = &atmel_pmxops,986};987 988static int __maybe_unused atmel_pctrl_suspend(struct device *dev)989{990 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);991 int i, j;992 993 /*994 * For each bank, save IMR to restore it later and disable all GPIO995 * interrupts excepting the ones marked as wakeup sources.996 */997 for (i = 0; i < atmel_pioctrl->nbanks; i++) {998 atmel_pioctrl->pm_suspend_backup[i].imr =999 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);1000 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,1001 ~atmel_pioctrl->pm_wakeup_sources[i]);1002 atmel_pioctrl->pm_suspend_backup[i].odsr =1003 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);1004 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {1005 atmel_gpio_write(atmel_pioctrl, i,1006 ATMEL_PIO_MSKR, BIT(j));1007 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =1008 atmel_gpio_read(atmel_pioctrl, i,1009 ATMEL_PIO_CFGR);1010 }1011 }1012 1013 return 0;1014}1015 1016static int __maybe_unused atmel_pctrl_resume(struct device *dev)1017{1018 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);1019 int i, j;1020 1021 for (i = 0; i < atmel_pioctrl->nbanks; i++) {1022 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,1023 atmel_pioctrl->pm_suspend_backup[i].imr);1024 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,1025 atmel_pioctrl->pm_suspend_backup[i].odsr);1026 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {1027 atmel_gpio_write(atmel_pioctrl, i,1028 ATMEL_PIO_MSKR, BIT(j));1029 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,1030 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);1031 }1032 }1033 1034 return 0;1035}1036 1037static const struct dev_pm_ops atmel_pctrl_pm_ops = {1038 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)1039};1040 1041/*1042 * The number of banks can be different from a SoC to another one.1043 * We can have up to 16 banks.1044 */1045static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {1046 .nbanks = 4,1047 .last_bank_count = ATMEL_PIO_NPINS_PER_BANK,1048};1049 1050static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {1051 .nbanks = 5,1052 .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */1053 .slew_rate_support = 1,1054};1055 1056static const struct of_device_id atmel_pctrl_of_match[] = {1057 {1058 .compatible = "atmel,sama5d2-pinctrl",1059 .data = &atmel_sama5d2_pioctrl_data,1060 }, {1061 .compatible = "microchip,sama7g5-pinctrl",1062 .data = µchip_sama7g5_pioctrl_data,1063 }, {1064 /* sentinel */1065 }1066};1067 1068/*1069 * This lock class allows to tell lockdep that parent IRQ and children IRQ do1070 * not share the same class so it does not raise false positive1071 */1072static struct lock_class_key atmel_lock_key;1073static struct lock_class_key atmel_request_key;1074 1075static int atmel_pinctrl_probe(struct platform_device *pdev)1076{1077 struct device *dev = &pdev->dev;1078 struct pinctrl_pin_desc *pin_desc;1079 const char **group_names;1080 int i, ret;1081 struct atmel_pioctrl *atmel_pioctrl;1082 const struct atmel_pioctrl_data *atmel_pioctrl_data;1083 1084 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);1085 if (!atmel_pioctrl)1086 return -ENOMEM;1087 atmel_pioctrl->dev = dev;1088 atmel_pioctrl->node = dev->of_node;1089 platform_set_drvdata(pdev, atmel_pioctrl);1090 1091 atmel_pioctrl_data = device_get_match_data(dev);1092 if (!atmel_pioctrl_data)1093 return dev_err_probe(dev, -ENODEV, "Invalid device data\n");1094 1095 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;1096 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;1097 /* if last bank has limited number of pins, adjust accordingly */1098 if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {1099 atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;1100 atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;1101 }1102 atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;1103 1104 atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);1105 if (IS_ERR(atmel_pioctrl->reg_base))1106 return PTR_ERR(atmel_pioctrl->reg_base);1107 1108 atmel_pioctrl->clk = devm_clk_get_enabled(dev, NULL);1109 if (IS_ERR(atmel_pioctrl->clk))1110 return dev_err_probe(dev, PTR_ERR(atmel_pioctrl->clk), "failed to get clock\n");1111 1112 atmel_pioctrl->pins = devm_kcalloc(dev,1113 atmel_pioctrl->npins,1114 sizeof(*atmel_pioctrl->pins),1115 GFP_KERNEL);1116 if (!atmel_pioctrl->pins)1117 return -ENOMEM;1118 1119 pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),1120 GFP_KERNEL);1121 if (!pin_desc)1122 return -ENOMEM;1123 atmel_pinctrl_desc.pins = pin_desc;1124 atmel_pinctrl_desc.npins = atmel_pioctrl->npins;1125 atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);1126 atmel_pinctrl_desc.custom_params = atmel_custom_bindings;1127 1128 /* One pin is one group since a pin can achieve all functions. */1129 group_names = devm_kcalloc(dev,1130 atmel_pioctrl->npins, sizeof(*group_names),1131 GFP_KERNEL);1132 if (!group_names)1133 return -ENOMEM;1134 atmel_pioctrl->group_names = group_names;1135 1136 atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,1137 atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),1138 GFP_KERNEL);1139 if (!atmel_pioctrl->groups)1140 return -ENOMEM;1141 for (i = 0 ; i < atmel_pioctrl->npins; i++) {1142 struct atmel_group *group = atmel_pioctrl->groups + i;1143 unsigned int bank = ATMEL_PIO_BANK(i);1144 unsigned int line = ATMEL_PIO_LINE(i);1145 1146 atmel_pioctrl->pins[i] = devm_kzalloc(dev,1147 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);1148 if (!atmel_pioctrl->pins[i])1149 return -ENOMEM;1150 1151 atmel_pioctrl->pins[i]->pin_id = i;1152 atmel_pioctrl->pins[i]->bank = bank;1153 atmel_pioctrl->pins[i]->line = line;1154 1155 pin_desc[i].number = i;1156 /* Pin naming convention: P(bank_name)(bank_pin_number). */1157 pin_desc[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "P%c%u",1158 bank + 'A', line);1159 if (!pin_desc[i].name)1160 return -ENOMEM;1161 1162 group->name = group_names[i] = pin_desc[i].name;1163 group->pin = pin_desc[i].number;1164 1165 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);1166 }1167 1168 atmel_pioctrl->gpio_chip = &atmel_gpio_chip;1169 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;1170 atmel_pioctrl->gpio_chip->label = dev_name(dev);1171 atmel_pioctrl->gpio_chip->parent = dev;1172 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;1173 atmel_pioctrl->gpio_chip->set_config = gpiochip_generic_config;1174 1175 atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,1176 atmel_pioctrl->nbanks,1177 sizeof(*atmel_pioctrl->pm_wakeup_sources),1178 GFP_KERNEL);1179 if (!atmel_pioctrl->pm_wakeup_sources)1180 return -ENOMEM;1181 1182 atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,1183 atmel_pioctrl->nbanks,1184 sizeof(*atmel_pioctrl->pm_suspend_backup),1185 GFP_KERNEL);1186 if (!atmel_pioctrl->pm_suspend_backup)1187 return -ENOMEM;1188 1189 atmel_pioctrl->irqs = devm_kcalloc(dev,1190 atmel_pioctrl->nbanks,1191 sizeof(*atmel_pioctrl->irqs),1192 GFP_KERNEL);1193 if (!atmel_pioctrl->irqs)1194 return -ENOMEM;1195 1196 /* There is one controller but each bank has its own irq line. */1197 for (i = 0; i < atmel_pioctrl->nbanks; i++) {1198 ret = platform_get_irq(pdev, i);1199 if (ret < 0) {1200 dev_dbg(dev, "missing irq resource for group %c\n",1201 'A' + i);1202 return ret;1203 }1204 atmel_pioctrl->irqs[i] = ret;1205 irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl);1206 dev_dbg(dev, "bank %i: irq=%d\n", i, ret);1207 }1208 1209 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,1210 atmel_pioctrl->gpio_chip->ngpio,1211 &irq_domain_simple_ops, NULL);1212 if (!atmel_pioctrl->irq_domain)1213 return dev_err_probe(dev, -ENODEV, "can't add the irq domain\n");1214 1215 for (i = 0; i < atmel_pioctrl->npins; i++) {1216 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);1217 1218 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,1219 handle_simple_irq);1220 irq_set_chip_data(irq, atmel_pioctrl);1221 irq_set_lockdep_class(irq, &atmel_lock_key, &atmel_request_key);1222 dev_dbg(dev,1223 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",1224 i, irq);1225 }1226 1227 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,1228 &atmel_pinctrl_desc,1229 atmel_pioctrl);1230 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {1231 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);1232 dev_err(dev, "pinctrl registration failed\n");1233 goto irq_domain_remove_error;1234 }1235 1236 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);1237 if (ret) {1238 dev_err(dev, "failed to add gpiochip\n");1239 goto irq_domain_remove_error;1240 }1241 1242 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),1243 0, 0, atmel_pioctrl->gpio_chip->ngpio);1244 if (ret) {1245 dev_err(dev, "failed to add gpio pin range\n");1246 goto gpiochip_add_pin_range_error;1247 }1248 1249 dev_info(&pdev->dev, "atmel pinctrl initialized\n");1250 1251 return 0;1252 1253gpiochip_add_pin_range_error:1254 gpiochip_remove(atmel_pioctrl->gpio_chip);1255 1256irq_domain_remove_error:1257 irq_domain_remove(atmel_pioctrl->irq_domain);1258 1259 return ret;1260}1261 1262static struct platform_driver atmel_pinctrl_driver = {1263 .driver = {1264 .name = "pinctrl-at91-pio4",1265 .of_match_table = atmel_pctrl_of_match,1266 .pm = &atmel_pctrl_pm_ops,1267 .suppress_bind_attrs = true,1268 },1269 .probe = atmel_pinctrl_probe,1270};1271builtin_platform_driver(atmel_pinctrl_driver);1272