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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support4 *5 * Copyright (C) 2022 9elements GmbH6 * Authors: Patrick Rudolph <patrick.rudolph@9elements.com>7 * Naresh Solanki <Naresh.Solanki@9elements.com>8 */9 10#include <linux/acpi.h>11#include <linux/bitmap.h>12#include <linux/cleanup.h>13#include <linux/dmi.h>14#include <linux/gpio/driver.h>15#include <linux/gpio/consumer.h>16#include <linux/i2c.h>17#include <linux/init.h>18#include <linux/interrupt.h>19#include <linux/mod_devicetable.h>20#include <linux/module.h>21#include <linux/property.h>22#include <linux/regmap.h>23#include <linux/regulator/consumer.h>24#include <linux/seq_file.h>25 26#include <linux/pinctrl/consumer.h>27#include <linux/pinctrl/pinconf.h>28#include <linux/pinctrl/pinconf-generic.h>29#include <linux/pinctrl/pinctrl.h>30#include <linux/pinctrl/pinmux.h>31 32/* Fast access registers */33#define CY8C95X0_INPUT 0x0034#define CY8C95X0_OUTPUT 0x0835#define CY8C95X0_INTSTATUS 0x1036 37#define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x))38#define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x))39#define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x))40 41/* Port Select configures the port */42#define CY8C95X0_PORTSEL 0x1843/* Port settings, write PORTSEL first */44#define CY8C95X0_INTMASK 0x1945#define CY8C95X0_PWMSEL 0x1A46#define CY8C95X0_INVERT 0x1B47#define CY8C95X0_DIRECTION 0x1C48/* Drive mode register change state on writing '1' */49#define CY8C95X0_DRV_PU 0x1D50#define CY8C95X0_DRV_PD 0x1E51#define CY8C95X0_DRV_ODH 0x1F52#define CY8C95X0_DRV_ODL 0x2053#define CY8C95X0_DRV_PP_FAST 0x2154#define CY8C95X0_DRV_PP_SLOW 0x2255#define CY8C95X0_DRV_HIZ 0x2356#define CY8C95X0_DEVID 0x2E57#define CY8C95X0_WATCHDOG 0x2F58#define CY8C95X0_COMMAND 0x3059 60#define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))61 62#define MAX_BANK 863#define BANK_SZ 864#define MAX_LINE (MAX_BANK * BANK_SZ)65#define MUXED_STRIDE 1666#define CY8C95X0_GPIO_MASK GENMASK(7, 0)67#define CY8C95X0_VIRTUAL 0x4068#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \69 (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE)70 71static const struct i2c_device_id cy8c95x0_id[] = {72 { "cy8c9520", 20, },73 { "cy8c9540", 40, },74 { "cy8c9560", 60, },75 { }76};77MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);78 79#define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))80 81static const struct of_device_id cy8c95x0_dt_ids[] = {82 { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },83 { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },84 { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },85 { }86};87MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);88 89static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };90 91static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {92 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },93 { }94};95 96static int cy8c95x0_acpi_get_irq(struct device *dev)97{98 int ret;99 100 ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios);101 if (ret)102 dev_warn(dev, "can't add GPIO ACPI mapping\n");103 104 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0);105 if (ret < 0)106 return ret;107 108 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);109 return ret;110}111 112static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {113 {114 /*115 * On Intel Galileo Gen 1 board the IRQ pin is provided116 * as an absolute number instead of being relative.117 * Since first controller (gpio-sch.c) and second118 * (gpio-dwapb.c) are at the fixed bases, we may safely119 * refer to the number in the global space to get an IRQ120 * out of it.121 */122 .matches = {123 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),124 },125 },126 {}127};128 129/**130 * struct cy8c95x0_pinctrl - driver data131 * @regmap: Device's regmap. Only direct access registers.132 * @irq_lock: IRQ bus lock133 * @i2c_lock: Mutex to hold while using the regmap134 * @irq_mask: I/O bits affected by interrupts135 * @irq_trig_raise: I/O bits affected by raising voltage level136 * @irq_trig_fall: I/O bits affected by falling voltage level137 * @irq_trig_low: I/O bits affected by a low voltage level138 * @irq_trig_high: I/O bits affected by a high voltage level139 * @push_pull: I/O bits configured as push pull driver140 * @shiftmask: Mask used to compensate for Gport2 width141 * @nport: Number of Gports in this chip142 * @gpio_chip: gpiolib chip143 * @driver_data: private driver data144 * @regulator: Pointer to the regulator for the IC145 * @dev: struct device146 * @pctldev: pin controller device147 * @pinctrl_desc: pin controller description148 * @name: Chip controller name149 * @tpin: Total number of pins150 * @gpio_reset: GPIO line handler that can reset the IC151 */152struct cy8c95x0_pinctrl {153 struct regmap *regmap;154 struct mutex irq_lock;155 struct mutex i2c_lock;156 DECLARE_BITMAP(irq_mask, MAX_LINE);157 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);158 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);159 DECLARE_BITMAP(irq_trig_low, MAX_LINE);160 DECLARE_BITMAP(irq_trig_high, MAX_LINE);161 DECLARE_BITMAP(push_pull, MAX_LINE);162 DECLARE_BITMAP(shiftmask, MAX_LINE);163 int nport;164 struct gpio_chip gpio_chip;165 unsigned long driver_data;166 struct regulator *regulator;167 struct device *dev;168 struct pinctrl_dev *pctldev;169 struct pinctrl_desc pinctrl_desc;170 char name[32];171 unsigned int tpin;172 struct gpio_desc *gpio_reset;173};174 175static const struct pinctrl_pin_desc cy8c9560_pins[] = {176 PINCTRL_PIN(0, "gp00"),177 PINCTRL_PIN(1, "gp01"),178 PINCTRL_PIN(2, "gp02"),179 PINCTRL_PIN(3, "gp03"),180 PINCTRL_PIN(4, "gp04"),181 PINCTRL_PIN(5, "gp05"),182 PINCTRL_PIN(6, "gp06"),183 PINCTRL_PIN(7, "gp07"),184 185 PINCTRL_PIN(8, "gp10"),186 PINCTRL_PIN(9, "gp11"),187 PINCTRL_PIN(10, "gp12"),188 PINCTRL_PIN(11, "gp13"),189 PINCTRL_PIN(12, "gp14"),190 PINCTRL_PIN(13, "gp15"),191 PINCTRL_PIN(14, "gp16"),192 PINCTRL_PIN(15, "gp17"),193 194 PINCTRL_PIN(16, "gp20"),195 PINCTRL_PIN(17, "gp21"),196 PINCTRL_PIN(18, "gp22"),197 PINCTRL_PIN(19, "gp23"),198 199 PINCTRL_PIN(20, "gp30"),200 PINCTRL_PIN(21, "gp31"),201 PINCTRL_PIN(22, "gp32"),202 PINCTRL_PIN(23, "gp33"),203 PINCTRL_PIN(24, "gp34"),204 PINCTRL_PIN(25, "gp35"),205 PINCTRL_PIN(26, "gp36"),206 PINCTRL_PIN(27, "gp37"),207 208 PINCTRL_PIN(28, "gp40"),209 PINCTRL_PIN(29, "gp41"),210 PINCTRL_PIN(30, "gp42"),211 PINCTRL_PIN(31, "gp43"),212 PINCTRL_PIN(32, "gp44"),213 PINCTRL_PIN(33, "gp45"),214 PINCTRL_PIN(34, "gp46"),215 PINCTRL_PIN(35, "gp47"),216 217 PINCTRL_PIN(36, "gp50"),218 PINCTRL_PIN(37, "gp51"),219 PINCTRL_PIN(38, "gp52"),220 PINCTRL_PIN(39, "gp53"),221 PINCTRL_PIN(40, "gp54"),222 PINCTRL_PIN(41, "gp55"),223 PINCTRL_PIN(42, "gp56"),224 PINCTRL_PIN(43, "gp57"),225 226 PINCTRL_PIN(44, "gp60"),227 PINCTRL_PIN(45, "gp61"),228 PINCTRL_PIN(46, "gp62"),229 PINCTRL_PIN(47, "gp63"),230 PINCTRL_PIN(48, "gp64"),231 PINCTRL_PIN(49, "gp65"),232 PINCTRL_PIN(50, "gp66"),233 PINCTRL_PIN(51, "gp67"),234 235 PINCTRL_PIN(52, "gp70"),236 PINCTRL_PIN(53, "gp71"),237 PINCTRL_PIN(54, "gp72"),238 PINCTRL_PIN(55, "gp73"),239 PINCTRL_PIN(56, "gp74"),240 PINCTRL_PIN(57, "gp75"),241 PINCTRL_PIN(58, "gp76"),242 PINCTRL_PIN(59, "gp77"),243};244 245static const char * const cy8c95x0_groups[] = {246 "gp00",247 "gp01",248 "gp02",249 "gp03",250 "gp04",251 "gp05",252 "gp06",253 "gp07",254 255 "gp10",256 "gp11",257 "gp12",258 "gp13",259 "gp14",260 "gp15",261 "gp16",262 "gp17",263 264 "gp20",265 "gp21",266 "gp22",267 "gp23",268 269 "gp30",270 "gp31",271 "gp32",272 "gp33",273 "gp34",274 "gp35",275 "gp36",276 "gp37",277 278 "gp40",279 "gp41",280 "gp42",281 "gp43",282 "gp44",283 "gp45",284 "gp46",285 "gp47",286 287 "gp50",288 "gp51",289 "gp52",290 "gp53",291 "gp54",292 "gp55",293 "gp56",294 "gp57",295 296 "gp60",297 "gp61",298 "gp62",299 "gp63",300 "gp64",301 "gp65",302 "gp66",303 "gp67",304 305 "gp70",306 "gp71",307 "gp72",308 "gp73",309 "gp74",310 "gp75",311 "gp76",312 "gp77",313};314 315static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,316 unsigned int pin, bool input);317 318static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)319{320 /* Account for GPORT2 which only has 4 bits */321 return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;322}323 324static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)325{326 /* Account for GPORT2 which only has 4 bits */327 return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);328}329 330static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)331{332 /*333 * Only 12 registers are present per port (see Table 6 in the334 * datasheet).335 */336 if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) < 12)337 return true;338 339 switch (reg) {340 case 0x24 ... 0x27:341 return false;342 default:343 return true;344 }345}346 347static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)348{349 if (reg >= CY8C95X0_VIRTUAL)350 return true;351 352 switch (reg) {353 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):354 return false;355 case CY8C95X0_DEVID:356 return false;357 case 0x24 ... 0x27:358 return false;359 default:360 return true;361 }362}363 364static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)365{366 switch (reg) {367 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):368 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):369 case CY8C95X0_INTMASK:370 case CY8C95X0_INVERT:371 case CY8C95X0_PWMSEL:372 case CY8C95X0_DIRECTION:373 case CY8C95X0_DRV_PU:374 case CY8C95X0_DRV_PD:375 case CY8C95X0_DRV_ODH:376 case CY8C95X0_DRV_ODL:377 case CY8C95X0_DRV_PP_FAST:378 case CY8C95X0_DRV_PP_SLOW:379 case CY8C95X0_DRV_HIZ:380 return true;381 default:382 return false;383 }384}385 386static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)387{388 switch (reg) {389 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):390 return true;391 default:392 return false;393 }394}395 396static bool cy8c95x0_muxed_register(unsigned int reg)397{398 switch (reg) {399 case CY8C95X0_INTMASK:400 case CY8C95X0_PWMSEL:401 case CY8C95X0_INVERT:402 case CY8C95X0_DIRECTION:403 case CY8C95X0_DRV_PU:404 case CY8C95X0_DRV_PD:405 case CY8C95X0_DRV_ODH:406 case CY8C95X0_DRV_ODL:407 case CY8C95X0_DRV_PP_FAST:408 case CY8C95X0_DRV_PP_SLOW:409 case CY8C95X0_DRV_HIZ:410 return true;411 default:412 return false;413 }414}415 416static bool cy8c95x0_wc_register(unsigned int reg)417{418 switch (reg) {419 case CY8C95X0_DRV_PU:420 case CY8C95X0_DRV_PD:421 case CY8C95X0_DRV_ODH:422 case CY8C95X0_DRV_ODL:423 case CY8C95X0_DRV_PP_FAST:424 case CY8C95X0_DRV_PP_SLOW:425 case CY8C95X0_DRV_HIZ:426 return true;427 default:428 return false;429 }430}431 432static bool cy8c95x0_quick_path_register(unsigned int reg)433{434 switch (reg) {435 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):436 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):437 case CY8C95X0_OUTPUT_(0) ... CY8C95X0_OUTPUT_(7):438 return true;439 default:440 return false;441 }442}443 444static const struct regmap_range_cfg cy8c95x0_ranges[] = {445 {446 .range_min = CY8C95X0_VIRTUAL,447 .range_max = 0, /* Updated at runtime */448 .selector_reg = CY8C95X0_PORTSEL,449 .selector_mask = 0x07,450 .selector_shift = 0x0,451 .window_start = CY8C95X0_PORTSEL,452 .window_len = MUXED_STRIDE,453 }454};455 456static const struct regmap_config cy8c9520_i2c_regmap = {457 .reg_bits = 8,458 .val_bits = 8,459 460 .readable_reg = cy8c95x0_readable_register,461 .writeable_reg = cy8c95x0_writeable_register,462 .volatile_reg = cy8c95x0_volatile_register,463 .precious_reg = cy8c95x0_precious_register,464 465 .cache_type = REGCACHE_MAPLE,466 .ranges = NULL, /* Updated at runtime */467 .num_ranges = 1,468 .max_register = 0, /* Updated at runtime */469 .num_reg_defaults_raw = 0, /* Updated at runtime */470 .use_single_read = true, /* Workaround for regcache bug */471 .disable_locking = true,472};473 474static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip,475 unsigned int reg,476 unsigned int port,477 unsigned int mask,478 unsigned int val,479 bool *change, bool async,480 bool force)481{482 int ret, off, i;483 484 /* Caller should never modify PORTSEL directly */485 if (reg == CY8C95X0_PORTSEL)486 return -EINVAL;487 488 /* Registers behind the PORTSEL mux have their own range in regmap */489 if (cy8c95x0_muxed_register(reg)) {490 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);491 } else {492 /* Quick path direct access registers honor the port argument */493 if (cy8c95x0_quick_path_register(reg))494 off = reg + port;495 else496 off = reg;497 }498 guard(mutex)(&chip->i2c_lock);499 500 ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force);501 if (ret < 0)502 return ret;503 504 /* Mimic what hardware does and update the cache when a WC bit is written.505 * Allows to mark the registers as non-volatile and reduces I/O cycles.506 */507 if (cy8c95x0_wc_register(reg) && (mask & val)) {508 /* Writing a 1 clears set bits in the other drive mode registers */509 regcache_cache_only(chip->regmap, true);510 for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) {511 if (i == reg)512 continue;513 514 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port);515 regmap_clear_bits(chip->regmap, off, mask & val);516 }517 regcache_cache_only(chip->regmap, false);518 }519 520 return ret;521}522 523/**524 * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache525 * @chip: The pinctrl to work on526 * @reg: The register to write to. Can be direct access or muxed register.527 * MUST NOT be the PORTSEL register.528 * @port: The port to be used for muxed registers or quick path direct access529 * registers. Otherwise unused.530 * @mask: Bitmask to change531 * @val: New value for bitmask532 *533 * This function handles the register writes to the direct access registers and534 * the muxed registers while caching all register accesses, internally handling535 * the correct state of the PORTSEL register and protecting the access to muxed536 * registers.537 * The caller must only use this function to change registers behind the PORTSEL mux.538 *539 * Return: 0 for successful request, else a corresponding error value540 */541static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,542 unsigned int port, unsigned int mask, unsigned int val)543{544 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, true);545}546 547/**548 * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache549 * @chip: The pinctrl to work on550 * @reg: The register to write to. Can be direct access or muxed register.551 * MUST NOT be the PORTSEL register.552 * @port: The port to be used for muxed registers or quick path direct access553 * registers. Otherwise unused.554 * @mask: Bitmask to change555 * @val: New value for bitmask556 *557 * This function handles the register updates to the direct access registers and558 * the muxed registers while caching all register accesses, internally handling559 * the correct state of the PORTSEL register and protecting the access to muxed560 * registers.561 * The caller must only use this function to change registers behind the PORTSEL mux.562 *563 * Return: 0 for successful request, else a corresponding error value564 */565static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,566 unsigned int port, unsigned int mask, unsigned int val)567{568 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, false);569}570 571/**572 * cy8c95x0_regmap_read() - reads a register using the regmap cache573 * @chip: The pinctrl to work on574 * @reg: The register to read from. Can be direct access or muxed register.575 * @port: The port to be used for muxed registers or quick path direct access576 * registers. Otherwise unused.577 * @read_val: Value read from hardware or cache578 *579 * This function handles the register reads from the direct access registers and580 * the muxed registers while caching all register accesses, internally handling581 * the correct state of the PORTSEL register and protecting the access to muxed582 * registers.583 * The caller must only use this function to read registers behind the PORTSEL mux.584 *585 * Return: 0 for successful request, else a corresponding error value586 */587static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg,588 unsigned int port, unsigned int *read_val)589{590 int off, ret;591 592 /* Registers behind the PORTSEL mux have their own range in regmap */593 if (cy8c95x0_muxed_register(reg)) {594 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);595 } else {596 /* Quick path direct access registers honor the port argument */597 if (cy8c95x0_quick_path_register(reg))598 off = reg + port;599 else600 off = reg;601 }602 guard(mutex)(&chip->i2c_lock);603 604 ret = regmap_read(chip->regmap, off, read_val);605 606 return ret;607}608 609static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,610 unsigned long *val, unsigned long *mask)611{612 DECLARE_BITMAP(tmask, MAX_LINE);613 DECLARE_BITMAP(tval, MAX_LINE);614 int write_val;615 int ret = 0;616 int i;617 u8 bits;618 619 /* Add the 4 bit gap of Gport2 */620 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);621 bitmap_shift_left(tmask, tmask, 4, MAX_LINE);622 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);623 624 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);625 bitmap_shift_left(tval, tval, 4, MAX_LINE);626 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);627 628 for (i = 0; i < chip->nport; i++) {629 /* Skip over unused banks */630 bits = bitmap_get_value8(tmask, i * BANK_SZ);631 if (!bits)632 continue;633 634 write_val = bitmap_get_value8(tval, i * BANK_SZ);635 636 ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val);637 if (ret < 0)638 goto out;639 }640out:641 642 if (ret < 0)643 dev_err(chip->dev, "failed writing register %d, port %d: err %d\n", reg, i, ret);644 645 return ret;646}647 648static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,649 unsigned long *val, unsigned long *mask)650{651 DECLARE_BITMAP(tmask, MAX_LINE);652 DECLARE_BITMAP(tval, MAX_LINE);653 DECLARE_BITMAP(tmp, MAX_LINE);654 int read_val;655 int ret = 0;656 int i;657 u8 bits;658 659 /* Add the 4 bit gap of Gport2 */660 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);661 bitmap_shift_left(tmask, tmask, 4, MAX_LINE);662 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);663 664 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);665 bitmap_shift_left(tval, tval, 4, MAX_LINE);666 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);667 668 for (i = 0; i < chip->nport; i++) {669 /* Skip over unused banks */670 bits = bitmap_get_value8(tmask, i * BANK_SZ);671 if (!bits)672 continue;673 674 ret = cy8c95x0_regmap_read(chip, reg, i, &read_val);675 if (ret < 0)676 goto out;677 678 read_val &= bits;679 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;680 bitmap_set_value8(tval, read_val, i * BANK_SZ);681 }682 683 /* Fill the 4 bit gap of Gport2 */684 bitmap_shift_right(tmp, tval, 4, MAX_LINE);685 bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);686 687out:688 if (ret < 0)689 dev_err(chip->dev, "failed reading register %d, port %d: err %d\n", reg, i, ret);690 691 return ret;692}693 694static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)695{696 return pinctrl_gpio_direction_input(gc, off);697}698 699static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,700 unsigned int off, int val)701{702 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);703 u8 port = cypress_get_port(chip, off);704 u8 bit = cypress_get_pin_mask(chip, off);705 int ret;706 707 /* Set output level */708 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);709 if (ret)710 return ret;711 712 return pinctrl_gpio_direction_output(gc, off);713}714 715static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)716{717 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);718 u8 port = cypress_get_port(chip, off);719 u8 bit = cypress_get_pin_mask(chip, off);720 u32 reg_val;721 int ret;722 723 ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, ®_val);724 if (ret < 0) {725 /*726 * NOTE:727 * Diagnostic already emitted; that's all we should728 * do unless gpio_*_value_cansleep() calls become different729 * from their nonsleeping siblings (and report faults).730 */731 return 0;732 }733 734 return !!(reg_val & bit);735}736 737static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,738 int val)739{740 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);741 u8 port = cypress_get_port(chip, off);742 u8 bit = cypress_get_pin_mask(chip, off);743 744 cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);745}746 747static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)748{749 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);750 u8 port = cypress_get_port(chip, off);751 u8 bit = cypress_get_pin_mask(chip, off);752 u32 reg_val;753 int ret;754 755 ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, ®_val);756 if (ret < 0)757 goto out;758 759 if (reg_val & bit)760 return GPIO_LINE_DIRECTION_IN;761 762 return GPIO_LINE_DIRECTION_OUT;763out:764 return ret;765}766 767static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,768 unsigned int off,769 unsigned long *config)770{771 enum pin_config_param param = pinconf_to_config_param(*config);772 u8 port = cypress_get_port(chip, off);773 u8 bit = cypress_get_pin_mask(chip, off);774 unsigned int reg;775 u32 reg_val;776 u16 arg = 0;777 int ret;778 779 switch (param) {780 case PIN_CONFIG_BIAS_PULL_UP:781 reg = CY8C95X0_DRV_PU;782 break;783 case PIN_CONFIG_BIAS_PULL_DOWN:784 reg = CY8C95X0_DRV_PD;785 break;786 case PIN_CONFIG_BIAS_DISABLE:787 reg = CY8C95X0_DRV_HIZ;788 break;789 case PIN_CONFIG_DRIVE_OPEN_DRAIN:790 reg = CY8C95X0_DRV_ODL;791 break;792 case PIN_CONFIG_DRIVE_OPEN_SOURCE:793 reg = CY8C95X0_DRV_ODH;794 break;795 case PIN_CONFIG_DRIVE_PUSH_PULL:796 reg = CY8C95X0_DRV_PP_FAST;797 break;798 case PIN_CONFIG_INPUT_ENABLE:799 reg = CY8C95X0_DIRECTION;800 break;801 case PIN_CONFIG_MODE_PWM:802 reg = CY8C95X0_PWMSEL;803 break;804 case PIN_CONFIG_OUTPUT:805 reg = CY8C95X0_OUTPUT;806 break;807 case PIN_CONFIG_OUTPUT_ENABLE:808 reg = CY8C95X0_DIRECTION;809 break;810 811 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:812 case PIN_CONFIG_BIAS_BUS_HOLD:813 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:814 case PIN_CONFIG_DRIVE_STRENGTH:815 case PIN_CONFIG_DRIVE_STRENGTH_UA:816 case PIN_CONFIG_INPUT_DEBOUNCE:817 case PIN_CONFIG_INPUT_SCHMITT:818 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:819 case PIN_CONFIG_MODE_LOW_POWER:820 case PIN_CONFIG_PERSIST_STATE:821 case PIN_CONFIG_POWER_SOURCE:822 case PIN_CONFIG_SKEW_DELAY:823 case PIN_CONFIG_SLEEP_HARDWARE_STATE:824 case PIN_CONFIG_SLEW_RATE:825 default:826 ret = -ENOTSUPP;827 goto out;828 }829 /*830 * Writing 1 to one of the drive mode registers will automatically831 * clear conflicting set bits in the other drive mode registers.832 */833 ret = cy8c95x0_regmap_read(chip, reg, port, ®_val);834 if (ret < 0)835 goto out;836 837 if (reg_val & bit)838 arg = 1;839 if (param == PIN_CONFIG_OUTPUT_ENABLE)840 arg = !arg;841 842 *config = pinconf_to_config_packed(param, (u16)arg);843out:844 return ret;845}846 847static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,848 unsigned int off,849 unsigned long config)850{851 u8 port = cypress_get_port(chip, off);852 u8 bit = cypress_get_pin_mask(chip, off);853 unsigned long param = pinconf_to_config_param(config);854 unsigned long arg = pinconf_to_config_argument(config);855 unsigned int reg;856 int ret;857 858 switch (param) {859 case PIN_CONFIG_BIAS_PULL_UP:860 __clear_bit(off, chip->push_pull);861 reg = CY8C95X0_DRV_PU;862 break;863 case PIN_CONFIG_BIAS_PULL_DOWN:864 __clear_bit(off, chip->push_pull);865 reg = CY8C95X0_DRV_PD;866 break;867 case PIN_CONFIG_BIAS_DISABLE:868 __clear_bit(off, chip->push_pull);869 reg = CY8C95X0_DRV_HIZ;870 break;871 case PIN_CONFIG_DRIVE_OPEN_DRAIN:872 __clear_bit(off, chip->push_pull);873 reg = CY8C95X0_DRV_ODL;874 break;875 case PIN_CONFIG_DRIVE_OPEN_SOURCE:876 __clear_bit(off, chip->push_pull);877 reg = CY8C95X0_DRV_ODH;878 break;879 case PIN_CONFIG_DRIVE_PUSH_PULL:880 __set_bit(off, chip->push_pull);881 reg = CY8C95X0_DRV_PP_FAST;882 break;883 case PIN_CONFIG_MODE_PWM:884 reg = CY8C95X0_PWMSEL;885 break;886 case PIN_CONFIG_OUTPUT_ENABLE:887 ret = cy8c95x0_pinmux_direction(chip, off, !arg);888 goto out;889 case PIN_CONFIG_INPUT_ENABLE:890 ret = cy8c95x0_pinmux_direction(chip, off, arg);891 goto out;892 default:893 ret = -ENOTSUPP;894 goto out;895 }896 /*897 * Writing 1 to one of the drive mode registers will automatically898 * clear conflicting set bits in the other drive mode registers.899 */900 ret = cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit);901out:902 return ret;903}904 905static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,906 unsigned long *mask, unsigned long *bits)907{908 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);909 910 return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);911}912 913static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,914 unsigned long *mask, unsigned long *bits)915{916 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);917 918 cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);919}920 921static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)922{923 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);924 struct device *dev = chip->dev;925 int ret;926 927 ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin);928 if (ret)929 dev_err(dev, "failed to add GPIO pin range\n");930 931 return ret;932}933 934static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)935{936 struct gpio_chip *gc = &chip->gpio_chip;937 938 gc->request = gpiochip_generic_request;939 gc->free = gpiochip_generic_free;940 gc->direction_input = cy8c95x0_gpio_direction_input;941 gc->direction_output = cy8c95x0_gpio_direction_output;942 gc->get = cy8c95x0_gpio_get_value;943 gc->set = cy8c95x0_gpio_set_value;944 gc->get_direction = cy8c95x0_gpio_get_direction;945 gc->get_multiple = cy8c95x0_gpio_get_multiple;946 gc->set_multiple = cy8c95x0_gpio_set_multiple;947 gc->set_config = gpiochip_generic_config;948 gc->can_sleep = true;949 gc->add_pin_ranges = cy8c95x0_add_pin_ranges;950 951 gc->base = -1;952 gc->ngpio = chip->tpin;953 954 gc->parent = chip->dev;955 gc->owner = THIS_MODULE;956 gc->names = NULL;957 958 gc->label = dev_name(chip->dev);959 960 return devm_gpiochip_add_data(chip->dev, gc, chip);961}962 963static void cy8c95x0_irq_mask(struct irq_data *d)964{965 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);966 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);967 irq_hw_number_t hwirq = irqd_to_hwirq(d);968 969 set_bit(hwirq, chip->irq_mask);970 gpiochip_disable_irq(gc, hwirq);971}972 973static void cy8c95x0_irq_unmask(struct irq_data *d)974{975 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);976 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);977 irq_hw_number_t hwirq = irqd_to_hwirq(d);978 979 gpiochip_enable_irq(gc, hwirq);980 clear_bit(hwirq, chip->irq_mask);981}982 983static void cy8c95x0_irq_bus_lock(struct irq_data *d)984{985 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);986 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);987 988 mutex_lock(&chip->irq_lock);989}990 991static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)992{993 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);994 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);995 DECLARE_BITMAP(ones, MAX_LINE);996 DECLARE_BITMAP(irq_mask, MAX_LINE);997 DECLARE_BITMAP(reg_direction, MAX_LINE);998 999 bitmap_fill(ones, MAX_LINE);1000 1001 cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);1002 1003 /* Switch direction to input if needed */1004 cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);1005 bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);1006 bitmap_complement(irq_mask, irq_mask, MAX_LINE);1007 1008 /* Look for any newly setup interrupt */1009 cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);1010 1011 mutex_unlock(&chip->irq_lock);1012}1013 1014static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)1015{1016 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);1017 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);1018 irq_hw_number_t hwirq = irqd_to_hwirq(d);1019 unsigned int trig_type;1020 1021 switch (type) {1022 case IRQ_TYPE_EDGE_RISING:1023 case IRQ_TYPE_EDGE_FALLING:1024 case IRQ_TYPE_EDGE_BOTH:1025 trig_type = type;1026 break;1027 case IRQ_TYPE_LEVEL_HIGH:1028 trig_type = IRQ_TYPE_EDGE_RISING;1029 break;1030 case IRQ_TYPE_LEVEL_LOW:1031 trig_type = IRQ_TYPE_EDGE_FALLING;1032 break;1033 default:1034 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);1035 return -EINVAL;1036 }1037 1038 assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);1039 assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);1040 assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);1041 assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);1042 1043 return 0;1044}1045 1046static void cy8c95x0_irq_shutdown(struct irq_data *d)1047{1048 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);1049 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);1050 irq_hw_number_t hwirq = irqd_to_hwirq(d);1051 1052 clear_bit(hwirq, chip->irq_trig_raise);1053 clear_bit(hwirq, chip->irq_trig_fall);1054 clear_bit(hwirq, chip->irq_trig_low);1055 clear_bit(hwirq, chip->irq_trig_high);1056}1057 1058static const struct irq_chip cy8c95x0_irqchip = {1059 .name = "cy8c95x0-irq",1060 .irq_mask = cy8c95x0_irq_mask,1061 .irq_unmask = cy8c95x0_irq_unmask,1062 .irq_bus_lock = cy8c95x0_irq_bus_lock,1063 .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,1064 .irq_set_type = cy8c95x0_irq_set_type,1065 .irq_shutdown = cy8c95x0_irq_shutdown,1066 .flags = IRQCHIP_IMMUTABLE,1067 GPIOCHIP_IRQ_RESOURCE_HELPERS,1068};1069 1070static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)1071{1072 DECLARE_BITMAP(ones, MAX_LINE);1073 DECLARE_BITMAP(cur_stat, MAX_LINE);1074 DECLARE_BITMAP(new_stat, MAX_LINE);1075 DECLARE_BITMAP(trigger, MAX_LINE);1076 1077 bitmap_fill(ones, MAX_LINE);1078 1079 /* Read the current interrupt status from the device */1080 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))1081 return false;1082 1083 /* Check latched inputs */1084 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))1085 return false;1086 1087 /* Apply filter for rising/falling edge selection */1088 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,1089 cur_stat, MAX_LINE);1090 1091 bitmap_and(pending, new_stat, trigger, MAX_LINE);1092 1093 return !bitmap_empty(pending, MAX_LINE);1094}1095 1096static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)1097{1098 struct cy8c95x0_pinctrl *chip = devid;1099 struct gpio_chip *gc = &chip->gpio_chip;1100 DECLARE_BITMAP(pending, MAX_LINE);1101 int nested_irq, level;1102 bool ret;1103 1104 ret = cy8c95x0_irq_pending(chip, pending);1105 if (!ret)1106 return IRQ_RETVAL(0);1107 1108 ret = 0;1109 for_each_set_bit(level, pending, MAX_LINE) {1110 /* Already accounted for 4bit gap in GPort2 */1111 nested_irq = irq_find_mapping(gc->irq.domain, level);1112 1113 if (unlikely(nested_irq <= 0)) {1114 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);1115 continue;1116 }1117 1118 if (test_bit(level, chip->irq_trig_low))1119 while (!cy8c95x0_gpio_get_value(gc, level))1120 handle_nested_irq(nested_irq);1121 else if (test_bit(level, chip->irq_trig_high))1122 while (cy8c95x0_gpio_get_value(gc, level))1123 handle_nested_irq(nested_irq);1124 else1125 handle_nested_irq(nested_irq);1126 1127 ret = 1;1128 }1129 1130 return IRQ_RETVAL(ret);1131}1132 1133static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)1134{1135 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);1136 1137 return chip->tpin;1138}1139 1140static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,1141 unsigned int group)1142{1143 return cy8c95x0_groups[group];1144}1145 1146static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,1147 unsigned int group,1148 const unsigned int **pins,1149 unsigned int *num_pins)1150{1151 *pins = &cy8c9560_pins[group].number;1152 *num_pins = 1;1153 return 0;1154}1155 1156static const char *cy8c95x0_get_fname(unsigned int selector)1157{1158 if (selector == 0)1159 return "gpio";1160 else1161 return "pwm";1162}1163 1164static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,1165 unsigned int pin)1166{1167 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);1168 DECLARE_BITMAP(mask, MAX_LINE);1169 DECLARE_BITMAP(pwm, MAX_LINE);1170 1171 bitmap_zero(mask, MAX_LINE);1172 __set_bit(pin, mask);1173 1174 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {1175 seq_puts(s, "not available");1176 return;1177 }1178 1179 seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));1180}1181 1182static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {1183 .get_groups_count = cy8c95x0_pinctrl_get_groups_count,1184 .get_group_name = cy8c95x0_pinctrl_get_group_name,1185 .get_group_pins = cy8c95x0_pinctrl_get_group_pins,1186#ifdef CONFIG_OF1187 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,1188 .dt_free_map = pinconf_generic_dt_free_map,1189#endif1190 .pin_dbg_show = cy8c95x0_pin_dbg_show,1191};1192 1193static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)1194{1195 return cy8c95x0_get_fname(selector);1196}1197 1198static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)1199{1200 return 2;1201}1202 1203static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,1204 const char * const **groups,1205 unsigned int * const num_groups)1206{1207 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);1208 1209 *groups = cy8c95x0_groups;1210 *num_groups = chip->tpin;1211 return 0;1212}1213 1214static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode)1215{1216 u8 port = cypress_get_port(chip, off);1217 u8 bit = cypress_get_pin_mask(chip, off);1218 1219 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode ? bit : 0);1220}1221 1222static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,1223 unsigned int selector, unsigned int group)1224{1225 u8 port = cypress_get_port(chip, group);1226 u8 bit = cypress_get_pin_mask(chip, group);1227 int ret;1228 1229 ret = cy8c95x0_set_mode(chip, group, selector);1230 if (ret < 0)1231 return ret;1232 1233 if (selector == 0)1234 return 0;1235 1236 /* Set direction to output & set output to 1 so that PWM can work */1237 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, bit);1238 if (ret < 0)1239 return ret;1240 1241 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, bit);1242}1243 1244static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,1245 unsigned int group)1246{1247 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);1248 1249 return cy8c95x0_pinmux_mode(chip, selector, group);1250}1251 1252static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev,1253 struct pinctrl_gpio_range *range,1254 unsigned int pin)1255{1256 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);1257 1258 return cy8c95x0_set_mode(chip, pin, false);1259}1260 1261static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,1262 unsigned int pin, bool input)1263{1264 u8 port = cypress_get_port(chip, pin);1265 u8 bit = cypress_get_pin_mask(chip, pin);1266 int ret;1267 1268 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0);1269 if (ret)1270 return ret;1271 1272 /*1273 * Disable driving the pin by forcing it to HighZ. Only setting1274 * the direction register isn't sufficient in Push-Pull mode.1275 */1276 if (input && test_bit(pin, chip->push_pull)) {1277 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit);1278 if (ret)1279 return ret;1280 1281 __clear_bit(pin, chip->push_pull);1282 }1283 1284 return 0;1285}1286 1287static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev,1288 struct pinctrl_gpio_range *range,1289 unsigned int pin, bool input)1290{1291 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);1292 1293 return cy8c95x0_pinmux_direction(chip, pin, input);1294}1295 1296static const struct pinmux_ops cy8c95x0_pmxops = {1297 .get_functions_count = cy8c95x0_get_functions_count,1298 .get_function_name = cy8c95x0_get_function_name,1299 .get_function_groups = cy8c95x0_get_function_groups,1300 .set_mux = cy8c95x0_set_mux,1301 .gpio_request_enable = cy8c95x0_gpio_request_enable,1302 .gpio_set_direction = cy8c95x0_gpio_set_direction,1303 .strict = true,1304};1305 1306static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,1307 unsigned long *config)1308{1309 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);1310 1311 return cy8c95x0_gpio_get_pincfg(chip, pin, config);1312}1313 1314static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,1315 unsigned long *configs, unsigned int num_configs)1316{1317 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);1318 int ret = 0;1319 int i;1320 1321 for (i = 0; i < num_configs; i++) {1322 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);1323 if (ret)1324 return ret;1325 }1326 1327 return ret;1328}1329 1330static const struct pinconf_ops cy8c95x0_pinconf_ops = {1331 .pin_config_get = cy8c95x0_pinconf_get,1332 .pin_config_set = cy8c95x0_pinconf_set,1333 .is_generic = true,1334};1335 1336static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)1337{1338 struct gpio_irq_chip *girq = &chip->gpio_chip.irq;1339 DECLARE_BITMAP(pending_irqs, MAX_LINE);1340 int ret;1341 1342 mutex_init(&chip->irq_lock);1343 1344 bitmap_zero(pending_irqs, MAX_LINE);1345 1346 /* Read IRQ status register to clear all pending interrupts */1347 ret = cy8c95x0_irq_pending(chip, pending_irqs);1348 if (ret) {1349 dev_err(chip->dev, "failed to clear irq status register\n");1350 return ret;1351 }1352 1353 /* Mask all interrupts */1354 bitmap_fill(chip->irq_mask, MAX_LINE);1355 1356 gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);1357 1358 /* This will let us handle the parent IRQ in the driver */1359 girq->parent_handler = NULL;1360 girq->num_parents = 0;1361 girq->parents = NULL;1362 girq->default_type = IRQ_TYPE_NONE;1363 girq->handler = handle_simple_irq;1364 girq->threaded = true;1365 1366 ret = devm_request_threaded_irq(chip->dev, irq,1367 NULL, cy8c95x0_irq_handler,1368 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,1369 dev_name(chip->dev), chip);1370 if (ret) {1371 dev_err(chip->dev, "failed to request irq %d\n", irq);1372 return ret;1373 }1374 dev_info(chip->dev, "Registered threaded IRQ\n");1375 1376 return 0;1377}1378 1379static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)1380{1381 struct pinctrl_desc *pd = &chip->pinctrl_desc;1382 1383 pd->pctlops = &cy8c95x0_pinctrl_ops;1384 pd->confops = &cy8c95x0_pinconf_ops;1385 pd->pmxops = &cy8c95x0_pmxops;1386 pd->name = dev_name(chip->dev);1387 pd->pins = cy8c9560_pins;1388 pd->npins = chip->tpin;1389 pd->owner = THIS_MODULE;1390 1391 chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);1392 if (IS_ERR(chip->pctldev))1393 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),1394 "can't register controller\n");1395 1396 return 0;1397}1398 1399static int cy8c95x0_detect(struct i2c_client *client,1400 struct i2c_board_info *info)1401{1402 struct i2c_adapter *adapter = client->adapter;1403 int ret;1404 const char *name;1405 1406 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))1407 return -ENODEV;1408 1409 ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);1410 if (ret < 0)1411 return ret;1412 switch (ret & GENMASK(7, 4)) {1413 case 0x20:1414 name = cy8c95x0_id[0].name;1415 break;1416 case 0x40:1417 name = cy8c95x0_id[1].name;1418 break;1419 case 0x60:1420 name = cy8c95x0_id[2].name;1421 break;1422 default:1423 return -ENODEV;1424 }1425 1426 dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);1427 strscpy(info->type, name, I2C_NAME_SIZE);1428 1429 return 0;1430}1431 1432static int cy8c95x0_probe(struct i2c_client *client)1433{1434 struct cy8c95x0_pinctrl *chip;1435 struct regmap_config regmap_conf;1436 struct regmap_range_cfg regmap_range_conf;1437 struct regulator *reg;1438 int ret;1439 1440 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);1441 if (!chip)1442 return -ENOMEM;1443 1444 chip->dev = &client->dev;1445 1446 /* Set the device type */1447 chip->driver_data = (uintptr_t)i2c_get_match_data(client);1448 if (!chip->driver_data)1449 return -ENODEV;1450 1451 i2c_set_clientdata(client, chip);1452 1453 chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;1454 chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);1455 1456 memcpy(®map_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf));1457 1458 switch (chip->tpin) {1459 case 20:1460 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);1461 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE;1462 break;1463 case 40:1464 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);1465 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE;1466 break;1467 case 60:1468 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);1469 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE;1470 break;1471 default:1472 return -ENODEV;1473 }1474 1475 reg = devm_regulator_get(&client->dev, "vdd");1476 if (IS_ERR(reg)) {1477 if (PTR_ERR(reg) == -EPROBE_DEFER)1478 return -EPROBE_DEFER;1479 } else {1480 ret = regulator_enable(reg);1481 if (ret) {1482 dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret);1483 return ret;1484 }1485 chip->regulator = reg;1486 }1487 1488 /* bring the chip out of reset if reset pin is provided */1489 chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH);1490 if (IS_ERR(chip->gpio_reset)) {1491 ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset),1492 "Failed to get GPIO 'reset'\n");1493 goto err_exit;1494 } else if (chip->gpio_reset) {1495 usleep_range(1000, 2000);1496 gpiod_set_value_cansleep(chip->gpio_reset, 0);1497 usleep_range(250000, 300000);1498 1499 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");1500 }1501 1502 /* Regmap for direct and paged registers */1503 memcpy(®map_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf));1504 regmap_conf.ranges = ®map_range_conf;1505 regmap_conf.max_register = regmap_range_conf.range_max;1506 regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max;1507 1508 chip->regmap = devm_regmap_init_i2c(client, ®map_conf);1509 if (IS_ERR(chip->regmap)) {1510 ret = PTR_ERR(chip->regmap);1511 goto err_exit;1512 }1513 1514 bitmap_zero(chip->push_pull, MAX_LINE);1515 bitmap_zero(chip->shiftmask, MAX_LINE);1516 bitmap_set(chip->shiftmask, 0, 20);1517 mutex_init(&chip->i2c_lock);1518 1519 if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {1520 ret = cy8c95x0_acpi_get_irq(&client->dev);1521 if (ret > 0)1522 client->irq = ret;1523 }1524 1525 if (client->irq) {1526 ret = cy8c95x0_irq_setup(chip, client->irq);1527 if (ret)1528 goto err_exit;1529 }1530 1531 ret = cy8c95x0_setup_pinctrl(chip);1532 if (ret)1533 goto err_exit;1534 1535 ret = cy8c95x0_setup_gpiochip(chip);1536 if (ret)1537 goto err_exit;1538 1539 return 0;1540 1541err_exit:1542 if (!IS_ERR_OR_NULL(chip->regulator))1543 regulator_disable(chip->regulator);1544 return ret;1545}1546 1547static void cy8c95x0_remove(struct i2c_client *client)1548{1549 struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client);1550 1551 if (!IS_ERR_OR_NULL(chip->regulator))1552 regulator_disable(chip->regulator);1553}1554 1555static const struct acpi_device_id cy8c95x0_acpi_ids[] = {1556 { "INT3490", 40, },1557 { }1558};1559MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);1560 1561static struct i2c_driver cy8c95x0_driver = {1562 .driver = {1563 .name = "cy8c95x0-pinctrl",1564 .of_match_table = cy8c95x0_dt_ids,1565 .acpi_match_table = cy8c95x0_acpi_ids,1566 },1567 .probe = cy8c95x0_probe,1568 .remove = cy8c95x0_remove,1569 .id_table = cy8c95x0_id,1570 .detect = cy8c95x0_detect,1571};1572module_i2c_driver(cy8c95x0_driver);1573 1574MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>");1575MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>");1576MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");1577MODULE_LICENSE("GPL");1578