brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Ingenic SoCs pinctrl driver4 *5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>6 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>7 * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>8 */9 10#include <linux/compiler.h>11#include <linux/gpio/driver.h>12#include <linux/interrupt.h>13#include <linux/io.h>14#include <linux/kernel.h>15#include <linux/mod_devicetable.h>16#include <linux/of.h>17#include <linux/platform_device.h>18#include <linux/property.h>19#include <linux/regmap.h>20#include <linux/seq_file.h>21#include <linux/slab.h>22 23#include <linux/pinctrl/consumer.h>24#include <linux/pinctrl/pinconf-generic.h>25#include <linux/pinctrl/pinconf.h>26#include <linux/pinctrl/pinctrl.h>27#include <linux/pinctrl/pinmux.h>28 29#include "core.h"30#include "pinconf.h"31#include "pinmux.h"32 33#define GPIO_PIN					0x0034#define GPIO_MSK					0x2035 36#define JZ4730_GPIO_DATA			0x0037#define JZ4730_GPIO_GPDIR			0x0438#define JZ4730_GPIO_GPPUR			0x0c39#define JZ4730_GPIO_GPALR			0x1040#define JZ4730_GPIO_GPAUR			0x1441#define JZ4730_GPIO_GPIDLR			0x1842#define JZ4730_GPIO_GPIDUR			0x1c43#define JZ4730_GPIO_GPIER			0x2044#define JZ4730_GPIO_GPIMR			0x2445#define JZ4730_GPIO_GPFR			0x2846 47#define JZ4740_GPIO_DATA			0x1048#define JZ4740_GPIO_PULL_DIS		0x3049#define JZ4740_GPIO_FUNC			0x4050#define JZ4740_GPIO_SELECT			0x5051#define JZ4740_GPIO_DIR				0x6052#define JZ4740_GPIO_TRIG			0x7053#define JZ4740_GPIO_FLAG			0x8054 55#define JZ4770_GPIO_INT				0x1056#define JZ4770_GPIO_PAT1			0x3057#define JZ4770_GPIO_PAT0			0x4058#define JZ4770_GPIO_FLAG			0x5059#define JZ4770_GPIO_PEN				0x7060 61#define X1830_GPIO_PEL				0x11062#define X1830_GPIO_PEH				0x12063#define X1830_GPIO_SR				0x15064#define X1830_GPIO_SMT				0x16065 66#define X2000_GPIO_EDG				0x7067#define X2000_GPIO_PEPU				0x8068#define X2000_GPIO_PEPD				0x9069#define X2000_GPIO_SR				0xd070#define X2000_GPIO_SMT				0xe071 72#define REG_SET(x)					((x) + 0x4)73#define REG_CLEAR(x)				((x) + 0x8)74 75#define REG_PZ_BASE(x)				((x) * 7)76#define REG_PZ_GID2LD(x)			((x) * 7 + 0xf0)77 78#define GPIO_PULL_DIS				079#define GPIO_PULL_UP				180#define GPIO_PULL_DOWN				281 82#define PINS_PER_GPIO_CHIP			3283#define JZ4730_PINS_PER_PAIRED_REG	1684 85#define INGENIC_PIN_GROUP_FUNCS(_name_, id, funcs)					\86	{										\87		.grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)),	\88		.data = funcs,								\89	}90 91#define INGENIC_PIN_GROUP(_name_, id, func)						\92	{										\93		.grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)),	\94		.data = (void *)func,							\95	}96 97#define INGENIC_PIN_FUNCTION(_name_, id)							\98	{											\99		.func = PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups)),	\100		.data = NULL,									\101	}102 103enum jz_version {104	ID_JZ4730,105	ID_JZ4740,106	ID_JZ4725B,107	ID_JZ4750,108	ID_JZ4755,109	ID_JZ4760,110	ID_JZ4770,111	ID_JZ4775,112	ID_JZ4780,113	ID_X1000,114	ID_X1500,115	ID_X1830,116	ID_X2000,117	ID_X2100,118};119 120struct ingenic_chip_info {121	unsigned int num_chips;122	unsigned int reg_offset;123	enum jz_version version;124 125	const struct group_desc *groups;126	unsigned int num_groups;127 128	const struct function_desc *functions;129	unsigned int num_functions;130 131	const u32 *pull_ups, *pull_downs;132 133	const struct regmap_access_table *access_table;134};135 136struct ingenic_pinctrl {137	struct device *dev;138	struct regmap *map;139	struct pinctrl_dev *pctl;140	struct pinctrl_pin_desc *pdesc;141 142	const struct ingenic_chip_info *info;143 144	struct gpio_chip *gc;145};146 147struct ingenic_gpio_chip {148	struct ingenic_pinctrl *jzpc;149	struct gpio_chip gc;150	unsigned int irq, reg_base;151};152 153static const unsigned long enabled_socs =154	IS_ENABLED(CONFIG_MACH_JZ4730) << ID_JZ4730 |155	IS_ENABLED(CONFIG_MACH_JZ4740) << ID_JZ4740 |156	IS_ENABLED(CONFIG_MACH_JZ4725B) << ID_JZ4725B |157	IS_ENABLED(CONFIG_MACH_JZ4750) << ID_JZ4750 |158	IS_ENABLED(CONFIG_MACH_JZ4755) << ID_JZ4755 |159	IS_ENABLED(CONFIG_MACH_JZ4760) << ID_JZ4760 |160	IS_ENABLED(CONFIG_MACH_JZ4770) << ID_JZ4770 |161	IS_ENABLED(CONFIG_MACH_JZ4775) << ID_JZ4775 |162	IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 |163	IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 |164	IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 |165	IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 |166	IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 |167	IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100;168 169static bool170is_soc_or_above(const struct ingenic_pinctrl *jzpc, enum jz_version version)171{172	return (enabled_socs >> version) &&173		(!(enabled_socs & GENMASK(version - 1, 0))174		 || jzpc->info->version >= version);175}176 177static const u32 jz4730_pull_ups[4] = {178	0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff,179};180 181static const u32 jz4730_pull_downs[4] = {182	0x00000df0, 0x0dff0000, 0x00000000, 0x00000000,183};184 185static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, };186static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, };187static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, };188static int jz4730_uart1_data_pins[] = { 0x18, 0x19, };189static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, };190static int jz4730_uart3_data_pins[] = { 0x10, 0x15, };191static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, };192static int jz4730_lcd_8bit_pins[] = {193	0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,194	0x3a, 0x39, 0x38,195};196static int jz4730_lcd_16bit_pins[] = {197	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,198};199static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, };200static int jz4730_lcd_generic_pins[] = { 0x3b, };201static int jz4730_nand_cs1_pins[] = { 0x53, };202static int jz4730_nand_cs2_pins[] = { 0x54, };203static int jz4730_nand_cs3_pins[] = { 0x55, };204static int jz4730_nand_cs4_pins[] = { 0x56, };205static int jz4730_nand_cs5_pins[] = { 0x57, };206static int jz4730_pwm_pwm0_pins[] = { 0x5e, };207static int jz4730_pwm_pwm1_pins[] = { 0x5f, };208 209static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, };210 211static const struct group_desc jz4730_groups[] = {212	INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),213	INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),214	INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),215	INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),216	INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),217	INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),218	INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),219	INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),220	INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),221	INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),222	INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),223	INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),224	INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),225	INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),226	INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),227	INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),228	INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1),229	INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1),230};231 232static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };233static const char *jz4730_uart0_groups[] = { "uart0-data", };234static const char *jz4730_uart1_groups[] = { "uart1-data", };235static const char *jz4730_uart2_groups[] = { "uart2-data", };236static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };237static const char *jz4730_lcd_groups[] = {238	"lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",239};240static const char *jz4730_nand_groups[] = {241	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",242};243static const char *jz4730_pwm0_groups[] = { "pwm0", };244static const char *jz4730_pwm1_groups[] = { "pwm1", };245 246static const struct function_desc jz4730_functions[] = {247	INGENIC_PIN_FUNCTION("mmc", jz4730_mmc),248	INGENIC_PIN_FUNCTION("uart0", jz4730_uart0),249	INGENIC_PIN_FUNCTION("uart1", jz4730_uart1),250	INGENIC_PIN_FUNCTION("uart2", jz4730_uart2),251	INGENIC_PIN_FUNCTION("uart3", jz4730_uart3),252	INGENIC_PIN_FUNCTION("lcd", jz4730_lcd),253	INGENIC_PIN_FUNCTION("nand", jz4730_nand),254	INGENIC_PIN_FUNCTION("pwm0", jz4730_pwm0),255	INGENIC_PIN_FUNCTION("pwm1", jz4730_pwm1),256};257 258static const struct ingenic_chip_info jz4730_chip_info = {259	.num_chips = 4,260	.reg_offset = 0x30,261	.version = ID_JZ4730,262	.groups = jz4730_groups,263	.num_groups = ARRAY_SIZE(jz4730_groups),264	.functions = jz4730_functions,265	.num_functions = ARRAY_SIZE(jz4730_functions),266	.pull_ups = jz4730_pull_ups,267	.pull_downs = jz4730_pull_downs,268};269 270static const u32 jz4740_pull_ups[4] = {271	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,272};273 274static const u32 jz4740_pull_downs[4] = {275	0x00000000, 0x00000000, 0x00000000, 0x00000000,276};277 278static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };279static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };280static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };281static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };282static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };283static int jz4740_lcd_8bit_pins[] = {284	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,285	0x52, 0x53, 0x54,286};287static int jz4740_lcd_16bit_pins[] = {288	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,289};290static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };291static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, };292static int jz4740_lcd_generic_pins[] = { 0x55, };293static int jz4740_nand_cs1_pins[] = { 0x39, };294static int jz4740_nand_cs2_pins[] = { 0x3a, };295static int jz4740_nand_cs3_pins[] = { 0x3b, };296static int jz4740_nand_cs4_pins[] = { 0x3c, };297static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };298static int jz4740_pwm_pwm0_pins[] = { 0x77, };299static int jz4740_pwm_pwm1_pins[] = { 0x78, };300static int jz4740_pwm_pwm2_pins[] = { 0x79, };301static int jz4740_pwm_pwm3_pins[] = { 0x7a, };302static int jz4740_pwm_pwm4_pins[] = { 0x7b, };303static int jz4740_pwm_pwm5_pins[] = { 0x7c, };304static int jz4740_pwm_pwm6_pins[] = { 0x7e, };305static int jz4740_pwm_pwm7_pins[] = { 0x7f, };306 307static const struct group_desc jz4740_groups[] = {308	INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),309	INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),310	INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),311	INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),312	INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),313	INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),314	INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),315	INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),316	INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),317	INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),318	INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),319	INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),320	INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),321	INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),322	INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),323	INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0),324	INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0),325	INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0),326	INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0),327	INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0),328	INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0),329	INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0),330	INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0),331};332 333static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };334static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };335static const char *jz4740_uart1_groups[] = { "uart1-data", };336static const char *jz4740_lcd_groups[] = {337	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",338};339static const char *jz4740_nand_groups[] = {340	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",341};342static const char *jz4740_pwm0_groups[] = { "pwm0", };343static const char *jz4740_pwm1_groups[] = { "pwm1", };344static const char *jz4740_pwm2_groups[] = { "pwm2", };345static const char *jz4740_pwm3_groups[] = { "pwm3", };346static const char *jz4740_pwm4_groups[] = { "pwm4", };347static const char *jz4740_pwm5_groups[] = { "pwm5", };348static const char *jz4740_pwm6_groups[] = { "pwm6", };349static const char *jz4740_pwm7_groups[] = { "pwm7", };350 351static const struct function_desc jz4740_functions[] = {352	INGENIC_PIN_FUNCTION("mmc", jz4740_mmc),353	INGENIC_PIN_FUNCTION("uart0", jz4740_uart0),354	INGENIC_PIN_FUNCTION("uart1", jz4740_uart1),355	INGENIC_PIN_FUNCTION("lcd", jz4740_lcd),356	INGENIC_PIN_FUNCTION("nand", jz4740_nand),357	INGENIC_PIN_FUNCTION("pwm0", jz4740_pwm0),358	INGENIC_PIN_FUNCTION("pwm1", jz4740_pwm1),359	INGENIC_PIN_FUNCTION("pwm2", jz4740_pwm2),360	INGENIC_PIN_FUNCTION("pwm3", jz4740_pwm3),361	INGENIC_PIN_FUNCTION("pwm4", jz4740_pwm4),362	INGENIC_PIN_FUNCTION("pwm5", jz4740_pwm5),363	INGENIC_PIN_FUNCTION("pwm6", jz4740_pwm6),364	INGENIC_PIN_FUNCTION("pwm7", jz4740_pwm7),365};366 367static const struct ingenic_chip_info jz4740_chip_info = {368	.num_chips = 4,369	.reg_offset = 0x100,370	.version = ID_JZ4740,371	.groups = jz4740_groups,372	.num_groups = ARRAY_SIZE(jz4740_groups),373	.functions = jz4740_functions,374	.num_functions = ARRAY_SIZE(jz4740_functions),375	.pull_ups = jz4740_pull_ups,376	.pull_downs = jz4740_pull_downs,377};378 379static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };380static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };381static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };382static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };383static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };384static int jz4725b_lcd_8bit_pins[] = {385	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,386	0x72, 0x73, 0x74,387};388static int jz4725b_lcd_16bit_pins[] = {389	0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,390};391static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };392static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };393static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };394static int jz4725b_lcd_generic_pins[] = { 0x75, };395static int jz4725b_nand_cs1_pins[] = { 0x55, };396static int jz4725b_nand_cs2_pins[] = { 0x56, };397static int jz4725b_nand_cs3_pins[] = { 0x57, };398static int jz4725b_nand_cs4_pins[] = { 0x58, };399static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };400static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };401static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };402static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };403static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };404static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };405static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };406static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };407 408static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };409 410static const struct group_desc jz4725b_groups[] = {411	INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),412	INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,413				jz4725b_mmc0_4bit_funcs),414	INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),415	INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),416	INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),417	INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),418	INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),419	INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),420	INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),421	INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),422	INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),423	INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),424	INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),425	INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),426	INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),427	INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),428	INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),429	INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0),430	INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0),431	INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0),432	INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0),433	INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0),434	INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0),435};436 437static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };438static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };439static const char *jz4725b_uart_groups[] = { "uart-data", };440static const char *jz4725b_lcd_groups[] = {441	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",442	"lcd-special", "lcd-generic",443};444static const char *jz4725b_nand_groups[] = {445	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",446	"nand-cle-ale", "nand-fre-fwe",447};448static const char *jz4725b_pwm0_groups[] = { "pwm0", };449static const char *jz4725b_pwm1_groups[] = { "pwm1", };450static const char *jz4725b_pwm2_groups[] = { "pwm2", };451static const char *jz4725b_pwm3_groups[] = { "pwm3", };452static const char *jz4725b_pwm4_groups[] = { "pwm4", };453static const char *jz4725b_pwm5_groups[] = { "pwm5", };454 455static const struct function_desc jz4725b_functions[] = {456	INGENIC_PIN_FUNCTION("mmc0", jz4725b_mmc0),457	INGENIC_PIN_FUNCTION("mmc1", jz4725b_mmc1),458	INGENIC_PIN_FUNCTION("uart", jz4725b_uart),459	INGENIC_PIN_FUNCTION("nand", jz4725b_nand),460	INGENIC_PIN_FUNCTION("pwm0", jz4725b_pwm0),461	INGENIC_PIN_FUNCTION("pwm1", jz4725b_pwm1),462	INGENIC_PIN_FUNCTION("pwm2", jz4725b_pwm2),463	INGENIC_PIN_FUNCTION("pwm3", jz4725b_pwm3),464	INGENIC_PIN_FUNCTION("pwm4", jz4725b_pwm4),465	INGENIC_PIN_FUNCTION("pwm5", jz4725b_pwm5),466	INGENIC_PIN_FUNCTION("lcd", jz4725b_lcd),467};468 469static const struct ingenic_chip_info jz4725b_chip_info = {470	.num_chips = 4,471	.reg_offset = 0x100,472	.version = ID_JZ4725B,473	.groups = jz4725b_groups,474	.num_groups = ARRAY_SIZE(jz4725b_groups),475	.functions = jz4725b_functions,476	.num_functions = ARRAY_SIZE(jz4725b_functions),477	.pull_ups = jz4740_pull_ups,478	.pull_downs = jz4740_pull_downs,479};480 481static const u32 jz4750_pull_ups[6] = {482	0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff,483};484 485static const u32 jz4750_pull_downs[6] = {486	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,487};488 489static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };490static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };491static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };492static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };493static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };494static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };495static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };496static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };497static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };498static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };499static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };500static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };501static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };502static int jz4750_cim_pins[] = {503	0x89, 0x8b, 0x8a, 0x88,504	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,505};506static int jz4750_lcd_8bit_pins[] = {507	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,508	0x72, 0x73, 0x74,509};510static int jz4750_lcd_16bit_pins[] = {511	0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,512};513static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };514static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, };515static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };516static int jz4750_lcd_generic_pins[] = { 0x75, };517static int jz4750_nand_cs1_pins[] = { 0x55, };518static int jz4750_nand_cs2_pins[] = { 0x56, };519static int jz4750_nand_cs3_pins[] = { 0x57, };520static int jz4750_nand_cs4_pins[] = { 0x58, };521static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };522static int jz4750_pwm_pwm0_pins[] = { 0x94, };523static int jz4750_pwm_pwm1_pins[] = { 0x95, };524static int jz4750_pwm_pwm2_pins[] = { 0x96, };525static int jz4750_pwm_pwm3_pins[] = { 0x97, };526static int jz4750_pwm_pwm4_pins[] = { 0x98, };527static int jz4750_pwm_pwm5_pins[] = { 0x99, };528 529static const struct group_desc jz4750_groups[] = {530	INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),531	INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),532	INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),533	INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),534	INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),535	INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),536	INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),537	INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),538	INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),539	INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),540	INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),541	INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),542	INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),543	INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),544	INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),545	INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),546	INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),547	INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),548	INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),549	INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),550	INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),551	INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),552	INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),553	INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),554	INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),555	INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),556	INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),557	INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),558	INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),559	INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),560	INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0),561};562 563static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };564static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };565static const char *jz4750_uart2_groups[] = { "uart2-data", };566static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };567static const char *jz4750_mmc0_groups[] = {568	"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",569};570static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };571static const char *jz4750_i2c_groups[] = { "i2c-data", };572static const char *jz4750_cim_groups[] = { "cim-data", };573static const char *jz4750_lcd_groups[] = {574	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",575	"lcd-special", "lcd-generic",576};577static const char *jz4750_nand_groups[] = {578	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",579};580static const char *jz4750_pwm0_groups[] = { "pwm0", };581static const char *jz4750_pwm1_groups[] = { "pwm1", };582static const char *jz4750_pwm2_groups[] = { "pwm2", };583static const char *jz4750_pwm3_groups[] = { "pwm3", };584static const char *jz4750_pwm4_groups[] = { "pwm4", };585static const char *jz4750_pwm5_groups[] = { "pwm5", };586 587static const struct function_desc jz4750_functions[] = {588	INGENIC_PIN_FUNCTION("uart0", jz4750_uart0),589	INGENIC_PIN_FUNCTION("uart1", jz4750_uart1),590	INGENIC_PIN_FUNCTION("uart2", jz4750_uart2),591	INGENIC_PIN_FUNCTION("uart3", jz4750_uart3),592	INGENIC_PIN_FUNCTION("mmc0", jz4750_mmc0),593	INGENIC_PIN_FUNCTION("mmc1", jz4750_mmc1),594	INGENIC_PIN_FUNCTION("i2c", jz4750_i2c),595	INGENIC_PIN_FUNCTION("cim", jz4750_cim),596	INGENIC_PIN_FUNCTION("lcd", jz4750_lcd),597	INGENIC_PIN_FUNCTION("nand", jz4750_nand),598	INGENIC_PIN_FUNCTION("pwm0", jz4750_pwm0),599	INGENIC_PIN_FUNCTION("pwm1", jz4750_pwm1),600	INGENIC_PIN_FUNCTION("pwm2", jz4750_pwm2),601	INGENIC_PIN_FUNCTION("pwm3", jz4750_pwm3),602	INGENIC_PIN_FUNCTION("pwm4", jz4750_pwm4),603	INGENIC_PIN_FUNCTION("pwm5", jz4750_pwm5),604};605 606static const struct ingenic_chip_info jz4750_chip_info = {607	.num_chips = 6,608	.reg_offset = 0x100,609	.version = ID_JZ4750,610	.groups = jz4750_groups,611	.num_groups = ARRAY_SIZE(jz4750_groups),612	.functions = jz4750_functions,613	.num_functions = ARRAY_SIZE(jz4750_functions),614	.pull_ups = jz4750_pull_ups,615	.pull_downs = jz4750_pull_downs,616};617 618static const u32 jz4755_pull_ups[6] = {619	0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00,620};621 622static const u32 jz4755_pull_downs[6] = {623	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,624};625 626static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };627static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };628static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };629static int jz4755_uart2_data_pins[] = { 0x9f, };630static int jz4755_ssi_dt_b_pins[] = { 0x3b, };631static int jz4755_ssi_dt_f_pins[] = { 0xa1, };632static int jz4755_ssi_dr_b_pins[] = { 0x3c, };633static int jz4755_ssi_dr_f_pins[] = { 0xa2, };634static int jz4755_ssi_clk_b_pins[] = { 0x3a, };635static int jz4755_ssi_clk_f_pins[] = { 0xa0, };636static int jz4755_ssi_gpc_b_pins[] = { 0x3e, };637static int jz4755_ssi_gpc_f_pins[] = { 0xa4, };638static int jz4755_ssi_ce0_b_pins[] = { 0x3d, };639static int jz4755_ssi_ce0_f_pins[] = { 0xa3, };640static int jz4755_ssi_ce1_b_pins[] = { 0x3f, };641static int jz4755_ssi_ce1_f_pins[] = { 0xa5, };642static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };643static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };644static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };645static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };646static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };647static int jz4755_cim_pins[] = {648	0x89, 0x8b, 0x8a, 0x88,649	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,650};651static int jz4755_lcd_8bit_pins[] = {652	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,653	0x72, 0x73, 0x74,654};655static int jz4755_lcd_16bit_pins[] = {656	0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,657};658static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, };659static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, };660static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };661static int jz4755_lcd_generic_pins[] = { 0x75, };662static int jz4755_nand_cs1_pins[] = { 0x55, };663static int jz4755_nand_cs2_pins[] = { 0x56, };664static int jz4755_nand_cs3_pins[] = { 0x57, };665static int jz4755_nand_cs4_pins[] = { 0x58, };666static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };667static int jz4755_pwm_pwm0_pins[] = { 0x94, };668static int jz4755_pwm_pwm1_pins[] = { 0xab, };669static int jz4755_pwm_pwm2_pins[] = { 0x96, };670static int jz4755_pwm_pwm3_pins[] = { 0x97, };671static int jz4755_pwm_pwm4_pins[] = { 0x98, };672static int jz4755_pwm_pwm5_pins[] = { 0x99, };673 674static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };675static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };676static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, };677 678static const struct group_desc jz4755_groups[] = {679	INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),680	INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),681	INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),682	INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),683	INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),684	INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),685	INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),686	INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),687	INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),688	INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),689	INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),690	INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),691	INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),692	INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),693	INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),694	INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),695	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,696				jz4755_mmc0_1bit_funcs),697	INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,698				jz4755_mmc0_4bit_funcs),699	INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),700	INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),701	INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),702	INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),703	INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),704	INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),705	INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),706	INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,707				jz4755_lcd_24bit_funcs),708	INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),709	INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),710	INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),711	INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),712	INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),713	INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),714	INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),715	INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0),716	INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1),717	INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0),718	INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0),719	INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0),720	INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0),721};722 723static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };724static const char *jz4755_uart1_groups[] = { "uart1-data", };725static const char *jz4755_uart2_groups[] = { "uart2-data", };726static const char *jz4755_ssi_groups[] = {727	"ssi-dt-b", "ssi-dt-f",728	"ssi-dr-b", "ssi-dr-f",729	"ssi-clk-b", "ssi-clk-f",730	"ssi-gpc-b", "ssi-gpc-f",731	"ssi-ce0-b", "ssi-ce0-f",732	"ssi-ce1-b", "ssi-ce1-f",733};734static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };735static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };736static const char *jz4755_i2c_groups[] = { "i2c-data", };737static const char *jz4755_cim_groups[] = { "cim-data", };738static const char *jz4755_lcd_groups[] = {739	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",740	"lcd-special", "lcd-generic",741};742static const char *jz4755_nand_groups[] = {743	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",744};745static const char *jz4755_pwm0_groups[] = { "pwm0", };746static const char *jz4755_pwm1_groups[] = { "pwm1", };747static const char *jz4755_pwm2_groups[] = { "pwm2", };748static const char *jz4755_pwm3_groups[] = { "pwm3", };749static const char *jz4755_pwm4_groups[] = { "pwm4", };750static const char *jz4755_pwm5_groups[] = { "pwm5", };751 752static const struct function_desc jz4755_functions[] = {753	INGENIC_PIN_FUNCTION("uart0", jz4755_uart0),754	INGENIC_PIN_FUNCTION("uart1", jz4755_uart1),755	INGENIC_PIN_FUNCTION("uart2", jz4755_uart2),756	INGENIC_PIN_FUNCTION("ssi", jz4755_ssi),757	INGENIC_PIN_FUNCTION("mmc0", jz4755_mmc0),758	INGENIC_PIN_FUNCTION("mmc1", jz4755_mmc1),759	INGENIC_PIN_FUNCTION("i2c", jz4755_i2c),760	INGENIC_PIN_FUNCTION("cim", jz4755_cim),761	INGENIC_PIN_FUNCTION("lcd", jz4755_lcd),762	INGENIC_PIN_FUNCTION("nand", jz4755_nand),763	INGENIC_PIN_FUNCTION("pwm0", jz4755_pwm0),764	INGENIC_PIN_FUNCTION("pwm1", jz4755_pwm1),765	INGENIC_PIN_FUNCTION("pwm2", jz4755_pwm2),766	INGENIC_PIN_FUNCTION("pwm3", jz4755_pwm3),767	INGENIC_PIN_FUNCTION("pwm4", jz4755_pwm4),768	INGENIC_PIN_FUNCTION("pwm5", jz4755_pwm5),769};770 771static const struct ingenic_chip_info jz4755_chip_info = {772	.num_chips = 6,773	.reg_offset = 0x100,774	.version = ID_JZ4755,775	.groups = jz4755_groups,776	.num_groups = ARRAY_SIZE(jz4755_groups),777	.functions = jz4755_functions,778	.num_functions = ARRAY_SIZE(jz4755_functions),779	.pull_ups = jz4755_pull_ups,780	.pull_downs = jz4755_pull_downs,781};782 783static const u32 jz4760_pull_ups[6] = {784	0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f,785};786 787static const u32 jz4760_pull_downs[6] = {788	0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,789};790 791static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };792static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };793static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };794static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };795static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };796static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };797static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };798static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };799static int jz4760_ssi0_dt_a_pins[] = { 0x15, };800static int jz4760_ssi0_dt_b_pins[] = { 0x35, };801static int jz4760_ssi0_dt_d_pins[] = { 0x75, };802static int jz4760_ssi0_dt_e_pins[] = { 0x91, };803static int jz4760_ssi0_dr_a_pins[] = { 0x14, };804static int jz4760_ssi0_dr_b_pins[] = { 0x34, };805static int jz4760_ssi0_dr_d_pins[] = { 0x74, };806static int jz4760_ssi0_dr_e_pins[] = { 0x8e, };807static int jz4760_ssi0_clk_a_pins[] = { 0x12, };808static int jz4760_ssi0_clk_b_pins[] = { 0x3c, };809static int jz4760_ssi0_clk_d_pins[] = { 0x78, };810static int jz4760_ssi0_clk_e_pins[] = { 0x8f, };811static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, };812static int jz4760_ssi0_gpc_d_pins[] = { 0x76, };813static int jz4760_ssi0_gpc_e_pins[] = { 0x93, };814static int jz4760_ssi0_ce0_a_pins[] = { 0x13, };815static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, };816static int jz4760_ssi0_ce0_d_pins[] = { 0x79, };817static int jz4760_ssi0_ce0_e_pins[] = { 0x90, };818static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, };819static int jz4760_ssi0_ce1_d_pins[] = { 0x77, };820static int jz4760_ssi0_ce1_e_pins[] = { 0x92, };821static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, };822static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, };823static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, };824static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, };825static int jz4760_ssi1_dt_e_pins[] = { 0x91, };826static int jz4760_ssi1_dt_f_pins[] = { 0xa3, };827static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, };828static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, };829static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, };830static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, };831static int jz4760_ssi1_dr_e_pins[] = { 0x8e, };832static int jz4760_ssi1_dr_f_pins[] = { 0xa0, };833static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, };834static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, };835static int jz4760_ssi1_clk_d_pins[] = { 0x78, };836static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, };837static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, };838static int jz4760_ssi1_clk_f_pins[] = { 0xa2, };839static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, };840static int jz4760_ssi1_gpc_d_pins[] = { 0x76, };841static int jz4760_ssi1_gpc_e_pins[] = { 0x93, };842static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, };843static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, };844static int jz4760_ssi1_ce0_d_pins[] = { 0x79, };845static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, };846static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, };847static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, };848static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, };849static int jz4760_ssi1_ce1_d_pins[] = { 0x77, };850static int jz4760_ssi1_ce1_e_pins[] = { 0x92, };851static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };852static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };853static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };854static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };855static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };856static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };857static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };858static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };859static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };860static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };861static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };862static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };863static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };864static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };865static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };866static int jz4760_nemc_8bit_data_pins[] = {867	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,868};869static int jz4760_nemc_16bit_data_pins[] = {870	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,871};872static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };873static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };874static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };875static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };876static int jz4760_nemc_wait_pins[] = { 0x1b, };877static int jz4760_nemc_cs1_pins[] = { 0x15, };878static int jz4760_nemc_cs2_pins[] = { 0x16, };879static int jz4760_nemc_cs3_pins[] = { 0x17, };880static int jz4760_nemc_cs4_pins[] = { 0x18, };881static int jz4760_nemc_cs5_pins[] = { 0x19, };882static int jz4760_nemc_cs6_pins[] = { 0x1a, };883static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };884static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };885static int jz4760_cim_pins[] = {886	0x26, 0x27, 0x28, 0x29,887	0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,888};889static int jz4760_lcd_8bit_pins[] = {890	0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c,891	0x4d, 0x52, 0x53,892};893static int jz4760_lcd_16bit_pins[] = {894	0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,895};896static int jz4760_lcd_18bit_pins[] = {897	0x5a, 0x5b,898};899static int jz4760_lcd_24bit_pins[] = {900	0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,901};902static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };903static int jz4760_lcd_generic_pins[] = { 0x49, };904static int jz4760_pwm_pwm0_pins[] = { 0x80, };905static int jz4760_pwm_pwm1_pins[] = { 0x81, };906static int jz4760_pwm_pwm2_pins[] = { 0x82, };907static int jz4760_pwm_pwm3_pins[] = { 0x83, };908static int jz4760_pwm_pwm4_pins[] = { 0x84, };909static int jz4760_pwm_pwm5_pins[] = { 0x85, };910static int jz4760_pwm_pwm6_pins[] = { 0x6a, };911static int jz4760_pwm_pwm7_pins[] = { 0x6b, };912static int jz4760_otg_pins[] = { 0x8a, };913 914static u8 jz4760_uart3_data_funcs[] = { 0, 1, };915static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };916 917static const struct group_desc jz4760_groups[] = {918	INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),919	INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),920	INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),921	INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),922	INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),923	INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),924	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,925				jz4760_uart3_data_funcs),926	INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),927	INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),928	INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),929	INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),930	INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),931	INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),932	INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),933	INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),934	INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),935	INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),936	INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),937	INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),938	INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),939	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),940	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),941	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),942	INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),943	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),944	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),945	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),946	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),947	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),948	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),949	INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),950	INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),951	INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),952	INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),953	INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),954	INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),955	INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),956	INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),957	INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),958	INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),959	INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),960	INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),961	INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),962	INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),963	INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),964	INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),965	INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),966	INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),967	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),968	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),969	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),970	INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),971	INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),972	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),973	INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),974	INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),975	INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),976	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),977	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),978	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),979	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,980				jz4760_mmc0_1bit_a_funcs),981	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),982	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),983	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),984	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),985	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),986	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),987	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),988	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),989	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),990	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),991	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),992	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),993	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),994	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),995	INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),996	INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),997	INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),998	INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),999	INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),1000	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),1001	INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),1002	INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),1003	INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),1004	INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),1005	INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),1006	INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),1007	INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),1008	INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),1009	INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),1010	INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),1011	INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),1012	INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),1013	INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),1014	INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),1015	INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),1016	INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),1017	INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),1018	INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),1019	INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),1020	INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0),1021	INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0),1022	INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),1023	INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),1024	INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),1025	INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),1026};1027 1028static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };1029static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };1030static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };1031static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };1032static const char *jz4760_ssi0_groups[] = {1033	"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",1034	"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",1035	"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",1036	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",1037	"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",1038	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",1039};1040static const char *jz4760_ssi1_groups[] = {1041	"ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",1042	"ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",1043	"ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",1044	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",1045	"ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",1046	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",1047};1048static const char *jz4760_mmc0_groups[] = {1049	"mmc0-1bit-a", "mmc0-4bit-a",1050	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",1051};1052static const char *jz4760_mmc1_groups[] = {1053	"mmc1-1bit-d", "mmc1-4bit-d",1054	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",1055};1056static const char *jz4760_mmc2_groups[] = {1057	"mmc2-1bit-b", "mmc2-4bit-b",1058	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",1059};1060static const char *jz4760_nemc_groups[] = {1061	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",1062	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",1063};1064static const char *jz4760_cs1_groups[] = { "nemc-cs1", };1065static const char *jz4760_cs2_groups[] = { "nemc-cs2", };1066static const char *jz4760_cs3_groups[] = { "nemc-cs3", };1067static const char *jz4760_cs4_groups[] = { "nemc-cs4", };1068static const char *jz4760_cs5_groups[] = { "nemc-cs5", };1069static const char *jz4760_cs6_groups[] = { "nemc-cs6", };1070static const char *jz4760_i2c0_groups[] = { "i2c0-data", };1071static const char *jz4760_i2c1_groups[] = { "i2c1-data", };1072static const char *jz4760_cim_groups[] = { "cim-data", };1073static const char *jz4760_lcd_groups[] = {1074	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",1075	"lcd-special", "lcd-generic",1076};1077static const char *jz4760_pwm0_groups[] = { "pwm0", };1078static const char *jz4760_pwm1_groups[] = { "pwm1", };1079static const char *jz4760_pwm2_groups[] = { "pwm2", };1080static const char *jz4760_pwm3_groups[] = { "pwm3", };1081static const char *jz4760_pwm4_groups[] = { "pwm4", };1082static const char *jz4760_pwm5_groups[] = { "pwm5", };1083static const char *jz4760_pwm6_groups[] = { "pwm6", };1084static const char *jz4760_pwm7_groups[] = { "pwm7", };1085static const char *jz4760_otg_groups[] = { "otg-vbus", };1086 1087static const struct function_desc jz4760_functions[] = {1088	INGENIC_PIN_FUNCTION("uart0", jz4760_uart0),1089	INGENIC_PIN_FUNCTION("uart1", jz4760_uart1),1090	INGENIC_PIN_FUNCTION("uart2", jz4760_uart2),1091	INGENIC_PIN_FUNCTION("uart3", jz4760_uart3),1092	INGENIC_PIN_FUNCTION("ssi0", jz4760_ssi0),1093	INGENIC_PIN_FUNCTION("ssi1", jz4760_ssi1),1094	INGENIC_PIN_FUNCTION("mmc0", jz4760_mmc0),1095	INGENIC_PIN_FUNCTION("mmc1", jz4760_mmc1),1096	INGENIC_PIN_FUNCTION("mmc2", jz4760_mmc2),1097	INGENIC_PIN_FUNCTION("nemc", jz4760_nemc),1098	INGENIC_PIN_FUNCTION("nemc-cs1", jz4760_cs1),1099	INGENIC_PIN_FUNCTION("nemc-cs2", jz4760_cs2),1100	INGENIC_PIN_FUNCTION("nemc-cs3", jz4760_cs3),1101	INGENIC_PIN_FUNCTION("nemc-cs4", jz4760_cs4),1102	INGENIC_PIN_FUNCTION("nemc-cs5", jz4760_cs5),1103	INGENIC_PIN_FUNCTION("nemc-cs6", jz4760_cs6),1104	INGENIC_PIN_FUNCTION("i2c0", jz4760_i2c0),1105	INGENIC_PIN_FUNCTION("i2c1", jz4760_i2c1),1106	INGENIC_PIN_FUNCTION("cim", jz4760_cim),1107	INGENIC_PIN_FUNCTION("lcd", jz4760_lcd),1108	INGENIC_PIN_FUNCTION("pwm0", jz4760_pwm0),1109	INGENIC_PIN_FUNCTION("pwm1", jz4760_pwm1),1110	INGENIC_PIN_FUNCTION("pwm2", jz4760_pwm2),1111	INGENIC_PIN_FUNCTION("pwm3", jz4760_pwm3),1112	INGENIC_PIN_FUNCTION("pwm4", jz4760_pwm4),1113	INGENIC_PIN_FUNCTION("pwm5", jz4760_pwm5),1114	INGENIC_PIN_FUNCTION("pwm6", jz4760_pwm6),1115	INGENIC_PIN_FUNCTION("pwm7", jz4760_pwm7),1116	INGENIC_PIN_FUNCTION("otg", jz4760_otg),1117};1118 1119static const struct ingenic_chip_info jz4760_chip_info = {1120	.num_chips = 6,1121	.reg_offset = 0x100,1122	.version = ID_JZ4760,1123	.groups = jz4760_groups,1124	.num_groups = ARRAY_SIZE(jz4760_groups),1125	.functions = jz4760_functions,1126	.num_functions = ARRAY_SIZE(jz4760_functions),1127	.pull_ups = jz4760_pull_ups,1128	.pull_downs = jz4760_pull_downs,1129};1130 1131static const u32 jz4770_pull_ups[6] = {1132	0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f,1133};1134 1135static const u32 jz4770_pull_downs[6] = {1136	0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0,1137};1138 1139static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };1140static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };1141static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };1142static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };1143static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };1144static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };1145static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };1146static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };1147static int jz4770_ssi0_dt_a_pins[] = { 0x15, };1148static int jz4770_ssi0_dt_b_pins[] = { 0x35, };1149static int jz4770_ssi0_dt_d_pins[] = { 0x75, };1150static int jz4770_ssi0_dt_e_pins[] = { 0x91, };1151static int jz4770_ssi0_dr_a_pins[] = { 0x14, };1152static int jz4770_ssi0_dr_b_pins[] = { 0x34, };1153static int jz4770_ssi0_dr_d_pins[] = { 0x74, };1154static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };1155static int jz4770_ssi0_clk_a_pins[] = { 0x12, };1156static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };1157static int jz4770_ssi0_clk_d_pins[] = { 0x78, };1158static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };1159static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };1160static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };1161static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };1162static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };1163static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };1164static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };1165static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };1166static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };1167static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };1168static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };1169static int jz4770_ssi1_dt_b_pins[] = { 0x35, };1170static int jz4770_ssi1_dt_d_pins[] = { 0x75, };1171static int jz4770_ssi1_dt_e_pins[] = { 0x91, };1172static int jz4770_ssi1_dr_b_pins[] = { 0x34, };1173static int jz4770_ssi1_dr_d_pins[] = { 0x74, };1174static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };1175static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };1176static int jz4770_ssi1_clk_d_pins[] = { 0x78, };1177static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };1178static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };1179static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };1180static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };1181static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };1182static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };1183static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };1184static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };1185static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };1186static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };1187static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };1188static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };1189static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };1190static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };1191static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };1192static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };1193static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };1194static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };1195static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };1196static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };1197static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };1198static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };1199static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };1200static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };1201static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };1202static int jz4770_nemc_8bit_data_pins[] = {1203	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,1204};1205static int jz4770_nemc_16bit_data_pins[] = {1206	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,1207};1208static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };1209static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };1210static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };1211static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };1212static int jz4770_nemc_wait_pins[] = { 0x1b, };1213static int jz4770_nemc_cs1_pins[] = { 0x15, };1214static int jz4770_nemc_cs2_pins[] = { 0x16, };1215static int jz4770_nemc_cs3_pins[] = { 0x17, };1216static int jz4770_nemc_cs4_pins[] = { 0x18, };1217static int jz4770_nemc_cs5_pins[] = { 0x19, };1218static int jz4770_nemc_cs6_pins[] = { 0x1a, };1219static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };1220static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };1221static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };1222static int jz4770_cim_8bit_pins[] = {1223	0x26, 0x27, 0x28, 0x29,1224	0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,1225};1226static int jz4770_cim_12bit_pins[] = {1227	0x32, 0x33, 0xb0, 0xb1,1228};1229static int jz4770_lcd_8bit_pins[] = {1230	0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,1231	0x48, 0x52, 0x53,1232};1233static int jz4770_lcd_16bit_pins[] = {1234	0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,1235};1236static int jz4770_lcd_18bit_pins[] = {1237	0x5a, 0x5b,1238};1239static int jz4770_lcd_24bit_pins[] = {1240	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,1241	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,1242	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,1243	0x58, 0x59, 0x5a, 0x5b,1244};1245static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };1246static int jz4770_lcd_generic_pins[] = { 0x49, };1247static int jz4770_pwm_pwm0_pins[] = { 0x80, };1248static int jz4770_pwm_pwm1_pins[] = { 0x81, };1249static int jz4770_pwm_pwm2_pins[] = { 0x82, };1250static int jz4770_pwm_pwm3_pins[] = { 0x83, };1251static int jz4770_pwm_pwm4_pins[] = { 0x84, };1252static int jz4770_pwm_pwm5_pins[] = { 0x85, };1253static int jz4770_pwm_pwm6_pins[] = { 0x6a, };1254static int jz4770_pwm_pwm7_pins[] = { 0x6b, };1255static int jz4770_mac_rmii_pins[] = {1256	0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,1257};1258static int jz4770_mac_mii_pins[] = {1259	0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,1260};1261 1262static const struct group_desc jz4770_groups[] = {1263	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),1264	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),1265	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),1266	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),1267	INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),1268	INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),1269	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,1270				jz4760_uart3_data_funcs),1271	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),1272	INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),1273	INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),1274	INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),1275	INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),1276	INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),1277	INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),1278	INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),1279	INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),1280	INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),1281	INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),1282	INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),1283	INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),1284	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),1285	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),1286	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),1287	INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),1288	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),1289	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),1290	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),1291	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),1292	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),1293	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),1294	INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),1295	INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),1296	INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),1297	INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),1298	INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),1299	INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),1300	INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),1301	INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),1302	INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),1303	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),1304	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),1305	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),1306	INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),1307	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),1308	INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),1309	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),1310	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),1311	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),1312	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,1313				jz4760_mmc0_1bit_a_funcs),1314	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),1315	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),1316	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),1317	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),1318	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),1319	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),1320	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),1321	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),1322	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),1323	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),1324	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),1325	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),1326	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),1327	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),1328	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),1329	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),1330	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),1331	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),1332	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),1333	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),1334	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),1335	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),1336	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),1337	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),1338	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),1339	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),1340	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),1341	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),1342	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),1343	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),1344	INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),1345	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),1346	INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),1347	INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),1348	INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),1349	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),1350	INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),1351	INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),1352	INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),1353	INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),1354	INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),1355	INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),1356	INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),1357	INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),1358	INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),1359	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),1360	INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),1361	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),1362	INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),1363};1364 1365static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };1366static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };1367static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };1368static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };1369static const char *jz4770_ssi0_groups[] = {1370	"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",1371	"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",1372	"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",1373	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",1374	"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",1375	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",1376};1377static const char *jz4770_ssi1_groups[] = {1378	"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",1379	"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",1380	"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",1381	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",1382	"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",1383	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",1384};1385static const char *jz4770_mmc0_groups[] = {1386	"mmc0-1bit-a", "mmc0-4bit-a",1387	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",1388};1389static const char *jz4770_mmc1_groups[] = {1390	"mmc1-1bit-d", "mmc1-4bit-d",1391	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",1392};1393static const char *jz4770_mmc2_groups[] = {1394	"mmc2-1bit-b", "mmc2-4bit-b",1395	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",1396};1397static const char *jz4770_nemc_groups[] = {1398	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",1399	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",1400};1401static const char *jz4770_cs1_groups[] = { "nemc-cs1", };1402static const char *jz4770_cs2_groups[] = { "nemc-cs2", };1403static const char *jz4770_cs3_groups[] = { "nemc-cs3", };1404static const char *jz4770_cs4_groups[] = { "nemc-cs4", };1405static const char *jz4770_cs5_groups[] = { "nemc-cs5", };1406static const char *jz4770_cs6_groups[] = { "nemc-cs6", };1407static const char *jz4770_i2c0_groups[] = { "i2c0-data", };1408static const char *jz4770_i2c1_groups[] = { "i2c1-data", };1409static const char *jz4770_i2c2_groups[] = { "i2c2-data", };1410static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };1411static const char *jz4770_lcd_groups[] = {1412	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",1413	"lcd-special", "lcd-generic",1414};1415static const char *jz4770_pwm0_groups[] = { "pwm0", };1416static const char *jz4770_pwm1_groups[] = { "pwm1", };1417static const char *jz4770_pwm2_groups[] = { "pwm2", };1418static const char *jz4770_pwm3_groups[] = { "pwm3", };1419static const char *jz4770_pwm4_groups[] = { "pwm4", };1420static const char *jz4770_pwm5_groups[] = { "pwm5", };1421static const char *jz4770_pwm6_groups[] = { "pwm6", };1422static const char *jz4770_pwm7_groups[] = { "pwm7", };1423static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };1424 1425static const struct function_desc jz4770_functions[] = {1426	INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),1427	INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),1428	INGENIC_PIN_FUNCTION("uart2", jz4770_uart2),1429	INGENIC_PIN_FUNCTION("uart3", jz4770_uart3),1430	INGENIC_PIN_FUNCTION("ssi0", jz4770_ssi0),1431	INGENIC_PIN_FUNCTION("ssi1", jz4770_ssi1),1432	INGENIC_PIN_FUNCTION("mmc0", jz4770_mmc0),1433	INGENIC_PIN_FUNCTION("mmc1", jz4770_mmc1),1434	INGENIC_PIN_FUNCTION("mmc2", jz4770_mmc2),1435	INGENIC_PIN_FUNCTION("nemc", jz4770_nemc),1436	INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),1437	INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),1438	INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),1439	INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),1440	INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),1441	INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),1442	INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0),1443	INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1),1444	INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2),1445	INGENIC_PIN_FUNCTION("cim", jz4770_cim),1446	INGENIC_PIN_FUNCTION("lcd", jz4770_lcd),1447	INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0),1448	INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1),1449	INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2),1450	INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3),1451	INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4),1452	INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5),1453	INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6),1454	INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7),1455	INGENIC_PIN_FUNCTION("mac", jz4770_mac),1456	INGENIC_PIN_FUNCTION("otg", jz4760_otg),1457};1458 1459static const struct ingenic_chip_info jz4770_chip_info = {1460	.num_chips = 6,1461	.reg_offset = 0x100,1462	.version = ID_JZ4770,1463	.groups = jz4770_groups,1464	.num_groups = ARRAY_SIZE(jz4770_groups),1465	.functions = jz4770_functions,1466	.num_functions = ARRAY_SIZE(jz4770_functions),1467	.pull_ups = jz4770_pull_ups,1468	.pull_downs = jz4770_pull_downs,1469};1470 1471static const u32 jz4775_pull_ups[7] = {1472	0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0,1473};1474 1475static const u32 jz4775_pull_downs[7] = {1476	0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00,1477};1478 1479static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, };1480static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, };1481static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, };1482static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, };1483static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, };1484static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, };1485static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, };1486static int jz4775_ssi_dt_a_pins[] = { 0x13, };1487static int jz4775_ssi_dt_d_pins[] = { 0x75, };1488static int jz4775_ssi_dr_a_pins[] = { 0x14, };1489static int jz4775_ssi_dr_d_pins[] = { 0x74, };1490static int jz4775_ssi_clk_a_pins[] = { 0x12, };1491static int jz4775_ssi_clk_d_pins[] = { 0x78, };1492static int jz4775_ssi_gpc_pins[] = { 0x76, };1493static int jz4775_ssi_ce0_a_pins[] = { 0x17, };1494static int jz4775_ssi_ce0_d_pins[] = { 0x79, };1495static int jz4775_ssi_ce1_pins[] = { 0x77, };1496static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };1497static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };1498static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, };1499static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };1500static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };1501static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };1502static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };1503static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };1504static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };1505static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };1506static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };1507static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };1508static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };1509static int jz4775_nemc_8bit_data_pins[] = {1510	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,1511};1512static int jz4775_nemc_16bit_data_pins[] = {1513	0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1,1514};1515static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, };1516static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };1517static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, };1518static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, };1519static int jz4775_nemc_wait_pins[] = { 0x1b, };1520static int jz4775_nemc_cs1_pins[] = { 0x15, };1521static int jz4775_nemc_cs2_pins[] = { 0x16, };1522static int jz4775_nemc_cs3_pins[] = { 0x17, };1523static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, };1524static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, };1525static int jz4775_i2c2_pins[] = { 0x80, 0x83, };1526static int jz4775_i2s_data_tx_pins[] = { 0xa3, };1527static int jz4775_i2s_data_rx_pins[] = { 0xa2, };1528static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, };1529static int jz4775_i2s_sysclk_pins[] = { 0x83, };1530static int jz4775_dmic_pins[] = { 0xaa, 0xab, };1531static int jz4775_cim_pins[] = {1532	0x26, 0x27, 0x28, 0x29,1533	0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,1534};1535static int jz4775_lcd_8bit_pins[] = {1536	0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,1537	0x48, 0x52, 0x53,1538};1539static int jz4775_lcd_16bit_pins[] = {1540	0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,1541};1542static int jz4775_lcd_18bit_pins[] = {1543	0x5a, 0x5b,1544};1545static int jz4775_lcd_24bit_pins[] = {1546	0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,1547};1548static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };1549static int jz4775_lcd_generic_pins[] = { 0x49, };1550static int jz4775_pwm_pwm0_pins[] = { 0x80, };1551static int jz4775_pwm_pwm1_pins[] = { 0x81, };1552static int jz4775_pwm_pwm2_pins[] = { 0x82, };1553static int jz4775_pwm_pwm3_pins[] = { 0x83, };1554static int jz4775_mac_rmii_pins[] = {1555	0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,1556};1557static int jz4775_mac_mii_pins[] = {1558	0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,1559};1560static int jz4775_mac_rgmii_pins[] = {1561	0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4,1562	0xad, 0xae, 0xa7, 0xa6,1563};1564static int jz4775_mac_gmii_pins[] = {1565	0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a,1566	0xa8, 0x28, 0x24, 0xaf,1567};1568static int jz4775_otg_pins[] = { 0x8a, };1569 1570static u8 jz4775_uart3_data_funcs[] = { 0, 1, };1571static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, };1572static u8 jz4775_mac_rgmii_funcs[] = {1573	0, 1, 1, 0, 0, 0, 1, 1, 0, 0,1574	0, 0, 0, 0,1575};1576static u8 jz4775_mac_gmii_funcs[] = {1577	1, 1, 1, 1, 1, 1, 1, 1,1578	0, 1, 1, 0,1579};1580 1581static const struct group_desc jz4775_groups[] = {1582	INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),1583	INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),1584	INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),1585	INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),1586	INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),1587	INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),1588	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,1589				jz4775_uart3_data_funcs),1590	INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),1591	INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),1592	INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),1593	INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),1594	INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),1595	INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),1596	INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),1597	INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),1598	INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),1599	INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),1600	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),1601	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),1602	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),1603	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),1604	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),1605	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),1606	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),1607	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),1608	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),1609	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),1610	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),1611	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),1612	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),1613	INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),1614	INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),1615	INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),1616	INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),1617	INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),1618	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),1619	INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),1620	INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),1621	INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),1622	INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),1623	INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),1624	INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),1625	INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),1626	INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),1627	INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),1628	INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),1629	INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),1630	INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1),1631	INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),1632	INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),1633	INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),1634	INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),1635	INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),1636	INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),1637	INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),1638	INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0),1639	INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0),1640	INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0),1641	INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0),1642	INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),1643	INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,1644				jz4775_mac_mii_funcs),1645	INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,1646				jz4775_mac_rgmii_funcs),1647	INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,1648				jz4775_mac_gmii_funcs),1649	INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),1650};1651 1652static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };1653static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };1654static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };1655static const char *jz4775_uart3_groups[] = { "uart3-data", };1656static const char *jz4775_ssi_groups[] = {1657	"ssi-dt-a", "ssi-dt-d",1658	"ssi-dr-a", "ssi-dr-d",1659	"ssi-clk-a", "ssi-clk-d",1660	"ssi-gpc",1661	"ssi-ce0-a", "ssi-ce0-d",1662	"ssi-ce1",1663};1664static const char *jz4775_mmc0_groups[] = {1665	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",1666	"mmc0-1bit-e", "mmc0-4bit-e",1667};1668static const char *jz4775_mmc1_groups[] = {1669	"mmc1-1bit-d", "mmc1-4bit-d",1670	"mmc1-1bit-e", "mmc1-4bit-e",1671};1672static const char *jz4775_mmc2_groups[] = {1673	"mmc2-1bit-b", "mmc2-4bit-b",1674	"mmc2-1bit-e", "mmc2-4bit-e",1675};1676static const char *jz4775_nemc_groups[] = {1677	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",1678	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",1679};1680static const char *jz4775_cs1_groups[] = { "nemc-cs1", };1681static const char *jz4775_cs2_groups[] = { "nemc-cs2", };1682static const char *jz4775_cs3_groups[] = { "nemc-cs3", };1683static const char *jz4775_i2c0_groups[] = { "i2c0-data", };1684static const char *jz4775_i2c1_groups[] = { "i2c1-data", };1685static const char *jz4775_i2c2_groups[] = { "i2c2-data", };1686static const char *jz4775_i2s_groups[] = {1687	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",1688};1689static const char *jz4775_dmic_groups[] = { "dmic", };1690static const char *jz4775_cim_groups[] = { "cim-data", };1691static const char *jz4775_lcd_groups[] = {1692	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",1693	"lcd-special", "lcd-generic",1694};1695static const char *jz4775_pwm0_groups[] = { "pwm0", };1696static const char *jz4775_pwm1_groups[] = { "pwm1", };1697static const char *jz4775_pwm2_groups[] = { "pwm2", };1698static const char *jz4775_pwm3_groups[] = { "pwm3", };1699static const char *jz4775_mac_groups[] = {1700	"mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",1701};1702static const char *jz4775_otg_groups[] = { "otg-vbus", };1703 1704static const struct function_desc jz4775_functions[] = {1705	INGENIC_PIN_FUNCTION("uart0", jz4775_uart0),1706	INGENIC_PIN_FUNCTION("uart1", jz4775_uart1),1707	INGENIC_PIN_FUNCTION("uart2", jz4775_uart2),1708	INGENIC_PIN_FUNCTION("uart3", jz4775_uart3),1709	INGENIC_PIN_FUNCTION("ssi", jz4775_ssi),1710	INGENIC_PIN_FUNCTION("mmc0", jz4775_mmc0),1711	INGENIC_PIN_FUNCTION("mmc1", jz4775_mmc1),1712	INGENIC_PIN_FUNCTION("mmc2", jz4775_mmc2),1713	INGENIC_PIN_FUNCTION("nemc", jz4775_nemc),1714	INGENIC_PIN_FUNCTION("nemc-cs1", jz4775_cs1),1715	INGENIC_PIN_FUNCTION("nemc-cs2", jz4775_cs2),1716	INGENIC_PIN_FUNCTION("nemc-cs3", jz4775_cs3),1717	INGENIC_PIN_FUNCTION("i2c0", jz4775_i2c0),1718	INGENIC_PIN_FUNCTION("i2c1", jz4775_i2c1),1719	INGENIC_PIN_FUNCTION("i2c2", jz4775_i2c2),1720	INGENIC_PIN_FUNCTION("i2s", jz4775_i2s),1721	INGENIC_PIN_FUNCTION("dmic", jz4775_dmic),1722	INGENIC_PIN_FUNCTION("cim", jz4775_cim),1723	INGENIC_PIN_FUNCTION("lcd", jz4775_lcd),1724	INGENIC_PIN_FUNCTION("pwm0", jz4775_pwm0),1725	INGENIC_PIN_FUNCTION("pwm1", jz4775_pwm1),1726	INGENIC_PIN_FUNCTION("pwm2", jz4775_pwm2),1727	INGENIC_PIN_FUNCTION("pwm3", jz4775_pwm3),1728	INGENIC_PIN_FUNCTION("mac", jz4775_mac),1729	INGENIC_PIN_FUNCTION("otg", jz4775_otg),1730};1731 1732static const struct ingenic_chip_info jz4775_chip_info = {1733	.num_chips = 7,1734	.reg_offset = 0x100,1735	.version = ID_JZ4775,1736	.groups = jz4775_groups,1737	.num_groups = ARRAY_SIZE(jz4775_groups),1738	.functions = jz4775_functions,1739	.num_functions = ARRAY_SIZE(jz4775_functions),1740	.pull_ups = jz4775_pull_ups,1741	.pull_downs = jz4775_pull_downs,1742};1743 1744static const u32 jz4780_pull_ups[6] = {1745	0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,1746};1747 1748static const u32 jz4780_pull_downs[6] = {1749	0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,1750};1751 1752static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };1753static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };1754static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };1755static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };1756static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };1757static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };1758static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };1759static int jz4780_ssi0_dt_d_pins[] = { 0x79, };1760static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };1761static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };1762static int jz4780_ssi0_dr_b_pins[] = { 0x34, };1763static int jz4780_ssi0_dr_d_pins[] = { 0x74, };1764static int jz4780_ssi0_clk_a_pins[] = { 0x12, };1765static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };1766static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };1767static int jz4780_ssi0_clk_d_pins[] = { 0x78, };1768static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };1769static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };1770static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };1771static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };1772static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };1773static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };1774static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };1775static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };1776static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };1777static int jz4780_ssi1_dt_d_pins[] = { 0x79, };1778static int jz4780_ssi1_dr_b_pins[] = { 0x34, };1779static int jz4780_ssi1_dr_d_pins[] = { 0x74, };1780static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };1781static int jz4780_ssi1_clk_d_pins[] = { 0x78, };1782static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };1783static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };1784static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };1785static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };1786static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };1787static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };1788static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };1789static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };1790static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };1791static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };1792static int jz4780_i2s_data_tx_pins[] = { 0x87, };1793static int jz4780_i2s_data_rx_pins[] = { 0x86, };1794static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };1795static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };1796static int jz4780_i2s_sysclk_pins[] = { 0x85, };1797static int jz4780_dmic_pins[] = { 0x32, 0x33, };1798static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };1799 1800static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };1801 1802static const struct group_desc jz4780_groups[] = {1803	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),1804	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),1805	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),1806	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),1807	INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),1808	INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),1809	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,1810				jz4760_uart3_data_funcs),1811	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),1812	INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),1813	INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),1814	INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),1815	INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),1816	INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),1817	INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),1818	INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),1819	INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),1820	INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),1821	INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),1822	INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),1823	INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),1824	INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),1825	INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),1826	INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),1827	INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),1828	INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),1829	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),1830	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),1831	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),1832	INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),1833	INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),1834	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),1835	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),1836	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),1837	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),1838	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),1839	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),1840	INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),1841	INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),1842	INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),1843	INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),1844	INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),1845	INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),1846	INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),1847	INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),1848	INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),1849	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),1850	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),1851	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),1852	INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),1853	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),1854	INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),1855	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),1856	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),1857	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),1858	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,1859				jz4760_mmc0_1bit_a_funcs),1860	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),1861	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),1862	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),1863	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),1864	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),1865	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),1866	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),1867	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),1868	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),1869	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),1870	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),1871	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),1872	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),1873	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),1874	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),1875	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),1876	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),1877	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),1878	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),1879	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),1880	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),1881	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),1882	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),1883	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),1884	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),1885	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),1886	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),1887	INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),1888	INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),1889	INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),1890	INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),1891	INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),1892	INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,1893				jz4780_i2s_clk_txrx_funcs),1894	INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),1895	INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),1896	INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1),1897	INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),1898	INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),1899	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),1900	INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),1901	INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),1902	INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),1903	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),1904	INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),1905	INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),1906	INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),1907	INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),1908	INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),1909	INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),1910	INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),1911	INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),1912	INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),1913	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),1914};1915 1916static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };1917static const char *jz4780_uart4_groups[] = { "uart4-data", };1918static const char *jz4780_ssi0_groups[] = {1919	"ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",1920	"ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",1921	"ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",1922	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",1923	"ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",1924	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",1925};1926static const char *jz4780_ssi1_groups[] = {1927	"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",1928	"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",1929	"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",1930	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",1931	"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",1932	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",1933};1934static const char *jz4780_mmc0_groups[] = {1935	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",1936	"mmc0-1bit-e", "mmc0-4bit-e",1937};1938static const char *jz4780_mmc1_groups[] = {1939	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",1940};1941static const char *jz4780_mmc2_groups[] = {1942	"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",1943};1944static const char *jz4780_nemc_groups[] = {1945	"nemc-data", "nemc-cle-ale", "nemc-addr",1946	"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",1947};1948static const char *jz4780_i2c3_groups[] = { "i2c3-data", };1949static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };1950static const char *jz4780_i2s_groups[] = {1951	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",1952};1953static const char *jz4780_dmic_groups[] = { "dmic", };1954static const char *jz4780_cim_groups[] = { "cim-data", };1955static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };1956 1957static const struct function_desc jz4780_functions[] = {1958	INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),1959	INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),1960	INGENIC_PIN_FUNCTION("uart2", jz4780_uart2),1961	INGENIC_PIN_FUNCTION("uart3", jz4770_uart3),1962	INGENIC_PIN_FUNCTION("uart4", jz4780_uart4),1963	INGENIC_PIN_FUNCTION("ssi0", jz4780_ssi0),1964	INGENIC_PIN_FUNCTION("ssi1", jz4780_ssi1),1965	INGENIC_PIN_FUNCTION("mmc0", jz4780_mmc0),1966	INGENIC_PIN_FUNCTION("mmc1", jz4780_mmc1),1967	INGENIC_PIN_FUNCTION("mmc2", jz4780_mmc2),1968	INGENIC_PIN_FUNCTION("nemc", jz4780_nemc),1969	INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),1970	INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),1971	INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),1972	INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),1973	INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),1974	INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),1975	INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0),1976	INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1),1977	INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2),1978	INGENIC_PIN_FUNCTION("i2c3", jz4780_i2c3),1979	INGENIC_PIN_FUNCTION("i2c4", jz4780_i2c4),1980	INGENIC_PIN_FUNCTION("i2s", jz4780_i2s),1981	INGENIC_PIN_FUNCTION("dmic", jz4780_dmic),1982	INGENIC_PIN_FUNCTION("cim", jz4780_cim),1983	INGENIC_PIN_FUNCTION("lcd", jz4770_lcd),1984	INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0),1985	INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1),1986	INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2),1987	INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3),1988	INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4),1989	INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5),1990	INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6),1991	INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7),1992	INGENIC_PIN_FUNCTION("hdmi-ddc", jz4780_hdmi_ddc),1993};1994 1995static const struct ingenic_chip_info jz4780_chip_info = {1996	.num_chips = 6,1997	.reg_offset = 0x100,1998	.version = ID_JZ4780,1999	.groups = jz4780_groups,2000	.num_groups = ARRAY_SIZE(jz4780_groups),2001	.functions = jz4780_functions,2002	.num_functions = ARRAY_SIZE(jz4780_functions),2003	.pull_ups = jz4780_pull_ups,2004	.pull_downs = jz4780_pull_downs,2005};2006 2007static const u32 x1000_pull_ups[4] = {2008	0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,2009};2010 2011static const u32 x1000_pull_downs[4] = {2012	0x00000000, 0x02000000, 0x02000000, 0x00000000,2013};2014 2015static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };2016static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };2017static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };2018static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };2019static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };2020static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };2021static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };2022static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, };2023static int x1000_sfc_clk_pins[] = { 0x1a, };2024static int x1000_sfc_ce_pins[] = { 0x1b, };2025static int x1000_ssi_dt_a_22_pins[] = { 0x16, };2026static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };2027static int x1000_ssi_dt_d_pins[] = { 0x62, };2028static int x1000_ssi_dr_a_23_pins[] = { 0x17, };2029static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };2030static int x1000_ssi_dr_d_pins[] = { 0x63, };2031static int x1000_ssi_clk_a_24_pins[] = { 0x18, };2032static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };2033static int x1000_ssi_clk_d_pins[] = { 0x60, };2034static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };2035static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };2036static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };2037static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };2038static int x1000_ssi_ce0_d_pins[] = { 0x61, };2039static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };2040static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };2041static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };2042static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };2043static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };2044static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };2045static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };2046static int x1000_emc_8bit_data_pins[] = {2047	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,2048};2049static int x1000_emc_16bit_data_pins[] = {2050	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,2051};2052static int x1000_emc_addr_pins[] = {2053	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,2054	0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,2055};2056static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };2057static int x1000_emc_wait_pins[] = { 0x34, };2058static int x1000_emc_cs1_pins[] = { 0x32, };2059static int x1000_emc_cs2_pins[] = { 0x33, };2060static int x1000_i2c0_pins[] = { 0x38, 0x37, };2061static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };2062static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };2063static int x1000_i2c2_pins[] = { 0x61, 0x60, };2064static int x1000_i2s_data_tx_pins[] = { 0x24, };2065static int x1000_i2s_data_rx_pins[] = { 0x23, };2066static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };2067static int x1000_i2s_sysclk_pins[] = { 0x20, };2068static int x1000_dmic_if0_pins[] = { 0x35, 0x36, };2069static int x1000_dmic_if1_pins[] = { 0x25, };2070static int x1000_cim_pins[] = {2071	0x08, 0x09, 0x0a, 0x0b,2072	0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,2073};2074static int x1000_lcd_8bit_pins[] = {2075	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,2076	0x30, 0x31, 0x32, 0x33, 0x34,2077};2078static int x1000_lcd_16bit_pins[] = {2079	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,2080};2081static int x1000_pwm_pwm0_pins[] = { 0x59, };2082static int x1000_pwm_pwm1_pins[] = { 0x5a, };2083static int x1000_pwm_pwm2_pins[] = { 0x5b, };2084static int x1000_pwm_pwm3_pins[] = { 0x26, };2085static int x1000_pwm_pwm4_pins[] = { 0x58, };2086static int x1000_mac_pins[] = {2087	0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,2088};2089 2090static const struct group_desc x1000_groups[] = {2091	INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),2092	INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),2093	INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),2094	INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),2095	INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),2096	INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),2097	INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),2098	INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),2099	INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),2100	INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),2101	INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),2102	INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),2103	INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),2104	INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),2105	INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),2106	INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),2107	INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),2108	INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),2109	INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),2110	INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),2111	INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),2112	INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),2113	INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),2114	INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),2115	INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),2116	INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),2117	INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),2118	INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),2119	INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),2120	INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),2121	INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),2122	INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),2123	INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),2124	INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),2125	INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),2126	INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),2127	INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),2128	INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),2129	INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),2130	INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),2131	INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),2132	INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),2133	INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),2134	INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),2135	INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),2136	INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),2137	INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),2138	INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),2139	INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),2140	INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),2141	INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),2142	INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0),2143	INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1),2144	INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1),2145	INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),2146	INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0),2147	INGENIC_PIN_GROUP("mac", x1000_mac, 1),2148};2149 2150static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };2151static const char *x1000_uart1_groups[] = {2152	"uart1-data-a", "uart1-data-d", "uart1-hwflow",2153};2154static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };2155static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };2156static const char *x1000_ssi_groups[] = {2157	"ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",2158	"ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",2159	"ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",2160	"ssi-gpc-a-20", "ssi-gpc-a-31",2161	"ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",2162	"ssi-ce1-a-21", "ssi-ce1-a-30",2163};2164static const char *x1000_mmc0_groups[] = {2165	"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",2166};2167static const char *x1000_mmc1_groups[] = {2168	"mmc1-1bit", "mmc1-4bit",2169};2170static const char *x1000_emc_groups[] = {2171	"emc-8bit-data", "emc-16bit-data",2172	"emc-addr", "emc-rd-we", "emc-wait",2173};2174static const char *x1000_cs1_groups[] = { "emc-cs1", };2175static const char *x1000_cs2_groups[] = { "emc-cs2", };2176static const char *x1000_i2c0_groups[] = { "i2c0-data", };2177static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };2178static const char *x1000_i2c2_groups[] = { "i2c2-data", };2179static const char *x1000_i2s_groups[] = {2180	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",2181};2182static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };2183static const char *x1000_cim_groups[] = { "cim-data", };2184static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };2185static const char *x1000_pwm0_groups[] = { "pwm0", };2186static const char *x1000_pwm1_groups[] = { "pwm1", };2187static const char *x1000_pwm2_groups[] = { "pwm2", };2188static const char *x1000_pwm3_groups[] = { "pwm3", };2189static const char *x1000_pwm4_groups[] = { "pwm4", };2190static const char *x1000_mac_groups[] = { "mac", };2191 2192static const struct function_desc x1000_functions[] = {2193	INGENIC_PIN_FUNCTION("uart0", x1000_uart0),2194	INGENIC_PIN_FUNCTION("uart1", x1000_uart1),2195	INGENIC_PIN_FUNCTION("uart2", x1000_uart2),2196	INGENIC_PIN_FUNCTION("sfc", x1000_sfc),2197	INGENIC_PIN_FUNCTION("ssi", x1000_ssi),2198	INGENIC_PIN_FUNCTION("mmc0", x1000_mmc0),2199	INGENIC_PIN_FUNCTION("mmc1", x1000_mmc1),2200	INGENIC_PIN_FUNCTION("emc", x1000_emc),2201	INGENIC_PIN_FUNCTION("emc-cs1", x1000_cs1),2202	INGENIC_PIN_FUNCTION("emc-cs2", x1000_cs2),2203	INGENIC_PIN_FUNCTION("i2c0", x1000_i2c0),2204	INGENIC_PIN_FUNCTION("i2c1", x1000_i2c1),2205	INGENIC_PIN_FUNCTION("i2c2", x1000_i2c2),2206	INGENIC_PIN_FUNCTION("i2s", x1000_i2s),2207	INGENIC_PIN_FUNCTION("dmic", x1000_dmic),2208	INGENIC_PIN_FUNCTION("cim", x1000_cim),2209	INGENIC_PIN_FUNCTION("lcd", x1000_lcd),2210	INGENIC_PIN_FUNCTION("pwm0", x1000_pwm0),2211	INGENIC_PIN_FUNCTION("pwm1", x1000_pwm1),2212	INGENIC_PIN_FUNCTION("pwm2", x1000_pwm2),2213	INGENIC_PIN_FUNCTION("pwm3", x1000_pwm3),2214	INGENIC_PIN_FUNCTION("pwm4", x1000_pwm4),2215	INGENIC_PIN_FUNCTION("mac", x1000_mac),2216};2217 2218static const struct regmap_range x1000_access_ranges[] = {2219	regmap_reg_range(0x000, 0x400 - 4),2220	regmap_reg_range(0x700, 0x800 - 4),2221};2222 2223/* shared with X1500 */2224static const struct regmap_access_table x1000_access_table = {2225	.yes_ranges = x1000_access_ranges,2226	.n_yes_ranges = ARRAY_SIZE(x1000_access_ranges),2227};2228 2229static const struct ingenic_chip_info x1000_chip_info = {2230	.num_chips = 4,2231	.reg_offset = 0x100,2232	.version = ID_X1000,2233	.groups = x1000_groups,2234	.num_groups = ARRAY_SIZE(x1000_groups),2235	.functions = x1000_functions,2236	.num_functions = ARRAY_SIZE(x1000_functions),2237	.pull_ups = x1000_pull_ups,2238	.pull_downs = x1000_pull_downs,2239	.access_table = &x1000_access_table,2240};2241 2242static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };2243static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };2244static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };2245static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };2246static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };2247static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };2248static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };2249static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };2250static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };2251static int x1500_i2c0_pins[] = { 0x38, 0x37, };2252static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };2253static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };2254static int x1500_i2c2_pins[] = { 0x61, 0x60, };2255static int x1500_i2s_data_tx_pins[] = { 0x24, };2256static int x1500_i2s_data_rx_pins[] = { 0x23, };2257static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };2258static int x1500_i2s_sysclk_pins[] = { 0x20, };2259static int x1500_dmic_if0_pins[] = { 0x35, 0x36, };2260static int x1500_dmic_if1_pins[] = { 0x25, };2261static int x1500_cim_pins[] = {2262	0x08, 0x09, 0x0a, 0x0b,2263	0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,2264};2265static int x1500_pwm_pwm0_pins[] = { 0x59, };2266static int x1500_pwm_pwm1_pins[] = { 0x5a, };2267static int x1500_pwm_pwm2_pins[] = { 0x5b, };2268static int x1500_pwm_pwm3_pins[] = { 0x26, };2269static int x1500_pwm_pwm4_pins[] = { 0x58, };2270 2271static const struct group_desc x1500_groups[] = {2272	INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),2273	INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),2274	INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),2275	INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),2276	INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),2277	INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),2278	INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),2279	INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),2280	INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),2281	INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),2282	INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),2283	INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),2284	INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),2285	INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),2286	INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),2287	INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),2288	INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),2289	INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),2290	INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),2291	INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),2292	INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),2293	INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),2294	INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),2295	INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),2296	INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),2297	INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1),2298	INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),2299	INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0),2300};2301 2302static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };2303static const char *x1500_uart1_groups[] = {2304	"uart1-data-a", "uart1-data-d", "uart1-hwflow",2305};2306static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };2307static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };2308static const char *x1500_i2c0_groups[] = { "i2c0-data", };2309static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };2310static const char *x1500_i2c2_groups[] = { "i2c2-data", };2311static const char *x1500_i2s_groups[] = {2312	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",2313};2314static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };2315static const char *x1500_cim_groups[] = { "cim-data", };2316static const char *x1500_pwm0_groups[] = { "pwm0", };2317static const char *x1500_pwm1_groups[] = { "pwm1", };2318static const char *x1500_pwm2_groups[] = { "pwm2", };2319static const char *x1500_pwm3_groups[] = { "pwm3", };2320static const char *x1500_pwm4_groups[] = { "pwm4", };2321 2322static const struct function_desc x1500_functions[] = {2323	INGENIC_PIN_FUNCTION("uart0", x1500_uart0),2324	INGENIC_PIN_FUNCTION("uart1", x1500_uart1),2325	INGENIC_PIN_FUNCTION("uart2", x1500_uart2),2326	INGENIC_PIN_FUNCTION("sfc", x1000_sfc),2327	INGENIC_PIN_FUNCTION("mmc", x1500_mmc),2328	INGENIC_PIN_FUNCTION("i2c0", x1500_i2c0),2329	INGENIC_PIN_FUNCTION("i2c1", x1500_i2c1),2330	INGENIC_PIN_FUNCTION("i2c2", x1500_i2c2),2331	INGENIC_PIN_FUNCTION("i2s", x1500_i2s),2332	INGENIC_PIN_FUNCTION("dmic", x1500_dmic),2333	INGENIC_PIN_FUNCTION("cim", x1500_cim),2334	INGENIC_PIN_FUNCTION("pwm0", x1500_pwm0),2335	INGENIC_PIN_FUNCTION("pwm1", x1500_pwm1),2336	INGENIC_PIN_FUNCTION("pwm2", x1500_pwm2),2337	INGENIC_PIN_FUNCTION("pwm3", x1500_pwm3),2338	INGENIC_PIN_FUNCTION("pwm4", x1500_pwm4),2339};2340 2341static const struct ingenic_chip_info x1500_chip_info = {2342	.num_chips = 4,2343	.reg_offset = 0x100,2344	.version = ID_X1500,2345	.groups = x1500_groups,2346	.num_groups = ARRAY_SIZE(x1500_groups),2347	.functions = x1500_functions,2348	.num_functions = ARRAY_SIZE(x1500_functions),2349	.pull_ups = x1000_pull_ups,2350	.pull_downs = x1000_pull_downs,2351	.access_table = &x1000_access_table,2352};2353 2354static const u32 x1830_pull_ups[4] = {2355	0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,2356};2357 2358static const u32 x1830_pull_downs[4] = {2359	0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,2360};2361 2362static int x1830_uart0_data_pins[] = { 0x33, 0x36, };2363static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };2364static int x1830_uart1_data_pins[] = { 0x38, 0x37, };2365static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, };2366static int x1830_sfc_clk_pins[] = { 0x1b, };2367static int x1830_sfc_ce_pins[] = { 0x1c, };2368static int x1830_ssi0_dt_pins[] = { 0x4c, };2369static int x1830_ssi0_dr_pins[] = { 0x4b, };2370static int x1830_ssi0_clk_pins[] = { 0x4f, };2371static int x1830_ssi0_gpc_pins[] = { 0x4d, };2372static int x1830_ssi0_ce0_pins[] = { 0x50, };2373static int x1830_ssi0_ce1_pins[] = { 0x4e, };2374static int x1830_ssi1_dt_c_pins[] = { 0x53, };2375static int x1830_ssi1_dt_d_pins[] = { 0x62, };2376static int x1830_ssi1_dr_c_pins[] = { 0x54, };2377static int x1830_ssi1_dr_d_pins[] = { 0x63, };2378static int x1830_ssi1_clk_c_pins[] = { 0x57, };2379static int x1830_ssi1_clk_d_pins[] = { 0x66, };2380static int x1830_ssi1_gpc_c_pins[] = { 0x55, };2381static int x1830_ssi1_gpc_d_pins[] = { 0x64, };2382static int x1830_ssi1_ce0_c_pins[] = { 0x58, };2383static int x1830_ssi1_ce0_d_pins[] = { 0x67, };2384static int x1830_ssi1_ce1_c_pins[] = { 0x56, };2385static int x1830_ssi1_ce1_d_pins[] = { 0x65, };2386static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };2387static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };2388static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };2389static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };2390static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };2391static int x1830_i2c1_pins[] = { 0x39, 0x3a, };2392static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };2393static int x1830_i2s_data_tx_pins[] = { 0x53, };2394static int x1830_i2s_data_rx_pins[] = { 0x54, };2395static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };2396static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };2397static int x1830_i2s_sysclk_pins[] = { 0x57, };2398static int x1830_dmic_if0_pins[] = { 0x48, 0x59, };2399static int x1830_dmic_if1_pins[] = { 0x5a, };2400static int x1830_lcd_tft_8bit_pins[] = {2401	0x62, 0x63, 0x64, 0x65, 0x66, 0x67,2402	0x68, 0x73, 0x72, 0x69,2403};2404static int x1830_lcd_tft_24bit_pins[] = {2405	0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71,2406	0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b,2407};2408static int x1830_lcd_slcd_8bit_pins[] = {2409	0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,2410	0x69, 0x72, 0x73, 0x7b, 0x7a,2411};2412static int x1830_lcd_slcd_16bit_pins[] = {2413	0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,2414};2415static int x1830_pwm_pwm0_b_pins[] = { 0x31, };2416static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };2417static int x1830_pwm_pwm1_b_pins[] = { 0x32, };2418static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };2419static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };2420static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };2421static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };2422static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };2423static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };2424static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };2425static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };2426static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };2427static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };2428static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };2429static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };2430static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };2431static int x1830_mac_pins[] = {2432	0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,2433};2434 2435static const struct group_desc x1830_groups[] = {2436	INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),2437	INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),2438	INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),2439	INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),2440	INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),2441	INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),2442	INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),2443	INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),2444	INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),2445	INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),2446	INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),2447	INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),2448	INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),2449	INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),2450	INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),2451	INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),2452	INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),2453	INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),2454	INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),2455	INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),2456	INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),2457	INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),2458	INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),2459	INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),2460	INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),2461	INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),2462	INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),2463	INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),2464	INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),2465	INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),2466	INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),2467	INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),2468	INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),2469	INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),2470	INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),2471	INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),2472	INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),2473	INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),2474	INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),2475	INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),2476	INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),2477	INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),2478	INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),2479	INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),2480	INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),2481	INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),2482	INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),2483	INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),2484	INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),2485	INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),2486	INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),2487	INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),2488	INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),2489	INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),2490	INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),2491	INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),2492	INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),2493	INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),2494	INGENIC_PIN_GROUP("mac", x1830_mac, 0),2495};2496 2497static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };2498static const char *x1830_uart1_groups[] = { "uart1-data", };2499static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };2500static const char *x1830_ssi0_groups[] = {2501	"ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",2502};2503static const char *x1830_ssi1_groups[] = {2504	"ssi1-dt-c", "ssi1-dt-d",2505	"ssi1-dr-c", "ssi1-dr-d",2506	"ssi1-clk-c", "ssi1-clk-d",2507	"ssi1-gpc-c", "ssi1-gpc-d",2508	"ssi1-ce0-c", "ssi1-ce0-d",2509	"ssi1-ce1-c", "ssi1-ce1-d",2510};2511static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };2512static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };2513static const char *x1830_i2c0_groups[] = { "i2c0-data", };2514static const char *x1830_i2c1_groups[] = { "i2c1-data", };2515static const char *x1830_i2c2_groups[] = { "i2c2-data", };2516static const char *x1830_i2s_groups[] = {2517	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",2518};2519static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };2520static const char *x1830_lcd_groups[] = {2521	"lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",2522};2523static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };2524static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };2525static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };2526static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };2527static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };2528static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };2529static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };2530static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };2531static const char *x1830_mac_groups[] = { "mac", };2532 2533static const struct function_desc x1830_functions[] = {2534	INGENIC_PIN_FUNCTION("uart0", x1830_uart0),2535	INGENIC_PIN_FUNCTION("uart1", x1830_uart1),2536	INGENIC_PIN_FUNCTION("sfc", x1830_sfc),2537	INGENIC_PIN_FUNCTION("ssi0", x1830_ssi0),2538	INGENIC_PIN_FUNCTION("ssi1", x1830_ssi1),2539	INGENIC_PIN_FUNCTION("mmc0", x1830_mmc0),2540	INGENIC_PIN_FUNCTION("mmc1", x1830_mmc1),2541	INGENIC_PIN_FUNCTION("i2c0", x1830_i2c0),2542	INGENIC_PIN_FUNCTION("i2c1", x1830_i2c1),2543	INGENIC_PIN_FUNCTION("i2c2", x1830_i2c2),2544	INGENIC_PIN_FUNCTION("i2s", x1830_i2s),2545	INGENIC_PIN_FUNCTION("dmic", x1830_dmic),2546	INGENIC_PIN_FUNCTION("lcd", x1830_lcd),2547	INGENIC_PIN_FUNCTION("pwm0", x1830_pwm0),2548	INGENIC_PIN_FUNCTION("pwm1", x1830_pwm1),2549	INGENIC_PIN_FUNCTION("pwm2", x1830_pwm2),2550	INGENIC_PIN_FUNCTION("pwm3", x1830_pwm3),2551	INGENIC_PIN_FUNCTION("pwm4", x1830_pwm4),2552	INGENIC_PIN_FUNCTION("pwm5", x1830_pwm5),2553	INGENIC_PIN_FUNCTION("pwm6", x1830_pwm6),2554	INGENIC_PIN_FUNCTION("pwm7", x1830_pwm7),2555	INGENIC_PIN_FUNCTION("mac", x1830_mac),2556};2557 2558static const struct regmap_range x1830_access_ranges[] = {2559	regmap_reg_range(0x0000, 0x4000 - 4),2560	regmap_reg_range(0x7000, 0x8000 - 4),2561};2562 2563static const struct regmap_access_table x1830_access_table = {2564	.yes_ranges = x1830_access_ranges,2565	.n_yes_ranges = ARRAY_SIZE(x1830_access_ranges),2566};2567 2568static const struct ingenic_chip_info x1830_chip_info = {2569	.num_chips = 4,2570	.reg_offset = 0x1000,2571	.version = ID_X1830,2572	.groups = x1830_groups,2573	.num_groups = ARRAY_SIZE(x1830_groups),2574	.functions = x1830_functions,2575	.num_functions = ARRAY_SIZE(x1830_functions),2576	.pull_ups = x1830_pull_ups,2577	.pull_downs = x1830_pull_downs,2578	.access_table = &x1830_access_table,2579};2580 2581static const u32 x2000_pull_ups[5] = {2582	0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f,2583};2584 2585static const u32 x2000_pull_downs[5] = {2586	0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f,2587};2588 2589static int x2000_uart0_data_pins[] = { 0x77, 0x78, };2590static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, };2591static int x2000_uart1_data_pins[] = { 0x57, 0x58, };2592static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, };2593static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, };2594static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, };2595static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, };2596static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, };2597static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, };2598static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, };2599static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, };2600static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, };2601static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, };2602static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, };2603static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, };2604static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, };2605static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, };2606static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, };2607static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, };2608static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, };2609static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, };2610static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, };2611static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, };2612static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };2613static int x2000_sfc_clk_d_pins[] = { 0x71, };2614static int x2000_sfc_clk_e_pins[] = { 0x90, };2615static int x2000_sfc_ce_d_pins[] = { 0x72, };2616static int x2000_sfc_ce_e_pins[] = { 0x91, };2617static int x2000_ssi0_dt_b_pins[] = { 0x3e, };2618static int x2000_ssi0_dt_d_pins[] = { 0x69, };2619static int x2000_ssi0_dr_b_pins[] = { 0x3d, };2620static int x2000_ssi0_dr_d_pins[] = { 0x6a, };2621static int x2000_ssi0_clk_b_pins[] = { 0x3f, };2622static int x2000_ssi0_clk_d_pins[] = { 0x68, };2623static int x2000_ssi0_ce_b_pins[] = { 0x3c, };2624static int x2000_ssi0_ce_d_pins[] = { 0x6d, };2625static int x2000_ssi1_dt_c_pins[] = { 0x4b, };2626static int x2000_ssi1_dt_d_pins[] = { 0x72, };2627static int x2000_ssi1_dt_e_pins[] = { 0x91, };2628static int x2000_ssi1_dr_c_pins[] = { 0x4a, };2629static int x2000_ssi1_dr_d_pins[] = { 0x73, };2630static int x2000_ssi1_dr_e_pins[] = { 0x92, };2631static int x2000_ssi1_clk_c_pins[] = { 0x4c, };2632static int x2000_ssi1_clk_d_pins[] = { 0x71, };2633static int x2000_ssi1_clk_e_pins[] = { 0x90, };2634static int x2000_ssi1_ce_c_pins[] = { 0x49, };2635static int x2000_ssi1_ce_d_pins[] = { 0x76, };2636static int x2000_ssi1_ce_e_pins[] = { 0x95, };2637static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, };2638static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, };2639static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, };2640static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, };2641static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };2642static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, };2643static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, };2644static int x2000_emc_8bit_data_pins[] = {2645	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,2646};2647static int x2000_emc_16bit_data_pins[] = {2648	0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,2649};2650static int x2000_emc_addr_pins[] = {2651	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,2652	0x28, 0x29, 0x2a, 0x2b, 0x2c,2653};2654static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, };2655static int x2000_emc_wait_pins[] = { 0x2f, };2656static int x2000_emc_cs1_pins[] = { 0x57, };2657static int x2000_emc_cs2_pins[] = { 0x58, };2658static int x2000_i2c0_pins[] = { 0x4e, 0x4d, };2659static int x2000_i2c1_c_pins[] = { 0x58, 0x57, };2660static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, };2661static int x2000_i2c2_b_pins[] = { 0x37, 0x36, };2662static int x2000_i2c2_d_pins[] = { 0x75, 0x74, };2663static int x2000_i2c2_e_pins[] = { 0x94, 0x93, };2664static int x2000_i2c3_a_pins[] = { 0x11, 0x10, };2665static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, };2666static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, };2667static int x2000_i2c4_d_pins[] = { 0x61, 0x60, };2668static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, };2669static int x2000_i2c5_d_pins[] = { 0x65, 0x64, };2670static int x2000_i2s1_data_tx_pins[] = { 0x47, };2671static int x2000_i2s1_data_rx_pins[] = { 0x44, };2672static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, };2673static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, };2674static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, };2675static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, };2676static int x2000_i2s2_data_rx0_pins[] = { 0x0a, };2677static int x2000_i2s2_data_rx1_pins[] = { 0x0b, };2678static int x2000_i2s2_data_rx2_pins[] = { 0x0c, };2679static int x2000_i2s2_data_rx3_pins[] = { 0x0d, };2680static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, };2681static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, };2682static int x2000_i2s3_data_tx0_pins[] = { 0x03, };2683static int x2000_i2s3_data_tx1_pins[] = { 0x04, };2684static int x2000_i2s3_data_tx2_pins[] = { 0x05, };2685static int x2000_i2s3_data_tx3_pins[] = { 0x06, };2686static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, };2687static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, };2688static int x2000_dmic_if0_pins[] = { 0x54, 0x55, };2689static int x2000_dmic_if1_pins[] = { 0x56, };2690static int x2000_dmic_if2_pins[] = { 0x57, };2691static int x2000_dmic_if3_pins[] = { 0x58, };2692static int x2000_cim_8bit_pins[] = {2693	0x0e, 0x0c, 0x0d, 0x4f,2694	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,2695};2696static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, };2697static int x2000_lcd_tft_8bit_pins[] = {2698	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,2699	0x38, 0x3a, 0x39, 0x3b,2700};2701static int x2000_lcd_tft_16bit_pins[] = {2702	0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,2703};2704static int x2000_lcd_tft_18bit_pins[] = {2705	0x30, 0x31,2706};2707static int x2000_lcd_tft_24bit_pins[] = {2708	0x32, 0x33, 0x34, 0x35, 0x36, 0x37,2709};2710static int x2000_lcd_slcd_8bit_pins[] = {2711	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,2712	0x3a, 0x38, 0x3b, 0x30, 0x39,2713};2714static int x2000_pwm_pwm0_c_pins[] = { 0x40, };2715static int x2000_pwm_pwm0_d_pins[] = { 0x7e, };2716static int x2000_pwm_pwm1_c_pins[] = { 0x41, };2717static int x2000_pwm_pwm1_d_pins[] = { 0x7f, };2718static int x2000_pwm_pwm2_c_pins[] = { 0x42, };2719static int x2000_pwm_pwm2_e_pins[] = { 0x80, };2720static int x2000_pwm_pwm3_c_pins[] = { 0x43, };2721static int x2000_pwm_pwm3_e_pins[] = { 0x81, };2722static int x2000_pwm_pwm4_c_pins[] = { 0x44, };2723static int x2000_pwm_pwm4_e_pins[] = { 0x82, };2724static int x2000_pwm_pwm5_c_pins[] = { 0x45, };2725static int x2000_pwm_pwm5_e_pins[] = { 0x83, };2726static int x2000_pwm_pwm6_c_pins[] = { 0x46, };2727static int x2000_pwm_pwm6_e_pins[] = { 0x84, };2728static int x2000_pwm_pwm7_c_pins[] = { 0x47, };2729static int x2000_pwm_pwm7_e_pins[] = { 0x85, };2730static int x2000_pwm_pwm8_pins[] = { 0x48, };2731static int x2000_pwm_pwm9_pins[] = { 0x49, };2732static int x2000_pwm_pwm10_pins[] = { 0x4a, };2733static int x2000_pwm_pwm11_pins[] = { 0x4b, };2734static int x2000_pwm_pwm12_pins[] = { 0x4c, };2735static int x2000_pwm_pwm13_pins[] = { 0x4d, };2736static int x2000_pwm_pwm14_pins[] = { 0x4e, };2737static int x2000_pwm_pwm15_pins[] = { 0x4f, };2738static int x2000_mac0_rmii_pins[] = {2739	0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41,2740};2741static int x2000_mac0_rgmii_pins[] = {2742	0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42,2743	0x4c, 0x4d, 0x4f, 0x4e, 0x41,2744};2745static int x2000_mac1_rmii_pins[] = {2746	0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37,2747};2748static int x2000_mac1_rgmii_pins[] = {2749	0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28,2750	0x33, 0x34, 0x36, 0x35, 0x37,2751};2752static int x2000_otg_pins[] = { 0x96, };2753 2754static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, };2755 2756static const struct group_desc x2000_groups[] = {2757	INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),2758	INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),2759	INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),2760	INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),2761	INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),2762	INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),2763	INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),2764	INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),2765	INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),2766	INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),2767	INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),2768	INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),2769	INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),2770	INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),2771	INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),2772	INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),2773	INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),2774	INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),2775	INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),2776	INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),2777	INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),2778	INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),2779	INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),2780	INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),2781	INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),2782	INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),2783	INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),2784	INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),2785	INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),2786	INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),2787	INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),2788	INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),2789	INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),2790	INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),2791	INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),2792	INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),2793	INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),2794	INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),2795	INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),2796	INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),2797	INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),2798	INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),2799	INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),2800	INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),2801	INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),2802	INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),2803	INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),2804	INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),2805	INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),2806	INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),2807	INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),2808	INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),2809	INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),2810	INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),2811	INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),2812	INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),2813	INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),2814	INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),2815	INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),2816	INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),2817	INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),2818	INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),2819	INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),2820	INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),2821	INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),2822	INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),2823	INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),2824	INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),2825	INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),2826	INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),2827	INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),2828	INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),2829	INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),2830	INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),2831	INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),2832	INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),2833	INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),2834	INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),2835	INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),2836	INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),2837	INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),2838	INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),2839	INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),2840	INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),2841	INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),2842	INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),2843	INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),2844	INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),2845	INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),2846	INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),2847	INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),2848	INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),2849	INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),2850	INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),2851	INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),2852	INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),2853	INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,2854				x2000_cim_8bit_funcs),2855	INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),2856	INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),2857	INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),2858	INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),2859	INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),2860	INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),2861	INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),2862	INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),2863	INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),2864	INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),2865	INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),2866	INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),2867	INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),2868	INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),2869	INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),2870	INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),2871	INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),2872	INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),2873	INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),2874	INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),2875	INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),2876	INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),2877	INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),2878	INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),2879	INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),2880	INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),2881	INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),2882	INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),2883	INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),2884	INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),2885	INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),2886	INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),2887	INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),2888	INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),2889	INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),2890	INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),2891};2892 2893static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };2894static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };2895static const char *x2000_uart2_groups[] = { "uart2-data", };2896static const char *x2000_uart3_groups[] = {2897	"uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",2898};2899static const char *x2000_uart4_groups[] = {2900	"uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",2901};2902static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };2903static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };2904static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };2905static const char *x2000_uart8_groups[] = { "uart8-data", };2906static const char *x2000_uart9_groups[] = { "uart9-data", };2907static const char *x2000_sfc_groups[] = {2908	"sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",2909	"sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",2910};2911static const char *x2000_ssi0_groups[] = {2912	"ssi0-dt-b", "ssi0-dt-d",2913	"ssi0-dr-b", "ssi0-dr-d",2914	"ssi0-clk-b", "ssi0-clk-d",2915	"ssi0-ce-b", "ssi0-ce-d",2916};2917static const char *x2000_ssi1_groups[] = {2918	"ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",2919	"ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",2920	"ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",2921	"ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",2922};2923static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };2924static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };2925static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };2926static const char *x2000_emc_groups[] = {2927	"emc-8bit-data", "emc-16bit-data",2928	"emc-addr", "emc-rd-we", "emc-wait",2929};2930static const char *x2000_cs1_groups[] = { "emc-cs1", };2931static const char *x2000_cs2_groups[] = { "emc-cs2", };2932static const char *x2000_i2c0_groups[] = { "i2c0-data", };2933static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };2934static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };2935static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };2936static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };2937static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };2938static const char *x2000_i2s1_groups[] = {2939	"i2s1-data-tx", "i2s1-data-rx",2940	"i2s1-clk-tx", "i2s1-clk-rx",2941	"i2s1-sysclk-tx", "i2s1-sysclk-rx",2942};2943static const char *x2000_i2s2_groups[] = {2944	"i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",2945	"i2s2-clk-rx", "i2s2-sysclk-rx",2946};2947static const char *x2000_i2s3_groups[] = {2948	"i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",2949	"i2s3-clk-tx", "i2s3-sysclk-tx",2950};2951static const char *x2000_dmic_groups[] = {2952	"dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",2953};2954static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };2955static const char *x2000_lcd_groups[] = {2956	"lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",2957	"lcd-slcd-8bit", "lcd-slcd-16bit",2958};2959static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };2960static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };2961static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };2962static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };2963static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };2964static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };2965static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };2966static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };2967static const char *x2000_pwm8_groups[] = { "pwm8", };2968static const char *x2000_pwm9_groups[] = { "pwm9", };2969static const char *x2000_pwm10_groups[] = { "pwm10", };2970static const char *x2000_pwm11_groups[] = { "pwm11", };2971static const char *x2000_pwm12_groups[] = { "pwm12", };2972static const char *x2000_pwm13_groups[] = { "pwm13", };2973static const char *x2000_pwm14_groups[] = { "pwm14", };2974static const char *x2000_pwm15_groups[] = { "pwm15", };2975static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };2976static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };2977static const char *x2000_otg_groups[] = { "otg-vbus", };2978 2979static const struct function_desc x2000_functions[] = {2980	INGENIC_PIN_FUNCTION("uart0", x2000_uart0),2981	INGENIC_PIN_FUNCTION("uart1", x2000_uart1),2982	INGENIC_PIN_FUNCTION("uart2", x2000_uart2),2983	INGENIC_PIN_FUNCTION("uart3", x2000_uart3),2984	INGENIC_PIN_FUNCTION("uart4", x2000_uart4),2985	INGENIC_PIN_FUNCTION("uart5", x2000_uart5),2986	INGENIC_PIN_FUNCTION("uart6", x2000_uart6),2987	INGENIC_PIN_FUNCTION("uart7", x2000_uart7),2988	INGENIC_PIN_FUNCTION("uart8", x2000_uart8),2989	INGENIC_PIN_FUNCTION("uart9", x2000_uart9),2990	INGENIC_PIN_FUNCTION("sfc", x2000_sfc),2991	INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0),2992	INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1),2993	INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0),2994	INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1),2995	INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2),2996	INGENIC_PIN_FUNCTION("emc", x2000_emc),2997	INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),2998	INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),2999	INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0),3000	INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1),3001	INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2),3002	INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3),3003	INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4),3004	INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5),3005	INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1),3006	INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2),3007	INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3),3008	INGENIC_PIN_FUNCTION("dmic", x2000_dmic),3009	INGENIC_PIN_FUNCTION("cim", x2000_cim),3010	INGENIC_PIN_FUNCTION("lcd", x2000_lcd),3011	INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0),3012	INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1),3013	INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2),3014	INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3),3015	INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4),3016	INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5),3017	INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6),3018	INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7),3019	INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8),3020	INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9),3021	INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10),3022	INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11),3023	INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12),3024	INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13),3025	INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14),3026	INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15),3027	INGENIC_PIN_FUNCTION("mac0", x2000_mac0),3028	INGENIC_PIN_FUNCTION("mac1", x2000_mac1),3029	INGENIC_PIN_FUNCTION("otg", x2000_otg),3030};3031 3032static const struct regmap_range x2000_access_ranges[] = {3033	regmap_reg_range(0x000, 0x500 - 4),3034	regmap_reg_range(0x700, 0x800 - 4),3035};3036 3037/* shared with X2100 */3038static const struct regmap_access_table x2000_access_table = {3039	.yes_ranges = x2000_access_ranges,3040	.n_yes_ranges = ARRAY_SIZE(x2000_access_ranges),3041};3042 3043static const struct ingenic_chip_info x2000_chip_info = {3044	.num_chips = 5,3045	.reg_offset = 0x100,3046	.version = ID_X2000,3047	.groups = x2000_groups,3048	.num_groups = ARRAY_SIZE(x2000_groups),3049	.functions = x2000_functions,3050	.num_functions = ARRAY_SIZE(x2000_functions),3051	.pull_ups = x2000_pull_ups,3052	.pull_downs = x2000_pull_downs,3053	.access_table = &x2000_access_table,3054};3055 3056static const u32 x2100_pull_ups[5] = {3057	0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f,3058};3059 3060static const u32 x2100_pull_downs[5] = {3061	0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f,3062};3063 3064static int x2100_mac_pins[] = {3065	0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41,3066};3067 3068static const struct group_desc x2100_groups[] = {3069	INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),3070	INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),3071	INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),3072	INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),3073	INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),3074	INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),3075	INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),3076	INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),3077	INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),3078	INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),3079	INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),3080	INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),3081	INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),3082	INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),3083	INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),3084	INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),3085	INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),3086	INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),3087	INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),3088	INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),3089	INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),3090	INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),3091	INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),3092	INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),3093	INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),3094	INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),3095	INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),3096	INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),3097	INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),3098	INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),3099	INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),3100	INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),3101	INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),3102	INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),3103	INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),3104	INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),3105	INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),3106	INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),3107	INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),3108	INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),3109	INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),3110	INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),3111	INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),3112	INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),3113	INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),3114	INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),3115	INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),3116	INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),3117	INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),3118	INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),3119	INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),3120	INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),3121	INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),3122	INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),3123	INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),3124	INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),3125	INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),3126	INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),3127	INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),3128	INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),3129	INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),3130	INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),3131	INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),3132	INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),3133	INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),3134	INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),3135	INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),3136	INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),3137	INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),3138	INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),3139	INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),3140	INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),3141	INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),3142	INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),3143	INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),3144	INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),3145	INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),3146	INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),3147	INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),3148	INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),3149	INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),3150	INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),3151	INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),3152	INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),3153	INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),3154	INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),3155	INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),3156	INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),3157	INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),3158	INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),3159	INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),3160	INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),3161	INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),3162	INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),3163	INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),3164	INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),3165	INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,3166				x2000_cim_8bit_funcs),3167	INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),3168	INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),3169	INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),3170	INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),3171	INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),3172	INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),3173	INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),3174	INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),3175	INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),3176	INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),3177	INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),3178	INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),3179	INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),3180	INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),3181	INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),3182	INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),3183	INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),3184	INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),3185	INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),3186	INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),3187	INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),3188	INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),3189	INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),3190	INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),3191	INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),3192	INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),3193	INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),3194	INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),3195	INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),3196	INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),3197	INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),3198	INGENIC_PIN_GROUP("mac", x2100_mac, 1),3199};3200 3201static const char *x2100_mac_groups[] = { "mac", };3202 3203static const struct function_desc x2100_functions[] = {3204	INGENIC_PIN_FUNCTION("uart0", x2000_uart0),3205	INGENIC_PIN_FUNCTION("uart1", x2000_uart1),3206	INGENIC_PIN_FUNCTION("uart2", x2000_uart2),3207	INGENIC_PIN_FUNCTION("uart3", x2000_uart3),3208	INGENIC_PIN_FUNCTION("uart4", x2000_uart4),3209	INGENIC_PIN_FUNCTION("uart5", x2000_uart5),3210	INGENIC_PIN_FUNCTION("uart6", x2000_uart6),3211	INGENIC_PIN_FUNCTION("uart7", x2000_uart7),3212	INGENIC_PIN_FUNCTION("uart8", x2000_uart8),3213	INGENIC_PIN_FUNCTION("uart9", x2000_uart9),3214	INGENIC_PIN_FUNCTION("sfc", x2000_sfc),3215	INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0),3216	INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1),3217	INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0),3218	INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1),3219	INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2),3220	INGENIC_PIN_FUNCTION("emc", x2000_emc),3221	INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),3222	INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),3223	INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0),3224	INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1),3225	INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2),3226	INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3),3227	INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4),3228	INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5),3229	INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1),3230	INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2),3231	INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3),3232	INGENIC_PIN_FUNCTION("dmic", x2000_dmic),3233	INGENIC_PIN_FUNCTION("cim", x2000_cim),3234	INGENIC_PIN_FUNCTION("lcd", x2000_lcd),3235	INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0),3236	INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1),3237	INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2),3238	INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3),3239	INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4),3240	INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5),3241	INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6),3242	INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7),3243	INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8),3244	INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9),3245	INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10),3246	INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11),3247	INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12),3248	INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13),3249	INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14),3250	INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15),3251	INGENIC_PIN_FUNCTION("mac", x2100_mac),3252};3253 3254static const struct ingenic_chip_info x2100_chip_info = {3255	.num_chips = 5,3256	.reg_offset = 0x100,3257	.version = ID_X2100,3258	.groups = x2100_groups,3259	.num_groups = ARRAY_SIZE(x2100_groups),3260	.functions = x2100_functions,3261	.num_functions = ARRAY_SIZE(x2100_functions),3262	.pull_ups = x2100_pull_ups,3263	.pull_downs = x2100_pull_downs,3264	.access_table = &x2000_access_table,3265};3266 3267static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)3268{3269	unsigned int val;3270 3271	regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);3272 3273	return (u32) val;3274}3275 3276static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,3277		u8 reg, u8 offset, bool set)3278{3279	if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {3280		regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,3281				BIT(offset), set ? BIT(offset) : 0);3282		return;3283	}3284 3285	if (set)3286		reg = REG_SET(reg);3287	else3288		reg = REG_CLEAR(reg);3289 3290	regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));3291}3292 3293static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,3294		u8 reg, u8 offset, bool set)3295{3296	if (set)3297		reg = REG_SET(reg);3298	else3299		reg = REG_CLEAR(reg);3300 3301	regmap_write(jzgc->jzpc->map, REG_PZ_BASE(3302			jzgc->jzpc->info->reg_offset) + reg, BIT(offset));3303}3304 3305static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)3306{3307	regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(3308			jzgc->jzpc->info->reg_offset),3309			jzgc->gc.base / PINS_PER_GPIO_CHIP);3310}3311 3312static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc,3313		u8 reg_upper, u8 reg_lower, u8 offset, u8 value)3314{3315	/*3316	 * JZ4730 function and IRQ registers support two-bits-per-pin3317	 * definitions, split into two groups of 16.3318	 */3319	u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;3320	unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG;3321	unsigned int mask = GENMASK(1, 0) << idx * 2;3322 3323	regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));3324}3325 3326static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,3327					  u8 offset)3328{3329	unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);3330 3331	return !!(val & BIT(offset));3332}3333 3334static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,3335				   u8 offset, int value)3336{3337	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))3338		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);3339	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))3340		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);3341	else3342		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value);3343}3344 3345static void irq_set_type(struct ingenic_gpio_chip *jzgc,3346		u8 offset, unsigned int type)3347{3348	u8 reg1, reg2;3349	bool val1, val2, val3;3350 3351	switch (type) {3352	case IRQ_TYPE_EDGE_BOTH:3353		val1 = val2 = false;3354		val3 = true;3355		break;3356	case IRQ_TYPE_EDGE_RISING:3357		val1 = val2 = true;3358		val3 = false;3359		break;3360	case IRQ_TYPE_EDGE_FALLING:3361		val1 = val3 = false;3362		val2 = true;3363		break;3364	case IRQ_TYPE_LEVEL_HIGH:3365		val1 = true;3366		val2 = val3 = false;3367		break;3368	case IRQ_TYPE_LEVEL_LOW:3369	default:3370		val1 = val2 = val3 = false;3371		break;3372	}3373 3374	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {3375		reg1 = JZ4770_GPIO_PAT1;3376		reg2 = JZ4770_GPIO_PAT0;3377	} else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {3378		reg1 = JZ4740_GPIO_TRIG;3379		reg2 = JZ4740_GPIO_DIR;3380	} else {3381		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false);3382		jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR,3383				JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1);3384		return;3385	}3386 3387	if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {3388		ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);3389		ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);3390		ingenic_gpio_shadow_set_bit_load(jzgc);3391		ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3);3392	} else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {3393		ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);3394		ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);3395		ingenic_gpio_shadow_set_bit_load(jzgc);3396	} else {3397		ingenic_gpio_set_bit(jzgc, reg2, offset, val1);3398		ingenic_gpio_set_bit(jzgc, reg1, offset, val2);3399	}3400}3401 3402static void ingenic_gpio_irq_mask(struct irq_data *irqd)3403{3404	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);3405	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3406	irq_hw_number_t irq = irqd_to_hwirq(irqd);3407 3408	if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))3409		ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);3410	else3411		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true);3412}3413 3414static void ingenic_gpio_irq_unmask(struct irq_data *irqd)3415{3416	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);3417	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3418	irq_hw_number_t irq = irqd_to_hwirq(irqd);3419 3420	if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))3421		ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);3422	else3423		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false);3424}3425 3426static void ingenic_gpio_irq_enable(struct irq_data *irqd)3427{3428	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);3429	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3430	irq_hw_number_t irq = irqd_to_hwirq(irqd);3431 3432	gpiochip_enable_irq(gc, irq);3433 3434	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))3435		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);3436	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))3437		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);3438	else3439		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true);3440 3441	ingenic_gpio_irq_unmask(irqd);3442}3443 3444static void ingenic_gpio_irq_disable(struct irq_data *irqd)3445{3446	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);3447	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3448	irq_hw_number_t irq = irqd_to_hwirq(irqd);3449 3450	ingenic_gpio_irq_mask(irqd);3451 3452	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))3453		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);3454	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))3455		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);3456	else3457		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);3458 3459	gpiochip_disable_irq(gc, irq);3460}3461 3462static void ingenic_gpio_irq_ack(struct irq_data *irqd)3463{3464	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);3465	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3466	irq_hw_number_t irq = irqd_to_hwirq(irqd);3467	bool high;3468 3469	if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) &&3470	    !is_soc_or_above(jzgc->jzpc, ID_X2000)) {3471		/*3472		 * Switch to an interrupt for the opposite edge to the one that3473		 * triggered the interrupt being ACKed.3474		 */3475		high = ingenic_gpio_get_value(jzgc, irq);3476		if (high)3477			irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);3478		else3479			irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);3480	}3481 3482	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))3483		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);3484	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))3485		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);3486	else3487		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false);3488}3489 3490static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)3491{3492	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);3493	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3494	irq_hw_number_t irq = irqd_to_hwirq(irqd);3495 3496	switch (type) {3497	case IRQ_TYPE_EDGE_BOTH:3498	case IRQ_TYPE_EDGE_RISING:3499	case IRQ_TYPE_EDGE_FALLING:3500		irq_set_handler_locked(irqd, handle_edge_irq);3501		break;3502	case IRQ_TYPE_LEVEL_HIGH:3503	case IRQ_TYPE_LEVEL_LOW:3504		irq_set_handler_locked(irqd, handle_level_irq);3505		break;3506	default:3507		irq_set_handler_locked(irqd, handle_bad_irq);3508	}3509 3510	if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {3511		/*3512		 * The hardware does not support interrupts on both edges. The3513		 * best we can do is to set up a single-edge interrupt and then3514		 * switch to the opposing edge when ACKing the interrupt.3515		 */3516		bool high = ingenic_gpio_get_value(jzgc, irq);3517 3518		type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;3519	}3520 3521	irq_set_type(jzgc, irq, type);3522	return 0;3523}3524 3525static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)3526{3527	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);3528	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3529 3530	return irq_set_irq_wake(jzgc->irq, on);3531}3532 3533static void ingenic_gpio_irq_handler(struct irq_desc *desc)3534{3535	struct gpio_chip *gc = irq_desc_get_handler_data(desc);3536	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3537	struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);3538	unsigned long flag, i;3539 3540	chained_irq_enter(irq_chip, desc);3541 3542	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))3543		flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);3544	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))3545		flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);3546	else3547		flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);3548 3549	for_each_set_bit(i, &flag, 32)3550		generic_handle_domain_irq(gc->irq.domain, i);3551	chained_irq_exit(irq_chip, desc);3552}3553 3554static void ingenic_gpio_set(struct gpio_chip *gc,3555		unsigned int offset, int value)3556{3557	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3558 3559	ingenic_gpio_set_value(jzgc, offset, value);3560}3561 3562static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)3563{3564	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3565 3566	return (int) ingenic_gpio_get_value(jzgc, offset);3567}3568 3569static int ingenic_gpio_direction_output(struct gpio_chip *gc,3570		unsigned int offset, int value)3571{3572	ingenic_gpio_set(gc, offset, value);3573	return pinctrl_gpio_direction_output(gc, offset);3574}3575 3576static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,3577		unsigned int pin, unsigned int reg, bool set)3578{3579	unsigned int idx = pin % PINS_PER_GPIO_CHIP;3580	unsigned int offt = pin / PINS_PER_GPIO_CHIP;3581 3582	if (set) {3583		if (is_soc_or_above(jzpc, ID_JZ4740))3584			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +3585					REG_SET(reg), BIT(idx));3586		else3587			regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +3588					reg, BIT(idx));3589	} else {3590		if (is_soc_or_above(jzpc, ID_JZ4740))3591			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +3592					REG_CLEAR(reg), BIT(idx));3593		else3594			regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset +3595					reg, BIT(idx));3596	}3597}3598 3599static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,3600		unsigned int pin, u8 reg, bool set)3601{3602	unsigned int idx = pin % PINS_PER_GPIO_CHIP;3603 3604	regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +3605			(set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));3606}3607 3608static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,3609		unsigned int pin)3610{3611	regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),3612			pin / PINS_PER_GPIO_CHIP);3613}3614 3615static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc,3616		unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value)3617{3618	/*3619	 * JZ4730 function and IRQ registers support two-bits-per-pin3620	 * definitions, split into two groups of 16.3621	 */3622	unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG;3623	unsigned int mask = GENMASK(1, 0) << idx * 2;3624	unsigned int offt = pin / PINS_PER_GPIO_CHIP;3625	u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;3626 3627	regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg,3628			mask, value << (idx * 2));3629}3630 3631static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,3632		unsigned int pin, unsigned int reg)3633{3634	unsigned int idx = pin % PINS_PER_GPIO_CHIP;3635	unsigned int offt = pin / PINS_PER_GPIO_CHIP;3636	unsigned int val;3637 3638	regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);3639 3640	return val & BIT(idx);3641}3642 3643static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)3644{3645	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);3646	struct ingenic_pinctrl *jzpc = jzgc->jzpc;3647	unsigned int pin = gc->base + offset;3648 3649	if (is_soc_or_above(jzpc, ID_JZ4770)) {3650		if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) ||3651		    ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1))3652			return GPIO_LINE_DIRECTION_IN;3653		return GPIO_LINE_DIRECTION_OUT;3654	} else if (!is_soc_or_above(jzpc, ID_JZ4740)) {3655		if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR))3656			return GPIO_LINE_DIRECTION_IN;3657		return GPIO_LINE_DIRECTION_OUT;3658	}3659 3660	if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))3661		return GPIO_LINE_DIRECTION_IN;3662 3663	if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))3664		return GPIO_LINE_DIRECTION_OUT;3665 3666	return GPIO_LINE_DIRECTION_IN;3667}3668 3669static const struct pinctrl_ops ingenic_pctlops = {3670	.get_groups_count = pinctrl_generic_get_group_count,3671	.get_group_name = pinctrl_generic_get_group_name,3672	.get_group_pins = pinctrl_generic_get_group_pins,3673	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,3674	.dt_free_map = pinconf_generic_dt_free_map,3675};3676 3677static int ingenic_gpio_irq_request(struct irq_data *data)3678{3679	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);3680	irq_hw_number_t irq = irqd_to_hwirq(data);3681	int ret;3682 3683	ret = pinctrl_gpio_direction_input(gpio_chip, irq);3684	if (ret)3685		return ret;3686 3687	return gpiochip_reqres_irq(gpio_chip, irq);3688}3689 3690static void ingenic_gpio_irq_release(struct irq_data *data)3691{3692	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);3693	irq_hw_number_t irq = irqd_to_hwirq(data);3694 3695	return gpiochip_relres_irq(gpio_chip, irq);3696}3697 3698static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)3699{3700	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);3701 3702	seq_printf(p, "%s", gpio_chip->label);3703}3704 3705static const struct irq_chip ingenic_gpio_irqchip = {3706	.irq_enable		= ingenic_gpio_irq_enable,3707	.irq_disable		= ingenic_gpio_irq_disable,3708	.irq_unmask		= ingenic_gpio_irq_unmask,3709	.irq_mask		= ingenic_gpio_irq_mask,3710	.irq_ack		= ingenic_gpio_irq_ack,3711	.irq_set_type		= ingenic_gpio_irq_set_type,3712	.irq_set_wake		= ingenic_gpio_irq_set_wake,3713	.irq_request_resources	= ingenic_gpio_irq_request,3714	.irq_release_resources	= ingenic_gpio_irq_release,3715	.irq_print_chip		= ingenic_gpio_irq_print_chip,3716	.flags			= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,3717};3718 3719static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,3720		int pin, int func)3721{3722	unsigned int idx = pin % PINS_PER_GPIO_CHIP;3723	unsigned int offt = pin / PINS_PER_GPIO_CHIP;3724 3725	dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",3726			'A' + offt, idx, func);3727 3728	if (is_soc_or_above(jzpc, ID_X1000)) {3729		ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);3730		ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);3731		ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);3732		ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);3733		ingenic_shadow_config_pin_load(jzpc, pin);3734	} else if (is_soc_or_above(jzpc, ID_JZ4770)) {3735		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);3736		ingenic_config_pin(jzpc, pin, GPIO_MSK, false);3737		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);3738		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);3739	} else if (is_soc_or_above(jzpc, ID_JZ4740)) {3740		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);3741		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);3742		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);3743	} else {3744		ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);3745		jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func);3746	}3747 3748	return 0;3749}3750 3751static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,3752		unsigned int selector, unsigned int group)3753{3754	struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);3755	struct function_desc *func;3756	struct group_desc *grp;3757	unsigned int i;3758	uintptr_t mode;3759	u8 *pin_modes;3760 3761	func = pinmux_generic_get_function(pctldev, selector);3762	if (!func)3763		return -EINVAL;3764 3765	grp = pinctrl_generic_get_group(pctldev, group);3766	if (!grp)3767		return -EINVAL;3768 3769	dev_dbg(pctldev->dev, "enable function %s group %s\n",3770		func->func.name, grp->grp.name);3771 3772	mode = (uintptr_t)grp->data;3773	if (mode <= 3) {3774		for (i = 0; i < grp->grp.npins; i++)3775			ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], mode);3776	} else {3777		pin_modes = grp->data;3778 3779		for (i = 0; i < grp->grp.npins; i++)3780			ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], pin_modes[i]);3781	}3782 3783	return 0;3784}3785 3786static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,3787		struct pinctrl_gpio_range *range,3788		unsigned int pin, bool input)3789{3790	struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);3791	unsigned int idx = pin % PINS_PER_GPIO_CHIP;3792	unsigned int offt = pin / PINS_PER_GPIO_CHIP;3793 3794	dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",3795			'A' + offt, idx, input ? "in" : "out");3796 3797	if (is_soc_or_above(jzpc, ID_X1000)) {3798		ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);3799		ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);3800		ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);3801		ingenic_shadow_config_pin_load(jzpc, pin);3802	} else if (is_soc_or_above(jzpc, ID_JZ4770)) {3803		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);3804		ingenic_config_pin(jzpc, pin, GPIO_MSK, true);3805		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);3806	} else if (is_soc_or_above(jzpc, ID_JZ4740)) {3807		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);3808		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);3809		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);3810	} else {3811		ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);3812		ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input);3813		jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0);3814	}3815 3816	return 0;3817}3818 3819static const struct pinmux_ops ingenic_pmxops = {3820	.get_functions_count = pinmux_generic_get_function_count,3821	.get_function_name = pinmux_generic_get_function_name,3822	.get_function_groups = pinmux_generic_get_function_groups,3823	.set_mux = ingenic_pinmux_set_mux,3824	.gpio_set_direction = ingenic_pinmux_gpio_set_direction,3825};3826 3827static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,3828		unsigned int pin, unsigned long *config)3829{3830	struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);3831	enum pin_config_param param = pinconf_to_config_param(*config);3832	unsigned int idx = pin % PINS_PER_GPIO_CHIP;3833	unsigned int offt = pin / PINS_PER_GPIO_CHIP;3834	unsigned int arg = 1;3835	unsigned int bias, reg;3836	bool pull, pullup, pulldown;3837 3838	if (is_soc_or_above(jzpc, ID_X2000)) {3839		pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&3840				!ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&3841				(jzpc->info->pull_ups[offt] & BIT(idx));3842		pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&3843				!ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&3844				(jzpc->info->pull_downs[offt] & BIT(idx));3845 3846	} else if (is_soc_or_above(jzpc, ID_X1830)) {3847		unsigned int half = PINS_PER_GPIO_CHIP / 2;3848		unsigned int idxh = (pin % half) * 2;3849 3850		if (idx < half)3851			regmap_read(jzpc->map, offt * jzpc->info->reg_offset +3852					X1830_GPIO_PEL, &bias);3853		else3854			regmap_read(jzpc->map, offt * jzpc->info->reg_offset +3855					X1830_GPIO_PEH, &bias);3856 3857		bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN);3858 3859		pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx));3860		pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));3861 3862	} else {3863		if (is_soc_or_above(jzpc, ID_JZ4770))3864			pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);3865		else if (is_soc_or_above(jzpc, ID_JZ4740))3866			pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);3867		else3868			pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR);3869 3870		pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));3871		pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));3872	}3873 3874	switch (param) {3875	case PIN_CONFIG_BIAS_DISABLE:3876		if (pullup || pulldown)3877			return -EINVAL;3878 3879		break;3880 3881	case PIN_CONFIG_BIAS_PULL_UP:3882		if (!pullup)3883			return -EINVAL;3884 3885		break;3886 3887	case PIN_CONFIG_BIAS_PULL_DOWN:3888		if (!pulldown)3889			return -EINVAL;3890 3891		break;3892 3893	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:3894		if (is_soc_or_above(jzpc, ID_X2000))3895			reg = X2000_GPIO_SMT;3896		else if (is_soc_or_above(jzpc, ID_X1830))3897			reg = X1830_GPIO_SMT;3898		else3899			return -EINVAL;3900 3901		arg = !!ingenic_get_pin_config(jzpc, pin, reg);3902		break;3903 3904	case PIN_CONFIG_SLEW_RATE:3905		if (is_soc_or_above(jzpc, ID_X2000))3906			reg = X2000_GPIO_SR;3907		else if (is_soc_or_above(jzpc, ID_X1830))3908			reg = X1830_GPIO_SR;3909		else3910			return -EINVAL;3911 3912		arg = !!ingenic_get_pin_config(jzpc, pin, reg);3913		break;3914 3915	default:3916		return -ENOTSUPP;3917	}3918 3919	*config = pinconf_to_config_packed(param, arg);3920	return 0;3921}3922 3923static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,3924		unsigned int pin, unsigned int bias)3925{3926	if (is_soc_or_above(jzpc, ID_X2000)) {3927		switch (bias) {3928		case GPIO_PULL_UP:3929			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);3930			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true);3931			break;3932 3933		case GPIO_PULL_DOWN:3934			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);3935			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true);3936			break;3937 3938		case GPIO_PULL_DIS:3939		default:3940			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);3941			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);3942		}3943 3944	} else if (is_soc_or_above(jzpc, ID_X1830)) {3945		unsigned int idx = pin % PINS_PER_GPIO_CHIP;3946		unsigned int half = PINS_PER_GPIO_CHIP / 2;3947		unsigned int idxh = (pin % half) * 2;3948		unsigned int offt = pin / PINS_PER_GPIO_CHIP;3949 3950		if (idx < half) {3951			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +3952					REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);3953			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +3954					REG_SET(X1830_GPIO_PEL), bias << idxh);3955		} else {3956			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +3957					REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);3958			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +3959					REG_SET(X1830_GPIO_PEH), bias << idxh);3960		}3961 3962	} else if (is_soc_or_above(jzpc, ID_JZ4770)) {3963		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);3964	} else if (is_soc_or_above(jzpc, ID_JZ4740)) {3965		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);3966	} else {3967		ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias);3968	}3969}3970 3971static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc,3972		unsigned int pin, bool enable)3973{3974	if (is_soc_or_above(jzpc, ID_X2000))3975		ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable);3976	else3977		ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable);3978}3979 3980static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,3981				     unsigned int pin, bool high)3982{3983	if (is_soc_or_above(jzpc, ID_JZ4770))3984		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high);3985	else if (is_soc_or_above(jzpc, ID_JZ4740))3986		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);3987	else3988		ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high);3989}3990 3991static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc,3992		unsigned int pin, unsigned int slew)3993{3994	if (is_soc_or_above(jzpc, ID_X2000))3995		ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew);3996	else3997		ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew);3998}3999 4000static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,4001		unsigned long *configs, unsigned int num_configs)4002{4003	struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);4004	unsigned int idx = pin % PINS_PER_GPIO_CHIP;4005	unsigned int offt = pin / PINS_PER_GPIO_CHIP;4006	unsigned int cfg, arg;4007	int ret;4008 4009	for (cfg = 0; cfg < num_configs; cfg++) {4010		switch (pinconf_to_config_param(configs[cfg])) {4011		case PIN_CONFIG_BIAS_DISABLE:4012		case PIN_CONFIG_BIAS_PULL_UP:4013		case PIN_CONFIG_BIAS_PULL_DOWN:4014		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:4015		case PIN_CONFIG_OUTPUT:4016		case PIN_CONFIG_SLEW_RATE:4017			continue;4018		default:4019			return -ENOTSUPP;4020		}4021	}4022 4023	for (cfg = 0; cfg < num_configs; cfg++) {4024		arg = pinconf_to_config_argument(configs[cfg]);4025 4026		switch (pinconf_to_config_param(configs[cfg])) {4027		case PIN_CONFIG_BIAS_DISABLE:4028			dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",4029					'A' + offt, idx);4030			ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);4031			break;4032 4033		case PIN_CONFIG_BIAS_PULL_UP:4034			if (!(jzpc->info->pull_ups[offt] & BIT(idx)))4035				return -EINVAL;4036			dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",4037					'A' + offt, idx);4038			ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);4039			break;4040 4041		case PIN_CONFIG_BIAS_PULL_DOWN:4042			if (!(jzpc->info->pull_downs[offt] & BIT(idx)))4043				return -EINVAL;4044			dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",4045					'A' + offt, idx);4046			ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);4047			break;4048 4049		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:4050			if (!is_soc_or_above(jzpc, ID_X1830))4051				return -EINVAL;4052 4053			ingenic_set_schmitt_trigger(jzpc, pin, arg);4054			break;4055 4056		case PIN_CONFIG_OUTPUT:4057			ret = pinctrl_gpio_direction_output(jzpc->gc,4058							pin - jzpc->gc->base);4059			if (ret)4060				return ret;4061 4062			ingenic_set_output_level(jzpc, pin, arg);4063			break;4064 4065		case PIN_CONFIG_SLEW_RATE:4066			if (!is_soc_or_above(jzpc, ID_X1830))4067				return -EINVAL;4068 4069			ingenic_set_slew_rate(jzpc, pin, arg);4070			break;4071 4072		default:4073			/* unreachable */4074			break;4075		}4076	}4077 4078	return 0;4079}4080 4081static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,4082		unsigned int group, unsigned long *config)4083{4084	const unsigned int *pins;4085	unsigned int i, npins, old = 0;4086	int ret;4087 4088	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);4089	if (ret)4090		return ret;4091 4092	for (i = 0; i < npins; i++) {4093		if (ingenic_pinconf_get(pctldev, pins[i], config))4094			return -ENOTSUPP;4095 4096		/* configs do not match between two pins */4097		if (i && (old != *config))4098			return -ENOTSUPP;4099 4100		old = *config;4101	}4102 4103	return 0;4104}4105 4106static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,4107		unsigned int group, unsigned long *configs,4108		unsigned int num_configs)4109{4110	const unsigned int *pins;4111	unsigned int i, npins;4112	int ret;4113 4114	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);4115	if (ret)4116		return ret;4117 4118	for (i = 0; i < npins; i++) {4119		ret = ingenic_pinconf_set(pctldev,4120				pins[i], configs, num_configs);4121		if (ret)4122			return ret;4123	}4124 4125	return 0;4126}4127 4128static const struct pinconf_ops ingenic_confops = {4129	.is_generic = true,4130	.pin_config_get = ingenic_pinconf_get,4131	.pin_config_set = ingenic_pinconf_set,4132	.pin_config_group_get = ingenic_pinconf_group_get,4133	.pin_config_group_set = ingenic_pinconf_group_set,4134};4135 4136static const struct regmap_config ingenic_pinctrl_regmap_config = {4137	.reg_bits = 32,4138	.val_bits = 32,4139	.reg_stride = 4,4140};4141 4142static const struct of_device_id ingenic_gpio_of_matches[] __initconst = {4143	{ .compatible = "ingenic,jz4730-gpio" },4144	{ .compatible = "ingenic,jz4740-gpio" },4145	{ .compatible = "ingenic,jz4725b-gpio" },4146	{ .compatible = "ingenic,jz4750-gpio" },4147	{ .compatible = "ingenic,jz4755-gpio" },4148	{ .compatible = "ingenic,jz4760-gpio" },4149	{ .compatible = "ingenic,jz4770-gpio" },4150	{ .compatible = "ingenic,jz4775-gpio" },4151	{ .compatible = "ingenic,jz4780-gpio" },4152	{ .compatible = "ingenic,x1000-gpio" },4153	{ .compatible = "ingenic,x1830-gpio" },4154	{ .compatible = "ingenic,x2000-gpio" },4155	{ .compatible = "ingenic,x2100-gpio" },4156	{},4157};4158 4159static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,4160				     struct fwnode_handle *fwnode)4161{4162	struct ingenic_gpio_chip *jzgc;4163	struct device *dev = jzpc->dev;4164	struct gpio_irq_chip *girq;4165	unsigned int bank;4166	int err;4167 4168	err = fwnode_property_read_u32(fwnode, "reg", &bank);4169	if (err) {4170		dev_err(dev, "Cannot read \"reg\" property: %i\n", err);4171		return err;4172	}4173 4174	jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);4175	if (!jzgc)4176		return -ENOMEM;4177 4178	jzpc->gc = &jzgc->gc;4179 4180	jzgc->jzpc = jzpc;4181	jzgc->reg_base = bank * jzpc->info->reg_offset;4182 4183	jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);4184	if (!jzgc->gc.label)4185		return -ENOMEM;4186 4187	/* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY4188	 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN4189	 * <linux/gpio/consumer.h> INSTEAD.4190	 */4191	jzgc->gc.base = bank * 32;4192 4193	jzgc->gc.ngpio = 32;4194	jzgc->gc.parent = dev;4195	jzgc->gc.fwnode = fwnode;4196	jzgc->gc.owner = THIS_MODULE;4197 4198	jzgc->gc.set = ingenic_gpio_set;4199	jzgc->gc.get = ingenic_gpio_get;4200	jzgc->gc.direction_input = pinctrl_gpio_direction_input;4201	jzgc->gc.direction_output = ingenic_gpio_direction_output;4202	jzgc->gc.get_direction = ingenic_gpio_get_direction;4203	jzgc->gc.request = gpiochip_generic_request;4204	jzgc->gc.free = gpiochip_generic_free;4205 4206	err = fwnode_irq_get(fwnode, 0);4207	if (err < 0)4208		return err;4209	if (!err)4210		return -EINVAL;4211	jzgc->irq = err;4212 4213	girq = &jzgc->gc.irq;4214	gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip);4215	girq->parent_handler = ingenic_gpio_irq_handler;4216	girq->num_parents = 1;4217	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),4218				     GFP_KERNEL);4219	if (!girq->parents)4220		return -ENOMEM;4221 4222	girq->parents[0] = jzgc->irq;4223	girq->default_type = IRQ_TYPE_NONE;4224	girq->handler = handle_level_irq;4225 4226	err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);4227	if (err)4228		return err;4229 4230	return 0;4231}4232 4233static int __init ingenic_pinctrl_probe(struct platform_device *pdev)4234{4235	struct device *dev = &pdev->dev;4236	struct ingenic_pinctrl *jzpc;4237	struct pinctrl_desc *pctl_desc;4238	void __iomem *base;4239	const struct ingenic_chip_info *chip_info;4240	struct regmap_config regmap_config;4241	struct fwnode_handle *fwnode;4242	unsigned int i;4243	int err;4244 4245	chip_info = device_get_match_data(dev);4246	if (!chip_info) {4247		dev_err(dev, "Unsupported SoC\n");4248		return -EINVAL;4249	}4250 4251	jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);4252	if (!jzpc)4253		return -ENOMEM;4254 4255	base = devm_platform_ioremap_resource(pdev, 0);4256	if (IS_ERR(base))4257		return PTR_ERR(base);4258 4259	regmap_config = ingenic_pinctrl_regmap_config;4260	if (chip_info->access_table) {4261		regmap_config.rd_table = chip_info->access_table;4262		regmap_config.wr_table = chip_info->access_table;4263	} else {4264		regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;4265	}4266 4267	jzpc->map = devm_regmap_init_mmio(dev, base, &regmap_config);4268	if (IS_ERR(jzpc->map)) {4269		dev_err(dev, "Failed to create regmap\n");4270		return PTR_ERR(jzpc->map);4271	}4272 4273	jzpc->dev = dev;4274	jzpc->info = chip_info;4275 4276	pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);4277	if (!pctl_desc)4278		return -ENOMEM;4279 4280	/* fill in pinctrl_desc structure */4281	pctl_desc->name = dev_name(dev);4282	pctl_desc->owner = THIS_MODULE;4283	pctl_desc->pctlops = &ingenic_pctlops;4284	pctl_desc->pmxops = &ingenic_pmxops;4285	pctl_desc->confops = &ingenic_confops;4286	pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;4287	pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,4288			pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);4289	if (!jzpc->pdesc)4290		return -ENOMEM;4291 4292	for (i = 0; i < pctl_desc->npins; i++) {4293		jzpc->pdesc[i].number = i;4294		jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",4295						'A' + (i / PINS_PER_GPIO_CHIP),4296						i % PINS_PER_GPIO_CHIP);4297	}4298 4299	jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);4300	if (IS_ERR(jzpc->pctl)) {4301		dev_err(dev, "Failed to register pinctrl\n");4302		return PTR_ERR(jzpc->pctl);4303	}4304 4305	for (i = 0; i < chip_info->num_groups; i++) {4306		const struct group_desc *group = &chip_info->groups[i];4307		const struct pingroup *grp = &group->grp;4308 4309		err = pinctrl_generic_add_group(jzpc->pctl, grp->name, grp->pins, grp->npins,4310						group->data);4311		if (err < 0) {4312			dev_err(dev, "Failed to register group %s\n", grp->name);4313			return err;4314		}4315	}4316 4317	for (i = 0; i < chip_info->num_functions; i++) {4318		const struct function_desc *function = &chip_info->functions[i];4319		const struct pinfunction *func = &function->func;4320 4321		err = pinmux_generic_add_function(jzpc->pctl, func->name,4322						  func->groups, func->ngroups,4323						  function->data);4324		if (err < 0) {4325			dev_err(dev, "Failed to register function %s\n", func->name);4326			return err;4327		}4328	}4329 4330	dev_set_drvdata(dev, jzpc->map);4331 4332	device_for_each_child_node(dev, fwnode) {4333		if (of_match_node(ingenic_gpio_of_matches, to_of_node(fwnode))) {4334			err = ingenic_gpio_probe(jzpc, fwnode);4335			if (err) {4336				fwnode_handle_put(fwnode);4337				return err;4338			}4339		}4340	}4341 4342	return 0;4343}4344 4345#define IF_ENABLED(cfg, ptr)	PTR_IF(IS_ENABLED(cfg), (ptr))4346 4347static const struct of_device_id ingenic_pinctrl_of_matches[] = {4348	{4349		.compatible = "ingenic,jz4730-pinctrl",4350		.data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info)4351	},4352	{4353		.compatible = "ingenic,jz4740-pinctrl",4354		.data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info)4355	},4356	{4357		.compatible = "ingenic,jz4725b-pinctrl",4358		.data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info)4359	},4360	{4361		.compatible = "ingenic,jz4750-pinctrl",4362		.data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info)4363	},4364	{4365		.compatible = "ingenic,jz4755-pinctrl",4366		.data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info)4367	},4368	{4369		.compatible = "ingenic,jz4760-pinctrl",4370		.data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)4371	},4372	{4373		.compatible = "ingenic,jz4760b-pinctrl",4374		.data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)4375	},4376	{4377		.compatible = "ingenic,jz4770-pinctrl",4378		.data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info)4379	},4380	{4381		.compatible = "ingenic,jz4775-pinctrl",4382		.data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info)4383	},4384	{4385		.compatible = "ingenic,jz4780-pinctrl",4386		.data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info)4387	},4388	{4389		.compatible = "ingenic,x1000-pinctrl",4390		.data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)4391	},4392	{4393		.compatible = "ingenic,x1000e-pinctrl",4394		.data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)4395	},4396	{4397		.compatible = "ingenic,x1500-pinctrl",4398		.data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)4399	},4400	{4401		.compatible = "ingenic,x1830-pinctrl",4402		.data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)4403	},4404	{4405		.compatible = "ingenic,x2000-pinctrl",4406		.data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)4407	},4408	{4409		.compatible = "ingenic,x2000e-pinctrl",4410		.data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)4411	},4412	{4413		.compatible = "ingenic,x2100-pinctrl",4414		.data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info)4415	},4416	{ /* sentinel */ },4417};4418 4419static struct platform_driver ingenic_pinctrl_driver = {4420	.driver = {4421		.name = "pinctrl-ingenic",4422		.of_match_table = ingenic_pinctrl_of_matches,4423	},4424};4425 4426static int __init ingenic_pinctrl_drv_register(void)4427{4428	return platform_driver_probe(&ingenic_pinctrl_driver,4429				     ingenic_pinctrl_probe);4430}4431subsys_initcall(ingenic_pinctrl_drv_register);4432