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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * linux/drivers/pinctrl/pinctrl-lantiq.h4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h5 *6 * Copyright (C) 2012 John Crispin <john@phrozen.org>7 */8 9#ifndef __PINCTRL_LANTIQ_H10#define __PINCTRL_LANTIQ_H11 12#include <linux/clkdev.h>13 14#include <linux/pinctrl/consumer.h>15#include <linux/pinctrl/machine.h>16#include <linux/pinctrl/pinconf.h>17#include <linux/pinctrl/pinctrl.h>18#include <linux/pinctrl/pinmux.h>19 20#include "core.h"21 22#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)23 24#define LTQ_MAX_MUX 425#define MFPR_FUNC_MASK 0x326 27#define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg))28#define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16)29#define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff)30 31enum ltq_pinconf_param {32 LTQ_PINCONF_PARAM_PULL,33 LTQ_PINCONF_PARAM_OPEN_DRAIN,34 LTQ_PINCONF_PARAM_DRIVE_CURRENT,35 LTQ_PINCONF_PARAM_SLEW_RATE,36 LTQ_PINCONF_PARAM_OUTPUT,37};38 39struct ltq_cfg_param {40 const char *property;41 enum ltq_pinconf_param param;42};43 44struct ltq_mfp_pin {45 const char *name;46 const unsigned int pin;47 const unsigned short func[LTQ_MAX_MUX];48};49 50struct ltq_pin_group {51 const char *name;52 const unsigned mux;53 const unsigned *pins;54 const unsigned npins;55};56 57struct ltq_pmx_func {58 const char *name;59 const char * const *groups;60 const unsigned num_groups;61};62 63struct ltq_pinmux_info {64 struct device *dev;65 struct pinctrl_dev *pctrl;66 67 /* we need to manage up to 5 pad controllers */68 void __iomem *membase[5];69 70 /* the descriptor for the subsystem */71 struct pinctrl_desc *desc;72 73 /* we expose our pads to the subsystem */74 struct pinctrl_pin_desc *pads;75 76 /* the number of pads. this varies between socs */77 unsigned int num_pads;78 79 /* these are our multifunction pins */80 const struct ltq_mfp_pin *mfp;81 unsigned int num_mfp;82 83 /* a number of multifunction pins can be grouped together */84 const struct ltq_pin_group *grps;85 unsigned int num_grps;86 87 /* a mapping between function string and id */88 const struct ltq_pmx_func *funcs;89 unsigned int num_funcs;90 91 /* the pinconf options that we are able to read from the DT */92 const struct ltq_cfg_param *params;93 unsigned int num_params;94 95 /* the pad controller can have a irq mapping */96 const unsigned *exin;97 unsigned int num_exin;98 99 /* we need 5 clocks max */100 struct clk *clk[5];101 102 /* soc specific callback used to apply muxing */103 int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);104};105 106enum ltq_pin {107 GPIO0 = 0,108 GPIO1,109 GPIO2,110 GPIO3,111 GPIO4,112 GPIO5,113 GPIO6,114 GPIO7,115 GPIO8,116 GPIO9,117 GPIO10, /* 10 */118 GPIO11,119 GPIO12,120 GPIO13,121 GPIO14,122 GPIO15,123 GPIO16,124 GPIO17,125 GPIO18,126 GPIO19,127 GPIO20, /* 20 */128 GPIO21,129 GPIO22,130 GPIO23,131 GPIO24,132 GPIO25,133 GPIO26,134 GPIO27,135 GPIO28,136 GPIO29,137 GPIO30, /* 30 */138 GPIO31,139 GPIO32,140 GPIO33,141 GPIO34,142 GPIO35,143 GPIO36,144 GPIO37,145 GPIO38,146 GPIO39,147 GPIO40, /* 40 */148 GPIO41,149 GPIO42,150 GPIO43,151 GPIO44,152 GPIO45,153 GPIO46,154 GPIO47,155 GPIO48,156 GPIO49,157 GPIO50, /* 50 */158 GPIO51,159 GPIO52,160 GPIO53,161 GPIO54,162 GPIO55,163 GPIO56,164 GPIO57,165 GPIO58,166 GPIO59,167 GPIO60, /* 60 */168 GPIO61,169 GPIO62,170 GPIO63,171 172 GPIO64,173 GPIO65,174 GPIO66,175 GPIO67,176 GPIO68,177 GPIO69,178 GPIO70,179 GPIO71,180 GPIO72,181 GPIO73,182 GPIO74,183 GPIO75,184 GPIO76,185 GPIO77,186 GPIO78,187 GPIO79,188 GPIO80,189 GPIO81,190 GPIO82,191 GPIO83,192 GPIO84,193 GPIO85,194 GPIO86,195 GPIO87,196 GPIO88,197};198 199extern int ltq_pinctrl_register(struct platform_device *pdev,200 struct ltq_pinmux_info *info);201#endif /* __PINCTRL_LANTIQ_H */202