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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * MAX77620 pin control driver.4 *5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.6 *7 * Author:8 * Chaitanya Bandi <bandik@nvidia.com>9 * Laxman Dewangan <ldewangan@nvidia.com>10 */11 12#include <linux/mfd/max77620.h>13#include <linux/mod_devicetable.h>14#include <linux/module.h>15#include <linux/platform_device.h>16#include <linux/property.h>17#include <linux/regmap.h>18 19#include <linux/pinctrl/pinctrl.h>20#include <linux/pinctrl/pinconf-generic.h>21#include <linux/pinctrl/pinconf.h>22#include <linux/pinctrl/pinmux.h>23 24#include "core.h"25#include "pinconf.h"26#include "pinctrl-utils.h"27 28#define MAX77620_PIN_NUM 829 30enum max77620_pin_ppdrv {31 MAX77620_PIN_UNCONFIG_DRV,32 MAX77620_PIN_OD_DRV,33 MAX77620_PIN_PP_DRV,34};35 36#define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1)37#define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2)38#define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3)39#define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4)40#define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5)41#define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6)42 43struct max77620_pin_function {44 const char *name;45 const char * const *groups;46 unsigned int ngroups;47 int mux_option;48};49 50static const struct pinconf_generic_params max77620_cfg_params[] = {51 {52 .property = "maxim,active-fps-source",53 .param = MAX77620_ACTIVE_FPS_SOURCE,54 }, {55 .property = "maxim,active-fps-power-up-slot",56 .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,57 }, {58 .property = "maxim,active-fps-power-down-slot",59 .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,60 }, {61 .property = "maxim,suspend-fps-source",62 .param = MAX77620_SUSPEND_FPS_SOURCE,63 }, {64 .property = "maxim,suspend-fps-power-up-slot",65 .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,66 }, {67 .property = "maxim,suspend-fps-power-down-slot",68 .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,69 },70};71 72enum max77620_alternate_pinmux_option {73 MAX77620_PINMUX_GPIO = 0,74 MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,75 MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,76 MAX77620_PINMUX_32K_OUT1 = 3,77 MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,78 MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,79 MAX77620_PINMUX_REFERENCE_OUT = 6,80};81 82struct max77620_pingroup {83 const char *name;84 const unsigned int pins[1];85 unsigned int npins;86 enum max77620_alternate_pinmux_option alt_option;87};88 89struct max77620_pin_info {90 enum max77620_pin_ppdrv drv_type;91};92 93struct max77620_fps_config {94 int active_fps_src;95 int active_power_up_slots;96 int active_power_down_slots;97 int suspend_fps_src;98 int suspend_power_up_slots;99 int suspend_power_down_slots;100};101 102struct max77620_pctrl_info {103 struct device *dev;104 struct pinctrl_dev *pctl;105 struct regmap *rmap;106 const struct max77620_pin_function *functions;107 unsigned int num_functions;108 const struct max77620_pingroup *pin_groups;109 int num_pin_groups;110 const struct pinctrl_pin_desc *pins;111 unsigned int num_pins;112 struct max77620_pin_info pin_info[MAX77620_PIN_NUM];113 struct max77620_fps_config fps_config[MAX77620_PIN_NUM];114};115 116static const struct pinctrl_pin_desc max77620_pins_desc[] = {117 PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),118 PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),119 PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),120 PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),121 PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),122 PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),123 PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),124 PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),125};126 127static const char * const gpio_groups[] = {128 "gpio0",129 "gpio1",130 "gpio2",131 "gpio3",132 "gpio4",133 "gpio5",134 "gpio6",135 "gpio7",136};137 138#define FUNCTION_GROUP(fname, mux) \139 { \140 .name = fname, \141 .groups = gpio_groups, \142 .ngroups = ARRAY_SIZE(gpio_groups), \143 .mux_option = MAX77620_PINMUX_##mux, \144 }145 146static const struct max77620_pin_function max77620_pin_function[] = {147 FUNCTION_GROUP("gpio", GPIO),148 FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),149 FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),150 FUNCTION_GROUP("32k-out1", 32K_OUT1),151 FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),152 FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),153 FUNCTION_GROUP("reference-out", REFERENCE_OUT),154};155 156#define MAX77620_PINGROUP(pg_name, pin_id, option) \157 { \158 .name = #pg_name, \159 .pins = {MAX77620_##pin_id}, \160 .npins = 1, \161 .alt_option = MAX77620_PINMUX_##option, \162 }163 164static const struct max77620_pingroup max77620_pingroups[] = {165 MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),166 MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),167 MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),168 MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),169 MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),170 MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),171 MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),172 MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),173};174 175static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)176{177 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);178 179 return mpci->num_pin_groups;180}181 182static const char *max77620_pinctrl_get_group_name(183 struct pinctrl_dev *pctldev, unsigned int group)184{185 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);186 187 return mpci->pin_groups[group].name;188}189 190static int max77620_pinctrl_get_group_pins(191 struct pinctrl_dev *pctldev, unsigned int group,192 const unsigned int **pins, unsigned int *num_pins)193{194 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);195 196 *pins = mpci->pin_groups[group].pins;197 *num_pins = mpci->pin_groups[group].npins;198 199 return 0;200}201 202static const struct pinctrl_ops max77620_pinctrl_ops = {203 .get_groups_count = max77620_pinctrl_get_groups_count,204 .get_group_name = max77620_pinctrl_get_group_name,205 .get_group_pins = max77620_pinctrl_get_group_pins,206 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,207 .dt_free_map = pinctrl_utils_free_map,208};209 210static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)211{212 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);213 214 return mpci->num_functions;215}216 217static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,218 unsigned int function)219{220 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);221 222 return mpci->functions[function].name;223}224 225static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,226 unsigned int function,227 const char * const **groups,228 unsigned int * const num_groups)229{230 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);231 232 *groups = mpci->functions[function].groups;233 *num_groups = mpci->functions[function].ngroups;234 235 return 0;236}237 238static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,239 unsigned int function, unsigned int group)240{241 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);242 u8 val;243 int ret;244 245 if (function == MAX77620_PINMUX_GPIO) {246 val = 0;247 } else if (function == mpci->pin_groups[group].alt_option) {248 val = 1 << group;249 } else {250 dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",251 group, function);252 return -EINVAL;253 }254 ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,255 BIT(group), val);256 if (ret < 0)257 dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);258 259 return ret;260}261 262static const struct pinmux_ops max77620_pinmux_ops = {263 .get_functions_count = max77620_pinctrl_get_funcs_count,264 .get_function_name = max77620_pinctrl_get_func_name,265 .get_function_groups = max77620_pinctrl_get_func_groups,266 .set_mux = max77620_pinctrl_enable,267};268 269static int max77620_pinconf_get(struct pinctrl_dev *pctldev,270 unsigned int pin, unsigned long *config)271{272 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);273 struct device *dev = mpci->dev;274 enum pin_config_param param = pinconf_to_config_param(*config);275 unsigned int val;276 int arg = 0;277 int ret;278 279 switch (param) {280 case PIN_CONFIG_DRIVE_OPEN_DRAIN:281 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)282 arg = 1;283 break;284 285 case PIN_CONFIG_DRIVE_PUSH_PULL:286 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)287 arg = 1;288 break;289 290 case PIN_CONFIG_BIAS_PULL_UP:291 ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);292 if (ret < 0) {293 dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);294 return ret;295 }296 if (val & BIT(pin))297 arg = 1;298 break;299 300 case PIN_CONFIG_BIAS_PULL_DOWN:301 ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);302 if (ret < 0) {303 dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);304 return ret;305 }306 if (val & BIT(pin))307 arg = 1;308 break;309 310 default:311 dev_err(dev, "Properties not supported\n");312 return -ENOTSUPP;313 }314 315 *config = pinconf_to_config_packed(param, (u16)arg);316 317 return 0;318}319 320static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,321 int addr, int *fps)322{323 unsigned int val;324 int ret;325 326 ret = regmap_read(mpci->rmap, addr, &val);327 if (ret < 0) {328 dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);329 return ret;330 }331 *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;332 333 return 0;334}335 336static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,337 int pin, int param)338{339 struct max77620_fps_config *fps_config = &mpci->fps_config[pin];340 int addr, ret;341 int param_val;342 int mask, shift;343 344 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))345 return 0;346 347 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;348 switch (param) {349 case MAX77620_ACTIVE_FPS_SOURCE:350 case MAX77620_SUSPEND_FPS_SOURCE:351 mask = MAX77620_FPS_SRC_MASK;352 shift = MAX77620_FPS_SRC_SHIFT;353 param_val = fps_config->active_fps_src;354 if (param == MAX77620_SUSPEND_FPS_SOURCE)355 param_val = fps_config->suspend_fps_src;356 break;357 358 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:359 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:360 mask = MAX77620_FPS_PU_PERIOD_MASK;361 shift = MAX77620_FPS_PU_PERIOD_SHIFT;362 param_val = fps_config->active_power_up_slots;363 if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)364 param_val = fps_config->suspend_power_up_slots;365 break;366 367 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:368 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:369 mask = MAX77620_FPS_PD_PERIOD_MASK;370 shift = MAX77620_FPS_PD_PERIOD_SHIFT;371 param_val = fps_config->active_power_down_slots;372 if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)373 param_val = fps_config->suspend_power_down_slots;374 break;375 376 default:377 dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",378 param, pin);379 return -EINVAL;380 }381 382 if (param_val < 0)383 return 0;384 385 ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);386 if (ret < 0)387 dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);388 389 return ret;390}391 392static int max77620_pinconf_set(struct pinctrl_dev *pctldev,393 unsigned int pin, unsigned long *configs,394 unsigned int num_configs)395{396 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);397 struct device *dev = mpci->dev;398 struct max77620_fps_config *fps_config;399 int param;400 u32 param_val;401 unsigned int val;402 unsigned int pu_val;403 unsigned int pd_val;404 int addr, ret;405 int i;406 407 for (i = 0; i < num_configs; i++) {408 param = pinconf_to_config_param(configs[i]);409 param_val = pinconf_to_config_argument(configs[i]);410 411 switch (param) {412 case PIN_CONFIG_DRIVE_OPEN_DRAIN:413 val = param_val ? 0 : 1;414 ret = regmap_update_bits(mpci->rmap,415 MAX77620_REG_GPIO0 + pin,416 MAX77620_CNFG_GPIO_DRV_MASK,417 val);418 if (ret)419 goto report_update_failure;420 421 mpci->pin_info[pin].drv_type = val ?422 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;423 break;424 425 case PIN_CONFIG_DRIVE_PUSH_PULL:426 val = param_val ? 1 : 0;427 ret = regmap_update_bits(mpci->rmap,428 MAX77620_REG_GPIO0 + pin,429 MAX77620_CNFG_GPIO_DRV_MASK,430 val);431 if (ret)432 goto report_update_failure;433 434 mpci->pin_info[pin].drv_type = val ?435 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;436 break;437 438 case MAX77620_ACTIVE_FPS_SOURCE:439 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:440 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:441 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))442 return -EINVAL;443 444 fps_config = &mpci->fps_config[pin];445 446 if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&447 (param_val == MAX77620_FPS_SRC_DEF)) {448 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;449 ret = max77620_get_default_fps(450 mpci, addr,451 &fps_config->active_fps_src);452 if (ret < 0)453 return ret;454 break;455 }456 457 if (param == MAX77620_ACTIVE_FPS_SOURCE)458 fps_config->active_fps_src = param_val;459 else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)460 fps_config->active_power_up_slots = param_val;461 else462 fps_config->active_power_down_slots = param_val;463 464 ret = max77620_set_fps_param(mpci, pin, param);465 if (ret < 0)466 return ret;467 break;468 469 case MAX77620_SUSPEND_FPS_SOURCE:470 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:471 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:472 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))473 return -EINVAL;474 475 fps_config = &mpci->fps_config[pin];476 477 if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&478 (param_val == MAX77620_FPS_SRC_DEF)) {479 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;480 ret = max77620_get_default_fps(481 mpci, addr,482 &fps_config->suspend_fps_src);483 if (ret < 0)484 return ret;485 break;486 }487 488 if (param == MAX77620_SUSPEND_FPS_SOURCE)489 fps_config->suspend_fps_src = param_val;490 else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)491 fps_config->suspend_power_up_slots = param_val;492 else493 fps_config->suspend_power_down_slots =494 param_val;495 break;496 497 case PIN_CONFIG_BIAS_PULL_UP:498 case PIN_CONFIG_BIAS_PULL_DOWN:499 pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?500 BIT(pin) : 0;501 pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?502 BIT(pin) : 0;503 504 ret = regmap_update_bits(mpci->rmap,505 MAX77620_REG_PUE_GPIO,506 BIT(pin), pu_val);507 if (ret < 0) {508 dev_err(dev, "PUE_GPIO update failed: %d\n",509 ret);510 return ret;511 }512 513 ret = regmap_update_bits(mpci->rmap,514 MAX77620_REG_PDE_GPIO,515 BIT(pin), pd_val);516 if (ret < 0) {517 dev_err(dev, "PDE_GPIO update failed: %d\n",518 ret);519 return ret;520 }521 break;522 523 default:524 dev_err(dev, "Properties not supported\n");525 return -ENOTSUPP;526 }527 }528 529 return 0;530 531report_update_failure:532 dev_err(dev, "Reg 0x%02x update failed %d\n",533 MAX77620_REG_GPIO0 + pin, ret);534 return ret;535}536 537static const struct pinconf_ops max77620_pinconf_ops = {538 .pin_config_get = max77620_pinconf_get,539 .pin_config_set = max77620_pinconf_set,540};541 542static struct pinctrl_desc max77620_pinctrl_desc = {543 .pctlops = &max77620_pinctrl_ops,544 .pmxops = &max77620_pinmux_ops,545 .confops = &max77620_pinconf_ops,546};547 548static int max77620_pinctrl_probe(struct platform_device *pdev)549{550 struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);551 struct max77620_pctrl_info *mpci;552 int i;553 554 device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));555 556 mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);557 if (!mpci)558 return -ENOMEM;559 560 mpci->dev = &pdev->dev;561 mpci->rmap = max77620->rmap;562 563 mpci->pins = max77620_pins_desc;564 mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);565 mpci->functions = max77620_pin_function;566 mpci->num_functions = ARRAY_SIZE(max77620_pin_function);567 mpci->pin_groups = max77620_pingroups;568 mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);569 platform_set_drvdata(pdev, mpci);570 571 max77620_pinctrl_desc.name = dev_name(&pdev->dev);572 max77620_pinctrl_desc.pins = max77620_pins_desc;573 max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);574 max77620_pinctrl_desc.num_custom_params =575 ARRAY_SIZE(max77620_cfg_params);576 max77620_pinctrl_desc.custom_params = max77620_cfg_params;577 578 for (i = 0; i < MAX77620_PIN_NUM; ++i) {579 mpci->fps_config[i].active_fps_src = -1;580 mpci->fps_config[i].active_power_up_slots = -1;581 mpci->fps_config[i].active_power_down_slots = -1;582 mpci->fps_config[i].suspend_fps_src = -1;583 mpci->fps_config[i].suspend_power_up_slots = -1;584 mpci->fps_config[i].suspend_power_down_slots = -1;585 }586 587 mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,588 mpci);589 if (IS_ERR(mpci->pctl)) {590 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");591 return PTR_ERR(mpci->pctl);592 }593 594 return 0;595}596 597#ifdef CONFIG_PM_SLEEP598static int max77620_suspend_fps_param[] = {599 MAX77620_SUSPEND_FPS_SOURCE,600 MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,601 MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,602};603 604static int max77620_active_fps_param[] = {605 MAX77620_ACTIVE_FPS_SOURCE,606 MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,607 MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,608};609 610static int max77620_pinctrl_suspend(struct device *dev)611{612 struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);613 int pin, p;614 615 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {616 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))617 continue;618 for (p = 0; p < 3; ++p)619 max77620_set_fps_param(620 mpci, pin, max77620_suspend_fps_param[p]);621 }622 623 return 0;624};625 626static int max77620_pinctrl_resume(struct device *dev)627{628 struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);629 int pin, p;630 631 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {632 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))633 continue;634 for (p = 0; p < 3; ++p)635 max77620_set_fps_param(636 mpci, pin, max77620_active_fps_param[p]);637 }638 639 return 0;640}641#endif642 643static const struct dev_pm_ops max77620_pinctrl_pm_ops = {644 SET_SYSTEM_SLEEP_PM_OPS(645 max77620_pinctrl_suspend, max77620_pinctrl_resume)646};647 648static const struct platform_device_id max77620_pinctrl_devtype[] = {649 { .name = "max77620-pinctrl", },650 { .name = "max20024-pinctrl", },651 {},652};653MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);654 655static struct platform_driver max77620_pinctrl_driver = {656 .driver = {657 .name = "max77620-pinctrl",658 .pm = &max77620_pinctrl_pm_ops,659 },660 .probe = max77620_pinctrl_probe,661 .id_table = max77620_pinctrl_devtype,662};663 664module_platform_driver(max77620_pinctrl_driver);665 666MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");667MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");668MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");669MODULE_LICENSE("GPL v2");670