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1// SPDX-License-Identifier: GPL-2.0-only2/* MCP23S08 SPI/I2C GPIO driver */3 4#include <linux/bitops.h>5#include <linux/kernel.h>6#include <linux/device.h>7#include <linux/mutex.h>8#include <linux/mod_devicetable.h>9#include <linux/module.h>10#include <linux/export.h>11#include <linux/gpio/driver.h>12#include <linux/gpio/consumer.h>13#include <linux/seq_file.h>14#include <linux/slab.h>15#include <asm/byteorder.h>16#include <linux/interrupt.h>17#include <linux/regmap.h>18#include <linux/pinctrl/pinctrl.h>19#include <linux/pinctrl/pinconf.h>20#include <linux/pinctrl/pinconf-generic.h>21 22#include "pinctrl-mcp23s08.h"23 24/* Registers are all 8 bits wide.25 *26 * The mcp23s17 has twice as many bits, and can be configured to work27 * with either 16 bit registers or with two adjacent 8 bit banks.28 */29#define MCP_IODIR 0x00 /* init/reset: all ones */30#define MCP_IPOL 0x0131#define MCP_GPINTEN 0x0232#define MCP_DEFVAL 0x0333#define MCP_INTCON 0x0434#define MCP_IOCON 0x0535# define IOCON_MIRROR (1 << 6)36# define IOCON_SEQOP (1 << 5)37# define IOCON_HAEN (1 << 3)38# define IOCON_ODR (1 << 2)39# define IOCON_INTPOL (1 << 1)40# define IOCON_INTCC (1)41#define MCP_GPPU 0x0642#define MCP_INTF 0x0743#define MCP_INTCAP 0x0844#define MCP_GPIO 0x0945#define MCP_OLAT 0x0a46 47static const struct reg_default mcp23x08_defaults[] = {48 {.reg = MCP_IODIR, .def = 0xff},49 {.reg = MCP_IPOL, .def = 0x00},50 {.reg = MCP_GPINTEN, .def = 0x00},51 {.reg = MCP_DEFVAL, .def = 0x00},52 {.reg = MCP_INTCON, .def = 0x00},53 {.reg = MCP_IOCON, .def = 0x00},54 {.reg = MCP_GPPU, .def = 0x00},55 {.reg = MCP_OLAT, .def = 0x00},56};57 58static const struct regmap_range mcp23x08_volatile_range = {59 .range_min = MCP_INTF,60 .range_max = MCP_GPIO,61};62 63static const struct regmap_access_table mcp23x08_volatile_table = {64 .yes_ranges = &mcp23x08_volatile_range,65 .n_yes_ranges = 1,66};67 68static const struct regmap_range mcp23x08_precious_range = {69 .range_min = MCP_GPIO,70 .range_max = MCP_GPIO,71};72 73static const struct regmap_access_table mcp23x08_precious_table = {74 .yes_ranges = &mcp23x08_precious_range,75 .n_yes_ranges = 1,76};77 78const struct regmap_config mcp23x08_regmap = {79 .reg_bits = 8,80 .val_bits = 8,81 82 .reg_stride = 1,83 .volatile_table = &mcp23x08_volatile_table,84 .precious_table = &mcp23x08_precious_table,85 .reg_defaults = mcp23x08_defaults,86 .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),87 .cache_type = REGCACHE_FLAT,88 .max_register = MCP_OLAT,89};90EXPORT_SYMBOL_GPL(mcp23x08_regmap);91 92static const struct reg_default mcp23x17_defaults[] = {93 {.reg = MCP_IODIR << 1, .def = 0xffff},94 {.reg = MCP_IPOL << 1, .def = 0x0000},95 {.reg = MCP_GPINTEN << 1, .def = 0x0000},96 {.reg = MCP_DEFVAL << 1, .def = 0x0000},97 {.reg = MCP_INTCON << 1, .def = 0x0000},98 {.reg = MCP_IOCON << 1, .def = 0x0000},99 {.reg = MCP_GPPU << 1, .def = 0x0000},100 {.reg = MCP_OLAT << 1, .def = 0x0000},101};102 103static const struct regmap_range mcp23x17_volatile_range = {104 .range_min = MCP_INTF << 1,105 .range_max = MCP_GPIO << 1,106};107 108static const struct regmap_access_table mcp23x17_volatile_table = {109 .yes_ranges = &mcp23x17_volatile_range,110 .n_yes_ranges = 1,111};112 113static const struct regmap_range mcp23x17_precious_range = {114 .range_min = MCP_INTCAP << 1,115 .range_max = MCP_GPIO << 1,116};117 118static const struct regmap_access_table mcp23x17_precious_table = {119 .yes_ranges = &mcp23x17_precious_range,120 .n_yes_ranges = 1,121};122 123const struct regmap_config mcp23x17_regmap = {124 .reg_bits = 8,125 .val_bits = 16,126 127 .reg_stride = 2,128 .max_register = MCP_OLAT << 1,129 .volatile_table = &mcp23x17_volatile_table,130 .precious_table = &mcp23x17_precious_table,131 .reg_defaults = mcp23x17_defaults,132 .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),133 .cache_type = REGCACHE_FLAT,134 .val_format_endian = REGMAP_ENDIAN_LITTLE,135};136EXPORT_SYMBOL_GPL(mcp23x17_regmap);137 138static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)139{140 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);141}142 143static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)144{145 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);146}147 148static int mcp_update_bits(struct mcp23s08 *mcp, unsigned int reg,149 unsigned int mask, unsigned int val)150{151 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,152 mask, val);153}154 155static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,156 unsigned int pin, bool enabled)157{158 u16 mask = BIT(pin);159 return mcp_update_bits(mcp, reg, mask, enabled ? mask : 0);160}161 162static const struct pinctrl_pin_desc mcp23x08_pins[] = {163 PINCTRL_PIN(0, "gpio0"),164 PINCTRL_PIN(1, "gpio1"),165 PINCTRL_PIN(2, "gpio2"),166 PINCTRL_PIN(3, "gpio3"),167 PINCTRL_PIN(4, "gpio4"),168 PINCTRL_PIN(5, "gpio5"),169 PINCTRL_PIN(6, "gpio6"),170 PINCTRL_PIN(7, "gpio7"),171};172 173static const struct pinctrl_pin_desc mcp23x17_pins[] = {174 PINCTRL_PIN(0, "gpio0"),175 PINCTRL_PIN(1, "gpio1"),176 PINCTRL_PIN(2, "gpio2"),177 PINCTRL_PIN(3, "gpio3"),178 PINCTRL_PIN(4, "gpio4"),179 PINCTRL_PIN(5, "gpio5"),180 PINCTRL_PIN(6, "gpio6"),181 PINCTRL_PIN(7, "gpio7"),182 PINCTRL_PIN(8, "gpio8"),183 PINCTRL_PIN(9, "gpio9"),184 PINCTRL_PIN(10, "gpio10"),185 PINCTRL_PIN(11, "gpio11"),186 PINCTRL_PIN(12, "gpio12"),187 PINCTRL_PIN(13, "gpio13"),188 PINCTRL_PIN(14, "gpio14"),189 PINCTRL_PIN(15, "gpio15"),190};191 192static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)193{194 return 0;195}196 197static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,198 unsigned int group)199{200 return NULL;201}202 203static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,204 unsigned int group,205 const unsigned int **pins,206 unsigned int *num_pins)207{208 return -ENOTSUPP;209}210 211static const struct pinctrl_ops mcp_pinctrl_ops = {212 .get_groups_count = mcp_pinctrl_get_groups_count,213 .get_group_name = mcp_pinctrl_get_group_name,214 .get_group_pins = mcp_pinctrl_get_group_pins,215#ifdef CONFIG_OF216 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,217 .dt_free_map = pinconf_generic_dt_free_map,218#endif219};220 221static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,222 unsigned long *config)223{224 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);225 enum pin_config_param param = pinconf_to_config_param(*config);226 unsigned int data, status;227 int ret;228 229 switch (param) {230 case PIN_CONFIG_BIAS_PULL_UP:231 ret = mcp_read(mcp, MCP_GPPU, &data);232 if (ret < 0)233 return ret;234 status = (data & BIT(pin)) ? 1 : 0;235 break;236 default:237 return -ENOTSUPP;238 }239 240 *config = 0;241 242 return status ? 0 : -EINVAL;243}244 245static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,246 unsigned long *configs, unsigned int num_configs)247{248 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);249 enum pin_config_param param;250 u32 arg;251 int ret = 0;252 int i;253 254 for (i = 0; i < num_configs; i++) {255 param = pinconf_to_config_param(configs[i]);256 arg = pinconf_to_config_argument(configs[i]);257 258 switch (param) {259 case PIN_CONFIG_BIAS_PULL_UP:260 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);261 break;262 default:263 dev_dbg(mcp->dev, "Invalid config param %04x\n", param);264 return -ENOTSUPP;265 }266 }267 268 return ret;269}270 271static const struct pinconf_ops mcp_pinconf_ops = {272 .pin_config_get = mcp_pinconf_get,273 .pin_config_set = mcp_pinconf_set,274 .is_generic = true,275};276 277/*----------------------------------------------------------------------*/278 279static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)280{281 struct mcp23s08 *mcp = gpiochip_get_data(chip);282 int status;283 284 mutex_lock(&mcp->lock);285 status = mcp_set_bit(mcp, MCP_IODIR, offset, true);286 mutex_unlock(&mcp->lock);287 288 return status;289}290 291static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)292{293 struct mcp23s08 *mcp = gpiochip_get_data(chip);294 int status, ret;295 296 mutex_lock(&mcp->lock);297 298 /* REVISIT reading this clears any IRQ ... */299 ret = mcp_read(mcp, MCP_GPIO, &status);300 if (ret < 0)301 status = 0;302 else {303 mcp->cached_gpio = status;304 status = !!(status & (1 << offset));305 }306 307 mutex_unlock(&mcp->lock);308 return status;309}310 311static int mcp23s08_get_multiple(struct gpio_chip *chip,312 unsigned long *mask, unsigned long *bits)313{314 struct mcp23s08 *mcp = gpiochip_get_data(chip);315 unsigned int status;316 int ret;317 318 mutex_lock(&mcp->lock);319 320 /* REVISIT reading this clears any IRQ ... */321 ret = mcp_read(mcp, MCP_GPIO, &status);322 if (ret < 0)323 status = 0;324 else {325 mcp->cached_gpio = status;326 *bits = status;327 }328 329 mutex_unlock(&mcp->lock);330 return ret;331}332 333static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)334{335 return mcp_update_bits(mcp, MCP_OLAT, mask, value ? mask : 0);336}337 338static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)339{340 struct mcp23s08 *mcp = gpiochip_get_data(chip);341 unsigned mask = BIT(offset);342 343 mutex_lock(&mcp->lock);344 __mcp23s08_set(mcp, mask, !!value);345 mutex_unlock(&mcp->lock);346}347 348static void mcp23s08_set_multiple(struct gpio_chip *chip,349 unsigned long *mask, unsigned long *bits)350{351 struct mcp23s08 *mcp = gpiochip_get_data(chip);352 353 mutex_lock(&mcp->lock);354 mcp_update_bits(mcp, MCP_OLAT, *mask, *bits);355 mutex_unlock(&mcp->lock);356}357 358static int359mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)360{361 struct mcp23s08 *mcp = gpiochip_get_data(chip);362 unsigned mask = BIT(offset);363 int status;364 365 mutex_lock(&mcp->lock);366 status = __mcp23s08_set(mcp, mask, value);367 if (status == 0) {368 status = mcp_update_bits(mcp, MCP_IODIR, mask, 0);369 }370 mutex_unlock(&mcp->lock);371 return status;372}373 374/*----------------------------------------------------------------------*/375static irqreturn_t mcp23s08_irq(int irq, void *data)376{377 struct mcp23s08 *mcp = data;378 int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval, gpinten;379 unsigned long int enabled_interrupts;380 unsigned int child_irq;381 bool intf_set, intcap_changed, gpio_bit_changed,382 defval_changed, gpio_set;383 384 mutex_lock(&mcp->lock);385 if (mcp_read(mcp, MCP_INTF, &intf))386 goto unlock;387 388 if (intf == 0) {389 /* There is no interrupt pending */390 goto unlock;391 }392 393 if (mcp_read(mcp, MCP_INTCAP, &intcap))394 goto unlock;395 396 if (mcp_read(mcp, MCP_INTCON, &intcon))397 goto unlock;398 399 if (mcp_read(mcp, MCP_GPINTEN, &gpinten))400 goto unlock;401 402 if (mcp_read(mcp, MCP_DEFVAL, &defval))403 goto unlock;404 405 /* This clears the interrupt(configurable on S18) */406 if (mcp_read(mcp, MCP_GPIO, &gpio))407 goto unlock;408 409 gpio_orig = mcp->cached_gpio;410 mcp->cached_gpio = gpio;411 mutex_unlock(&mcp->lock);412 413 dev_dbg(mcp->chip.parent,414 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",415 intcap, intf, gpio_orig, gpio);416 417 enabled_interrupts = gpinten;418 for_each_set_bit(i, &enabled_interrupts, mcp->chip.ngpio) {419 /*420 * We must check all of the inputs with enabled interrupts421 * on the chip, otherwise we may not notice a change422 * on more than one pin.423 *424 * On at least the mcp23s17, INTCAP is only updated425 * one byte at a time(INTCAPA and INTCAPB are426 * not written to at the same time - only on a per-bank427 * basis).428 *429 * INTF only contains the single bit that caused the430 * interrupt per-bank. On the mcp23s17, there is431 * INTFA and INTFB. If two pins are changed on the A432 * side at the same time, INTF will only have one bit433 * set. If one pin on the A side and one pin on the B434 * side are changed at the same time, INTF will have435 * two bits set. Thus, INTF can't be the only check436 * to see if the input has changed.437 */438 439 intf_set = intf & BIT(i);440 if (i < 8 && intf_set)441 intcap_mask = 0x00FF;442 else if (i >= 8 && intf_set)443 intcap_mask = 0xFF00;444 else445 intcap_mask = 0x00;446 447 intcap_changed = (intcap_mask &448 (intcap & BIT(i))) !=449 (intcap_mask & (BIT(i) & gpio_orig));450 gpio_set = BIT(i) & gpio;451 gpio_bit_changed = (BIT(i) & gpio_orig) !=452 (BIT(i) & gpio);453 defval_changed = (BIT(i) & intcon) &&454 ((BIT(i) & gpio) !=455 (BIT(i) & defval));456 457 if (((gpio_bit_changed || intcap_changed) &&458 (BIT(i) & mcp->irq_rise) && gpio_set) ||459 ((gpio_bit_changed || intcap_changed) &&460 (BIT(i) & mcp->irq_fall) && !gpio_set) ||461 defval_changed) {462 child_irq = irq_find_mapping(mcp->chip.irq.domain, i);463 handle_nested_irq(child_irq);464 }465 }466 467 return IRQ_HANDLED;468 469unlock:470 mutex_unlock(&mcp->lock);471 return IRQ_HANDLED;472}473 474static void mcp23s08_irq_mask(struct irq_data *data)475{476 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);477 struct mcp23s08 *mcp = gpiochip_get_data(gc);478 unsigned int pos = irqd_to_hwirq(data);479 480 mcp_set_bit(mcp, MCP_GPINTEN, pos, false);481 gpiochip_disable_irq(gc, pos);482}483 484static void mcp23s08_irq_unmask(struct irq_data *data)485{486 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);487 struct mcp23s08 *mcp = gpiochip_get_data(gc);488 unsigned int pos = irqd_to_hwirq(data);489 490 gpiochip_enable_irq(gc, pos);491 mcp_set_bit(mcp, MCP_GPINTEN, pos, true);492}493 494static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)495{496 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);497 struct mcp23s08 *mcp = gpiochip_get_data(gc);498 unsigned int pos = irqd_to_hwirq(data);499 500 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {501 mcp_set_bit(mcp, MCP_INTCON, pos, false);502 mcp->irq_rise |= BIT(pos);503 mcp->irq_fall |= BIT(pos);504 } else if (type & IRQ_TYPE_EDGE_RISING) {505 mcp_set_bit(mcp, MCP_INTCON, pos, false);506 mcp->irq_rise |= BIT(pos);507 mcp->irq_fall &= ~BIT(pos);508 } else if (type & IRQ_TYPE_EDGE_FALLING) {509 mcp_set_bit(mcp, MCP_INTCON, pos, false);510 mcp->irq_rise &= ~BIT(pos);511 mcp->irq_fall |= BIT(pos);512 } else if (type & IRQ_TYPE_LEVEL_HIGH) {513 mcp_set_bit(mcp, MCP_INTCON, pos, true);514 mcp_set_bit(mcp, MCP_DEFVAL, pos, false);515 } else if (type & IRQ_TYPE_LEVEL_LOW) {516 mcp_set_bit(mcp, MCP_INTCON, pos, true);517 mcp_set_bit(mcp, MCP_DEFVAL, pos, true);518 } else519 return -EINVAL;520 521 return 0;522}523 524static void mcp23s08_irq_bus_lock(struct irq_data *data)525{526 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);527 struct mcp23s08 *mcp = gpiochip_get_data(gc);528 529 mutex_lock(&mcp->lock);530 regcache_cache_only(mcp->regmap, true);531}532 533static void mcp23s08_irq_bus_unlock(struct irq_data *data)534{535 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);536 struct mcp23s08 *mcp = gpiochip_get_data(gc);537 538 regcache_cache_only(mcp->regmap, false);539 regcache_sync(mcp->regmap);540 541 mutex_unlock(&mcp->lock);542}543 544static int mcp23s08_irq_setup(struct mcp23s08 *mcp)545{546 struct gpio_chip *chip = &mcp->chip;547 int err;548 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;549 550 if (mcp->irq_active_high)551 irqflags |= IRQF_TRIGGER_HIGH;552 else553 irqflags |= IRQF_TRIGGER_LOW;554 555 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,556 mcp23s08_irq,557 irqflags, dev_name(chip->parent), mcp);558 if (err != 0) {559 dev_err(chip->parent, "unable to request IRQ#%d: %d\n",560 mcp->irq, err);561 return err;562 }563 564 return 0;565}566 567static void mcp23s08_irq_print_chip(struct irq_data *d, struct seq_file *p)568{569 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);570 struct mcp23s08 *mcp = gpiochip_get_data(gc);571 572 seq_printf(p, dev_name(mcp->dev));573}574 575static const struct irq_chip mcp23s08_irq_chip = {576 .irq_mask = mcp23s08_irq_mask,577 .irq_unmask = mcp23s08_irq_unmask,578 .irq_set_type = mcp23s08_irq_set_type,579 .irq_bus_lock = mcp23s08_irq_bus_lock,580 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,581 .irq_print_chip = mcp23s08_irq_print_chip,582 .flags = IRQCHIP_IMMUTABLE,583 GPIOCHIP_IRQ_RESOURCE_HELPERS,584};585 586/*----------------------------------------------------------------------*/587 588int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,589 unsigned int addr, unsigned int type, unsigned int base)590{591 int status, ret;592 bool mirror = false;593 bool open_drain = false;594 595 mutex_init(&mcp->lock);596 597 mcp->dev = dev;598 mcp->addr = addr;599 600 mcp->irq_active_high = false;601 602 mcp->chip.direction_input = mcp23s08_direction_input;603 mcp->chip.get = mcp23s08_get;604 mcp->chip.get_multiple = mcp23s08_get_multiple;605 mcp->chip.direction_output = mcp23s08_direction_output;606 mcp->chip.set = mcp23s08_set;607 mcp->chip.set_multiple = mcp23s08_set_multiple;608 609 mcp->chip.base = base;610 mcp->chip.can_sleep = true;611 mcp->chip.parent = dev;612 mcp->chip.owner = THIS_MODULE;613 614 mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);615 616 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,617 * and MCP_IOCON.HAEN = 1, so we work with all chips.618 */619 620 ret = mcp_read(mcp, MCP_IOCON, &status);621 if (ret < 0)622 return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);623 624 mcp->irq_controller =625 device_property_read_bool(dev, "interrupt-controller");626 if (mcp->irq && mcp->irq_controller) {627 mcp->irq_active_high =628 device_property_read_bool(dev,629 "microchip,irq-active-high");630 631 mirror = device_property_read_bool(dev, "microchip,irq-mirror");632 open_drain = device_property_read_bool(dev, "drive-open-drain");633 }634 635 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||636 mcp->irq_active_high || open_drain) {637 /* mcp23s17 has IOCON twice, make sure they are in sync */638 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));639 status |= IOCON_HAEN | (IOCON_HAEN << 8);640 if (mcp->irq_active_high)641 status |= IOCON_INTPOL | (IOCON_INTPOL << 8);642 else643 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));644 645 if (mirror)646 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);647 648 if (open_drain)649 status |= IOCON_ODR | (IOCON_ODR << 8);650 651 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)652 status |= IOCON_INTCC | (IOCON_INTCC << 8);653 654 ret = mcp_write(mcp, MCP_IOCON, status);655 if (ret < 0)656 return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);657 }658 659 if (mcp->irq && mcp->irq_controller) {660 struct gpio_irq_chip *girq = &mcp->chip.irq;661 662 gpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip);663 /* This will let us handle the parent IRQ in the driver */664 girq->parent_handler = NULL;665 girq->num_parents = 0;666 girq->parents = NULL;667 girq->default_type = IRQ_TYPE_NONE;668 girq->handler = handle_simple_irq;669 girq->threaded = true;670 }671 672 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);673 if (ret < 0)674 return dev_err_probe(dev, ret, "can't add GPIO chip\n");675 676 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;677 mcp->pinctrl_desc.confops = &mcp_pinconf_ops;678 mcp->pinctrl_desc.npins = mcp->chip.ngpio;679 if (mcp->pinctrl_desc.npins == 8)680 mcp->pinctrl_desc.pins = mcp23x08_pins;681 else if (mcp->pinctrl_desc.npins == 16)682 mcp->pinctrl_desc.pins = mcp23x17_pins;683 mcp->pinctrl_desc.owner = THIS_MODULE;684 685 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);686 if (IS_ERR(mcp->pctldev))687 return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");688 689 if (mcp->irq) {690 ret = mcp23s08_irq_setup(mcp);691 if (ret)692 return dev_err_probe(dev, ret, "can't setup IRQ\n");693 }694 695 return 0;696}697EXPORT_SYMBOL_GPL(mcp23s08_probe_one);698 699MODULE_DESCRIPTION("MCP23S08 SPI/I2C GPIO driver");700MODULE_LICENSE("GPL");701