1051 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * pinctrl-palmas.c -- TI PALMAS series pin control driver.4 *5 * Copyright (c) 2013, NVIDIA Corporation.6 *7 * Author: Laxman Dewangan <ldewangan@nvidia.com>8 */9 10#include <linux/delay.h>11#include <linux/module.h>12#include <linux/mfd/palmas.h>13#include <linux/of.h>14#include <linux/platform_device.h>15#include <linux/pinctrl/machine.h>16#include <linux/pinctrl/pinctrl.h>17#include <linux/pinctrl/pinconf-generic.h>18#include <linux/pinctrl/pinconf.h>19#include <linux/pinctrl/pinmux.h>20#include <linux/pm.h>21#include <linux/slab.h>22 23#include "core.h"24#include "pinconf.h"25#include "pinctrl-utils.h"26 27#define PALMAS_PIN_GPIO0_ID 028#define PALMAS_PIN_GPIO1_VBUS_LED1_PWM1 129#define PALMAS_PIN_GPIO2_REGEN_LED2_PWM2 230#define PALMAS_PIN_GPIO3_CHRG_DET 331#define PALMAS_PIN_GPIO4_SYSEN1 432#define PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL 533#define PALMAS_PIN_GPIO6_SYSEN2 634#define PALMAS_PIN_GPIO7_MSECURE_PWRHOLD 735#define PALMAS_PIN_GPIO8_SIM1RSTI 836#define PALMAS_PIN_GPIO9_LOW_VBAT 937#define PALMAS_PIN_GPIO10_WIRELESS_CHRG1 1038#define PALMAS_PIN_GPIO11_RCM 1139#define PALMAS_PIN_GPIO12_SIM2RSTO 1240#define PALMAS_PIN_GPIO13 1341#define PALMAS_PIN_GPIO14 1442#define PALMAS_PIN_GPIO15_SIM2RSTI 1543#define PALMAS_PIN_VAC 1644#define PALMAS_PIN_POWERGOOD_USB_PSEL 1745#define PALMAS_PIN_NRESWARM 1846#define PALMAS_PIN_PWRDOWN 1947#define PALMAS_PIN_GPADC_START 2048#define PALMAS_PIN_RESET_IN 2149#define PALMAS_PIN_NSLEEP 2250#define PALMAS_PIN_ENABLE1 2351#define PALMAS_PIN_ENABLE2 2452#define PALMAS_PIN_INT 2553#define PALMAS_PIN_NUM (PALMAS_PIN_INT + 1)54 55struct palmas_pin_function {56 const char *name;57 const char * const *groups;58 unsigned ngroups;59};60 61struct palmas_pctrl_chip_info {62 struct device *dev;63 struct pinctrl_dev *pctl;64 struct palmas *palmas;65 int pins_current_opt[PALMAS_PIN_NUM];66 const struct palmas_pin_function *functions;67 unsigned num_functions;68 const struct palmas_pingroup *pin_groups;69 int num_pin_groups;70 const struct pinctrl_pin_desc *pins;71 unsigned num_pins;72};73 74static const struct pinctrl_pin_desc palmas_pins_desc[] = {75 PINCTRL_PIN(PALMAS_PIN_GPIO0_ID, "gpio0"),76 PINCTRL_PIN(PALMAS_PIN_GPIO1_VBUS_LED1_PWM1, "gpio1"),77 PINCTRL_PIN(PALMAS_PIN_GPIO2_REGEN_LED2_PWM2, "gpio2"),78 PINCTRL_PIN(PALMAS_PIN_GPIO3_CHRG_DET, "gpio3"),79 PINCTRL_PIN(PALMAS_PIN_GPIO4_SYSEN1, "gpio4"),80 PINCTRL_PIN(PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL, "gpio5"),81 PINCTRL_PIN(PALMAS_PIN_GPIO6_SYSEN2, "gpio6"),82 PINCTRL_PIN(PALMAS_PIN_GPIO7_MSECURE_PWRHOLD, "gpio7"),83 PINCTRL_PIN(PALMAS_PIN_GPIO8_SIM1RSTI, "gpio8"),84 PINCTRL_PIN(PALMAS_PIN_GPIO9_LOW_VBAT, "gpio9"),85 PINCTRL_PIN(PALMAS_PIN_GPIO10_WIRELESS_CHRG1, "gpio10"),86 PINCTRL_PIN(PALMAS_PIN_GPIO11_RCM, "gpio11"),87 PINCTRL_PIN(PALMAS_PIN_GPIO12_SIM2RSTO, "gpio12"),88 PINCTRL_PIN(PALMAS_PIN_GPIO13, "gpio13"),89 PINCTRL_PIN(PALMAS_PIN_GPIO14, "gpio14"),90 PINCTRL_PIN(PALMAS_PIN_GPIO15_SIM2RSTI, "gpio15"),91 PINCTRL_PIN(PALMAS_PIN_VAC, "vac"),92 PINCTRL_PIN(PALMAS_PIN_POWERGOOD_USB_PSEL, "powergood"),93 PINCTRL_PIN(PALMAS_PIN_NRESWARM, "nreswarm"),94 PINCTRL_PIN(PALMAS_PIN_PWRDOWN, "pwrdown"),95 PINCTRL_PIN(PALMAS_PIN_GPADC_START, "gpadc_start"),96 PINCTRL_PIN(PALMAS_PIN_RESET_IN, "reset_in"),97 PINCTRL_PIN(PALMAS_PIN_NSLEEP, "nsleep"),98 PINCTRL_PIN(PALMAS_PIN_ENABLE1, "enable1"),99 PINCTRL_PIN(PALMAS_PIN_ENABLE2, "enable2"),100 PINCTRL_PIN(PALMAS_PIN_INT, "int"),101};102 103static const char * const opt0_groups[] = {104 "gpio0",105 "gpio1",106 "gpio2",107 "gpio3",108 "gpio4",109 "gpio5",110 "gpio6",111 "gpio7",112 "gpio8",113 "gpio9",114 "gpio10",115 "gpio11",116 "gpio12",117 "gpio13",118 "gpio14",119 "gpio15",120 "vac",121 "powergood",122 "nreswarm",123 "pwrdown",124 "gpadc_start",125 "reset_in",126 "nsleep",127 "enable1",128 "enable2",129 "int",130};131 132static const char * const opt1_groups[] = {133 "gpio0",134 "gpio1",135 "gpio2",136 "gpio3",137 "gpio4",138 "gpio5",139 "gpio6",140 "gpio7",141 "gpio8",142 "gpio9",143 "gpio10",144 "gpio11",145 "gpio12",146 "gpio15",147 "vac",148 "powergood",149};150 151static const char * const opt2_groups[] = {152 "gpio1",153 "gpio2",154 "gpio5",155 "gpio7",156};157 158static const char * const opt3_groups[] = {159 "gpio1",160 "gpio2",161};162 163static const char * const gpio_groups[] = {164 "gpio0",165 "gpio1",166 "gpio2",167 "gpio3",168 "gpio4",169 "gpio5",170 "gpio6",171 "gpio7",172 "gpio8",173 "gpio9",174 "gpio10",175 "gpio11",176 "gpio12",177 "gpio13",178 "gpio14",179 "gpio15",180};181 182static const char * const led_groups[] = {183 "gpio1",184 "gpio2",185};186 187static const char * const pwm_groups[] = {188 "gpio1",189 "gpio2",190};191 192static const char * const regen_groups[] = {193 "gpio2",194};195 196static const char * const sysen_groups[] = {197 "gpio4",198 "gpio6",199};200 201static const char * const clk32kgaudio_groups[] = {202 "gpio5",203};204 205static const char * const id_groups[] = {206 "gpio0",207};208 209static const char * const vbus_det_groups[] = {210 "gpio1",211};212 213static const char * const chrg_det_groups[] = {214 "gpio3",215};216 217static const char * const vac_groups[] = {218 "vac",219};220 221static const char * const vacok_groups[] = {222 "vac",223};224 225static const char * const powergood_groups[] = {226 "powergood",227};228 229static const char * const usb_psel_groups[] = {230 "gpio5",231 "powergood",232};233 234static const char * const msecure_groups[] = {235 "gpio7",236};237 238static const char * const pwrhold_groups[] = {239 "gpio7",240};241 242static const char * const int_groups[] = {243 "int",244};245 246static const char * const nreswarm_groups[] = {247 "nreswarm",248};249 250static const char * const simrsto_groups[] = {251 "gpio12",252};253 254static const char * const simrsti_groups[] = {255 "gpio8",256 "gpio15",257};258 259static const char * const low_vbat_groups[] = {260 "gpio9",261};262 263static const char * const wireless_chrg1_groups[] = {264 "gpio10",265};266 267static const char * const rcm_groups[] = {268 "gpio11",269};270 271static const char * const pwrdown_groups[] = {272 "pwrdown",273};274 275static const char * const gpadc_start_groups[] = {276 "gpadc_start",277};278 279static const char * const reset_in_groups[] = {280 "reset_in",281};282 283static const char * const nsleep_groups[] = {284 "nsleep",285};286 287static const char * const enable_groups[] = {288 "enable1",289 "enable2",290};291 292#define FUNCTION_GROUPS \293 FUNCTION_GROUP(opt0, OPTION0), \294 FUNCTION_GROUP(opt1, OPTION1), \295 FUNCTION_GROUP(opt2, OPTION2), \296 FUNCTION_GROUP(opt3, OPTION3), \297 FUNCTION_GROUP(gpio, GPIO), \298 FUNCTION_GROUP(led, LED), \299 FUNCTION_GROUP(pwm, PWM), \300 FUNCTION_GROUP(regen, REGEN), \301 FUNCTION_GROUP(sysen, SYSEN), \302 FUNCTION_GROUP(clk32kgaudio, CLK32KGAUDIO), \303 FUNCTION_GROUP(id, ID), \304 FUNCTION_GROUP(vbus_det, VBUS_DET), \305 FUNCTION_GROUP(chrg_det, CHRG_DET), \306 FUNCTION_GROUP(vac, VAC), \307 FUNCTION_GROUP(vacok, VACOK), \308 FUNCTION_GROUP(powergood, POWERGOOD), \309 FUNCTION_GROUP(usb_psel, USB_PSEL), \310 FUNCTION_GROUP(msecure, MSECURE), \311 FUNCTION_GROUP(pwrhold, PWRHOLD), \312 FUNCTION_GROUP(int, INT), \313 FUNCTION_GROUP(nreswarm, NRESWARM), \314 FUNCTION_GROUP(simrsto, SIMRSTO), \315 FUNCTION_GROUP(simrsti, SIMRSTI), \316 FUNCTION_GROUP(low_vbat, LOW_VBAT), \317 FUNCTION_GROUP(wireless_chrg1, WIRELESS_CHRG1), \318 FUNCTION_GROUP(rcm, RCM), \319 FUNCTION_GROUP(pwrdown, PWRDOWN), \320 FUNCTION_GROUP(gpadc_start, GPADC_START), \321 FUNCTION_GROUP(reset_in, RESET_IN), \322 FUNCTION_GROUP(nsleep, NSLEEP), \323 FUNCTION_GROUP(enable, ENABLE)324 325static const struct palmas_pin_function palmas_pin_function[] = {326#undef FUNCTION_GROUP327#define FUNCTION_GROUP(fname, mux) \328 { \329 .name = #fname, \330 .groups = fname##_groups, \331 .ngroups = ARRAY_SIZE(fname##_groups), \332 }333 334 FUNCTION_GROUPS,335};336 337enum palmas_pinmux {338#undef FUNCTION_GROUP339#define FUNCTION_GROUP(fname, mux) PALMAS_PINMUX_##mux340 FUNCTION_GROUPS,341 PALMAS_PINMUX_NA = 0xFFFF,342};343 344struct palmas_pins_pullup_dn_info {345 int pullup_dn_reg_base;346 int pullup_dn_reg_add;347 int pullup_dn_mask;348 int normal_val;349 int pull_up_val;350 int pull_dn_val;351};352 353struct palmas_pins_od_info {354 int od_reg_base;355 int od_reg_add;356 int od_mask;357 int od_enable;358 int od_disable;359};360 361struct palmas_pin_info {362 enum palmas_pinmux mux_opt;363 const struct palmas_pins_pullup_dn_info *pud_info;364 const struct palmas_pins_od_info *od_info;365};366 367struct palmas_pingroup {368 const char *name;369 const unsigned pins[1];370 unsigned npins;371 unsigned mux_reg_base;372 unsigned mux_reg_add;373 unsigned mux_reg_mask;374 unsigned mux_bit_shift;375 const struct palmas_pin_info *opt[4];376};377 378#define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv) \379static const struct palmas_pins_pullup_dn_info pud_##_name##_info = { \380 .pullup_dn_reg_base = PALMAS_##_rbase##_BASE, \381 .pullup_dn_reg_add = _add, \382 .pullup_dn_mask = _mask, \383 .normal_val = _nv, \384 .pull_up_val = _uv, \385 .pull_dn_val = _dv, \386}387 388PULL_UP_DN(nreswarm, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x2, 0x0, 0x2, -1);389PULL_UP_DN(pwrdown, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x4, 0x0, -1, 0x4);390PULL_UP_DN(gpadc_start, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x30, 0x0, 0x20, 0x10);391PULL_UP_DN(reset_in, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x40, 0x0, -1, 0x40);392PULL_UP_DN(nsleep, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x3, 0x0, 0x2, 0x1);393PULL_UP_DN(enable1, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0xC, 0x0, 0x8, 0x4);394PULL_UP_DN(enable2, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x30, 0x0, 0x20, 0x10);395PULL_UP_DN(vacok, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x40, 0x0, -1, 0x40);396PULL_UP_DN(chrg_det, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x10, 0x0, -1, 0x10);397PULL_UP_DN(pwrhold, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x4, 0x0, -1, 0x4);398PULL_UP_DN(msecure, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x1, 0x0, -1, 0x1);399PULL_UP_DN(id, USB_OTG, PALMAS_USB_ID_CTRL_SET, 0x40, 0x0, 0x40, -1);400PULL_UP_DN(gpio0, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x04, 0, -1, 1);401PULL_UP_DN(gpio1, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x0C, 0, 0x8, 0x4);402PULL_UP_DN(gpio2, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x30, 0x0, 0x20, 0x10);403PULL_UP_DN(gpio3, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x40, 0x0, -1, 0x40);404PULL_UP_DN(gpio4, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x03, 0x0, 0x2, 0x1);405PULL_UP_DN(gpio5, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x0c, 0x0, 0x8, 0x4);406PULL_UP_DN(gpio6, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x30, 0x0, 0x20, 0x10);407PULL_UP_DN(gpio7, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x40, 0x0, -1, 0x40);408PULL_UP_DN(gpio9, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x0C, 0x0, 0x8, 0x4);409PULL_UP_DN(gpio10, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x30, 0x0, 0x20, 0x10);410PULL_UP_DN(gpio11, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0xC0, 0x0, 0x80, 0x40);411PULL_UP_DN(gpio13, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x04, 0x0, -1, 0x04);412PULL_UP_DN(gpio14, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x30, 0x0, 0x20, 0x10);413 414#define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv) \415static const struct palmas_pins_od_info od_##_name##_info = { \416 .od_reg_base = PALMAS_##_rbase##_BASE, \417 .od_reg_add = _add, \418 .od_mask = _mask, \419 .od_enable = _ev, \420 .od_disable = _dv, \421}422 423OD_INFO(gpio1, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x1, 0x1, 0x0);424OD_INFO(gpio2, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x2, 0x2, 0x0);425OD_INFO(gpio5, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x20, 0x20, 0x0);426OD_INFO(gpio10, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x04, 0x04, 0x0);427OD_INFO(gpio13, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x20, 0x20, 0x0);428OD_INFO(int, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x8, 0x8, 0x0);429OD_INFO(pwm1, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x20, 0x20, 0x0);430OD_INFO(pwm2, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x80, 0x80, 0x0);431OD_INFO(vbus_det, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x40, 0x40, 0x0);432 433#define PIN_INFO(_name, _id, _pud_info, _od_info) \434static const struct palmas_pin_info pin_##_name##_info = { \435 .mux_opt = PALMAS_PINMUX_##_id, \436 .pud_info = _pud_info, \437 .od_info = _od_info \438}439 440PIN_INFO(gpio0, GPIO, &pud_gpio0_info, NULL);441PIN_INFO(gpio1, GPIO, &pud_gpio1_info, &od_gpio1_info);442PIN_INFO(gpio2, GPIO, &pud_gpio2_info, &od_gpio2_info);443PIN_INFO(gpio3, GPIO, &pud_gpio3_info, NULL);444PIN_INFO(gpio4, GPIO, &pud_gpio4_info, NULL);445PIN_INFO(gpio5, GPIO, &pud_gpio5_info, &od_gpio5_info);446PIN_INFO(gpio6, GPIO, &pud_gpio6_info, NULL);447PIN_INFO(gpio7, GPIO, &pud_gpio7_info, NULL);448PIN_INFO(gpio8, GPIO, NULL, NULL);449PIN_INFO(gpio9, GPIO, &pud_gpio9_info, NULL);450PIN_INFO(gpio10, GPIO, &pud_gpio10_info, &od_gpio10_info);451PIN_INFO(gpio11, GPIO, &pud_gpio11_info, NULL);452PIN_INFO(gpio12, GPIO, NULL, NULL);453PIN_INFO(gpio13, GPIO, &pud_gpio13_info, &od_gpio13_info);454PIN_INFO(gpio14, GPIO, &pud_gpio14_info, NULL);455PIN_INFO(gpio15, GPIO, NULL, NULL);456PIN_INFO(id, ID, &pud_id_info, NULL);457PIN_INFO(led1, LED, NULL, NULL);458PIN_INFO(led2, LED, NULL, NULL);459PIN_INFO(regen, REGEN, NULL, NULL);460PIN_INFO(sysen1, SYSEN, NULL, NULL);461PIN_INFO(sysen2, SYSEN, NULL, NULL);462PIN_INFO(int, INT, NULL, &od_int_info);463PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info);464PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info);465PIN_INFO(vacok, VACOK, &pud_vacok_info, NULL);466PIN_INFO(chrg_det, CHRG_DET, &pud_chrg_det_info, NULL);467PIN_INFO(pwrhold, PWRHOLD, &pud_pwrhold_info, NULL);468PIN_INFO(msecure, MSECURE, &pud_msecure_info, NULL);469PIN_INFO(nreswarm, NA, &pud_nreswarm_info, NULL);470PIN_INFO(pwrdown, NA, &pud_pwrdown_info, NULL);471PIN_INFO(gpadc_start, NA, &pud_gpadc_start_info, NULL);472PIN_INFO(reset_in, NA, &pud_reset_in_info, NULL);473PIN_INFO(nsleep, NA, &pud_nsleep_info, NULL);474PIN_INFO(enable1, NA, &pud_enable1_info, NULL);475PIN_INFO(enable2, NA, &pud_enable2_info, NULL);476PIN_INFO(clk32kgaudio, CLK32KGAUDIO, NULL, NULL);477PIN_INFO(usb_psel, USB_PSEL, NULL, NULL);478PIN_INFO(vac, VAC, NULL, NULL);479PIN_INFO(powergood, POWERGOOD, NULL, NULL);480PIN_INFO(vbus_det, VBUS_DET, NULL, &od_vbus_det_info);481PIN_INFO(sim1rsti, SIMRSTI, NULL, NULL);482PIN_INFO(low_vbat, LOW_VBAT, NULL, NULL);483PIN_INFO(rcm, RCM, NULL, NULL);484PIN_INFO(sim2rsto, SIMRSTO, NULL, NULL);485PIN_INFO(sim2rsti, SIMRSTI, NULL, NULL);486PIN_INFO(wireless_chrg1, WIRELESS_CHRG1, NULL, NULL);487 488#define PALMAS_PRIMARY_SECONDARY_NONE 0489#define PALMAS_NONE_BASE 0490#define PALMAS_PRIMARY_SECONDARY_INPUT3 PALMAS_PU_PD_INPUT_CTRL3491 492#define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \493 { \494 .name = #pg_name, \495 .pins = {PALMAS_PIN_##pin_id}, \496 .npins = 1, \497 .mux_reg_base = PALMAS_##base##_BASE, \498 .mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg, \499 .mux_reg_mask = _mask, \500 .mux_bit_shift = _bshift, \501 .opt = { \502 o0, \503 o1, \504 o2, \505 o3, \506 }, \507 }508 509static const struct palmas_pingroup tps65913_pingroups[] = {510 PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL),511 PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info),512 PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info),513 PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL),514 PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL),515 PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL),516 PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL),517 PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL),518 PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL),519 PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL),520 PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL),521 PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL),522 PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL),523 PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL),524 PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL),525 PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL),526 PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL),527 PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL),528};529 530static const struct palmas_pingroup tps80036_pingroups[] = {531 PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL),532 PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info),533 PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info),534 PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL),535 PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL),536 PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL),537 PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL),538 PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL),539 PALMAS_PINGROUP(gpio8, GPIO8_SIM1RSTI, PU_PD_OD, PAD4, 0x01, 0x0, &pin_gpio8_info, &pin_sim1rsti_info, NULL, NULL),540 PALMAS_PINGROUP(gpio9, GPIO9_LOW_VBAT, PU_PD_OD, PAD4, 0x02, 0x1, &pin_gpio9_info, &pin_low_vbat_info, NULL, NULL),541 PALMAS_PINGROUP(gpio10, GPIO10_WIRELESS_CHRG1, PU_PD_OD, PAD4, 0x04, 0x2, &pin_gpio10_info, &pin_wireless_chrg1_info, NULL, NULL),542 PALMAS_PINGROUP(gpio11, GPIO11_RCM, PU_PD_OD, PAD4, 0x08, 0x3, &pin_gpio11_info, &pin_rcm_info, NULL, NULL),543 PALMAS_PINGROUP(gpio12, GPIO12_SIM2RSTO, PU_PD_OD, PAD4, 0x10, 0x4, &pin_gpio12_info, &pin_sim2rsto_info, NULL, NULL),544 PALMAS_PINGROUP(gpio13, GPIO13, NONE, NONE, 0x00, 0x0, &pin_gpio13_info, NULL, NULL, NULL),545 PALMAS_PINGROUP(gpio14, GPIO14, NONE, NONE, 0x00, 0x0, &pin_gpio14_info, NULL, NULL, NULL),546 PALMAS_PINGROUP(gpio15, GPIO15_SIM2RSTI, PU_PD_OD, PAD4, 0x80, 0x7, &pin_gpio15_info, &pin_sim2rsti_info, NULL, NULL),547 PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL),548 PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL),549 PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL),550 PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL),551 PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL),552 PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL),553 PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL),554 PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL),555 PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL),556 PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL),557};558 559static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci)560{561 const struct palmas_pingroup *g;562 unsigned int val;563 int ret;564 int i;565 566 for (i = 0; i < pci->num_pin_groups; ++i) {567 g = &pci->pin_groups[i];568 if (g->mux_reg_base == PALMAS_NONE_BASE) {569 pci->pins_current_opt[i] = 0;570 continue;571 }572 ret = palmas_read(pci->palmas, g->mux_reg_base,573 g->mux_reg_add, &val);574 if (ret < 0) {575 dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n",576 g->mux_reg_add, ret);577 return ret;578 }579 val &= g->mux_reg_mask;580 pci->pins_current_opt[i] = val >> g->mux_bit_shift;581 }582 return 0;583}584 585static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci,586 bool enable)587{588 int ret;589 int val;590 591 val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0;592 ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,593 PALMAS_PRIMARY_SECONDARY_PAD3,594 PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val);595 if (ret < 0)596 dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);597 return ret;598}599 600static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci,601 bool enable)602{603 int ret;604 int val;605 606 val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0;607 ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,608 PALMAS_PRIMARY_SECONDARY_PAD3,609 PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val);610 if (ret < 0)611 dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);612 return ret;613}614 615static int palmas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)616{617 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);618 619 return pci->num_pin_groups;620}621 622static const char *palmas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,623 unsigned group)624{625 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);626 627 return pci->pin_groups[group].name;628}629 630static int palmas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,631 unsigned group, const unsigned **pins, unsigned *num_pins)632{633 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);634 635 *pins = pci->pin_groups[group].pins;636 *num_pins = pci->pin_groups[group].npins;637 return 0;638}639 640static const struct pinctrl_ops palmas_pinctrl_ops = {641 .get_groups_count = palmas_pinctrl_get_groups_count,642 .get_group_name = palmas_pinctrl_get_group_name,643 .get_group_pins = palmas_pinctrl_get_group_pins,644 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,645 .dt_free_map = pinctrl_utils_free_map,646};647 648static int palmas_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)649{650 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);651 652 return pci->num_functions;653}654 655static const char *palmas_pinctrl_get_func_name(struct pinctrl_dev *pctldev,656 unsigned function)657{658 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);659 660 return pci->functions[function].name;661}662 663static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,664 unsigned function, const char * const **groups,665 unsigned * const num_groups)666{667 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);668 669 *groups = pci->functions[function].groups;670 *num_groups = pci->functions[function].ngroups;671 return 0;672}673 674static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev,675 unsigned function,676 unsigned group)677{678 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);679 const struct palmas_pingroup *g;680 int i;681 int ret;682 683 g = &pci->pin_groups[group];684 685 /* If direct option is provided here */686 if (function <= PALMAS_PINMUX_OPTION3) {687 if (!g->opt[function]) {688 dev_err(pci->dev, "Pin %s does not support option %d\n",689 g->name, function);690 return -EINVAL;691 }692 i = function;693 } else {694 for (i = 0; i < ARRAY_SIZE(g->opt); i++) {695 if (!g->opt[i])696 continue;697 if (g->opt[i]->mux_opt == function)698 break;699 }700 if (WARN_ON(i == ARRAY_SIZE(g->opt))) {701 dev_err(pci->dev, "Pin %s does not support option %d\n",702 g->name, function);703 return -EINVAL;704 }705 }706 707 if (g->mux_reg_base == PALMAS_NONE_BASE) {708 if (WARN_ON(i != 0))709 return -EINVAL;710 return 0;711 }712 713 dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n",714 __func__, g->mux_reg_base, g->mux_reg_add,715 g->mux_reg_mask, i << g->mux_bit_shift);716 717 ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add,718 g->mux_reg_mask, i << g->mux_bit_shift);719 if (ret < 0) {720 dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",721 g->mux_reg_add, ret);722 return ret;723 }724 pci->pins_current_opt[group] = i;725 return 0;726}727 728static const struct pinmux_ops palmas_pinmux_ops = {729 .get_functions_count = palmas_pinctrl_get_funcs_count,730 .get_function_name = palmas_pinctrl_get_func_name,731 .get_function_groups = palmas_pinctrl_get_func_groups,732 .set_mux = palmas_pinctrl_set_mux,733};734 735static int palmas_pinconf_get(struct pinctrl_dev *pctldev,736 unsigned pin, unsigned long *config)737{738 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);739 enum pin_config_param param = pinconf_to_config_param(*config);740 const struct palmas_pingroup *g;741 const struct palmas_pin_info *opt;742 unsigned int val;743 int ret;744 int base, add;745 int rval;746 int arg;747 int group_nr;748 749 for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {750 if (pci->pin_groups[group_nr].pins[0] == pin)751 break;752 }753 754 if (group_nr == pci->num_pin_groups) {755 dev_err(pci->dev,756 "Pinconf is not supported for pin-id %d\n", pin);757 return -ENOTSUPP;758 }759 760 g = &pci->pin_groups[group_nr];761 opt = g->opt[pci->pins_current_opt[group_nr]];762 if (!opt) {763 dev_err(pci->dev,764 "Pinconf is not supported for pin %s\n", g->name);765 return -ENOTSUPP;766 }767 768 switch (param) {769 case PIN_CONFIG_BIAS_DISABLE:770 case PIN_CONFIG_BIAS_PULL_UP:771 case PIN_CONFIG_BIAS_PULL_DOWN:772 if (!opt->pud_info) {773 dev_err(pci->dev,774 "PULL control not supported for pin %s\n",775 g->name);776 return -ENOTSUPP;777 }778 base = opt->pud_info->pullup_dn_reg_base;779 add = opt->pud_info->pullup_dn_reg_add;780 ret = palmas_read(pci->palmas, base, add, &val);781 if (ret < 0) {782 dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",783 add, ret);784 return ret;785 }786 787 rval = val & opt->pud_info->pullup_dn_mask;788 arg = 0;789 if ((opt->pud_info->normal_val >= 0) &&790 (opt->pud_info->normal_val == rval) &&791 (param == PIN_CONFIG_BIAS_DISABLE))792 arg = 1;793 else if ((opt->pud_info->pull_up_val >= 0) &&794 (opt->pud_info->pull_up_val == rval) &&795 (param == PIN_CONFIG_BIAS_PULL_UP))796 arg = 1;797 else if ((opt->pud_info->pull_dn_val >= 0) &&798 (opt->pud_info->pull_dn_val == rval) &&799 (param == PIN_CONFIG_BIAS_PULL_DOWN))800 arg = 1;801 break;802 803 case PIN_CONFIG_DRIVE_OPEN_DRAIN:804 if (!opt->od_info) {805 dev_err(pci->dev,806 "OD control not supported for pin %s\n",807 g->name);808 return -ENOTSUPP;809 }810 base = opt->od_info->od_reg_base;811 add = opt->od_info->od_reg_add;812 ret = palmas_read(pci->palmas, base, add, &val);813 if (ret < 0) {814 dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",815 add, ret);816 return ret;817 }818 rval = val & opt->od_info->od_mask;819 arg = -1;820 if ((opt->od_info->od_disable >= 0) &&821 (opt->od_info->od_disable == rval))822 arg = 0;823 else if ((opt->od_info->od_enable >= 0) &&824 (opt->od_info->od_enable == rval))825 arg = 1;826 if (arg < 0) {827 dev_err(pci->dev,828 "OD control not supported for pin %s\n",829 g->name);830 return -ENOTSUPP;831 }832 break;833 834 default:835 dev_err(pci->dev, "Properties not supported\n");836 return -ENOTSUPP;837 }838 839 *config = pinconf_to_config_packed(param, (u16)arg);840 return 0;841}842 843static int palmas_pinconf_set(struct pinctrl_dev *pctldev,844 unsigned pin, unsigned long *configs,845 unsigned num_configs)846{847 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);848 enum pin_config_param param;849 u32 param_val;850 const struct palmas_pingroup *g;851 const struct palmas_pin_info *opt;852 int ret;853 int base, add, mask;854 int rval;855 int group_nr;856 int i;857 858 for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {859 if (pci->pin_groups[group_nr].pins[0] == pin)860 break;861 }862 863 if (group_nr == pci->num_pin_groups) {864 dev_err(pci->dev,865 "Pinconf is not supported for pin-id %d\n", pin);866 return -ENOTSUPP;867 }868 869 g = &pci->pin_groups[group_nr];870 opt = g->opt[pci->pins_current_opt[group_nr]];871 if (!opt) {872 dev_err(pci->dev,873 "Pinconf is not supported for pin %s\n", g->name);874 return -ENOTSUPP;875 }876 877 for (i = 0; i < num_configs; i++) {878 param = pinconf_to_config_param(configs[i]);879 param_val = pinconf_to_config_argument(configs[i]);880 881 switch (param) {882 case PIN_CONFIG_BIAS_DISABLE:883 case PIN_CONFIG_BIAS_PULL_UP:884 case PIN_CONFIG_BIAS_PULL_DOWN:885 if (!opt->pud_info) {886 dev_err(pci->dev,887 "PULL control not supported for pin %s\n",888 g->name);889 return -ENOTSUPP;890 }891 base = opt->pud_info->pullup_dn_reg_base;892 add = opt->pud_info->pullup_dn_reg_add;893 mask = opt->pud_info->pullup_dn_mask;894 895 if (param == PIN_CONFIG_BIAS_DISABLE)896 rval = opt->pud_info->normal_val;897 else if (param == PIN_CONFIG_BIAS_PULL_UP)898 rval = opt->pud_info->pull_up_val;899 else900 rval = opt->pud_info->pull_dn_val;901 902 if (rval < 0) {903 dev_err(pci->dev,904 "PULL control not supported for pin %s\n",905 g->name);906 return -ENOTSUPP;907 }908 break;909 910 case PIN_CONFIG_DRIVE_OPEN_DRAIN:911 if (!opt->od_info) {912 dev_err(pci->dev,913 "OD control not supported for pin %s\n",914 g->name);915 return -ENOTSUPP;916 }917 base = opt->od_info->od_reg_base;918 add = opt->od_info->od_reg_add;919 mask = opt->od_info->od_mask;920 if (param_val == 0)921 rval = opt->od_info->od_disable;922 else923 rval = opt->od_info->od_enable;924 if (rval < 0) {925 dev_err(pci->dev,926 "OD control not supported for pin %s\n",927 g->name);928 return -ENOTSUPP;929 }930 break;931 default:932 dev_err(pci->dev, "Properties not supported\n");933 return -ENOTSUPP;934 }935 936 dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",937 __func__, base, add, mask, rval);938 ret = palmas_update_bits(pci->palmas, base, add, mask, rval);939 if (ret < 0) {940 dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",941 add, ret);942 return ret;943 }944 } /* for each config */945 946 return 0;947}948 949static const struct pinconf_ops palmas_pinconf_ops = {950 .pin_config_get = palmas_pinconf_get,951 .pin_config_set = palmas_pinconf_set,952};953 954static struct pinctrl_desc palmas_pinctrl_desc = {955 .pctlops = &palmas_pinctrl_ops,956 .pmxops = &palmas_pinmux_ops,957 .confops = &palmas_pinconf_ops,958 .owner = THIS_MODULE,959};960 961struct palmas_pinctrl_data {962 const struct palmas_pingroup *pin_groups;963 int num_pin_groups;964};965 966static struct palmas_pinctrl_data tps65913_pinctrl_data = {967 .pin_groups = tps65913_pingroups,968 .num_pin_groups = ARRAY_SIZE(tps65913_pingroups),969};970 971static struct palmas_pinctrl_data tps80036_pinctrl_data = {972 .pin_groups = tps80036_pingroups,973 .num_pin_groups = ARRAY_SIZE(tps80036_pingroups),974};975 976static const struct of_device_id palmas_pinctrl_of_match[] = {977 { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data},978 { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data},979 { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data},980 { },981};982MODULE_DEVICE_TABLE(of, palmas_pinctrl_of_match);983 984static int palmas_pinctrl_probe(struct platform_device *pdev)985{986 struct palmas_pctrl_chip_info *pci;987 const struct palmas_pinctrl_data *pinctrl_data = &tps65913_pinctrl_data;988 int ret;989 bool enable_dvfs1 = false;990 bool enable_dvfs2 = false;991 992 if (pdev->dev.of_node) {993 pinctrl_data = of_device_get_match_data(&pdev->dev);994 enable_dvfs1 = of_property_read_bool(pdev->dev.of_node,995 "ti,palmas-enable-dvfs1");996 enable_dvfs2 = of_property_read_bool(pdev->dev.of_node,997 "ti,palmas-enable-dvfs2");998 }999 1000 pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);1001 if (!pci)1002 return -ENOMEM;1003 1004 pci->dev = &pdev->dev;1005 pci->palmas = dev_get_drvdata(pdev->dev.parent);1006 1007 pci->pins = palmas_pins_desc;1008 pci->num_pins = ARRAY_SIZE(palmas_pins_desc);1009 pci->functions = palmas_pin_function;1010 pci->num_functions = ARRAY_SIZE(palmas_pin_function);1011 pci->pin_groups = pinctrl_data->pin_groups;1012 pci->num_pin_groups = pinctrl_data->num_pin_groups;1013 1014 platform_set_drvdata(pdev, pci);1015 1016 palmas_pinctrl_set_dvfs1(pci, enable_dvfs1);1017 palmas_pinctrl_set_dvfs2(pci, enable_dvfs2);1018 ret = palmas_pinctrl_get_pin_mux(pci);1019 if (ret < 0) {1020 dev_err(&pdev->dev,1021 "Reading pinctrol option register failed: %d\n", ret);1022 return ret;1023 }1024 1025 palmas_pinctrl_desc.name = dev_name(&pdev->dev);1026 palmas_pinctrl_desc.pins = palmas_pins_desc;1027 palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);1028 pci->pctl = devm_pinctrl_register(&pdev->dev, &palmas_pinctrl_desc,1029 pci);1030 if (IS_ERR(pci->pctl)) {1031 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");1032 return PTR_ERR(pci->pctl);1033 }1034 return 0;1035}1036 1037static struct platform_driver palmas_pinctrl_driver = {1038 .driver = {1039 .name = "palmas-pinctrl",1040 .of_match_table = palmas_pinctrl_of_match,1041 },1042 .probe = palmas_pinctrl_probe,1043};1044 1045module_platform_driver(palmas_pinctrl_driver);1046 1047MODULE_DESCRIPTION("Palmas pin control driver");1048MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");1049MODULE_ALIAS("platform:palmas-pinctrl");1050MODULE_LICENSE("GPL v2");1051