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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.4 *5 * Copyright (c) 2013 MundoReader S.L.6 * Author: Heiko Stuebner <heiko@sntech.de>7 *8 * With some ideas taken from pinctrl-samsung:9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.10 * http://www.samsung.com11 * Copyright (c) 2012 Linaro Ltd12 * https://www.linaro.org13 *14 * and pinctrl-at91:15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>16 */17 18#ifndef _PINCTRL_ROCKCHIP_H19#define _PINCTRL_ROCKCHIP_H20 21#define RK_GPIO0_A0 022#define RK_GPIO0_A1 123#define RK_GPIO0_A2 224#define RK_GPIO0_A3 325#define RK_GPIO0_A4 426#define RK_GPIO0_A5 527#define RK_GPIO0_A6 628#define RK_GPIO0_A7 729#define RK_GPIO0_B0 830#define RK_GPIO0_B1 931#define RK_GPIO0_B2 1032#define RK_GPIO0_B3 1133#define RK_GPIO0_B4 1234#define RK_GPIO0_B5 1335#define RK_GPIO0_B6 1436#define RK_GPIO0_B7 1537#define RK_GPIO0_C0 1638#define RK_GPIO0_C1 1739#define RK_GPIO0_C2 1840#define RK_GPIO0_C3 1941#define RK_GPIO0_C4 2042#define RK_GPIO0_C5 2143#define RK_GPIO0_C6 2244#define RK_GPIO0_C7 2345#define RK_GPIO0_D0 2446#define RK_GPIO0_D1 2547#define RK_GPIO0_D2 2648#define RK_GPIO0_D3 2749#define RK_GPIO0_D4 2850#define RK_GPIO0_D5 2951#define RK_GPIO0_D6 3052#define RK_GPIO0_D7 3153 54#define RK_GPIO1_A0 3255#define RK_GPIO1_A1 3356#define RK_GPIO1_A2 3457#define RK_GPIO1_A3 3558#define RK_GPIO1_A4 3659#define RK_GPIO1_A5 3760#define RK_GPIO1_A6 3861#define RK_GPIO1_A7 3962#define RK_GPIO1_B0 4063#define RK_GPIO1_B1 4164#define RK_GPIO1_B2 4265#define RK_GPIO1_B3 4366#define RK_GPIO1_B4 4467#define RK_GPIO1_B5 4568#define RK_GPIO1_B6 4669#define RK_GPIO1_B7 4770#define RK_GPIO1_C0 4871#define RK_GPIO1_C1 4972#define RK_GPIO1_C2 5073#define RK_GPIO1_C3 5174#define RK_GPIO1_C4 5275#define RK_GPIO1_C5 5376#define RK_GPIO1_C6 5477#define RK_GPIO1_C7 5578#define RK_GPIO1_D0 5679#define RK_GPIO1_D1 5780#define RK_GPIO1_D2 5881#define RK_GPIO1_D3 5982#define RK_GPIO1_D4 6083#define RK_GPIO1_D5 6184#define RK_GPIO1_D6 6285#define RK_GPIO1_D7 6386 87#define RK_GPIO2_A0 6488#define RK_GPIO2_A1 6589#define RK_GPIO2_A2 6690#define RK_GPIO2_A3 6791#define RK_GPIO2_A4 6892#define RK_GPIO2_A5 6993#define RK_GPIO2_A6 7094#define RK_GPIO2_A7 7195#define RK_GPIO2_B0 7296#define RK_GPIO2_B1 7397#define RK_GPIO2_B2 7498#define RK_GPIO2_B3 7599#define RK_GPIO2_B4 76100#define RK_GPIO2_B5 77101#define RK_GPIO2_B6 78102#define RK_GPIO2_B7 79103#define RK_GPIO2_C0 80104#define RK_GPIO2_C1 81105#define RK_GPIO2_C2 82106#define RK_GPIO2_C3 83107#define RK_GPIO2_C4 84108#define RK_GPIO2_C5 85109#define RK_GPIO2_C6 86110#define RK_GPIO2_C7 87111#define RK_GPIO2_D0 88112#define RK_GPIO2_D1 89113#define RK_GPIO2_D2 90114#define RK_GPIO2_D3 91115#define RK_GPIO2_D4 92116#define RK_GPIO2_D5 93117#define RK_GPIO2_D6 94118#define RK_GPIO2_D7 95119 120#define RK_GPIO3_A0 96121#define RK_GPIO3_A1 97122#define RK_GPIO3_A2 98123#define RK_GPIO3_A3 99124#define RK_GPIO3_A4 100125#define RK_GPIO3_A5 101126#define RK_GPIO3_A6 102127#define RK_GPIO3_A7 103128#define RK_GPIO3_B0 104129#define RK_GPIO3_B1 105130#define RK_GPIO3_B2 106131#define RK_GPIO3_B3 107132#define RK_GPIO3_B4 108133#define RK_GPIO3_B5 109134#define RK_GPIO3_B6 110135#define RK_GPIO3_B7 111136#define RK_GPIO3_C0 112137#define RK_GPIO3_C1 113138#define RK_GPIO3_C2 114139#define RK_GPIO3_C3 115140#define RK_GPIO3_C4 116141#define RK_GPIO3_C5 117142#define RK_GPIO3_C6 118143#define RK_GPIO3_C7 119144#define RK_GPIO3_D0 120145#define RK_GPIO3_D1 121146#define RK_GPIO3_D2 122147#define RK_GPIO3_D3 123148#define RK_GPIO3_D4 124149#define RK_GPIO3_D5 125150#define RK_GPIO3_D6 126151#define RK_GPIO3_D7 127152 153#define RK_GPIO4_A0 128154#define RK_GPIO4_A1 129155#define RK_GPIO4_A2 130156#define RK_GPIO4_A3 131157#define RK_GPIO4_A4 132158#define RK_GPIO4_A5 133159#define RK_GPIO4_A6 134160#define RK_GPIO4_A7 135161#define RK_GPIO4_B0 136162#define RK_GPIO4_B1 137163#define RK_GPIO4_B2 138164#define RK_GPIO4_B3 139165#define RK_GPIO4_B4 140166#define RK_GPIO4_B5 141167#define RK_GPIO4_B6 142168#define RK_GPIO4_B7 143169#define RK_GPIO4_C0 144170#define RK_GPIO4_C1 145171#define RK_GPIO4_C2 146172#define RK_GPIO4_C3 147173#define RK_GPIO4_C4 148174#define RK_GPIO4_C5 149175#define RK_GPIO4_C6 150176#define RK_GPIO4_C7 151177#define RK_GPIO4_D0 152178#define RK_GPIO4_D1 153179#define RK_GPIO4_D2 154180#define RK_GPIO4_D3 155181#define RK_GPIO4_D4 156182#define RK_GPIO4_D5 157183#define RK_GPIO4_D6 158184#define RK_GPIO4_D7 159185 186enum rockchip_pinctrl_type {187 PX30,188 RV1108,189 RV1126,190 RK2928,191 RK3066B,192 RK3128,193 RK3188,194 RK3288,195 RK3308,196 RK3328,197 RK3368,198 RK3399,199 RK3568,200 RK3576,201 RK3588,202};203 204/**205 * struct rockchip_gpio_regs206 * @port_dr: data register207 * @port_ddr: data direction register208 * @int_en: interrupt enable209 * @int_mask: interrupt mask210 * @int_type: interrupt trigger type, such as high, low, edge trriger type.211 * @int_polarity: interrupt polarity enable register212 * @int_bothedge: interrupt bothedge enable register213 * @int_status: interrupt status register214 * @int_rawstatus: int_status = int_rawstatus & int_mask215 * @debounce: enable debounce for interrupt signal216 * @dbclk_div_en: enable divider for debounce clock217 * @dbclk_div_con: setting for divider of debounce clock218 * @port_eoi: end of interrupt of the port219 * @ext_port: port data from external220 * @version_id: controller version register221 */222struct rockchip_gpio_regs {223 u32 port_dr;224 u32 port_ddr;225 u32 int_en;226 u32 int_mask;227 u32 int_type;228 u32 int_polarity;229 u32 int_bothedge;230 u32 int_status;231 u32 int_rawstatus;232 u32 debounce;233 u32 dbclk_div_en;234 u32 dbclk_div_con;235 u32 port_eoi;236 u32 ext_port;237 u32 version_id;238};239 240/**241 * struct rockchip_iomux242 * @type: iomux variant using IOMUX_* constants243 * @offset: if initialized to -1 it will be autocalculated, by specifying244 * an initial offset value the relevant source offset can be reset245 * to a new value for autocalculating the following iomux registers.246 */247struct rockchip_iomux {248 int type;249 int offset;250};251 252/*253 * enum type index corresponding to rockchip_perpin_drv_list arrays index.254 */255enum rockchip_pin_drv_type {256 DRV_TYPE_IO_DEFAULT = 0,257 DRV_TYPE_IO_1V8_OR_3V0,258 DRV_TYPE_IO_1V8_ONLY,259 DRV_TYPE_IO_1V8_3V0_AUTO,260 DRV_TYPE_IO_3V3_ONLY,261 DRV_TYPE_MAX262};263 264/*265 * enum type index corresponding to rockchip_pull_list arrays index.266 */267enum rockchip_pin_pull_type {268 PULL_TYPE_IO_DEFAULT = 0,269 PULL_TYPE_IO_1V8_ONLY,270 PULL_TYPE_MAX271};272 273/**274 * struct rockchip_drv275 * @drv_type: drive strength variant using rockchip_perpin_drv_type276 * @offset: if initialized to -1 it will be autocalculated, by specifying277 * an initial offset value the relevant source offset can be reset278 * to a new value for autocalculating the following drive strength279 * registers. if used chips own cal_drv func instead to calculate280 * registers offset, the variant could be ignored.281 */282struct rockchip_drv {283 enum rockchip_pin_drv_type drv_type;284 int offset;285};286 287/**288 * struct rockchip_pin_bank289 * @dev: the pinctrl device bind to the bank290 * @reg_base: register base of the gpio bank291 * @regmap_pull: optional separate register for additional pull settings292 * @clk: clock of the gpio bank293 * @db_clk: clock of the gpio debounce294 * @irq: interrupt of the gpio bank295 * @saved_masks: Saved content of GPIO_INTEN at suspend time.296 * @pin_base: first pin number297 * @nr_pins: number of pins in this bank298 * @name: name of the bank299 * @bank_num: number of the bank, to account for holes300 * @iomux: array describing the 4 iomux sources of the bank301 * @drv: array describing the 4 drive strength sources of the bank302 * @pull_type: array describing the 4 pull type sources of the bank303 * @valid: is all necessary information present304 * @of_node: dt node of this bank305 * @drvdata: common pinctrl basedata306 * @domain: irqdomain of the gpio bank307 * @gpio_chip: gpiolib chip308 * @grange: gpio range309 * @slock: spinlock for the gpio bank310 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode311 * @recalced_mask: bit mask to indicate a need to recalulate the mask312 * @route_mask: bits describing the routing pins of per bank313 * @deferred_output: gpio output settings to be done after gpio bank probed314 * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl315 */316struct rockchip_pin_bank {317 struct device *dev;318 void __iomem *reg_base;319 struct regmap *regmap_pull;320 struct clk *clk;321 struct clk *db_clk;322 int irq;323 u32 saved_masks;324 u32 pin_base;325 u8 nr_pins;326 char *name;327 u8 bank_num;328 struct rockchip_iomux iomux[4];329 struct rockchip_drv drv[4];330 enum rockchip_pin_pull_type pull_type[4];331 bool valid;332 struct device_node *of_node;333 struct rockchip_pinctrl *drvdata;334 struct irq_domain *domain;335 struct gpio_chip gpio_chip;336 struct pinctrl_gpio_range grange;337 raw_spinlock_t slock;338 const struct rockchip_gpio_regs *gpio_regs;339 u32 gpio_type;340 u32 toggle_edge_mode;341 u32 recalced_mask;342 u32 route_mask;343 struct list_head deferred_pins;344 struct mutex deferred_lock;345};346 347/**348 * struct rockchip_mux_recalced_data: represent a pin iomux data.349 * @num: bank number.350 * @pin: pin number.351 * @bit: index at register.352 * @reg: register offset.353 * @mask: mask bit354 */355struct rockchip_mux_recalced_data {356 u8 num;357 u8 pin;358 u32 reg;359 u8 bit;360 u8 mask;361};362 363enum rockchip_mux_route_location {364 ROCKCHIP_ROUTE_SAME = 0,365 ROCKCHIP_ROUTE_PMU,366 ROCKCHIP_ROUTE_GRF,367};368 369/**370 * struct rockchip_mux_recalced_data: represent a pin iomux data.371 * @bank_num: bank number.372 * @pin: index at register or used to calc index.373 * @func: the min pin.374 * @route_location: the mux route location (same, pmu, grf).375 * @route_offset: the max pin.376 * @route_val: the register offset.377 */378struct rockchip_mux_route_data {379 u8 bank_num;380 u8 pin;381 u8 func;382 enum rockchip_mux_route_location route_location;383 u32 route_offset;384 u32 route_val;385};386 387struct rockchip_pin_ctrl {388 struct rockchip_pin_bank *pin_banks;389 u32 nr_banks;390 u32 nr_pins;391 char *label;392 enum rockchip_pinctrl_type type;393 int grf_mux_offset;394 int pmu_mux_offset;395 int grf_drv_offset;396 int pmu_drv_offset;397 struct rockchip_mux_recalced_data *iomux_recalced;398 u32 niomux_recalced;399 struct rockchip_mux_route_data *iomux_routes;400 u32 niomux_routes;401 402 int (*pull_calc_reg)(struct rockchip_pin_bank *bank,403 int pin_num, struct regmap **regmap,404 int *reg, u8 *bit);405 int (*drv_calc_reg)(struct rockchip_pin_bank *bank,406 int pin_num, struct regmap **regmap,407 int *reg, u8 *bit);408 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,409 int pin_num, struct regmap **regmap,410 int *reg, u8 *bit);411};412 413struct rockchip_pin_config {414 unsigned int func;415 unsigned long *configs;416 unsigned int nconfigs;417};418 419enum pin_config_param;420 421struct rockchip_pin_deferred {422 struct list_head head;423 unsigned int pin;424 enum pin_config_param param;425 u32 arg;426};427 428/**429 * struct rockchip_pin_group: represent group of pins of a pinmux function.430 * @name: name of the pin group, used to lookup the group.431 * @pins: the pins included in this group.432 * @npins: number of pins included in this group.433 * @data: local pin configuration434 */435struct rockchip_pin_group {436 const char *name;437 unsigned int npins;438 unsigned int *pins;439 struct rockchip_pin_config *data;440};441 442/**443 * struct rockchip_pmx_func: represent a pin function.444 * @name: name of the pin function, used to lookup the function.445 * @groups: one or more names of pin groups that provide this function.446 * @ngroups: number of groups included in @groups.447 */448struct rockchip_pmx_func {449 const char *name;450 const char **groups;451 u8 ngroups;452};453 454struct rockchip_pinctrl {455 struct regmap *regmap_base;456 int reg_size;457 struct regmap *regmap_pull;458 struct regmap *regmap_pmu;459 struct device *dev;460 struct rockchip_pin_ctrl *ctrl;461 struct pinctrl_desc pctl;462 struct pinctrl_dev *pctl_dev;463 struct rockchip_pin_group *groups;464 unsigned int ngroups;465 struct rockchip_pmx_func *functions;466 unsigned int nfunctions;467};468 469#endif470