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1/*2 * Generic device tree based pinctrl driver for one register per pin3 * type pinmux controllers4 *5 * Copyright (C) 2012 Texas Instruments, Inc.6 *7 * This file is licensed under the terms of the GNU General Public8 * License version 2. This program is licensed "as is" without any9 * warranty of any kind, whether express or implied.10 */11 12#include <linux/init.h>13#include <linux/module.h>14#include <linux/io.h>15#include <linux/platform_device.h>16#include <linux/slab.h>17#include <linux/err.h>18#include <linux/list.h>19#include <linux/interrupt.h>20#include <linux/irqchip/chained_irq.h>21#include <linux/of.h>22#include <linux/of_irq.h>23#include <linux/seq_file.h>24 25#include <linux/pinctrl/pinconf-generic.h>26#include <linux/pinctrl/pinconf.h>27#include <linux/pinctrl/pinctrl.h>28#include <linux/pinctrl/pinmux.h>29 30#include <linux/platform_data/pinctrl-single.h>31 32#include "core.h"33#include "devicetree.h"34#include "pinconf.h"35#include "pinmux.h"36 37#define DRIVER_NAME "pinctrl-single"38#define PCS_OFF_DISABLED ~0U39 40/**41 * struct pcs_func_vals - mux function register offset and value pair42 * @reg: register virtual address43 * @val: register value44 * @mask: mask45 */46struct pcs_func_vals {47 void __iomem *reg;48 unsigned val;49 unsigned mask;50};51 52/**53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset54 * and value, enable, disable, mask55 * @param: config parameter56 * @val: user input bits in the pinconf register57 * @enable: enable bits in the pinconf register58 * @disable: disable bits in the pinconf register59 * @mask: mask bits in the register value60 */61struct pcs_conf_vals {62 enum pin_config_param param;63 unsigned val;64 unsigned enable;65 unsigned disable;66 unsigned mask;67};68 69/**70 * struct pcs_conf_type - pinconf property name, pinconf param pair71 * @name: property name in DTS file72 * @param: config parameter73 */74struct pcs_conf_type {75 const char *name;76 enum pin_config_param param;77};78 79/**80 * struct pcs_function - pinctrl function81 * @name: pinctrl function name82 * @vals: register and vals array83 * @nvals: number of entries in vals array84 * @conf: array of pin configurations85 * @nconfs: number of pin configurations available86 * @node: list node87 */88struct pcs_function {89 const char *name;90 struct pcs_func_vals *vals;91 unsigned nvals;92 struct pcs_conf_vals *conf;93 int nconfs;94 struct list_head node;95};96 97/**98 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function99 * @offset: offset base of pins100 * @npins: number pins with the same mux value of gpio function101 * @gpiofunc: mux value of gpio function102 * @node: list node103 */104struct pcs_gpiofunc_range {105 unsigned offset;106 unsigned npins;107 unsigned gpiofunc;108 struct list_head node;109};110 111/**112 * struct pcs_data - wrapper for data needed by pinctrl framework113 * @pa: pindesc array114 * @cur: index to current element115 *116 * REVISIT: We should be able to drop this eventually by adding117 * support for registering pins individually in the pinctrl118 * framework for those drivers that don't need a static array.119 */120struct pcs_data {121 struct pinctrl_pin_desc *pa;122 int cur;123};124 125/**126 * struct pcs_soc_data - SoC specific settings127 * @flags: initial SoC specific PCS_FEAT_xxx values128 * @irq: optional interrupt for the controller129 * @irq_enable_mask: optional SoC specific interrupt enable mask130 * @irq_status_mask: optional SoC specific interrupt status mask131 * @rearm: optional SoC specific wake-up rearm function132 */133struct pcs_soc_data {134 unsigned flags;135 int irq;136 unsigned irq_enable_mask;137 unsigned irq_status_mask;138 void (*rearm)(void);139};140 141/**142 * struct pcs_device - pinctrl device instance143 * @res: resources144 * @base: virtual address of the controller145 * @saved_vals: saved values for the controller146 * @size: size of the ioremapped area147 * @dev: device entry148 * @np: device tree node149 * @pctl: pin controller device150 * @flags: mask of PCS_FEAT_xxx values151 * @missing_nr_pinctrl_cells: for legacy binding, may go away152 * @socdata: soc specific data153 * @lock: spinlock for register access154 * @mutex: mutex protecting the lists155 * @width: bits per mux register156 * @fmask: function register mask157 * @fshift: function register shift158 * @foff: value to turn mux off159 * @fmax: max number of functions in fmask160 * @bits_per_mux: number of bits per mux161 * @bits_per_pin: number of bits per pin162 * @pins: physical pins on the SoC163 * @gpiofuncs: list of gpio functions164 * @irqs: list of interrupt registers165 * @chip: chip container for this instance166 * @domain: IRQ domain for this instance167 * @desc: pin controller descriptor168 * @read: register read function to use169 * @write: register write function to use170 */171struct pcs_device {172 struct resource *res;173 void __iomem *base;174 void *saved_vals;175 unsigned size;176 struct device *dev;177 struct device_node *np;178 struct pinctrl_dev *pctl;179 unsigned flags;180#define PCS_CONTEXT_LOSS_OFF (1 << 3)181#define PCS_QUIRK_SHARED_IRQ (1 << 2)182#define PCS_FEAT_IRQ (1 << 1)183#define PCS_FEAT_PINCONF (1 << 0)184 struct property *missing_nr_pinctrl_cells;185 struct pcs_soc_data socdata;186 raw_spinlock_t lock;187 struct mutex mutex;188 unsigned width;189 unsigned fmask;190 unsigned fshift;191 unsigned foff;192 unsigned fmax;193 bool bits_per_mux;194 unsigned bits_per_pin;195 struct pcs_data pins;196 struct list_head gpiofuncs;197 struct list_head irqs;198 struct irq_chip chip;199 struct irq_domain *domain;200 struct pinctrl_desc desc;201 unsigned (*read)(void __iomem *reg);202 void (*write)(unsigned val, void __iomem *reg);203};204 205#define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)206#define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)207#define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)208 209static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,210 unsigned long *config);211static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,212 unsigned long *configs, unsigned num_configs);213 214static enum pin_config_param pcs_bias[] = {215 PIN_CONFIG_BIAS_PULL_DOWN,216 PIN_CONFIG_BIAS_PULL_UP,217};218 219/*220 * This lock class tells lockdep that irqchip core that this single221 * pinctrl can be in a different category than its parents, so it won't222 * report false recursion.223 */224static struct lock_class_key pcs_lock_class;225 226/* Class for the IRQ request mutex */227static struct lock_class_key pcs_request_class;228 229/*230 * REVISIT: Reads and writes could eventually use regmap or something231 * generic. But at least on omaps, some mux registers are performance232 * critical as they may need to be remuxed every time before and after233 * idle. Adding tests for register access width for every read and234 * write like regmap is doing is not desired, and caching the registers235 * does not help in this case.236 */237 238static unsigned int pcs_readb(void __iomem *reg)239{240 return readb(reg);241}242 243static unsigned int pcs_readw(void __iomem *reg)244{245 return readw(reg);246}247 248static unsigned int pcs_readl(void __iomem *reg)249{250 return readl(reg);251}252 253static void pcs_writeb(unsigned int val, void __iomem *reg)254{255 writeb(val, reg);256}257 258static void pcs_writew(unsigned int val, void __iomem *reg)259{260 writew(val, reg);261}262 263static void pcs_writel(unsigned int val, void __iomem *reg)264{265 writel(val, reg);266}267 268static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,269 unsigned int pin)270{271 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;272 273 if (pcs->bits_per_mux) {274 unsigned int pin_offset_bytes;275 276 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;277 return (pin_offset_bytes / mux_bytes) * mux_bytes;278 }279 280 return pin * mux_bytes;281}282 283static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,284 unsigned int pin)285{286 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;287}288 289static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,290 struct seq_file *s,291 unsigned pin)292{293 struct pcs_device *pcs;294 unsigned int val;295 unsigned long offset;296 size_t pa;297 298 pcs = pinctrl_dev_get_drvdata(pctldev);299 300 offset = pcs_pin_reg_offset_get(pcs, pin);301 val = pcs->read(pcs->base + offset);302 303 if (pcs->bits_per_mux)304 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);305 306 pa = pcs->res->start + offset;307 308 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);309}310 311static void pcs_dt_free_map(struct pinctrl_dev *pctldev,312 struct pinctrl_map *map, unsigned num_maps)313{314 struct pcs_device *pcs;315 316 pcs = pinctrl_dev_get_drvdata(pctldev);317 devm_kfree(pcs->dev, map);318}319 320static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,321 struct device_node *np_config,322 struct pinctrl_map **map, unsigned *num_maps);323 324static const struct pinctrl_ops pcs_pinctrl_ops = {325 .get_groups_count = pinctrl_generic_get_group_count,326 .get_group_name = pinctrl_generic_get_group_name,327 .get_group_pins = pinctrl_generic_get_group_pins,328 .pin_dbg_show = pcs_pin_dbg_show,329 .dt_node_to_map = pcs_dt_node_to_map,330 .dt_free_map = pcs_dt_free_map,331};332 333static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,334 struct pcs_function **func)335{336 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);337 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);338 const struct pinctrl_setting_mux *setting;339 struct function_desc *function;340 unsigned fselector;341 342 /* If pin is not described in DTS & enabled, mux_setting is NULL. */343 setting = pdesc->mux_setting;344 if (!setting)345 return -ENOTSUPP;346 fselector = setting->func;347 function = pinmux_generic_get_function(pctldev, fselector);348 if (!function)349 return -EINVAL;350 *func = function->data;351 if (!(*func)) {352 dev_err(pcs->dev, "%s could not find function%i\n",353 __func__, fselector);354 return -ENOTSUPP;355 }356 return 0;357}358 359static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,360 unsigned group)361{362 struct pcs_device *pcs;363 struct function_desc *function;364 struct pcs_function *func;365 int i;366 367 pcs = pinctrl_dev_get_drvdata(pctldev);368 /* If function mask is null, needn't enable it. */369 if (!pcs->fmask)370 return 0;371 function = pinmux_generic_get_function(pctldev, fselector);372 if (!function)373 return -EINVAL;374 func = function->data;375 if (!func)376 return -EINVAL;377 378 dev_dbg(pcs->dev, "enabling %s function%i\n",379 func->name, fselector);380 381 for (i = 0; i < func->nvals; i++) {382 struct pcs_func_vals *vals;383 unsigned long flags;384 unsigned val, mask;385 386 vals = &func->vals[i];387 raw_spin_lock_irqsave(&pcs->lock, flags);388 val = pcs->read(vals->reg);389 390 if (pcs->bits_per_mux)391 mask = vals->mask;392 else393 mask = pcs->fmask;394 395 val &= ~mask;396 val |= (vals->val & mask);397 pcs->write(val, vals->reg);398 raw_spin_unlock_irqrestore(&pcs->lock, flags);399 }400 401 return 0;402}403 404static int pcs_request_gpio(struct pinctrl_dev *pctldev,405 struct pinctrl_gpio_range *range, unsigned pin)406{407 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);408 struct pcs_gpiofunc_range *frange = NULL;409 struct list_head *pos, *tmp;410 unsigned data;411 412 /* If function mask is null, return directly. */413 if (!pcs->fmask)414 return -ENOTSUPP;415 416 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {417 u32 offset;418 419 frange = list_entry(pos, struct pcs_gpiofunc_range, node);420 if (pin >= frange->offset + frange->npins421 || pin < frange->offset)422 continue;423 424 offset = pcs_pin_reg_offset_get(pcs, pin);425 426 if (pcs->bits_per_mux) {427 int pin_shift = pcs_pin_shift_reg_get(pcs, pin);428 429 data = pcs->read(pcs->base + offset);430 data &= ~(pcs->fmask << pin_shift);431 data |= frange->gpiofunc << pin_shift;432 pcs->write(data, pcs->base + offset);433 } else {434 data = pcs->read(pcs->base + offset);435 data &= ~pcs->fmask;436 data |= frange->gpiofunc;437 pcs->write(data, pcs->base + offset);438 }439 break;440 }441 return 0;442}443 444static const struct pinmux_ops pcs_pinmux_ops = {445 .get_functions_count = pinmux_generic_get_function_count,446 .get_function_name = pinmux_generic_get_function_name,447 .get_function_groups = pinmux_generic_get_function_groups,448 .set_mux = pcs_set_mux,449 .gpio_request_enable = pcs_request_gpio,450};451 452/* Clear BIAS value */453static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)454{455 unsigned long config;456 int i;457 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {458 config = pinconf_to_config_packed(pcs_bias[i], 0);459 pcs_pinconf_set(pctldev, pin, &config, 1);460 }461}462 463/*464 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.465 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.466 */467static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)468{469 unsigned long config;470 int i;471 472 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {473 config = pinconf_to_config_packed(pcs_bias[i], 0);474 if (!pcs_pinconf_get(pctldev, pin, &config))475 goto out;476 }477 return true;478out:479 return false;480}481 482static int pcs_pinconf_get(struct pinctrl_dev *pctldev,483 unsigned pin, unsigned long *config)484{485 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);486 struct pcs_function *func;487 enum pin_config_param param;488 unsigned offset = 0, data = 0, i, j, ret;489 490 ret = pcs_get_function(pctldev, pin, &func);491 if (ret)492 return ret;493 494 for (i = 0; i < func->nconfs; i++) {495 param = pinconf_to_config_param(*config);496 if (param == PIN_CONFIG_BIAS_DISABLE) {497 if (pcs_pinconf_bias_disable(pctldev, pin)) {498 *config = 0;499 return 0;500 } else {501 return -ENOTSUPP;502 }503 } else if (param != func->conf[i].param) {504 continue;505 }506 507 offset = pin * (pcs->width / BITS_PER_BYTE);508 data = pcs->read(pcs->base + offset) & func->conf[i].mask;509 switch (func->conf[i].param) {510 /* 4 parameters */511 case PIN_CONFIG_BIAS_PULL_DOWN:512 case PIN_CONFIG_BIAS_PULL_UP:513 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:514 if ((data != func->conf[i].enable) ||515 (data == func->conf[i].disable))516 return -ENOTSUPP;517 *config = 0;518 break;519 /* 2 parameters */520 case PIN_CONFIG_INPUT_SCHMITT:521 for (j = 0; j < func->nconfs; j++) {522 switch (func->conf[j].param) {523 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:524 if (data != func->conf[j].enable)525 return -ENOTSUPP;526 break;527 default:528 break;529 }530 }531 *config = data;532 break;533 case PIN_CONFIG_DRIVE_STRENGTH:534 case PIN_CONFIG_SLEW_RATE:535 case PIN_CONFIG_MODE_LOW_POWER:536 case PIN_CONFIG_INPUT_ENABLE:537 default:538 *config = data;539 break;540 }541 return 0;542 }543 return -ENOTSUPP;544}545 546static int pcs_pinconf_set(struct pinctrl_dev *pctldev,547 unsigned pin, unsigned long *configs,548 unsigned num_configs)549{550 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);551 struct pcs_function *func;552 unsigned offset = 0, shift = 0, i, data, ret;553 u32 arg;554 int j;555 enum pin_config_param param;556 557 ret = pcs_get_function(pctldev, pin, &func);558 if (ret)559 return ret;560 561 for (j = 0; j < num_configs; j++) {562 param = pinconf_to_config_param(configs[j]);563 564 /* BIAS_DISABLE has no entry in the func->conf table */565 if (param == PIN_CONFIG_BIAS_DISABLE) {566 /* This just disables all bias entries */567 pcs_pinconf_clear_bias(pctldev, pin);568 continue;569 }570 571 for (i = 0; i < func->nconfs; i++) {572 if (param != func->conf[i].param)573 continue;574 575 offset = pin * (pcs->width / BITS_PER_BYTE);576 data = pcs->read(pcs->base + offset);577 arg = pinconf_to_config_argument(configs[j]);578 switch (param) {579 /* 2 parameters */580 case PIN_CONFIG_INPUT_SCHMITT:581 case PIN_CONFIG_DRIVE_STRENGTH:582 case PIN_CONFIG_SLEW_RATE:583 case PIN_CONFIG_MODE_LOW_POWER:584 case PIN_CONFIG_INPUT_ENABLE:585 shift = ffs(func->conf[i].mask) - 1;586 data &= ~func->conf[i].mask;587 data |= (arg << shift) & func->conf[i].mask;588 break;589 /* 4 parameters */590 case PIN_CONFIG_BIAS_PULL_DOWN:591 case PIN_CONFIG_BIAS_PULL_UP:592 if (arg)593 pcs_pinconf_clear_bias(pctldev, pin);594 fallthrough;595 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:596 data &= ~func->conf[i].mask;597 if (arg)598 data |= func->conf[i].enable;599 else600 data |= func->conf[i].disable;601 break;602 default:603 return -ENOTSUPP;604 }605 pcs->write(data, pcs->base + offset);606 607 break;608 }609 if (i >= func->nconfs)610 return -ENOTSUPP;611 } /* for each config */612 613 return 0;614}615 616static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,617 unsigned group, unsigned long *config)618{619 const unsigned *pins;620 unsigned npins, old = 0;621 int i, ret;622 623 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);624 if (ret)625 return ret;626 for (i = 0; i < npins; i++) {627 if (pcs_pinconf_get(pctldev, pins[i], config))628 return -ENOTSUPP;629 /* configs do not match between two pins */630 if (i && (old != *config))631 return -ENOTSUPP;632 old = *config;633 }634 return 0;635}636 637static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,638 unsigned group, unsigned long *configs,639 unsigned num_configs)640{641 const unsigned *pins;642 unsigned npins;643 int i, ret;644 645 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);646 if (ret)647 return ret;648 for (i = 0; i < npins; i++) {649 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))650 return -ENOTSUPP;651 }652 return 0;653}654 655static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,656 struct seq_file *s, unsigned pin)657{658}659 660static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,661 struct seq_file *s, unsigned selector)662{663}664 665static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,666 struct seq_file *s,667 unsigned long config)668{669 pinconf_generic_dump_config(pctldev, s, config);670}671 672static const struct pinconf_ops pcs_pinconf_ops = {673 .pin_config_get = pcs_pinconf_get,674 .pin_config_set = pcs_pinconf_set,675 .pin_config_group_get = pcs_pinconf_group_get,676 .pin_config_group_set = pcs_pinconf_group_set,677 .pin_config_dbg_show = pcs_pinconf_dbg_show,678 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,679 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,680 .is_generic = true,681};682 683/**684 * pcs_add_pin() - add a pin to the static per controller pin array685 * @pcs: pcs driver instance686 * @offset: register offset from base687 */688static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)689{690 struct pcs_soc_data *pcs_soc = &pcs->socdata;691 struct pinctrl_pin_desc *pin;692 int i;693 694 i = pcs->pins.cur;695 if (i >= pcs->desc.npins) {696 dev_err(pcs->dev, "too many pins, max %i\n",697 pcs->desc.npins);698 return -ENOMEM;699 }700 701 if (pcs_soc->irq_enable_mask) {702 unsigned val;703 704 val = pcs->read(pcs->base + offset);705 if (val & pcs_soc->irq_enable_mask) {706 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",707 (unsigned long)pcs->res->start + offset, val);708 val &= ~pcs_soc->irq_enable_mask;709 pcs->write(val, pcs->base + offset);710 }711 }712 713 pin = &pcs->pins.pa[i];714 pin->number = i;715 pcs->pins.cur++;716 717 return i;718}719 720/**721 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver722 * @pcs: pcs driver instance723 *724 * In case of errors, resources are freed in pcs_free_resources.725 *726 * If your hardware needs holes in the address space, then just set727 * up multiple driver instances.728 */729static int pcs_allocate_pin_table(struct pcs_device *pcs)730{731 int mux_bytes, nr_pins, i;732 733 mux_bytes = pcs->width / BITS_PER_BYTE;734 735 if (pcs->bits_per_mux && pcs->fmask) {736 pcs->bits_per_pin = fls(pcs->fmask);737 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;738 } else {739 nr_pins = pcs->size / mux_bytes;740 }741 742 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);743 pcs->pins.pa = devm_kcalloc(pcs->dev,744 nr_pins, sizeof(*pcs->pins.pa),745 GFP_KERNEL);746 if (!pcs->pins.pa)747 return -ENOMEM;748 749 pcs->desc.pins = pcs->pins.pa;750 pcs->desc.npins = nr_pins;751 752 for (i = 0; i < pcs->desc.npins; i++) {753 unsigned offset;754 int res;755 756 offset = pcs_pin_reg_offset_get(pcs, i);757 res = pcs_add_pin(pcs, offset);758 if (res < 0) {759 dev_err(pcs->dev, "error adding pins: %i\n", res);760 return res;761 }762 }763 764 return 0;765}766 767/**768 * pcs_add_function() - adds a new function to the function list769 * @pcs: pcs driver instance770 * @fcn: new function allocated771 * @name: name of the function772 * @vals: array of mux register value pairs used by the function773 * @nvals: number of mux register value pairs774 * @pgnames: array of pingroup names for the function775 * @npgnames: number of pingroup names776 *777 * Caller must take care of locking.778 */779static int pcs_add_function(struct pcs_device *pcs,780 struct pcs_function **fcn,781 const char *name,782 struct pcs_func_vals *vals,783 unsigned int nvals,784 const char **pgnames,785 unsigned int npgnames)786{787 struct pcs_function *function;788 int selector;789 790 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);791 if (!function)792 return -ENOMEM;793 794 function->vals = vals;795 function->nvals = nvals;796 function->name = name;797 798 selector = pinmux_generic_add_function(pcs->pctl, name,799 pgnames, npgnames,800 function);801 if (selector < 0) {802 devm_kfree(pcs->dev, function);803 *fcn = NULL;804 } else {805 *fcn = function;806 }807 808 return selector;809}810 811/**812 * pcs_get_pin_by_offset() - get a pin index based on the register offset813 * @pcs: pcs driver instance814 * @offset: register offset from the base815 *816 * Note that this is OK as long as the pins are in a static array.817 */818static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)819{820 unsigned index;821 822 if (offset >= pcs->size) {823 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",824 offset, pcs->size);825 return -EINVAL;826 }827 828 if (pcs->bits_per_mux)829 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;830 else831 index = offset / (pcs->width / BITS_PER_BYTE);832 833 return index;834}835 836/*837 * check whether data matches enable bits or disable bits838 * Return value: 1 for matching enable bits, 0 for matching disable bits,839 * and negative value for matching failure.840 */841static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)842{843 int ret = -EINVAL;844 845 if (data == enable)846 ret = 1;847 else if (data == disable)848 ret = 0;849 return ret;850}851 852static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,853 unsigned value, unsigned enable, unsigned disable,854 unsigned mask)855{856 (*conf)->param = param;857 (*conf)->val = value;858 (*conf)->enable = enable;859 (*conf)->disable = disable;860 (*conf)->mask = mask;861 (*conf)++;862}863 864static void add_setting(unsigned long **setting, enum pin_config_param param,865 unsigned arg)866{867 **setting = pinconf_to_config_packed(param, arg);868 (*setting)++;869}870 871/* add pinconf setting with 2 parameters */872static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,873 const char *name, enum pin_config_param param,874 struct pcs_conf_vals **conf, unsigned long **settings)875{876 unsigned value[2], shift;877 int ret;878 879 ret = of_property_read_u32_array(np, name, value, 2);880 if (ret)881 return;882 /* set value & mask */883 value[0] &= value[1];884 shift = ffs(value[1]) - 1;885 /* skip enable & disable */886 add_config(conf, param, value[0], 0, 0, value[1]);887 add_setting(settings, param, value[0] >> shift);888}889 890/* add pinconf setting with 4 parameters */891static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,892 const char *name, enum pin_config_param param,893 struct pcs_conf_vals **conf, unsigned long **settings)894{895 unsigned value[4];896 int ret;897 898 /* value to set, enable, disable, mask */899 ret = of_property_read_u32_array(np, name, value, 4);900 if (ret)901 return;902 if (!value[3]) {903 dev_err(pcs->dev, "mask field of the property can't be 0\n");904 return;905 }906 value[0] &= value[3];907 value[1] &= value[3];908 value[2] &= value[3];909 ret = pcs_config_match(value[0], value[1], value[2]);910 if (ret < 0)911 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");912 add_config(conf, param, value[0], value[1], value[2], value[3]);913 add_setting(settings, param, ret);914}915 916static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,917 struct pcs_function *func,918 struct pinctrl_map **map)919 920{921 struct pinctrl_map *m = *map;922 int i = 0, nconfs = 0;923 unsigned long *settings = NULL, *s = NULL;924 struct pcs_conf_vals *conf = NULL;925 static const struct pcs_conf_type prop2[] = {926 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },927 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },928 { "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, },929 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },930 { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, },931 };932 static const struct pcs_conf_type prop4[] = {933 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },934 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },935 { "pinctrl-single,input-schmitt-enable",936 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },937 };938 939 /* If pinconf isn't supported, don't parse properties in below. */940 if (!PCS_HAS_PINCONF)941 return -ENOTSUPP;942 943 /* cacluate how much properties are supported in current node */944 for (i = 0; i < ARRAY_SIZE(prop2); i++) {945 if (of_property_present(np, prop2[i].name))946 nconfs++;947 }948 for (i = 0; i < ARRAY_SIZE(prop4); i++) {949 if (of_property_present(np, prop4[i].name))950 nconfs++;951 }952 if (!nconfs)953 return -ENOTSUPP;954 955 func->conf = devm_kcalloc(pcs->dev,956 nconfs, sizeof(struct pcs_conf_vals),957 GFP_KERNEL);958 if (!func->conf)959 return -ENOMEM;960 func->nconfs = nconfs;961 conf = &(func->conf[0]);962 m++;963 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),964 GFP_KERNEL);965 if (!settings)966 return -ENOMEM;967 s = &settings[0];968 969 for (i = 0; i < ARRAY_SIZE(prop2); i++)970 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,971 &conf, &s);972 for (i = 0; i < ARRAY_SIZE(prop4); i++)973 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,974 &conf, &s);975 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;976 m->data.configs.group_or_pin = np->name;977 m->data.configs.configs = settings;978 m->data.configs.num_configs = nconfs;979 return 0;980}981 982/**983 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry984 * @pcs: pinctrl driver instance985 * @np: device node of the mux entry986 * @map: map entry987 * @num_maps: number of map988 * @pgnames: pingroup names989 *990 * Note that this binding currently supports only sets of one register + value.991 *992 * Also note that this driver tries to avoid understanding pin and function993 * names because of the extra bloat they would cause especially in the case of994 * a large number of pins. This driver just sets what is specified for the board995 * in the .dts file. Further user space debugging tools can be developed to996 * decipher the pin and function names using debugfs.997 *998 * If you are concerned about the boot time, set up the static pins in999 * the bootloader, and only set up selected pins as device tree entries.1000 */1001static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,1002 struct device_node *np,1003 struct pinctrl_map **map,1004 unsigned *num_maps,1005 const char **pgnames)1006{1007 const char *name = "pinctrl-single,pins";1008 struct pcs_func_vals *vals;1009 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;1010 struct pcs_function *function = NULL;1011 1012 rows = pinctrl_count_index_with_args(np, name);1013 if (rows <= 0) {1014 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);1015 return -EINVAL;1016 }1017 1018 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);1019 if (!vals)1020 return -ENOMEM;1021 1022 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);1023 if (!pins)1024 goto free_vals;1025 1026 for (i = 0; i < rows; i++) {1027 struct of_phandle_args pinctrl_spec;1028 unsigned int offset;1029 int pin;1030 1031 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);1032 if (res)1033 return res;1034 1035 if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {1036 dev_err(pcs->dev, "invalid args_count for spec: %i\n",1037 pinctrl_spec.args_count);1038 break;1039 }1040 1041 offset = pinctrl_spec.args[0];1042 vals[found].reg = pcs->base + offset;1043 1044 switch (pinctrl_spec.args_count) {1045 case 2:1046 vals[found].val = pinctrl_spec.args[1];1047 break;1048 case 3:1049 vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);1050 break;1051 }1052 1053 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",1054 pinctrl_spec.np, offset, vals[found].val);1055 1056 pin = pcs_get_pin_by_offset(pcs, offset);1057 if (pin < 0) {1058 dev_err(pcs->dev,1059 "could not add functions for %pOFn %ux\n",1060 np, offset);1061 break;1062 }1063 pins[found++] = pin;1064 }1065 1066 pgnames[0] = np->name;1067 mutex_lock(&pcs->mutex);1068 fsel = pcs_add_function(pcs, &function, np->name, vals, found,1069 pgnames, 1);1070 if (fsel < 0) {1071 res = fsel;1072 goto free_pins;1073 }1074 1075 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);1076 if (gsel < 0) {1077 res = gsel;1078 goto free_function;1079 }1080 1081 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;1082 (*map)->data.mux.group = np->name;1083 (*map)->data.mux.function = np->name;1084 1085 if (PCS_HAS_PINCONF && function) {1086 res = pcs_parse_pinconf(pcs, np, function, map);1087 if (res == 0)1088 *num_maps = 2;1089 else if (res == -ENOTSUPP)1090 *num_maps = 1;1091 else1092 goto free_pingroups;1093 } else {1094 *num_maps = 1;1095 }1096 mutex_unlock(&pcs->mutex);1097 1098 return 0;1099 1100free_pingroups:1101 pinctrl_generic_remove_group(pcs->pctl, gsel);1102 *num_maps = 1;1103free_function:1104 pinmux_generic_remove_function(pcs->pctl, fsel);1105free_pins:1106 mutex_unlock(&pcs->mutex);1107 devm_kfree(pcs->dev, pins);1108 1109free_vals:1110 devm_kfree(pcs->dev, vals);1111 1112 return res;1113}1114 1115static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,1116 struct device_node *np,1117 struct pinctrl_map **map,1118 unsigned *num_maps,1119 const char **pgnames)1120{1121 const char *name = "pinctrl-single,bits";1122 struct pcs_func_vals *vals;1123 int rows, *pins, found = 0, res = -ENOMEM, i, fsel;1124 int npins_in_row;1125 struct pcs_function *function = NULL;1126 1127 rows = pinctrl_count_index_with_args(np, name);1128 if (rows <= 0) {1129 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);1130 return -EINVAL;1131 }1132 1133 if (PCS_HAS_PINCONF) {1134 dev_err(pcs->dev, "pinconf not supported\n");1135 return -ENOTSUPP;1136 }1137 1138 npins_in_row = pcs->width / pcs->bits_per_pin;1139 1140 vals = devm_kzalloc(pcs->dev,1141 array3_size(rows, npins_in_row, sizeof(*vals)),1142 GFP_KERNEL);1143 if (!vals)1144 return -ENOMEM;1145 1146 pins = devm_kzalloc(pcs->dev,1147 array3_size(rows, npins_in_row, sizeof(*pins)),1148 GFP_KERNEL);1149 if (!pins)1150 goto free_vals;1151 1152 for (i = 0; i < rows; i++) {1153 struct of_phandle_args pinctrl_spec;1154 unsigned offset, val;1155 unsigned mask, bit_pos, val_pos, mask_pos, submask;1156 unsigned pin_num_from_lsb;1157 int pin;1158 1159 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);1160 if (res)1161 return res;1162 1163 if (pinctrl_spec.args_count < 3) {1164 dev_err(pcs->dev, "invalid args_count for spec: %i\n",1165 pinctrl_spec.args_count);1166 break;1167 }1168 1169 /* Index plus two value cells */1170 offset = pinctrl_spec.args[0];1171 val = pinctrl_spec.args[1];1172 mask = pinctrl_spec.args[2];1173 1174 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",1175 pinctrl_spec.np, offset, val, mask);1176 1177 /* Parse pins in each row from LSB */1178 while (mask) {1179 bit_pos = __ffs(mask);1180 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;1181 mask_pos = ((pcs->fmask) << bit_pos);1182 val_pos = val & mask_pos;1183 submask = mask & mask_pos;1184 1185 if ((mask & mask_pos) == 0) {1186 dev_err(pcs->dev,1187 "Invalid mask for %pOFn at 0x%x\n",1188 np, offset);1189 break;1190 }1191 1192 mask &= ~mask_pos;1193 1194 if (submask != mask_pos) {1195 dev_warn(pcs->dev,1196 "Invalid submask 0x%x for %pOFn at 0x%x\n",1197 submask, np, offset);1198 continue;1199 }1200 1201 vals[found].mask = submask;1202 vals[found].reg = pcs->base + offset;1203 vals[found].val = val_pos;1204 1205 pin = pcs_get_pin_by_offset(pcs, offset);1206 if (pin < 0) {1207 dev_err(pcs->dev,1208 "could not add functions for %pOFn %ux\n",1209 np, offset);1210 break;1211 }1212 pins[found++] = pin + pin_num_from_lsb;1213 }1214 }1215 1216 pgnames[0] = np->name;1217 mutex_lock(&pcs->mutex);1218 fsel = pcs_add_function(pcs, &function, np->name, vals, found,1219 pgnames, 1);1220 if (fsel < 0) {1221 res = fsel;1222 goto free_pins;1223 }1224 1225 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);1226 if (res < 0)1227 goto free_function;1228 1229 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;1230 (*map)->data.mux.group = np->name;1231 (*map)->data.mux.function = np->name;1232 1233 *num_maps = 1;1234 mutex_unlock(&pcs->mutex);1235 1236 return 0;1237 1238free_function:1239 pinmux_generic_remove_function(pcs->pctl, fsel);1240free_pins:1241 mutex_unlock(&pcs->mutex);1242 devm_kfree(pcs->dev, pins);1243 1244free_vals:1245 devm_kfree(pcs->dev, vals);1246 1247 return res;1248}1249/**1250 * pcs_dt_node_to_map() - allocates and parses pinctrl maps1251 * @pctldev: pinctrl instance1252 * @np_config: device tree pinmux entry1253 * @map: array of map entries1254 * @num_maps: number of maps1255 */1256static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,1257 struct device_node *np_config,1258 struct pinctrl_map **map, unsigned *num_maps)1259{1260 struct pcs_device *pcs;1261 const char **pgnames;1262 int ret;1263 1264 pcs = pinctrl_dev_get_drvdata(pctldev);1265 1266 /* create 2 maps. One is for pinmux, and the other is for pinconf. */1267 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);1268 if (!*map)1269 return -ENOMEM;1270 1271 *num_maps = 0;1272 1273 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);1274 if (!pgnames) {1275 ret = -ENOMEM;1276 goto free_map;1277 }1278 1279 if (pcs->bits_per_mux) {1280 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,1281 num_maps, pgnames);1282 if (ret < 0) {1283 dev_err(pcs->dev, "no pins entries for %pOFn\n",1284 np_config);1285 goto free_pgnames;1286 }1287 } else {1288 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,1289 num_maps, pgnames);1290 if (ret < 0) {1291 dev_err(pcs->dev, "no pins entries for %pOFn\n",1292 np_config);1293 goto free_pgnames;1294 }1295 }1296 1297 return 0;1298 1299free_pgnames:1300 devm_kfree(pcs->dev, pgnames);1301free_map:1302 devm_kfree(pcs->dev, *map);1303 1304 return ret;1305}1306 1307/**1308 * pcs_irq_free() - free interrupt1309 * @pcs: pcs driver instance1310 */1311static void pcs_irq_free(struct pcs_device *pcs)1312{1313 struct pcs_soc_data *pcs_soc = &pcs->socdata;1314 1315 if (pcs_soc->irq < 0)1316 return;1317 1318 if (pcs->domain)1319 irq_domain_remove(pcs->domain);1320 1321 if (PCS_QUIRK_HAS_SHARED_IRQ)1322 free_irq(pcs_soc->irq, pcs_soc);1323 else1324 irq_set_chained_handler(pcs_soc->irq, NULL);1325}1326 1327/**1328 * pcs_free_resources() - free memory used by this driver1329 * @pcs: pcs driver instance1330 */1331static void pcs_free_resources(struct pcs_device *pcs)1332{1333 pcs_irq_free(pcs);1334 1335#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)1336 if (pcs->missing_nr_pinctrl_cells)1337 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);1338#endif1339}1340 1341static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)1342{1343 const char *propname = "pinctrl-single,gpio-range";1344 const char *cellname = "#pinctrl-single,gpio-range-cells";1345 struct of_phandle_args gpiospec;1346 struct pcs_gpiofunc_range *range;1347 int ret, i;1348 1349 for (i = 0; ; i++) {1350 ret = of_parse_phandle_with_args(node, propname, cellname,1351 i, &gpiospec);1352 /* Do not treat it as error. Only treat it as end condition. */1353 if (ret) {1354 ret = 0;1355 break;1356 }1357 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);1358 if (!range) {1359 ret = -ENOMEM;1360 break;1361 }1362 range->offset = gpiospec.args[0];1363 range->npins = gpiospec.args[1];1364 range->gpiofunc = gpiospec.args[2];1365 mutex_lock(&pcs->mutex);1366 list_add_tail(&range->node, &pcs->gpiofuncs);1367 mutex_unlock(&pcs->mutex);1368 }1369 return ret;1370}1371 1372/**1373 * struct pcs_interrupt1374 * @reg: virtual address of interrupt register1375 * @hwirq: hardware irq number1376 * @irq: virtual irq number1377 * @node: list node1378 */1379struct pcs_interrupt {1380 void __iomem *reg;1381 irq_hw_number_t hwirq;1382 unsigned int irq;1383 struct list_head node;1384};1385 1386/**1387 * pcs_irq_set() - enables or disables an interrupt1388 * @pcs_soc: SoC specific settings1389 * @irq: interrupt1390 * @enable: enable or disable the interrupt1391 *1392 * Note that this currently assumes one interrupt per pinctrl1393 * register that is typically used for wake-up events.1394 */1395static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,1396 int irq, const bool enable)1397{1398 struct pcs_device *pcs;1399 struct list_head *pos;1400 unsigned mask;1401 1402 pcs = container_of(pcs_soc, struct pcs_device, socdata);1403 list_for_each(pos, &pcs->irqs) {1404 struct pcs_interrupt *pcswi;1405 unsigned soc_mask;1406 1407 pcswi = list_entry(pos, struct pcs_interrupt, node);1408 if (irq != pcswi->irq)1409 continue;1410 1411 soc_mask = pcs_soc->irq_enable_mask;1412 raw_spin_lock(&pcs->lock);1413 mask = pcs->read(pcswi->reg);1414 if (enable)1415 mask |= soc_mask;1416 else1417 mask &= ~soc_mask;1418 pcs->write(mask, pcswi->reg);1419 1420 /* flush posted write */1421 mask = pcs->read(pcswi->reg);1422 raw_spin_unlock(&pcs->lock);1423 }1424 1425 if (pcs_soc->rearm)1426 pcs_soc->rearm();1427}1428 1429/**1430 * pcs_irq_mask() - mask pinctrl interrupt1431 * @d: interrupt data1432 */1433static void pcs_irq_mask(struct irq_data *d)1434{1435 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);1436 1437 pcs_irq_set(pcs_soc, d->irq, false);1438}1439 1440/**1441 * pcs_irq_unmask() - unmask pinctrl interrupt1442 * @d: interrupt data1443 */1444static void pcs_irq_unmask(struct irq_data *d)1445{1446 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);1447 1448 pcs_irq_set(pcs_soc, d->irq, true);1449}1450 1451/**1452 * pcs_irq_set_wake() - toggle the suspend and resume wake up1453 * @d: interrupt data1454 * @state: wake-up state1455 *1456 * Note that this should be called only for suspend and resume.1457 * For runtime PM, the wake-up events should be enabled by default.1458 */1459static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)1460{1461 if (state)1462 pcs_irq_unmask(d);1463 else1464 pcs_irq_mask(d);1465 1466 return 0;1467}1468 1469/**1470 * pcs_irq_handle() - common interrupt handler1471 * @pcs_soc: SoC specific settings1472 *1473 * Note that this currently assumes we have one interrupt bit per1474 * mux register. This interrupt is typically used for wake-up events.1475 * For more complex interrupts different handlers can be specified.1476 */1477static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)1478{1479 struct pcs_device *pcs;1480 struct list_head *pos;1481 int count = 0;1482 1483 pcs = container_of(pcs_soc, struct pcs_device, socdata);1484 list_for_each(pos, &pcs->irqs) {1485 struct pcs_interrupt *pcswi;1486 unsigned mask;1487 1488 pcswi = list_entry(pos, struct pcs_interrupt, node);1489 raw_spin_lock(&pcs->lock);1490 mask = pcs->read(pcswi->reg);1491 raw_spin_unlock(&pcs->lock);1492 if (mask & pcs_soc->irq_status_mask) {1493 generic_handle_domain_irq(pcs->domain,1494 pcswi->hwirq);1495 count++;1496 }1497 }1498 1499 return count;1500}1501 1502/**1503 * pcs_irq_handler() - handler for the shared interrupt case1504 * @irq: interrupt1505 * @d: data1506 *1507 * Use this for cases where multiple instances of1508 * pinctrl-single share a single interrupt like on omaps.1509 */1510static irqreturn_t pcs_irq_handler(int irq, void *d)1511{1512 struct pcs_soc_data *pcs_soc = d;1513 1514 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;1515}1516 1517/**1518 * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case1519 * @desc: interrupt descriptor1520 *1521 * Use this if you have a separate interrupt for each1522 * pinctrl-single instance.1523 */1524static void pcs_irq_chain_handler(struct irq_desc *desc)1525{1526 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);1527 struct irq_chip *chip;1528 1529 chip = irq_desc_get_chip(desc);1530 chained_irq_enter(chip, desc);1531 pcs_irq_handle(pcs_soc);1532 /* REVISIT: export and add handle_bad_irq(irq, desc)? */1533 chained_irq_exit(chip, desc);1534}1535 1536static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,1537 irq_hw_number_t hwirq)1538{1539 struct pcs_soc_data *pcs_soc = d->host_data;1540 struct pcs_device *pcs;1541 struct pcs_interrupt *pcswi;1542 1543 pcs = container_of(pcs_soc, struct pcs_device, socdata);1544 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);1545 if (!pcswi)1546 return -ENOMEM;1547 1548 pcswi->reg = pcs->base + hwirq;1549 pcswi->hwirq = hwirq;1550 pcswi->irq = irq;1551 1552 mutex_lock(&pcs->mutex);1553 list_add_tail(&pcswi->node, &pcs->irqs);1554 mutex_unlock(&pcs->mutex);1555 1556 irq_set_chip_data(irq, pcs_soc);1557 irq_set_chip_and_handler(irq, &pcs->chip,1558 handle_level_irq);1559 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);1560 irq_set_noprobe(irq);1561 1562 return 0;1563}1564 1565static const struct irq_domain_ops pcs_irqdomain_ops = {1566 .map = pcs_irqdomain_map,1567 .xlate = irq_domain_xlate_onecell,1568};1569 1570/**1571 * pcs_irq_init_chained_handler() - set up a chained interrupt handler1572 * @pcs: pcs driver instance1573 * @np: device node pointer1574 */1575static int pcs_irq_init_chained_handler(struct pcs_device *pcs,1576 struct device_node *np)1577{1578 struct pcs_soc_data *pcs_soc = &pcs->socdata;1579 const char *name = "pinctrl";1580 int num_irqs;1581 1582 if (!pcs_soc->irq_enable_mask ||1583 !pcs_soc->irq_status_mask) {1584 pcs_soc->irq = -1;1585 return -EINVAL;1586 }1587 1588 INIT_LIST_HEAD(&pcs->irqs);1589 pcs->chip.name = name;1590 pcs->chip.irq_ack = pcs_irq_mask;1591 pcs->chip.irq_mask = pcs_irq_mask;1592 pcs->chip.irq_unmask = pcs_irq_unmask;1593 pcs->chip.irq_set_wake = pcs_irq_set_wake;1594 1595 if (PCS_QUIRK_HAS_SHARED_IRQ) {1596 int res;1597 1598 res = request_irq(pcs_soc->irq, pcs_irq_handler,1599 IRQF_SHARED | IRQF_NO_SUSPEND |1600 IRQF_NO_THREAD,1601 name, pcs_soc);1602 if (res) {1603 pcs_soc->irq = -1;1604 return res;1605 }1606 } else {1607 irq_set_chained_handler_and_data(pcs_soc->irq,1608 pcs_irq_chain_handler,1609 pcs_soc);1610 }1611 1612 /*1613 * We can use the register offset as the hardirq1614 * number as irq_domain_add_simple maps them lazily.1615 * This way we can easily support more than one1616 * interrupt per function if needed.1617 */1618 num_irqs = pcs->size;1619 1620 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,1621 &pcs_irqdomain_ops,1622 pcs_soc);1623 if (!pcs->domain) {1624 irq_set_chained_handler(pcs_soc->irq, NULL);1625 return -EINVAL;1626 }1627 1628 return 0;1629}1630 1631static int pcs_save_context(struct pcs_device *pcs)1632{1633 int i, mux_bytes;1634 u64 *regsl;1635 u32 *regsw;1636 u16 *regshw;1637 1638 mux_bytes = pcs->width / BITS_PER_BYTE;1639 1640 if (!pcs->saved_vals) {1641 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);1642 if (!pcs->saved_vals)1643 return -ENOMEM;1644 }1645 1646 switch (pcs->width) {1647 case 64:1648 regsl = pcs->saved_vals;1649 for (i = 0; i < pcs->size; i += mux_bytes)1650 *regsl++ = pcs->read(pcs->base + i);1651 break;1652 case 32:1653 regsw = pcs->saved_vals;1654 for (i = 0; i < pcs->size; i += mux_bytes)1655 *regsw++ = pcs->read(pcs->base + i);1656 break;1657 case 16:1658 regshw = pcs->saved_vals;1659 for (i = 0; i < pcs->size; i += mux_bytes)1660 *regshw++ = pcs->read(pcs->base + i);1661 break;1662 }1663 1664 return 0;1665}1666 1667static void pcs_restore_context(struct pcs_device *pcs)1668{1669 int i, mux_bytes;1670 u64 *regsl;1671 u32 *regsw;1672 u16 *regshw;1673 1674 mux_bytes = pcs->width / BITS_PER_BYTE;1675 1676 switch (pcs->width) {1677 case 64:1678 regsl = pcs->saved_vals;1679 for (i = 0; i < pcs->size; i += mux_bytes)1680 pcs->write(*regsl++, pcs->base + i);1681 break;1682 case 32:1683 regsw = pcs->saved_vals;1684 for (i = 0; i < pcs->size; i += mux_bytes)1685 pcs->write(*regsw++, pcs->base + i);1686 break;1687 case 16:1688 regshw = pcs->saved_vals;1689 for (i = 0; i < pcs->size; i += mux_bytes)1690 pcs->write(*regshw++, pcs->base + i);1691 break;1692 }1693}1694 1695static int pinctrl_single_suspend_noirq(struct device *dev)1696{1697 struct pcs_device *pcs = dev_get_drvdata(dev);1698 1699 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {1700 int ret;1701 1702 ret = pcs_save_context(pcs);1703 if (ret < 0)1704 return ret;1705 }1706 1707 return pinctrl_force_sleep(pcs->pctl);1708}1709 1710static int pinctrl_single_resume_noirq(struct device *dev)1711{1712 struct pcs_device *pcs = dev_get_drvdata(dev);1713 1714 if (pcs->flags & PCS_CONTEXT_LOSS_OFF)1715 pcs_restore_context(pcs);1716 1717 return pinctrl_force_default(pcs->pctl);1718}1719 1720static DEFINE_NOIRQ_DEV_PM_OPS(pinctrl_single_pm_ops,1721 pinctrl_single_suspend_noirq,1722 pinctrl_single_resume_noirq);1723 1724/**1725 * pcs_quirk_missing_pinctrl_cells - handle legacy binding1726 * @pcs: pinctrl driver instance1727 * @np: device tree node1728 * @cells: number of cells1729 *1730 * Handle legacy binding with no #pinctrl-cells. This should be1731 * always two pinctrl-single,bit-per-mux and one for others.1732 * At some point we may want to consider removing this.1733 */1734static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,1735 struct device_node *np,1736 int cells)1737{1738 struct property *p;1739 const char *name = "#pinctrl-cells";1740 int error;1741 u32 val;1742 1743 error = of_property_read_u32(np, name, &val);1744 if (!error)1745 return 0;1746 1747 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",1748 name, cells);1749 1750 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);1751 if (!p)1752 return -ENOMEM;1753 1754 p->length = sizeof(__be32);1755 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);1756 if (!p->value)1757 return -ENOMEM;1758 *(__be32 *)p->value = cpu_to_be32(cells);1759 1760 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);1761 if (!p->name)1762 return -ENOMEM;1763 1764 pcs->missing_nr_pinctrl_cells = p;1765 1766#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)1767 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);1768#endif1769 1770 return error;1771}1772 1773static int pcs_probe(struct platform_device *pdev)1774{1775 struct device_node *np = pdev->dev.of_node;1776 struct pcs_pdata *pdata;1777 struct resource *res;1778 struct pcs_device *pcs;1779 const struct pcs_soc_data *soc;1780 int ret;1781 1782 soc = of_device_get_match_data(&pdev->dev);1783 if (WARN_ON(!soc))1784 return -EINVAL;1785 1786 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);1787 if (!pcs)1788 return -ENOMEM;1789 1790 pcs->dev = &pdev->dev;1791 pcs->np = np;1792 raw_spin_lock_init(&pcs->lock);1793 mutex_init(&pcs->mutex);1794 INIT_LIST_HEAD(&pcs->gpiofuncs);1795 pcs->flags = soc->flags;1796 memcpy(&pcs->socdata, soc, sizeof(*soc));1797 1798 ret = of_property_read_u32(np, "pinctrl-single,register-width",1799 &pcs->width);1800 if (ret) {1801 dev_err(pcs->dev, "register width not specified\n");1802 1803 return ret;1804 }1805 1806 ret = of_property_read_u32(np, "pinctrl-single,function-mask",1807 &pcs->fmask);1808 if (!ret) {1809 pcs->fshift = __ffs(pcs->fmask);1810 pcs->fmax = pcs->fmask >> pcs->fshift;1811 } else {1812 /* If mask property doesn't exist, function mux is invalid. */1813 pcs->fmask = 0;1814 pcs->fshift = 0;1815 pcs->fmax = 0;1816 }1817 1818 ret = of_property_read_u32(np, "pinctrl-single,function-off",1819 &pcs->foff);1820 if (ret)1821 pcs->foff = PCS_OFF_DISABLED;1822 1823 pcs->bits_per_mux = of_property_read_bool(np,1824 "pinctrl-single,bit-per-mux");1825 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,1826 pcs->bits_per_mux ? 2 : 1);1827 if (ret) {1828 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");1829 1830 return ret;1831 }1832 1833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);1834 if (!res) {1835 dev_err(pcs->dev, "could not get resource\n");1836 return -ENODEV;1837 }1838 1839 pcs->res = devm_request_mem_region(pcs->dev, res->start,1840 resource_size(res), DRIVER_NAME);1841 if (!pcs->res) {1842 dev_err(pcs->dev, "could not get mem_region\n");1843 return -EBUSY;1844 }1845 1846 pcs->size = resource_size(pcs->res);1847 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);1848 if (!pcs->base) {1849 dev_err(pcs->dev, "could not ioremap\n");1850 return -ENODEV;1851 }1852 1853 platform_set_drvdata(pdev, pcs);1854 1855 switch (pcs->width) {1856 case 8:1857 pcs->read = pcs_readb;1858 pcs->write = pcs_writeb;1859 break;1860 case 16:1861 pcs->read = pcs_readw;1862 pcs->write = pcs_writew;1863 break;1864 case 32:1865 pcs->read = pcs_readl;1866 pcs->write = pcs_writel;1867 break;1868 default:1869 break;1870 }1871 1872 pcs->desc.name = DRIVER_NAME;1873 pcs->desc.pctlops = &pcs_pinctrl_ops;1874 pcs->desc.pmxops = &pcs_pinmux_ops;1875 if (PCS_HAS_PINCONF)1876 pcs->desc.confops = &pcs_pinconf_ops;1877 pcs->desc.owner = THIS_MODULE;1878 1879 ret = pcs_allocate_pin_table(pcs);1880 if (ret < 0)1881 goto free;1882 1883 ret = devm_pinctrl_register_and_init(pcs->dev, &pcs->desc, pcs, &pcs->pctl);1884 if (ret) {1885 dev_err(pcs->dev, "could not register single pinctrl driver\n");1886 goto free;1887 }1888 1889 ret = pcs_add_gpio_func(np, pcs);1890 if (ret < 0)1891 goto free;1892 1893 pcs->socdata.irq = irq_of_parse_and_map(np, 0);1894 if (pcs->socdata.irq)1895 pcs->flags |= PCS_FEAT_IRQ;1896 1897 /* We still need auxdata for some omaps for PRM interrupts */1898 pdata = dev_get_platdata(&pdev->dev);1899 if (pdata) {1900 if (pdata->rearm)1901 pcs->socdata.rearm = pdata->rearm;1902 if (pdata->irq) {1903 pcs->socdata.irq = pdata->irq;1904 pcs->flags |= PCS_FEAT_IRQ;1905 }1906 }1907 1908 if (PCS_HAS_IRQ) {1909 ret = pcs_irq_init_chained_handler(pcs, np);1910 if (ret < 0)1911 dev_warn(pcs->dev, "initialized with no interrupts\n");1912 }1913 1914 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);1915 1916 ret = pinctrl_enable(pcs->pctl);1917 if (ret)1918 goto free;1919 1920 return 0;1921free:1922 pcs_free_resources(pcs);1923 1924 return ret;1925}1926 1927static void pcs_remove(struct platform_device *pdev)1928{1929 struct pcs_device *pcs = platform_get_drvdata(pdev);1930 1931 pcs_free_resources(pcs);1932}1933 1934static const struct pcs_soc_data pinctrl_single_omap_wkup = {1935 .flags = PCS_QUIRK_SHARED_IRQ,1936 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */1937 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */1938};1939 1940static const struct pcs_soc_data pinctrl_single_dra7 = {1941 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */1942 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */1943};1944 1945static const struct pcs_soc_data pinctrl_single_am437x = {1946 .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,1947 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */1948 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */1949};1950 1951static const struct pcs_soc_data pinctrl_single_am654 = {1952 .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,1953 .irq_enable_mask = (1 << 29), /* WKUP_EN */1954 .irq_status_mask = (1 << 30), /* WKUP_EVT */1955};1956 1957static const struct pcs_soc_data pinctrl_single_j7200 = {1958 .flags = PCS_CONTEXT_LOSS_OFF,1959};1960 1961static const struct pcs_soc_data pinctrl_single = {1962};1963 1964static const struct pcs_soc_data pinconf_single = {1965 .flags = PCS_FEAT_PINCONF,1966};1967 1968static const struct of_device_id pcs_of_match[] = {1969 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },1970 { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },1971 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },1972 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },1973 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },1974 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },1975 { .compatible = "ti,j7200-padconf", .data = &pinctrl_single_j7200 },1976 { .compatible = "pinctrl-single", .data = &pinctrl_single },1977 { .compatible = "pinconf-single", .data = &pinconf_single },1978 { },1979};1980MODULE_DEVICE_TABLE(of, pcs_of_match);1981 1982static struct platform_driver pcs_driver = {1983 .probe = pcs_probe,1984 .remove_new = pcs_remove,1985 .driver = {1986 .name = DRIVER_NAME,1987 .of_match_table = pcs_of_match,1988 .pm = pm_sleep_ptr(&pinctrl_single_pm_ops),1989 },1990};1991 1992module_platform_driver(pcs_driver);1993 1994MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");1995MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");1996MODULE_LICENSE("GPL v2");1997