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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.4 * Authors:5 * Srinivas Kandagatla <srinivas.kandagatla@st.com>6 */7 8#include <linux/err.h>9#include <linux/gpio/driver.h>10#include <linux/init.h>11#include <linux/io.h>12#include <linux/mfd/syscon.h>13#include <linux/module.h>14#include <linux/of.h>15#include <linux/of_address.h>16#include <linux/of_irq.h>17#include <linux/platform_device.h>18#include <linux/regmap.h>19#include <linux/seq_file.h>20#include <linux/slab.h>21#include <linux/string_helpers.h>22 23#include <linux/pinctrl/consumer.h>24#include <linux/pinctrl/pinconf.h>25#include <linux/pinctrl/pinctrl.h>26#include <linux/pinctrl/pinmux.h>27 28#include "core.h"29 30/* PIO Block registers */31/* PIO output */32#define REG_PIO_POUT 0x0033/* Set bits of POUT */34#define REG_PIO_SET_POUT 0x0435/* Clear bits of POUT */36#define REG_PIO_CLR_POUT 0x0837/* PIO input */38#define REG_PIO_PIN 0x1039/* PIO configuration */40#define REG_PIO_PC(n) (0x20 + (n) * 0x10)41/* Set bits of PC[2:0] */42#define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)43/* Clear bits of PC[2:0] */44#define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)45/* PIO input comparison */46#define REG_PIO_PCOMP 0x5047/* Set bits of PCOMP */48#define REG_PIO_SET_PCOMP 0x5449/* Clear bits of PCOMP */50#define REG_PIO_CLR_PCOMP 0x5851/* PIO input comparison mask */52#define REG_PIO_PMASK 0x6053/* Set bits of PMASK */54#define REG_PIO_SET_PMASK 0x6455/* Clear bits of PMASK */56#define REG_PIO_CLR_PMASK 0x6857 58#define ST_GPIO_DIRECTION_BIDIR 0x159#define ST_GPIO_DIRECTION_OUT 0x260#define ST_GPIO_DIRECTION_IN 0x461 62/*63 * Packed style retime configuration.64 * There are two registers cfg0 and cfg1 in this style for each bank.65 * Each field in this register is 8 bit corresponding to 8 pins in the bank.66 */67#define RT_P_CFGS_PER_BANK 268#define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)69#define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)70#define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)71#define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)72#define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)73#define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)74#define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)75 76/*77 * Dedicated style retime Configuration register78 * each register is dedicated per pin.79 */80#define RT_D_CFGS_PER_BANK 881#define RT_D_CFG_CLK_SHIFT 082#define RT_D_CFG_CLK_MASK (0x3 << 0)83#define RT_D_CFG_CLKNOTDATA_SHIFT 284#define RT_D_CFG_CLKNOTDATA_MASK BIT(2)85#define RT_D_CFG_DELAY_SHIFT 386#define RT_D_CFG_DELAY_MASK (0xf << 3)87#define RT_D_CFG_DELAY_INNOTOUT_SHIFT 788#define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)89#define RT_D_CFG_DOUBLE_EDGE_SHIFT 890#define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)91#define RT_D_CFG_INVERTCLK_SHIFT 992#define RT_D_CFG_INVERTCLK_MASK BIT(9)93#define RT_D_CFG_RETIME_SHIFT 1094#define RT_D_CFG_RETIME_MASK BIT(10)95 96/*97 * Pinconf is represented in an opaque unsigned long variable.98 * Below is the bit allocation details for each possible configuration.99 * All the bit fields can be encapsulated into four variables100 * (direction, retime-type, retime-clk, retime-delay)101 *102 * +----------------+103 *[31:28]| reserved-3 |104 * +----------------+-------------105 *[27] | oe | |106 * +----------------+ v107 *[26] | pu | [Direction ]108 * +----------------+ ^109 *[25] | od | |110 * +----------------+-------------111 *[24] | reserved-2 |112 * +----------------+-------------113 *[23] | retime | |114 * +----------------+ |115 *[22] | retime-invclk | |116 * +----------------+ v117 *[21] |retime-clknotdat| [Retime-type ]118 * +----------------+ ^119 *[20] | retime-de | |120 * +----------------+-------------121 *[19:18]| retime-clk |------>[Retime-Clk ]122 * +----------------+123 *[17:16]| reserved-1 |124 * +----------------+125 *[15..0]| retime-delay |------>[Retime Delay]126 * +----------------+127 */128 129#define ST_PINCONF_UNPACK(conf, param)\130 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \131 & ST_PINCONF_ ##param ##_MASK)132 133#define ST_PINCONF_PACK(conf, val, param) (conf |=\134 ((val & ST_PINCONF_ ##param ##_MASK) << \135 ST_PINCONF_ ##param ##_SHIFT))136 137/* Output enable */138#define ST_PINCONF_OE_MASK 0x1139#define ST_PINCONF_OE_SHIFT 27140#define ST_PINCONF_OE BIT(27)141#define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)142#define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)143 144/* Pull Up */145#define ST_PINCONF_PU_MASK 0x1146#define ST_PINCONF_PU_SHIFT 26147#define ST_PINCONF_PU BIT(26)148#define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)149#define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)150 151/* Open Drain */152#define ST_PINCONF_OD_MASK 0x1153#define ST_PINCONF_OD_SHIFT 25154#define ST_PINCONF_OD BIT(25)155#define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)156#define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)157 158#define ST_PINCONF_RT_MASK 0x1159#define ST_PINCONF_RT_SHIFT 23160#define ST_PINCONF_RT BIT(23)161#define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)162#define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)163 164#define ST_PINCONF_RT_INVERTCLK_MASK 0x1165#define ST_PINCONF_RT_INVERTCLK_SHIFT 22166#define ST_PINCONF_RT_INVERTCLK BIT(22)167#define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \168 ST_PINCONF_UNPACK(conf, RT_INVERTCLK)169#define ST_PINCONF_PACK_RT_INVERTCLK(conf) \170 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)171 172#define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1173#define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21174#define ST_PINCONF_RT_CLKNOTDATA BIT(21)175#define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \176 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)177#define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \178 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)179 180#define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1181#define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20182#define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)183#define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \184 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)185#define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \186 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)187 188#define ST_PINCONF_RT_CLK_MASK 0x3189#define ST_PINCONF_RT_CLK_SHIFT 18190#define ST_PINCONF_RT_CLK BIT(18)191#define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)192#define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)193 194/* RETIME_DELAY in Pico Secs */195#define ST_PINCONF_RT_DELAY_MASK 0xffff196#define ST_PINCONF_RT_DELAY_SHIFT 0197#define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)198#define ST_PINCONF_PACK_RT_DELAY(conf, val) \199 ST_PINCONF_PACK(conf, val, RT_DELAY)200 201#define ST_GPIO_PINS_PER_BANK (8)202#define OF_GPIO_ARGS_MIN (4)203#define OF_RT_ARGS_MIN (2)204 205#define gpio_range_to_bank(chip) \206 container_of(chip, struct st_gpio_bank, range)207 208#define pc_to_bank(pc) \209 container_of(pc, struct st_gpio_bank, pc)210 211enum st_retime_style {212 st_retime_style_none,213 st_retime_style_packed,214 st_retime_style_dedicated,215};216 217struct st_retime_dedicated {218 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];219};220 221struct st_retime_packed {222 struct regmap_field *clk1notclk0;223 struct regmap_field *delay_0;224 struct regmap_field *delay_1;225 struct regmap_field *invertclk;226 struct regmap_field *retime;227 struct regmap_field *clknotdata;228 struct regmap_field *double_edge;229};230 231struct st_pio_control {232 u32 rt_pin_mask;233 struct regmap_field *alt, *oe, *pu, *od;234 /* retiming */235 union {236 struct st_retime_packed rt_p;237 struct st_retime_dedicated rt_d;238 } rt;239};240 241struct st_pctl_data {242 const enum st_retime_style rt_style;243 const unsigned int *input_delays;244 const int ninput_delays;245 const unsigned int *output_delays;246 const int noutput_delays;247 /* register offset information */248 const int alt, oe, pu, od, rt;249};250 251struct st_pinconf {252 int pin;253 const char *name;254 unsigned long config;255 int altfunc;256};257 258struct st_pmx_func {259 const char *name;260 const char **groups;261 unsigned ngroups;262};263 264struct st_pctl_group {265 const char *name;266 unsigned int *pins;267 unsigned npins;268 struct st_pinconf *pin_conf;269};270 271/*272 * Edge triggers are not supported at hardware level, it is supported by273 * software by exploiting the level trigger support in hardware.274 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration275 * of each gpio pin in a GPIO bank.276 *277 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of278 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.279 *280 * bit allocation per pin is:281 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]282 * --------------------------------------------------------283 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |284 * --------------------------------------------------------285 *286 * A pin can have one of following the values in its edge configuration field.287 *288 * ------- ----------------------------289 * [0-3] - Description290 * ------- ----------------------------291 * 0000 - No edge IRQ.292 * 0001 - Falling edge IRQ.293 * 0010 - Rising edge IRQ.294 * 0011 - Rising and Falling edge IRQ.295 * ------- ----------------------------296 */297 298#define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4299#define ST_IRQ_EDGE_MASK 0xf300#define ST_IRQ_EDGE_FALLING BIT(0)301#define ST_IRQ_EDGE_RISING BIT(1)302#define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))303 304#define ST_IRQ_RISING_EDGE_CONF(pin) \305 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))306 307#define ST_IRQ_FALLING_EDGE_CONF(pin) \308 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))309 310#define ST_IRQ_BOTH_EDGE_CONF(pin) \311 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))312 313#define ST_IRQ_EDGE_CONF(conf, pin) \314 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)315 316struct st_gpio_bank {317 struct gpio_chip gpio_chip;318 struct pinctrl_gpio_range range;319 void __iomem *base;320 struct st_pio_control pc;321 unsigned long irq_edge_conf;322 spinlock_t lock;323};324 325struct st_pinctrl {326 struct device *dev;327 struct pinctrl_dev *pctl;328 struct st_gpio_bank *banks;329 int nbanks;330 struct st_pmx_func *functions;331 int nfunctions;332 struct st_pctl_group *groups;333 int ngroups;334 struct regmap *regmap;335 const struct st_pctl_data *data;336 void __iomem *irqmux_base;337};338 339/* SOC specific data */340 341static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,342 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };343 344static const struct st_pctl_data stih407_data = {345 .rt_style = st_retime_style_dedicated,346 .input_delays = stih407_delays,347 .ninput_delays = ARRAY_SIZE(stih407_delays),348 .output_delays = stih407_delays,349 .noutput_delays = ARRAY_SIZE(stih407_delays),350 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,351};352 353static const struct st_pctl_data stih407_flashdata = {354 .rt_style = st_retime_style_none,355 .input_delays = stih407_delays,356 .ninput_delays = ARRAY_SIZE(stih407_delays),357 .output_delays = stih407_delays,358 .noutput_delays = ARRAY_SIZE(stih407_delays),359 .alt = 0,360 .oe = -1, /* Not Available */361 .pu = -1, /* Not Available */362 .od = 60,363 .rt = 100,364};365 366static struct st_pio_control *st_get_pio_control(367 struct pinctrl_dev *pctldev, int pin)368{369 struct pinctrl_gpio_range *range =370 pinctrl_find_gpio_range_from_pin(pctldev, pin);371 struct st_gpio_bank *bank = gpio_range_to_bank(range);372 373 return &bank->pc;374}375 376/* Low level functions.. */377static inline int st_gpio_bank(int gpio)378{379 return gpio/ST_GPIO_PINS_PER_BANK;380}381 382static inline int st_gpio_pin(int gpio)383{384 return gpio%ST_GPIO_PINS_PER_BANK;385}386 387static void st_pinconf_set_config(struct st_pio_control *pc,388 int pin, unsigned long config)389{390 struct regmap_field *output_enable = pc->oe;391 struct regmap_field *pull_up = pc->pu;392 struct regmap_field *open_drain = pc->od;393 unsigned int oe_value, pu_value, od_value;394 unsigned long mask = BIT(pin);395 396 if (output_enable) {397 regmap_field_read(output_enable, &oe_value);398 oe_value &= ~mask;399 if (config & ST_PINCONF_OE)400 oe_value |= mask;401 regmap_field_write(output_enable, oe_value);402 }403 404 if (pull_up) {405 regmap_field_read(pull_up, &pu_value);406 pu_value &= ~mask;407 if (config & ST_PINCONF_PU)408 pu_value |= mask;409 regmap_field_write(pull_up, pu_value);410 }411 412 if (open_drain) {413 regmap_field_read(open_drain, &od_value);414 od_value &= ~mask;415 if (config & ST_PINCONF_OD)416 od_value |= mask;417 regmap_field_write(open_drain, od_value);418 }419}420 421static void st_pctl_set_function(struct st_pio_control *pc,422 int pin_id, int function)423{424 struct regmap_field *alt = pc->alt;425 unsigned int val;426 int pin = st_gpio_pin(pin_id);427 int offset = pin * 4;428 429 if (!alt)430 return;431 432 regmap_field_read(alt, &val);433 val &= ~(0xf << offset);434 val |= function << offset;435 regmap_field_write(alt, val);436}437 438static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)439{440 struct regmap_field *alt = pc->alt;441 unsigned int val;442 int offset = pin * 4;443 444 if (!alt)445 return 0;446 447 regmap_field_read(alt, &val);448 449 return (val >> offset) & 0xf;450}451 452static unsigned long st_pinconf_delay_to_bit(unsigned int delay,453 const struct st_pctl_data *data, unsigned long config)454{455 const unsigned int *delay_times;456 int num_delay_times, i, closest_index = -1;457 unsigned int closest_divergence = UINT_MAX;458 459 if (ST_PINCONF_UNPACK_OE(config)) {460 delay_times = data->output_delays;461 num_delay_times = data->noutput_delays;462 } else {463 delay_times = data->input_delays;464 num_delay_times = data->ninput_delays;465 }466 467 for (i = 0; i < num_delay_times; i++) {468 unsigned int divergence = abs(delay - delay_times[i]);469 470 if (divergence == 0)471 return i;472 473 if (divergence < closest_divergence) {474 closest_divergence = divergence;475 closest_index = i;476 }477 }478 479 pr_warn("Attempt to set delay %d, closest available %d\n",480 delay, delay_times[closest_index]);481 482 return closest_index;483}484 485static unsigned long st_pinconf_bit_to_delay(unsigned int index,486 const struct st_pctl_data *data, unsigned long output)487{488 const unsigned int *delay_times;489 int num_delay_times;490 491 if (output) {492 delay_times = data->output_delays;493 num_delay_times = data->noutput_delays;494 } else {495 delay_times = data->input_delays;496 num_delay_times = data->ninput_delays;497 }498 499 if (index < num_delay_times) {500 return delay_times[index];501 } else {502 pr_warn("Delay not found in/out delay list\n");503 return 0;504 }505}506 507static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,508 int enable, int pin)509{510 unsigned int val = 0;511 512 regmap_field_read(field, &val);513 if (enable)514 val |= BIT(pin);515 else516 val &= ~BIT(pin);517 regmap_field_write(field, val);518}519 520static void st_pinconf_set_retime_packed(struct st_pinctrl *info,521 struct st_pio_control *pc, unsigned long config, int pin)522{523 const struct st_pctl_data *data = info->data;524 struct st_retime_packed *rt_p = &pc->rt.rt_p;525 unsigned int delay;526 527 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,528 ST_PINCONF_UNPACK_RT_CLK(config), pin);529 530 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,531 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);532 533 st_regmap_field_bit_set_clear_pin(rt_p->double_edge,534 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);535 536 st_regmap_field_bit_set_clear_pin(rt_p->invertclk,537 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);538 539 st_regmap_field_bit_set_clear_pin(rt_p->retime,540 ST_PINCONF_UNPACK_RT(config), pin);541 542 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),543 data, config);544 /* 2 bit delay, lsb */545 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);546 /* 2 bit delay, msb */547 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);548}549 550static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,551 struct st_pio_control *pc, unsigned long config, int pin)552{553 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;554 int clk = ST_PINCONF_UNPACK_RT_CLK(config);555 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);556 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);557 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config);558 int retime = ST_PINCONF_UNPACK_RT(config);559 560 unsigned long delay = st_pinconf_delay_to_bit(561 ST_PINCONF_UNPACK_RT_DELAY(config),562 info->data, config);563 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;564 565 unsigned long retime_config =566 ((clk) << RT_D_CFG_CLK_SHIFT) |567 ((delay) << RT_D_CFG_DELAY_SHIFT) |568 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |569 ((retime) << RT_D_CFG_RETIME_SHIFT) |570 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |571 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |572 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);573 574 regmap_field_write(rt_d->rt[pin], retime_config);575}576 577static void st_pinconf_get_direction(struct st_pio_control *pc,578 int pin, unsigned long *config)579{580 unsigned int oe_value, pu_value, od_value;581 582 if (pc->oe) {583 regmap_field_read(pc->oe, &oe_value);584 if (oe_value & BIT(pin))585 ST_PINCONF_PACK_OE(*config);586 }587 588 if (pc->pu) {589 regmap_field_read(pc->pu, &pu_value);590 if (pu_value & BIT(pin))591 ST_PINCONF_PACK_PU(*config);592 }593 594 if (pc->od) {595 regmap_field_read(pc->od, &od_value);596 if (od_value & BIT(pin))597 ST_PINCONF_PACK_OD(*config);598 }599}600 601static int st_pinconf_get_retime_packed(struct st_pinctrl *info,602 struct st_pio_control *pc, int pin, unsigned long *config)603{604 const struct st_pctl_data *data = info->data;605 struct st_retime_packed *rt_p = &pc->rt.rt_p;606 unsigned int delay_bits, delay, delay0, delay1, val;607 int output = ST_PINCONF_UNPACK_OE(*config);608 609 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))610 ST_PINCONF_PACK_RT(*config);611 612 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))613 ST_PINCONF_PACK_RT_CLK(*config, 1);614 615 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))616 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);617 618 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))619 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);620 621 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))622 ST_PINCONF_PACK_RT_INVERTCLK(*config);623 624 regmap_field_read(rt_p->delay_0, &delay0);625 regmap_field_read(rt_p->delay_1, &delay1);626 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |627 (((delay0 & BIT(pin)) ? 1 : 0));628 delay = st_pinconf_bit_to_delay(delay_bits, data, output);629 ST_PINCONF_PACK_RT_DELAY(*config, delay);630 631 return 0;632}633 634static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,635 struct st_pio_control *pc, int pin, unsigned long *config)636{637 unsigned int value;638 unsigned long delay_bits, delay, rt_clk;639 int output = ST_PINCONF_UNPACK_OE(*config);640 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;641 642 regmap_field_read(rt_d->rt[pin], &value);643 644 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;645 ST_PINCONF_PACK_RT_CLK(*config, rt_clk);646 647 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;648 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output);649 ST_PINCONF_PACK_RT_DELAY(*config, delay);650 651 if (value & RT_D_CFG_CLKNOTDATA_MASK)652 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);653 654 if (value & RT_D_CFG_DOUBLE_EDGE_MASK)655 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);656 657 if (value & RT_D_CFG_INVERTCLK_MASK)658 ST_PINCONF_PACK_RT_INVERTCLK(*config);659 660 if (value & RT_D_CFG_RETIME_MASK)661 ST_PINCONF_PACK_RT(*config);662 663 return 0;664}665 666/* GPIO related functions */667 668static inline void __st_gpio_set(struct st_gpio_bank *bank,669 unsigned offset, int value)670{671 if (value)672 writel(BIT(offset), bank->base + REG_PIO_SET_POUT);673 else674 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);675}676 677static void st_gpio_direction(struct st_gpio_bank *bank,678 unsigned int gpio, unsigned int direction)679{680 int offset = st_gpio_pin(gpio);681 int i = 0;682 /**683 * There are three configuration registers (PIOn_PC0, PIOn_PC1684 * and PIOn_PC2) for each port. These are used to configure the685 * PIO port pins. Each pin can be configured as an input, output,686 * bidirectional, or alternative function pin. Three bits, one bit687 * from each of the three registers, configure the corresponding bit of688 * the port. Valid bit settings is:689 *690 * PC2 PC1 PC0 Direction.691 * 0 0 0 [Input Weak pull-up]692 * 0 0 or 1 1 [Bidirection]693 * 0 1 0 [Output]694 * 1 0 0 [Input]695 *696 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits697 * individually.698 */699 for (i = 0; i <= 2; i++) {700 if (direction & BIT(i))701 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));702 else703 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));704 }705}706 707static int st_gpio_get(struct gpio_chip *chip, unsigned offset)708{709 struct st_gpio_bank *bank = gpiochip_get_data(chip);710 711 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));712}713 714static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)715{716 struct st_gpio_bank *bank = gpiochip_get_data(chip);717 __st_gpio_set(bank, offset, value);718}719 720static int st_gpio_direction_output(struct gpio_chip *chip,721 unsigned offset, int value)722{723 struct st_gpio_bank *bank = gpiochip_get_data(chip);724 725 __st_gpio_set(bank, offset, value);726 727 return pinctrl_gpio_direction_output(chip, offset);728}729 730static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)731{732 struct st_gpio_bank *bank = gpiochip_get_data(chip);733 struct st_pio_control pc = bank->pc;734 unsigned long config;735 unsigned int direction = 0;736 unsigned int function;737 unsigned int value;738 int i = 0;739 740 /* Alternate function direction is handled by Pinctrl */741 function = st_pctl_get_pin_function(&pc, offset);742 if (function) {743 st_pinconf_get_direction(&pc, offset, &config);744 if (ST_PINCONF_UNPACK_OE(config))745 return GPIO_LINE_DIRECTION_OUT;746 747 return GPIO_LINE_DIRECTION_IN;748 }749 750 /*751 * GPIO direction is handled differently752 * - See st_gpio_direction() above for an explanation753 */754 for (i = 0; i <= 2; i++) {755 value = readl(bank->base + REG_PIO_PC(i));756 direction |= ((value >> offset) & 0x1) << i;757 }758 759 if (direction == ST_GPIO_DIRECTION_IN)760 return GPIO_LINE_DIRECTION_IN;761 762 return GPIO_LINE_DIRECTION_OUT;763}764 765/* Pinctrl Groups */766static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)767{768 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);769 770 return info->ngroups;771}772 773static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,774 unsigned selector)775{776 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);777 778 return info->groups[selector].name;779}780 781static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,782 unsigned selector, const unsigned **pins, unsigned *npins)783{784 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);785 786 if (selector >= info->ngroups)787 return -EINVAL;788 789 *pins = info->groups[selector].pins;790 *npins = info->groups[selector].npins;791 792 return 0;793}794 795static inline const struct st_pctl_group *st_pctl_find_group_by_name(796 const struct st_pinctrl *info, const char *name)797{798 int i;799 800 for (i = 0; i < info->ngroups; i++) {801 if (!strcmp(info->groups[i].name, name))802 return &info->groups[i];803 }804 805 return NULL;806}807 808static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,809 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)810{811 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);812 const struct st_pctl_group *grp;813 struct device *dev = info->dev;814 struct pinctrl_map *new_map;815 struct device_node *parent;816 int map_num, i;817 818 grp = st_pctl_find_group_by_name(info, np->name);819 if (!grp) {820 dev_err(dev, "unable to find group for node %pOFn\n", np);821 return -EINVAL;822 }823 824 map_num = grp->npins + 1;825 new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL);826 if (!new_map)827 return -ENOMEM;828 829 parent = of_get_parent(np);830 if (!parent) {831 devm_kfree(dev, new_map);832 return -EINVAL;833 }834 835 *map = new_map;836 *num_maps = map_num;837 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;838 new_map[0].data.mux.function = parent->name;839 new_map[0].data.mux.group = np->name;840 of_node_put(parent);841 842 /* create config map per pin */843 new_map++;844 for (i = 0; i < grp->npins; i++) {845 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;846 new_map[i].data.configs.group_or_pin =847 pin_get_name(pctldev, grp->pins[i]);848 new_map[i].data.configs.configs = &grp->pin_conf[i].config;849 new_map[i].data.configs.num_configs = 1;850 }851 dev_info(dev, "maps: function %s group %s num %d\n",852 (*map)->data.mux.function, grp->name, map_num);853 854 return 0;855}856 857static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,858 struct pinctrl_map *map, unsigned num_maps)859{860}861 862static const struct pinctrl_ops st_pctlops = {863 .get_groups_count = st_pctl_get_groups_count,864 .get_group_pins = st_pctl_get_group_pins,865 .get_group_name = st_pctl_get_group_name,866 .dt_node_to_map = st_pctl_dt_node_to_map,867 .dt_free_map = st_pctl_dt_free_map,868};869 870/* Pinmux */871static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)872{873 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);874 875 return info->nfunctions;876}877 878static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,879 unsigned selector)880{881 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);882 883 return info->functions[selector].name;884}885 886static int st_pmx_get_groups(struct pinctrl_dev *pctldev,887 unsigned selector, const char * const **grps, unsigned * const ngrps)888{889 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);890 *grps = info->functions[selector].groups;891 *ngrps = info->functions[selector].ngroups;892 893 return 0;894}895 896static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,897 unsigned group)898{899 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);900 struct st_pinconf *conf = info->groups[group].pin_conf;901 struct st_pio_control *pc;902 int i;903 904 for (i = 0; i < info->groups[group].npins; i++) {905 pc = st_get_pio_control(pctldev, conf[i].pin);906 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);907 }908 909 return 0;910}911 912static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,913 struct pinctrl_gpio_range *range, unsigned gpio,914 bool input)915{916 struct st_gpio_bank *bank = gpio_range_to_bank(range);917 /*918 * When a PIO bank is used in its primary function mode (altfunc = 0)919 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)920 * for the primary PIO functions are driven by the related PIO block921 */922 st_pctl_set_function(&bank->pc, gpio, 0);923 st_gpio_direction(bank, gpio, input ?924 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);925 926 return 0;927}928 929static const struct pinmux_ops st_pmxops = {930 .get_functions_count = st_pmx_get_funcs_count,931 .get_function_name = st_pmx_get_fname,932 .get_function_groups = st_pmx_get_groups,933 .set_mux = st_pmx_set_mux,934 .gpio_set_direction = st_pmx_set_gpio_direction,935 .strict = true,936};937 938/* Pinconf */939static void st_pinconf_get_retime(struct st_pinctrl *info,940 struct st_pio_control *pc, int pin, unsigned long *config)941{942 if (info->data->rt_style == st_retime_style_packed)943 st_pinconf_get_retime_packed(info, pc, pin, config);944 else if (info->data->rt_style == st_retime_style_dedicated)945 if ((BIT(pin) & pc->rt_pin_mask))946 st_pinconf_get_retime_dedicated(info, pc,947 pin, config);948}949 950static void st_pinconf_set_retime(struct st_pinctrl *info,951 struct st_pio_control *pc, int pin, unsigned long config)952{953 if (info->data->rt_style == st_retime_style_packed)954 st_pinconf_set_retime_packed(info, pc, config, pin);955 else if (info->data->rt_style == st_retime_style_dedicated)956 if ((BIT(pin) & pc->rt_pin_mask))957 st_pinconf_set_retime_dedicated(info, pc,958 config, pin);959}960 961static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,962 unsigned long *configs, unsigned num_configs)963{964 int pin = st_gpio_pin(pin_id);965 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);966 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);967 int i;968 969 for (i = 0; i < num_configs; i++) {970 st_pinconf_set_config(pc, pin, configs[i]);971 st_pinconf_set_retime(info, pc, pin, configs[i]);972 } /* for each config */973 974 return 0;975}976 977static int st_pinconf_get(struct pinctrl_dev *pctldev,978 unsigned pin_id, unsigned long *config)979{980 int pin = st_gpio_pin(pin_id);981 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);982 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);983 984 *config = 0;985 st_pinconf_get_direction(pc, pin, config);986 st_pinconf_get_retime(info, pc, pin, config);987 988 return 0;989}990 991static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,992 struct seq_file *s, unsigned pin_id)993{994 struct st_pio_control *pc;995 unsigned long config;996 unsigned int function;997 int offset = st_gpio_pin(pin_id);998 char f[16];999 int oe;1000 1001 mutex_unlock(&pctldev->mutex);1002 pc = st_get_pio_control(pctldev, pin_id);1003 st_pinconf_get(pctldev, pin_id, &config);1004 mutex_lock(&pctldev->mutex);1005 1006 function = st_pctl_get_pin_function(pc, offset);1007 if (function)1008 snprintf(f, 10, "Alt Fn %u", function);1009 else1010 snprintf(f, 5, "GPIO");1011 1012 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset);1013 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"1014 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"1015 "de:%ld,rt-clk:%ld,rt-delay:%ld]",1016 (oe == GPIO_LINE_DIRECTION_OUT),1017 ST_PINCONF_UNPACK_PU(config),1018 ST_PINCONF_UNPACK_OD(config),1019 f,1020 ST_PINCONF_UNPACK_RT(config),1021 ST_PINCONF_UNPACK_RT_INVERTCLK(config),1022 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),1023 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),1024 ST_PINCONF_UNPACK_RT_CLK(config),1025 ST_PINCONF_UNPACK_RT_DELAY(config));1026}1027 1028static const struct pinconf_ops st_confops = {1029 .pin_config_get = st_pinconf_get,1030 .pin_config_set = st_pinconf_set,1031 .pin_config_dbg_show = st_pinconf_dbg_show,1032};1033 1034static void st_pctl_dt_child_count(struct st_pinctrl *info,1035 struct device_node *np)1036{1037 struct device_node *child;1038 for_each_child_of_node(np, child) {1039 if (of_property_read_bool(child, "gpio-controller")) {1040 info->nbanks++;1041 } else {1042 info->nfunctions++;1043 info->ngroups += of_get_child_count(child);1044 }1045 }1046}1047 1048static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,1049 int bank, struct st_pio_control *pc)1050{1051 struct device *dev = info->dev;1052 struct regmap *rm = info->regmap;1053 const struct st_pctl_data *data = info->data;1054 /* 2 registers per bank */1055 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;1056 struct st_retime_packed *rt_p = &pc->rt.rt_p;1057 /* cfg0 */1058 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);1059 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);1060 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);1061 /* cfg1 */1062 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);1063 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);1064 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);1065 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);1066 1067 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);1068 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0);1069 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);1070 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);1071 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);1072 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);1073 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);1074 1075 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||1076 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||1077 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||1078 IS_ERR(rt_p->double_edge))1079 return -EINVAL;1080 1081 return 0;1082}1083 1084static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,1085 int bank, struct st_pio_control *pc)1086{1087 struct device *dev = info->dev;1088 struct regmap *rm = info->regmap;1089 const struct st_pctl_data *data = info->data;1090 /* 8 registers per bank */1091 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;1092 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;1093 unsigned int j;1094 u32 pin_mask = pc->rt_pin_mask;1095 1096 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {1097 if (BIT(j) & pin_mask) {1098 struct reg_field reg = REG_FIELD(reg_offset, 0, 31);1099 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);1100 if (IS_ERR(rt_d->rt[j]))1101 return -EINVAL;1102 reg_offset += 4;1103 }1104 }1105 return 0;1106}1107 1108static int st_pctl_dt_setup_retime(struct st_pinctrl *info,1109 int bank, struct st_pio_control *pc)1110{1111 const struct st_pctl_data *data = info->data;1112 if (data->rt_style == st_retime_style_packed)1113 return st_pctl_dt_setup_retime_packed(info, bank, pc);1114 else if (data->rt_style == st_retime_style_dedicated)1115 return st_pctl_dt_setup_retime_dedicated(info, bank, pc);1116 1117 return -EINVAL;1118}1119 1120 1121static struct regmap_field *st_pc_get_value(struct device *dev,1122 struct regmap *regmap, int bank,1123 int data, int lsb, int msb)1124{1125 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);1126 1127 if (data < 0)1128 return NULL;1129 1130 return devm_regmap_field_alloc(dev, regmap, reg);1131}1132 1133static void st_parse_syscfgs(struct st_pinctrl *info, int bank,1134 struct device_node *np)1135{1136 const struct st_pctl_data *data = info->data;1137 /**1138 * For a given shared register like OE/PU/OD, there are 8 bits per bank1139 * 0:7 belongs to bank0, 8:15 belongs to bank1 ...1140 * So each register is shared across 4 banks.1141 */1142 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;1143 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;1144 struct st_pio_control *pc = &info->banks[bank].pc;1145 struct device *dev = info->dev;1146 struct regmap *regmap = info->regmap;1147 1148 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);1149 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);1150 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);1151 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);1152 1153 /* retime avaiable for all pins by default */1154 pc->rt_pin_mask = 0xff;1155 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);1156 st_pctl_dt_setup_retime(info, bank, pc);1157 1158 return;1159}1160 1161static int st_pctl_dt_calculate_pin(struct st_pinctrl *info,1162 phandle bank, unsigned int offset)1163{1164 struct device_node *np;1165 struct gpio_chip *chip;1166 int retval = -EINVAL;1167 int i;1168 1169 np = of_find_node_by_phandle(bank);1170 if (!np)1171 return -EINVAL;1172 1173 for (i = 0; i < info->nbanks; i++) {1174 chip = &info->banks[i].gpio_chip;1175 if (chip->fwnode == of_fwnode_handle(np)) {1176 if (offset < chip->ngpio)1177 retval = chip->base + offset;1178 break;1179 }1180 }1181 1182 of_node_put(np);1183 return retval;1184}1185 1186/*1187 * Each pin is represented in of the below forms.1188 * <bank offset mux direction rt_type rt_delay rt_clk>1189 */1190static int st_pctl_dt_parse_groups(struct device_node *np,1191 struct st_pctl_group *grp, struct st_pinctrl *info, int idx)1192{1193 /* bank pad direction val altfunction */1194 const __be32 *list;1195 struct property *pp;1196 struct device *dev = info->dev;1197 struct st_pinconf *conf;1198 struct device_node *pins __free(device_node) = NULL;1199 phandle bank;1200 unsigned int offset;1201 int i = 0, npins = 0, nr_props;1202 1203 pins = of_get_child_by_name(np, "st,pins");1204 if (!pins)1205 return -ENODATA;1206 1207 for_each_property_of_node(pins, pp) {1208 /* Skip those we do not want to proceed */1209 if (!strcmp(pp->name, "name"))1210 continue;1211 1212 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {1213 npins++;1214 } else {1215 pr_warn("Invalid st,pins in %pOFn node\n", np);1216 return -EINVAL;1217 }1218 }1219 1220 grp->npins = npins;1221 grp->name = np->name;1222 grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL);1223 grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL);1224 1225 if (!grp->pins || !grp->pin_conf)1226 return -ENOMEM;1227 1228 /* <bank offset mux direction rt_type rt_delay rt_clk> */1229 for_each_property_of_node(pins, pp) {1230 if (!strcmp(pp->name, "name"))1231 continue;1232 nr_props = pp->length/sizeof(u32);1233 list = pp->value;1234 conf = &grp->pin_conf[i];1235 1236 /* bank & offset */1237 bank = be32_to_cpup(list++);1238 offset = be32_to_cpup(list++);1239 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset);1240 conf->name = pp->name;1241 grp->pins[i] = conf->pin;1242 /* mux */1243 conf->altfunc = be32_to_cpup(list++);1244 conf->config = 0;1245 /* direction */1246 conf->config |= be32_to_cpup(list++);1247 /* rt_type rt_delay rt_clk */1248 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {1249 /* rt_type */1250 conf->config |= be32_to_cpup(list++);1251 /* rt_delay */1252 conf->config |= be32_to_cpup(list++);1253 /* rt_clk */1254 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)1255 conf->config |= be32_to_cpup(list++);1256 }1257 i++;1258 }1259 1260 return 0;1261}1262 1263static int st_pctl_parse_functions(struct device_node *np,1264 struct st_pinctrl *info, u32 index, int *grp_index)1265{1266 struct device *dev = info->dev;1267 struct st_pmx_func *func;1268 struct st_pctl_group *grp;1269 int ret, i;1270 1271 func = &info->functions[index];1272 func->name = np->name;1273 func->ngroups = of_get_child_count(np);1274 if (func->ngroups == 0)1275 return dev_err_probe(dev, -EINVAL, "No groups defined\n");1276 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);1277 if (!func->groups)1278 return -ENOMEM;1279 1280 i = 0;1281 for_each_child_of_node_scoped(np, child) {1282 func->groups[i] = child->name;1283 grp = &info->groups[*grp_index];1284 *grp_index += 1;1285 ret = st_pctl_dt_parse_groups(child, grp, info, i++);1286 if (ret)1287 return ret;1288 }1289 dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups);1290 1291 return 0;1292}1293 1294static void st_gpio_irq_mask(struct irq_data *d)1295{1296 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);1297 struct st_gpio_bank *bank = gpiochip_get_data(gc);1298 1299 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK);1300 gpiochip_disable_irq(gc, irqd_to_hwirq(d));1301}1302 1303static void st_gpio_irq_unmask(struct irq_data *d)1304{1305 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);1306 struct st_gpio_bank *bank = gpiochip_get_data(gc);1307 1308 gpiochip_enable_irq(gc, irqd_to_hwirq(d));1309 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK);1310}1311 1312static int st_gpio_irq_request_resources(struct irq_data *d)1313{1314 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);1315 1316 pinctrl_gpio_direction_input(gc, d->hwirq);1317 1318 return gpiochip_reqres_irq(gc, d->hwirq);1319}1320 1321static void st_gpio_irq_release_resources(struct irq_data *d)1322{1323 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);1324 1325 gpiochip_relres_irq(gc, d->hwirq);1326}1327 1328static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)1329{1330 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);1331 struct st_gpio_bank *bank = gpiochip_get_data(gc);1332 unsigned long flags;1333 int comp, pin = d->hwirq;1334 u32 val;1335 u32 pin_edge_conf = 0;1336 1337 switch (type) {1338 case IRQ_TYPE_LEVEL_HIGH:1339 comp = 0;1340 break;1341 case IRQ_TYPE_EDGE_FALLING:1342 comp = 0;1343 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);1344 break;1345 case IRQ_TYPE_LEVEL_LOW:1346 comp = 1;1347 break;1348 case IRQ_TYPE_EDGE_RISING:1349 comp = 1;1350 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);1351 break;1352 case IRQ_TYPE_EDGE_BOTH:1353 comp = st_gpio_get(&bank->gpio_chip, pin);1354 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);1355 break;1356 default:1357 return -EINVAL;1358 }1359 1360 spin_lock_irqsave(&bank->lock, flags);1361 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (1362 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));1363 bank->irq_edge_conf |= pin_edge_conf;1364 spin_unlock_irqrestore(&bank->lock, flags);1365 1366 val = readl(bank->base + REG_PIO_PCOMP);1367 val &= ~BIT(pin);1368 val |= (comp << pin);1369 writel(val, bank->base + REG_PIO_PCOMP);1370 1371 return 0;1372}1373 1374/*1375 * As edge triggers are not supported at hardware level, it is supported by1376 * software by exploiting the level trigger support in hardware.1377 *1378 * Steps for detection raising edge interrupt in software.1379 *1380 * Step 1: CONFIGURE pin to detect level LOW interrupts.1381 *1382 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,1383 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.1384 * IGNORE calling the actual interrupt handler for the pin at this stage.1385 *1386 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler1387 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then1388 * DISPATCH the interrupt to the interrupt handler of the pin.1389 *1390 * step-1 ________ __________1391 * | | step - 31392 * | |1393 * step -2 |_____|1394 *1395 * falling edge is also detected int the same way.1396 *1397 */1398static void __gpio_irq_handler(struct st_gpio_bank *bank)1399{1400 unsigned long port_in, port_mask, port_comp, active_irqs;1401 unsigned long bank_edge_mask, flags;1402 int n, val, ecfg;1403 1404 spin_lock_irqsave(&bank->lock, flags);1405 bank_edge_mask = bank->irq_edge_conf;1406 spin_unlock_irqrestore(&bank->lock, flags);1407 1408 for (;;) {1409 port_in = readl(bank->base + REG_PIO_PIN);1410 port_comp = readl(bank->base + REG_PIO_PCOMP);1411 port_mask = readl(bank->base + REG_PIO_PMASK);1412 1413 active_irqs = (port_in ^ port_comp) & port_mask;1414 1415 if (active_irqs == 0)1416 break;1417 1418 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {1419 /* check if we are detecting fake edges ... */1420 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);1421 1422 if (ecfg) {1423 /* edge detection. */1424 val = st_gpio_get(&bank->gpio_chip, n);1425 1426 writel(BIT(n),1427 val ? bank->base + REG_PIO_SET_PCOMP :1428 bank->base + REG_PIO_CLR_PCOMP);1429 1430 if (ecfg != ST_IRQ_EDGE_BOTH &&1431 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))1432 continue;1433 }1434 1435 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n);1436 }1437 }1438}1439 1440static void st_gpio_irq_handler(struct irq_desc *desc)1441{1442 /* interrupt dedicated per bank */1443 struct irq_chip *chip = irq_desc_get_chip(desc);1444 struct gpio_chip *gc = irq_desc_get_handler_data(desc);1445 struct st_gpio_bank *bank = gpiochip_get_data(gc);1446 1447 chained_irq_enter(chip, desc);1448 __gpio_irq_handler(bank);1449 chained_irq_exit(chip, desc);1450}1451 1452static void st_gpio_irqmux_handler(struct irq_desc *desc)1453{1454 struct irq_chip *chip = irq_desc_get_chip(desc);1455 struct st_pinctrl *info = irq_desc_get_handler_data(desc);1456 unsigned long status;1457 int n;1458 1459 chained_irq_enter(chip, desc);1460 1461 status = readl(info->irqmux_base);1462 1463 for_each_set_bit(n, &status, info->nbanks)1464 __gpio_irq_handler(&info->banks[n]);1465 1466 chained_irq_exit(chip, desc);1467}1468 1469static const struct gpio_chip st_gpio_template = {1470 .request = gpiochip_generic_request,1471 .free = gpiochip_generic_free,1472 .get = st_gpio_get,1473 .set = st_gpio_set,1474 .direction_input = pinctrl_gpio_direction_input,1475 .direction_output = st_gpio_direction_output,1476 .get_direction = st_gpio_get_direction,1477 .ngpio = ST_GPIO_PINS_PER_BANK,1478};1479 1480static const struct irq_chip st_gpio_irqchip = {1481 .name = "GPIO",1482 .irq_request_resources = st_gpio_irq_request_resources,1483 .irq_release_resources = st_gpio_irq_release_resources,1484 .irq_disable = st_gpio_irq_mask,1485 .irq_mask = st_gpio_irq_mask,1486 .irq_unmask = st_gpio_irq_unmask,1487 .irq_set_type = st_gpio_irq_set_type,1488 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,1489};1490 1491static int st_gpiolib_register_bank(struct st_pinctrl *info,1492 int bank_nr, struct device_node *np)1493{1494 struct st_gpio_bank *bank = &info->banks[bank_nr];1495 struct pinctrl_gpio_range *range = &bank->range;1496 struct device *dev = info->dev;1497 int bank_num = of_alias_get_id(np, "gpio");1498 struct resource res, irq_res;1499 int err;1500 1501 if (of_address_to_resource(np, 0, &res))1502 return -ENODEV;1503 1504 bank->base = devm_ioremap_resource(dev, &res);1505 if (IS_ERR(bank->base))1506 return PTR_ERR(bank->base);1507 1508 bank->gpio_chip = st_gpio_template;1509 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;1510 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;1511 bank->gpio_chip.fwnode = of_fwnode_handle(np);1512 bank->gpio_chip.parent = dev;1513 spin_lock_init(&bank->lock);1514 1515 of_property_read_string(np, "st,bank-name", &range->name);1516 bank->gpio_chip.label = range->name;1517 1518 range->id = bank_num;1519 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;1520 range->npins = bank->gpio_chip.ngpio;1521 range->gc = &bank->gpio_chip;1522 1523 /**1524 * GPIO bank can have one of the two possible types of1525 * interrupt-wirings.1526 *1527 * First type is via irqmux, single interrupt is used by multiple1528 * gpio banks. This reduces number of overall interrupts numbers1529 * required. All these banks belong to a single pincontroller.1530 * _________1531 * | |----> [gpio-bank (n) ]1532 * | |----> [gpio-bank (n + 1)]1533 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]1534 * | |----> [gpio-bank (... )]1535 * |_________|----> [gpio-bank (n + 7)]1536 *1537 * Second type has a dedicated interrupt per each gpio bank.1538 *1539 * [irqN]----> [gpio-bank (n)]1540 */1541 1542 if (of_irq_to_resource(np, 0, &irq_res) > 0) {1543 struct gpio_irq_chip *girq;1544 int gpio_irq = irq_res.start;1545 1546 /* This is not a valid IRQ */1547 if (gpio_irq <= 0) {1548 dev_err(dev, "invalid IRQ for %pOF bank\n", np);1549 goto skip_irq;1550 }1551 /* We need to have a mux as well */1552 if (!info->irqmux_base) {1553 dev_err(dev, "no irqmux for %pOF bank\n", np);1554 goto skip_irq;1555 }1556 1557 girq = &bank->gpio_chip.irq;1558 gpio_irq_chip_set_chip(girq, &st_gpio_irqchip);1559 girq->parent_handler = st_gpio_irq_handler;1560 girq->num_parents = 1;1561 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),1562 GFP_KERNEL);1563 if (!girq->parents)1564 return -ENOMEM;1565 girq->parents[0] = gpio_irq;1566 girq->default_type = IRQ_TYPE_NONE;1567 girq->handler = handle_simple_irq;1568 }1569 1570skip_irq:1571 err = gpiochip_add_data(&bank->gpio_chip, bank);1572 if (err)1573 return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num);1574 dev_info(dev, "%s bank added.\n", range->name);1575 1576 return 0;1577}1578 1579static const struct of_device_id st_pctl_of_match[] = {1580 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},1581 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},1582 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},1583 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},1584 { /* sentinel */ }1585};1586 1587static int st_pctl_probe_dt(struct platform_device *pdev,1588 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)1589{1590 struct device *dev = &pdev->dev;1591 int ret = 0;1592 int i = 0, j = 0, k = 0, bank;1593 struct pinctrl_pin_desc *pdesc;1594 struct device_node *np = dev->of_node;1595 int grp_index = 0;1596 int irq = 0;1597 1598 st_pctl_dt_child_count(info, np);1599 if (!info->nbanks)1600 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n");1601 1602 dev_info(dev, "nbanks = %d\n", info->nbanks);1603 dev_info(dev, "nfunctions = %d\n", info->nfunctions);1604 dev_info(dev, "ngroups = %d\n", info->ngroups);1605 1606 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);1607 1608 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);1609 1610 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL);1611 1612 if (!info->functions || !info->groups || !info->banks)1613 return -ENOMEM;1614 1615 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");1616 if (IS_ERR(info->regmap))1617 return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n");1618 info->data = of_match_node(st_pctl_of_match, np)->data;1619 1620 irq = platform_get_irq(pdev, 0);1621 1622 if (irq > 0) {1623 info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux");1624 if (IS_ERR(info->irqmux_base))1625 return PTR_ERR(info->irqmux_base);1626 1627 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,1628 info);1629 }1630 1631 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;1632 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL);1633 if (!pdesc)1634 return -ENOMEM;1635 1636 pctl_desc->pins = pdesc;1637 1638 bank = 0;1639 for_each_child_of_node_scoped(np, child) {1640 if (of_property_read_bool(child, "gpio-controller")) {1641 const char *bank_name = NULL;1642 char **pin_names;1643 1644 ret = st_gpiolib_register_bank(info, bank, child);1645 if (ret)1646 return ret;1647 1648 k = info->banks[bank].range.pin_base;1649 bank_name = info->banks[bank].range.name;1650 1651 pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK);1652 if (IS_ERR(pin_names))1653 return PTR_ERR(pin_names);1654 1655 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {1656 pdesc->number = k;1657 pdesc->name = pin_names[j];1658 pdesc++;1659 }1660 st_parse_syscfgs(info, bank, child);1661 bank++;1662 } else {1663 ret = st_pctl_parse_functions(child, info,1664 i++, &grp_index);1665 if (ret) {1666 dev_err(dev, "No functions found.\n");1667 return ret;1668 }1669 }1670 }1671 1672 return 0;1673}1674 1675static int st_pctl_probe(struct platform_device *pdev)1676{1677 struct device *dev = &pdev->dev;1678 struct st_pinctrl *info;1679 struct pinctrl_desc *pctl_desc;1680 int ret, i;1681 1682 if (!dev->of_node) {1683 dev_err(dev, "device node not found.\n");1684 return -EINVAL;1685 }1686 1687 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);1688 if (!pctl_desc)1689 return -ENOMEM;1690 1691 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);1692 if (!info)1693 return -ENOMEM;1694 1695 info->dev = dev;1696 platform_set_drvdata(pdev, info);1697 ret = st_pctl_probe_dt(pdev, pctl_desc, info);1698 if (ret)1699 return ret;1700 1701 pctl_desc->owner = THIS_MODULE;1702 pctl_desc->pctlops = &st_pctlops;1703 pctl_desc->pmxops = &st_pmxops;1704 pctl_desc->confops = &st_confops;1705 pctl_desc->name = dev_name(dev);1706 1707 info->pctl = devm_pinctrl_register(dev, pctl_desc, info);1708 if (IS_ERR(info->pctl))1709 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n");1710 1711 for (i = 0; i < info->nbanks; i++)1712 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);1713 1714 return 0;1715}1716 1717static struct platform_driver st_pctl_driver = {1718 .driver = {1719 .name = "st-pinctrl",1720 .of_match_table = st_pctl_of_match,1721 },1722 .probe = st_pctl_probe,1723};1724 1725static int __init st_pctl_init(void)1726{1727 return platform_driver_register(&st_pctl_driver);1728}1729arch_initcall(st_pctl_init);1730