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1// SPDX-License-Identifier: GPL-2.02/*3 * r8a7792 processor support - PFC hardware block.4 *5 * Copyright (C) 2013-2014 Renesas Electronics Corporation6 * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>7 */8 9#include <linux/kernel.h>10 11#include "sh_pfc.h"12 13#define CPU_ALL_GP(fn, sfx) \14 PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \15 PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \16 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \17 PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \18 PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \19 PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \20 PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \21 PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \22 PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \23 PORT_GP_CFG_17(9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \24 PORT_GP_CFG_32(10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \25 PORT_GP_CFG_30(11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)26 27#define CPU_ALL_NOGP(fn) \28 PIN_NOGP_CFG(DU0_DOTCLKIN, "DU0_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \29 PIN_NOGP_CFG(DU0_DOTCLKOUT, "DU0_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \30 PIN_NOGP_CFG(DU1_DOTCLKIN, "DU1_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \31 PIN_NOGP_CFG(DU1_DOTCLKOUT, "DU1_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \32 PIN_NOGP_CFG(EDBGREQ, "EDBGREQ", fn, SH_PFC_PIN_CFG_PULL_DOWN), \33 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \34 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \35 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \36 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)37 38enum {39 PINMUX_RESERVED = 0,40 41 PINMUX_DATA_BEGIN,42 GP_ALL(DATA),43 PINMUX_DATA_END,44 45 PINMUX_FUNCTION_BEGIN,46 GP_ALL(FN),47 48 /* GPSR0 */49 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,50 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,51 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,52 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,53 FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,54 FN_IP1_3, FN_IP1_4,55 56 /* GPSR1 */57 FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,58 FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,59 FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,60 FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,61 FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,62 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,63 64 /* GPSR2 */65 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,66 FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,67 FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,68 FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,69 70 /* GPSR3 */71 FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,72 FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,73 FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,74 FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,75 FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,76 77 /* GPSR4 */78 FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,79 FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,80 FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,81 FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,82 FN_VI0_FIELD,83 84 /* GPSR5 */85 FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,86 FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,87 FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,88 FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,89 FN_VI1_FIELD,90 91 /* GPSR6 */92 FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,93 FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,94 FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,95 96 /* GPSR7 */97 FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,98 FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,99 FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,100 101 /* GPSR8 */102 FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,103 FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,104 FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,105 106 /* GPSR9 */107 FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,108 FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,109 FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,110 111 /* GPSR10 */112 FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,113 FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,114 FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,115 FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,116 FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,117 FN_CAN1_TX, FN_CAN1_RX,118 119 /* GPSR11 */120 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,121 FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,122 FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,123 FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,124 FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,125 FN_ADICHS2, FN_AVS1, FN_AVS2,126 127 /* IPSR0 */128 FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,129 FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,130 FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,131 FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,132 FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,133 FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,134 FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,135 FN_DU0_DB7_C5,136 137 /* IPSR1 */138 FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,139 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,140 FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,141 FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,142 FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,143 FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,144 FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,145 FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,146 147 /* IPSR2 */148 FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,149 FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,150 FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,151 FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,152 FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,153 FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,154 FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,155 FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,156 FN_VI2_FIELD, FN_AVB_TXD2,157 158 /* IPSR3 */159 FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,160 FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,161 FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,162 FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,163 FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,164 FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,165 FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,166 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,167 168 /* IPSR4 */169 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,170 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,171 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,172 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,173 FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,174 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,175 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,176 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,177 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,178 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,179 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,180 FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,181 FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,182 183 /* IPSR5 */184 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,185 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,186 FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,187 FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,188 FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,189 FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,190 191 /* IPSR6 */192 FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,193 FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,194 FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,195 FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,196 FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,197 FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,198 199 /* IPSR7 */200 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,201 FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,202 FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,203 FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,204 FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,205 FN_AUDIO_CLKA, FN_AUDIO_CLKB,206 207 /* MOD_SEL */208 FN_SEL_VI1_0, FN_SEL_VI1_1,209 PINMUX_FUNCTION_END,210 211 PINMUX_MARK_BEGIN,212 DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,213 DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,214 DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,215 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,216 DU1_DISP_MARK, DU1_CDE_MARK,217 218 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,219 D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,220 D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,221 A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,222 A12_MARK, A13_MARK, A14_MARK, A15_MARK,223 224 A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,225 EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,226 EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,227 WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,228 IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,229 230 VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,231 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,232 VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,233 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,234 VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,235 VI0_FIELD_MARK,236 237 VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,238 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,239 VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,240 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,241 VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,242 VI1_FIELD_MARK,243 244 VI3_D10_Y2_MARK, VI3_FIELD_MARK,245 246 VI4_CLK_MARK,247 248 VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,249 VI5_FIELD_MARK,250 251 HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,252 TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,253 TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,254 CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,255 256 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,257 SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,258 ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,259 ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,260 261 /* IPSR0 */262 DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,263 DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,264 DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,265 DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,266 DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,267 DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,268 DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,269 DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,270 271 /* IPSR1 */272 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,273 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,274 DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,275 DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,276 DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,277 DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,278 A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,279 A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,280 281 /* IPSR2 */282 VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,283 VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,284 VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,285 VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,286 VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,287 VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,288 VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,289 VI2_D10_Y2_MARK, AVB_TXD0_MARK,290 VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,291 292 /* IPSR3 */293 VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,294 VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,295 VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,296 VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,297 VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,298 VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,299 VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,300 VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,301 302 /* IPSR4 */303 VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,304 VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,305 RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,306 VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,307 VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,308 VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,309 VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,310 VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,311 VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,312 VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,313 VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,314 315 /* IPSR5 */316 VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,317 VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,318 VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,319 VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,320 VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,321 VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,322 VI5_D8_Y0_MARK, VI1_D23_R7_MARK,323 324 /* IPSR6 */325 MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,326 MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,327 MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,328 MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,329 DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,330 RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,331 RX3_MARK,332 333 /* IPSR7 */334 PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,335 FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,336 PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,337 SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,338 SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,339 AUDIO_CLKB_MARK,340 PINMUX_MARK_END,341};342 343static const u16 pinmux_data[] = {344 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */345 346 PINMUX_SINGLE(DU1_DB2_C0_DATA12),347 PINMUX_SINGLE(DU1_DB3_C1_DATA13),348 PINMUX_SINGLE(DU1_DB4_C2_DATA14),349 PINMUX_SINGLE(DU1_DB5_C3_DATA15),350 PINMUX_SINGLE(DU1_DB6_C4),351 PINMUX_SINGLE(DU1_DB7_C5),352 PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),353 PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),354 PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),355 PINMUX_SINGLE(DU1_DISP),356 PINMUX_SINGLE(DU1_CDE),357 PINMUX_SINGLE(D0),358 PINMUX_SINGLE(D1),359 PINMUX_SINGLE(D2),360 PINMUX_SINGLE(D3),361 PINMUX_SINGLE(D4),362 PINMUX_SINGLE(D5),363 PINMUX_SINGLE(D6),364 PINMUX_SINGLE(D7),365 PINMUX_SINGLE(D8),366 PINMUX_SINGLE(D9),367 PINMUX_SINGLE(D10),368 PINMUX_SINGLE(D11),369 PINMUX_SINGLE(D12),370 PINMUX_SINGLE(D13),371 PINMUX_SINGLE(D14),372 PINMUX_SINGLE(D15),373 PINMUX_SINGLE(A0),374 PINMUX_SINGLE(A1),375 PINMUX_SINGLE(A2),376 PINMUX_SINGLE(A3),377 PINMUX_SINGLE(A4),378 PINMUX_SINGLE(A5),379 PINMUX_SINGLE(A6),380 PINMUX_SINGLE(A7),381 PINMUX_SINGLE(A8),382 PINMUX_SINGLE(A9),383 PINMUX_SINGLE(A10),384 PINMUX_SINGLE(A11),385 PINMUX_SINGLE(A12),386 PINMUX_SINGLE(A13),387 PINMUX_SINGLE(A14),388 PINMUX_SINGLE(A15),389 PINMUX_SINGLE(A16),390 PINMUX_SINGLE(A17),391 PINMUX_SINGLE(A18),392 PINMUX_SINGLE(A19),393 PINMUX_SINGLE(CS1_N_A26),394 PINMUX_SINGLE(EX_CS0_N),395 PINMUX_SINGLE(EX_CS1_N),396 PINMUX_SINGLE(EX_CS2_N),397 PINMUX_SINGLE(EX_CS3_N),398 PINMUX_SINGLE(EX_CS4_N),399 PINMUX_SINGLE(EX_CS5_N),400 PINMUX_SINGLE(BS_N),401 PINMUX_SINGLE(RD_N),402 PINMUX_SINGLE(RD_WR_N),403 PINMUX_SINGLE(WE0_N),404 PINMUX_SINGLE(WE1_N),405 PINMUX_SINGLE(EX_WAIT0),406 PINMUX_SINGLE(IRQ0),407 PINMUX_SINGLE(IRQ1),408 PINMUX_SINGLE(IRQ2),409 PINMUX_SINGLE(IRQ3),410 PINMUX_SINGLE(CS0_N),411 PINMUX_SINGLE(VI0_CLK),412 PINMUX_SINGLE(VI0_CLKENB),413 PINMUX_SINGLE(VI0_HSYNC_N),414 PINMUX_SINGLE(VI0_VSYNC_N),415 PINMUX_SINGLE(VI0_D0_B0_C0),416 PINMUX_SINGLE(VI0_D1_B1_C1),417 PINMUX_SINGLE(VI0_D2_B2_C2),418 PINMUX_SINGLE(VI0_D3_B3_C3),419 PINMUX_SINGLE(VI0_D4_B4_C4),420 PINMUX_SINGLE(VI0_D5_B5_C5),421 PINMUX_SINGLE(VI0_D6_B6_C6),422 PINMUX_SINGLE(VI0_D7_B7_C7),423 PINMUX_SINGLE(VI0_D8_G0_Y0),424 PINMUX_SINGLE(VI0_D9_G1_Y1),425 PINMUX_SINGLE(VI0_D10_G2_Y2),426 PINMUX_SINGLE(VI0_D11_G3_Y3),427 PINMUX_SINGLE(VI0_FIELD),428 PINMUX_SINGLE(VI1_CLK),429 PINMUX_SINGLE(VI1_CLKENB),430 PINMUX_SINGLE(VI1_HSYNC_N),431 PINMUX_SINGLE(VI1_VSYNC_N),432 PINMUX_SINGLE(VI1_D0_B0_C0),433 PINMUX_SINGLE(VI1_D1_B1_C1),434 PINMUX_SINGLE(VI1_D2_B2_C2),435 PINMUX_SINGLE(VI1_D3_B3_C3),436 PINMUX_SINGLE(VI1_D4_B4_C4),437 PINMUX_SINGLE(VI1_D5_B5_C5),438 PINMUX_SINGLE(VI1_D6_B6_C6),439 PINMUX_SINGLE(VI1_D7_B7_C7),440 PINMUX_SINGLE(VI1_D8_G0_Y0),441 PINMUX_SINGLE(VI1_D9_G1_Y1),442 PINMUX_SINGLE(VI1_D10_G2_Y2),443 PINMUX_SINGLE(VI1_D11_G3_Y3),444 PINMUX_SINGLE(VI1_FIELD),445 PINMUX_SINGLE(VI3_D10_Y2),446 PINMUX_SINGLE(VI3_FIELD),447 PINMUX_SINGLE(VI4_CLK),448 PINMUX_SINGLE(VI5_CLK),449 PINMUX_SINGLE(VI5_D9_Y1),450 PINMUX_SINGLE(VI5_D10_Y2),451 PINMUX_SINGLE(VI5_D11_Y3),452 PINMUX_SINGLE(VI5_FIELD),453 PINMUX_SINGLE(HRTS0_N),454 PINMUX_SINGLE(HCTS1_N),455 PINMUX_SINGLE(SCK0),456 PINMUX_SINGLE(CTS0_N),457 PINMUX_SINGLE(RTS0_N),458 PINMUX_SINGLE(TX0),459 PINMUX_SINGLE(RX0),460 PINMUX_SINGLE(SCK1),461 PINMUX_SINGLE(CTS1_N),462 PINMUX_SINGLE(RTS1_N),463 PINMUX_SINGLE(TX1),464 PINMUX_SINGLE(RX1),465 PINMUX_SINGLE(SCIF_CLK),466 PINMUX_SINGLE(CAN0_TX),467 PINMUX_SINGLE(CAN0_RX),468 PINMUX_SINGLE(CAN_CLK),469 PINMUX_SINGLE(CAN1_TX),470 PINMUX_SINGLE(CAN1_RX),471 PINMUX_SINGLE(SD0_CLK),472 PINMUX_SINGLE(SD0_CMD),473 PINMUX_SINGLE(SD0_DAT0),474 PINMUX_SINGLE(SD0_DAT1),475 PINMUX_SINGLE(SD0_DAT2),476 PINMUX_SINGLE(SD0_DAT3),477 PINMUX_SINGLE(SD0_CD),478 PINMUX_SINGLE(SD0_WP),479 PINMUX_SINGLE(ADICLK),480 PINMUX_SINGLE(ADICS_SAMP),481 PINMUX_SINGLE(ADIDATA),482 PINMUX_SINGLE(ADICHS0),483 PINMUX_SINGLE(ADICHS1),484 PINMUX_SINGLE(ADICHS2),485 PINMUX_SINGLE(AVS1),486 PINMUX_SINGLE(AVS2),487 488 /* IPSR0 */489 PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),490 PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),491 PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),492 PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),493 PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),494 PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),495 PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),496 PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),497 PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),498 PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),499 PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),500 PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),501 PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),502 PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),503 PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),504 PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),505 PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),506 PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),507 PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),508 PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),509 PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),510 PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),511 PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),512 PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),513 514 /* IPSR1 */515 PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),516 PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),517 PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),518 PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),519 PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),520 PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),521 PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),522 PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),523 PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),524 PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),525 PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),526 PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),527 PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),528 PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),529 PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),530 PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),531 PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),532 PINMUX_IPSR_GPSR(IP1_17, A20),533 PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),534 PINMUX_IPSR_GPSR(IP1_18, A21),535 PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),536 PINMUX_IPSR_GPSR(IP1_19, A22),537 PINMUX_IPSR_GPSR(IP1_19, IO2),538 PINMUX_IPSR_GPSR(IP1_20, A23),539 PINMUX_IPSR_GPSR(IP1_20, IO3),540 PINMUX_IPSR_GPSR(IP1_21, A24),541 PINMUX_IPSR_GPSR(IP1_21, SPCLK),542 PINMUX_IPSR_GPSR(IP1_22, A25),543 PINMUX_IPSR_GPSR(IP1_22, SSL),544 545 /* IPSR2 */546 PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),547 PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),548 PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),549 PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),550 PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),551 PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),552 PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),553 PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),554 PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),555 PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),556 PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),557 PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),558 PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),559 PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),560 PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),561 PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),562 PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),563 PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),564 PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),565 PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),566 PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),567 PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),568 PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),569 PINMUX_IPSR_GPSR(IP2_11, AVB_COL),570 PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),571 PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),572 PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),573 PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),574 PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),575 PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),576 PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),577 PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),578 PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),579 PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),580 581 /* IPSR3 */582 PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),583 PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),584 PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),585 PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),586 PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),587 PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),588 PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),589 PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),590 PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),591 PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),592 PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),593 PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),594 PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),595 PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),596 PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),597 PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),598 PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),599 PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),600 PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),601 PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),602 PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),603 PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),604 PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),605 PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),606 PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),607 PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),608 PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),609 PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),610 PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),611 PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),612 613 /* IPSR4 */614 PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),615 PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),616 PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),617 PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),618 PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),619 PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),620 PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),621 PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),622 PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),623 PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),624 PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),625 PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),626 PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),627 PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),628 PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),629 PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),630 PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),631 PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),632 PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),633 PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),634 PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),635 PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),636 PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),637 PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),638 PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),639 PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),640 PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),641 PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),642 PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),643 PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),644 PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),645 PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),646 PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),647 PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),648 PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),649 PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),650 PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),651 PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),652 PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),653 PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),654 655 /* IPSR5 */656 PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),657 PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),658 PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),659 PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),660 PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),661 PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),662 PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),663 PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),664 PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),665 PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),666 PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),667 PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),668 PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),669 PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),670 PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),671 PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),672 PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),673 PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),674 PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),675 PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),676 PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),677 PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),678 PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),679 PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),680 681 /* IPSR6 */682 PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),683 PINMUX_IPSR_GPSR(IP6_0, HSCK0),684 PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),685 PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),686 PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),687 PINMUX_IPSR_GPSR(IP6_2, HTX0),688 PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),689 PINMUX_IPSR_GPSR(IP6_3, HRX0),690 PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),691 PINMUX_IPSR_GPSR(IP6_4, HSCK1),692 PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),693 PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),694 PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),695 PINMUX_IPSR_GPSR(IP6_6, HTX1),696 PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),697 PINMUX_IPSR_GPSR(IP6_7, HRX1),698 PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),699 PINMUX_IPSR_GPSR(IP6_9_8, SCK2),700 PINMUX_IPSR_GPSR(IP6_11_10, DACK0),701 PINMUX_IPSR_GPSR(IP6_11_10, TX2),702 PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),703 PINMUX_IPSR_GPSR(IP6_13_12, RX2),704 PINMUX_IPSR_GPSR(IP6_15_14, DACK1),705 PINMUX_IPSR_GPSR(IP6_15_14, SCK3),706 PINMUX_IPSR_GPSR(IP6_16, TX3),707 PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),708 PINMUX_IPSR_GPSR(IP6_18_17, RX3),709 710 /* IPSR7 */711 PINMUX_IPSR_GPSR(IP7_1_0, PWM0),712 PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),713 PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),714 PINMUX_IPSR_GPSR(IP7_3_2, PWM1),715 PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),716 PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),717 PINMUX_IPSR_GPSR(IP7_5_4, PWM2),718 PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),719 PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),720 PINMUX_IPSR_GPSR(IP7_6, PWM3),721 PINMUX_IPSR_GPSR(IP7_7, PWM4),722 PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),723 PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),724 PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),725 PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),726 PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),727 PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),728 PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),729 PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),730 PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),731 PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),732 PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),733 PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),734 PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),735};736 737/*738 * Pins not associated with a GPIO port.739 */740enum {741 GP_ASSIGN_LAST(),742 NOGP_ALL(),743};744 745static const struct sh_pfc_pin pinmux_pins[] = {746 PINMUX_GPIO_GP_ALL(),747 PINMUX_NOGP_ALL(),748};749 750/* - AVB -------------------------------------------------------------------- */751static const unsigned int avb_link_pins[] = {752 RCAR_GP_PIN(7, 9),753};754static const unsigned int avb_link_mux[] = {755 AVB_LINK_MARK,756};757static const unsigned int avb_magic_pins[] = {758 RCAR_GP_PIN(7, 10),759};760static const unsigned int avb_magic_mux[] = {761 AVB_MAGIC_MARK,762};763static const unsigned int avb_phy_int_pins[] = {764 RCAR_GP_PIN(7, 11),765};766static const unsigned int avb_phy_int_mux[] = {767 AVB_PHY_INT_MARK,768};769static const unsigned int avb_mdio_pins[] = {770 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),771};772static const unsigned int avb_mdio_mux[] = {773 AVB_MDC_MARK, AVB_MDIO_MARK,774};775static const unsigned int avb_mii_pins[] = {776 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),777 RCAR_GP_PIN(6, 12),778 779 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),780 RCAR_GP_PIN(6, 5),781 782 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),783 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),784 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11),785};786static const unsigned int avb_mii_mux[] = {787 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,788 AVB_TXD3_MARK,789 790 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,791 AVB_RXD3_MARK,792 793 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,794 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,795 AVB_TX_CLK_MARK, AVB_COL_MARK,796};797static const unsigned int avb_gmii_pins[] = {798 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),799 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 2),800 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),801 802 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),803 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),804 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),805 806 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),807 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),808 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),809 RCAR_GP_PIN(6, 11),810};811static const unsigned int avb_gmii_mux[] = {812 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,813 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,814 AVB_TXD6_MARK, AVB_TXD7_MARK,815 816 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,817 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,818 AVB_RXD6_MARK, AVB_RXD7_MARK,819 820 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,821 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,822 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,823 AVB_COL_MARK,824};825static const unsigned int avb_avtp_match_pins[] = {826 RCAR_GP_PIN(7, 15),827};828static const unsigned int avb_avtp_match_mux[] = {829 AVB_AVTP_MATCH_MARK,830};831/* - CAN -------------------------------------------------------------------- */832static const unsigned int can0_data_pins[] = {833 /* TX, RX */834 RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),835};836static const unsigned int can0_data_mux[] = {837 CAN0_TX_MARK, CAN0_RX_MARK,838};839static const unsigned int can1_data_pins[] = {840 /* TX, RX */841 RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),842};843static const unsigned int can1_data_mux[] = {844 CAN1_TX_MARK, CAN1_RX_MARK,845};846static const unsigned int can_clk_pins[] = {847 /* CAN_CLK */848 RCAR_GP_PIN(10, 29),849};850static const unsigned int can_clk_mux[] = {851 CAN_CLK_MARK,852};853/* - DU --------------------------------------------------------------------- */854static const unsigned int du0_rgb666_pins[] = {855 /* R[7:2], G[7:2], B[7:2] */856 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),857 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),858 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),859 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),860 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),861 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),862};863static const unsigned int du0_rgb666_mux[] = {864 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,865 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,866 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,867 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,868 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,869 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,870};871static const unsigned int du0_rgb888_pins[] = {872 /* R[7:0], G[7:0], B[7:0] */873 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),874 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),875 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),876 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),877 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),878 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),879 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),880 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),881 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),882};883static const unsigned int du0_rgb888_mux[] = {884 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,885 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,886 DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,887 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,888 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,889 DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,890 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,891 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,892 DU0_DB1_MARK, DU0_DB0_MARK,893};894static const unsigned int du0_sync_pins[] = {895 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */896 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),897};898static const unsigned int du0_sync_mux[] = {899 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,900};901static const unsigned int du0_oddf_pins[] = {902 /* EXODDF/ODDF/DISP/CDE */903 RCAR_GP_PIN(0, 26),904};905static const unsigned int du0_oddf_mux[] = {906 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK907};908static const unsigned int du0_disp_pins[] = {909 /* DISP */910 RCAR_GP_PIN(0, 27),911};912static const unsigned int du0_disp_mux[] = {913 DU0_DISP_MARK,914};915static const unsigned int du0_cde_pins[] = {916 /* CDE */917 RCAR_GP_PIN(0, 28),918};919static const unsigned int du0_cde_mux[] = {920 DU0_CDE_MARK,921};922static const unsigned int du1_rgb666_pins[] = {923 /* R[7:2], G[7:2], B[7:2] */924 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),925 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),926 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),927 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),928 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),929 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),930};931static const unsigned int du1_rgb666_mux[] = {932 DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,933 DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,934 DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,935 DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,936 DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,937 DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,938};939static const unsigned int du1_sync_pins[] = {940 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */941 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),942};943static const unsigned int du1_sync_mux[] = {944 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,945};946static const unsigned int du1_oddf_pins[] = {947 /* EXODDF/ODDF/DISP/CDE */948 RCAR_GP_PIN(1, 20),949};950static const unsigned int du1_oddf_mux[] = {951 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK952};953static const unsigned int du1_disp_pins[] = {954 /* DISP */955 RCAR_GP_PIN(1, 21),956};957static const unsigned int du1_disp_mux[] = {958 DU1_DISP_MARK,959};960static const unsigned int du1_cde_pins[] = {961 /* CDE */962 RCAR_GP_PIN(1, 22),963};964static const unsigned int du1_cde_mux[] = {965 DU1_CDE_MARK,966};967/* - INTC ------------------------------------------------------------------- */968static const unsigned int intc_irq0_pins[] = {969 /* IRQ0 */970 RCAR_GP_PIN(3, 19),971};972static const unsigned int intc_irq0_mux[] = {973 IRQ0_MARK,974};975static const unsigned int intc_irq1_pins[] = {976 /* IRQ1 */977 RCAR_GP_PIN(3, 20),978};979static const unsigned int intc_irq1_mux[] = {980 IRQ1_MARK,981};982static const unsigned int intc_irq2_pins[] = {983 /* IRQ2 */984 RCAR_GP_PIN(3, 21),985};986static const unsigned int intc_irq2_mux[] = {987 IRQ2_MARK,988};989static const unsigned int intc_irq3_pins[] = {990 /* IRQ3 */991 RCAR_GP_PIN(3, 22),992};993static const unsigned int intc_irq3_mux[] = {994 IRQ3_MARK,995};996/* - LBSC ------------------------------------------------------------------- */997static const unsigned int lbsc_cs0_pins[] = {998 /* CS0# */999 RCAR_GP_PIN(3, 27),1000};1001static const unsigned int lbsc_cs0_mux[] = {1002 CS0_N_MARK,1003};1004static const unsigned int lbsc_cs1_pins[] = {1005 /* CS1#_A26 */1006 RCAR_GP_PIN(3, 6),1007};1008static const unsigned int lbsc_cs1_mux[] = {1009 CS1_N_A26_MARK,1010};1011static const unsigned int lbsc_ex_cs0_pins[] = {1012 /* EX_CS0# */1013 RCAR_GP_PIN(3, 7),1014};1015static const unsigned int lbsc_ex_cs0_mux[] = {1016 EX_CS0_N_MARK,1017};1018static const unsigned int lbsc_ex_cs1_pins[] = {1019 /* EX_CS1# */1020 RCAR_GP_PIN(3, 8),1021};1022static const unsigned int lbsc_ex_cs1_mux[] = {1023 EX_CS1_N_MARK,1024};1025static const unsigned int lbsc_ex_cs2_pins[] = {1026 /* EX_CS2# */1027 RCAR_GP_PIN(3, 9),1028};1029static const unsigned int lbsc_ex_cs2_mux[] = {1030 EX_CS2_N_MARK,1031};1032static const unsigned int lbsc_ex_cs3_pins[] = {1033 /* EX_CS3# */1034 RCAR_GP_PIN(3, 10),1035};1036static const unsigned int lbsc_ex_cs3_mux[] = {1037 EX_CS3_N_MARK,1038};1039static const unsigned int lbsc_ex_cs4_pins[] = {1040 /* EX_CS4# */1041 RCAR_GP_PIN(3, 11),1042};1043static const unsigned int lbsc_ex_cs4_mux[] = {1044 EX_CS4_N_MARK,1045};1046static const unsigned int lbsc_ex_cs5_pins[] = {1047 /* EX_CS5# */1048 RCAR_GP_PIN(3, 12),1049};1050static const unsigned int lbsc_ex_cs5_mux[] = {1051 EX_CS5_N_MARK,1052};1053/* - MSIOF0 ----------------------------------------------------------------- */1054static const unsigned int msiof0_clk_pins[] = {1055 /* SCK */1056 RCAR_GP_PIN(10, 0),1057};1058static const unsigned int msiof0_clk_mux[] = {1059 MSIOF0_SCK_MARK,1060};1061static const unsigned int msiof0_sync_pins[] = {1062 /* SYNC */1063 RCAR_GP_PIN(10, 1),1064};1065static const unsigned int msiof0_sync_mux[] = {1066 MSIOF0_SYNC_MARK,1067};1068static const unsigned int msiof0_rx_pins[] = {1069 /* RXD */1070 RCAR_GP_PIN(10, 4),1071};1072static const unsigned int msiof0_rx_mux[] = {1073 MSIOF0_RXD_MARK,1074};1075static const unsigned int msiof0_tx_pins[] = {1076 /* TXD */1077 RCAR_GP_PIN(10, 3),1078};1079static const unsigned int msiof0_tx_mux[] = {1080 MSIOF0_TXD_MARK,1081};1082/* - MSIOF1 ----------------------------------------------------------------- */1083static const unsigned int msiof1_clk_pins[] = {1084 /* SCK */1085 RCAR_GP_PIN(10, 5),1086};1087static const unsigned int msiof1_clk_mux[] = {1088 MSIOF1_SCK_MARK,1089};1090static const unsigned int msiof1_sync_pins[] = {1091 /* SYNC */1092 RCAR_GP_PIN(10, 6),1093};1094static const unsigned int msiof1_sync_mux[] = {1095 MSIOF1_SYNC_MARK,1096};1097static const unsigned int msiof1_rx_pins[] = {1098 /* RXD */1099 RCAR_GP_PIN(10, 9),1100};1101static const unsigned int msiof1_rx_mux[] = {1102 MSIOF1_RXD_MARK,1103};1104static const unsigned int msiof1_tx_pins[] = {1105 /* TXD */1106 RCAR_GP_PIN(10, 8),1107};1108static const unsigned int msiof1_tx_mux[] = {1109 MSIOF1_TXD_MARK,1110};1111/* - QSPI ------------------------------------------------------------------- */1112static const unsigned int qspi_ctrl_pins[] = {1113 /* SPCLK, SSL */1114 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),1115};1116static const unsigned int qspi_ctrl_mux[] = {1117 SPCLK_MARK, SSL_MARK,1118};1119static const unsigned int qspi_data_pins[] = {1120 /* MOSI_IO0, MISO_IO1, IO2, IO3 */1121 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),1122 RCAR_GP_PIN(3, 24),1123};1124static const unsigned int qspi_data_mux[] = {1125 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,1126};1127/* - SCIF0 ------------------------------------------------------------------ */1128static const unsigned int scif0_data_pins[] = {1129 /* RX, TX */1130 RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),1131};1132static const unsigned int scif0_data_mux[] = {1133 RX0_MARK, TX0_MARK,1134};1135static const unsigned int scif0_clk_pins[] = {1136 /* SCK */1137 RCAR_GP_PIN(10, 10),1138};1139static const unsigned int scif0_clk_mux[] = {1140 SCK0_MARK,1141};1142static const unsigned int scif0_ctrl_pins[] = {1143 /* RTS, CTS */1144 RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),1145};1146static const unsigned int scif0_ctrl_mux[] = {1147 RTS0_N_MARK, CTS0_N_MARK,1148};1149/* - SCIF1 ------------------------------------------------------------------ */1150static const unsigned int scif1_data_pins[] = {1151 /* RX, TX */1152 RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),1153};1154static const unsigned int scif1_data_mux[] = {1155 RX1_MARK, TX1_MARK,1156};1157static const unsigned int scif1_clk_pins[] = {1158 /* SCK */1159 RCAR_GP_PIN(10, 15),1160};1161static const unsigned int scif1_clk_mux[] = {1162 SCK1_MARK,1163};1164static const unsigned int scif1_ctrl_pins[] = {1165 /* RTS, CTS */1166 RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),1167};1168static const unsigned int scif1_ctrl_mux[] = {1169 RTS1_N_MARK, CTS1_N_MARK,1170};1171/* - SCIF2 ------------------------------------------------------------------ */1172static const unsigned int scif2_data_pins[] = {1173 /* RX, TX */1174 RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),1175};1176static const unsigned int scif2_data_mux[] = {1177 RX2_MARK, TX2_MARK,1178};1179static const unsigned int scif2_clk_pins[] = {1180 /* SCK */1181 RCAR_GP_PIN(10, 20),1182};1183static const unsigned int scif2_clk_mux[] = {1184 SCK2_MARK,1185};1186/* - SCIF3 ------------------------------------------------------------------ */1187static const unsigned int scif3_data_pins[] = {1188 /* RX, TX */1189 RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),1190};1191static const unsigned int scif3_data_mux[] = {1192 RX3_MARK, TX3_MARK,1193};1194static const unsigned int scif3_clk_pins[] = {1195 /* SCK */1196 RCAR_GP_PIN(10, 23),1197};1198static const unsigned int scif3_clk_mux[] = {1199 SCK3_MARK,1200};1201/* - SDHI0 ------------------------------------------------------------------ */1202static const unsigned int sdhi0_data_pins[] = {1203 /* DAT[0-3] */1204 RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),1205 RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),1206};1207static const unsigned int sdhi0_data_mux[] = {1208 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,1209};1210static const unsigned int sdhi0_ctrl_pins[] = {1211 /* CLK, CMD */1212 RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),1213};1214static const unsigned int sdhi0_ctrl_mux[] = {1215 SD0_CLK_MARK, SD0_CMD_MARK,1216};1217static const unsigned int sdhi0_cd_pins[] = {1218 /* CD */1219 RCAR_GP_PIN(11, 11),1220};1221static const unsigned int sdhi0_cd_mux[] = {1222 SD0_CD_MARK,1223};1224static const unsigned int sdhi0_wp_pins[] = {1225 /* WP */1226 RCAR_GP_PIN(11, 12),1227};1228static const unsigned int sdhi0_wp_mux[] = {1229 SD0_WP_MARK,1230};1231/* - VIN0 ------------------------------------------------------------------- */1232static const unsigned int vin0_data_pins[] = {1233 /* B */1234 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),1235 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),1236 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),1237 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),1238 /* G */1239 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),1240 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),1241 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),1242 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),1243 /* R */1244 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),1245 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),1246 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),1247 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),1248};1249static const unsigned int vin0_data_mux[] = {1250 /* B */1251 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,1252 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,1253 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,1254 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,1255 /* G */1256 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,1257 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,1258 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,1259 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,1260 /* R */1261 VI0_D16_R0_MARK, VI0_D17_R1_MARK,1262 VI0_D18_R2_MARK, VI0_D19_R3_MARK,1263 VI0_D20_R4_MARK, VI0_D21_R5_MARK,1264 VI0_D22_R6_MARK, VI0_D23_R7_MARK,1265};1266static const unsigned int vin0_data18_pins[] = {1267 /* B */1268 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),1269 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),1270 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),1271 /* G */1272 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),1273 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),1274 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),1275 /* R */1276 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),1277 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),1278 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),1279};1280static const unsigned int vin0_data18_mux[] = {1281 /* B */1282 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,1283 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,1284 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,1285 /* G */1286 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,1287 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,1288 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,1289 /* R */1290 VI0_D18_R2_MARK, VI0_D19_R3_MARK,1291 VI0_D20_R4_MARK, VI0_D21_R5_MARK,1292 VI0_D22_R6_MARK, VI0_D23_R7_MARK,1293};1294static const unsigned int vin0_sync_pins[] = {1295 /* HSYNC#, VSYNC# */1296 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),1297};1298static const unsigned int vin0_sync_mux[] = {1299 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,1300};1301static const unsigned int vin0_field_pins[] = {1302 RCAR_GP_PIN(4, 16),1303};1304static const unsigned int vin0_field_mux[] = {1305 VI0_FIELD_MARK,1306};1307static const unsigned int vin0_clkenb_pins[] = {1308 RCAR_GP_PIN(4, 1),1309};1310static const unsigned int vin0_clkenb_mux[] = {1311 VI0_CLKENB_MARK,1312};1313static const unsigned int vin0_clk_pins[] = {1314 RCAR_GP_PIN(4, 0),1315};1316static const unsigned int vin0_clk_mux[] = {1317 VI0_CLK_MARK,1318};1319/* - VIN1 ------------------------------------------------------------------- */1320static const unsigned int vin1_data_pins[] = {1321 /* B */1322 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),1323 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),1324 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),1325 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),1326 /* G */1327 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),1328 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),1329 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),1330 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),1331 /* R */1332 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),1333 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),1334 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),1335 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),1336};1337static const unsigned int vin1_data_mux[] = {1338 /* B */1339 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,1340 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,1341 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,1342 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,1343 /* G */1344 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,1345 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,1346 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,1347 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,1348 /* R */1349 VI1_D16_R0_MARK, VI1_D17_R1_MARK,1350 VI1_D18_R2_MARK, VI1_D19_R3_MARK,1351 VI1_D20_R4_MARK, VI1_D21_R5_MARK,1352 VI1_D22_R6_MARK, VI1_D23_R7_MARK,1353};1354static const unsigned int vin1_data18_pins[] = {1355 /* B */1356 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),1357 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),1358 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),1359 /* G */1360 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),1361 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),1362 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),1363 /* R */1364 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),1365 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),1366 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),1367};1368static const unsigned int vin1_data18_mux[] = {1369 /* B */1370 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,1371 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,1372 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,1373 /* G */1374 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,1375 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,1376 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,1377 /* R */1378 VI1_D18_R2_MARK, VI1_D19_R3_MARK,1379 VI1_D20_R4_MARK, VI1_D21_R5_MARK,1380 VI1_D22_R6_MARK, VI1_D23_R7_MARK,1381};1382static const unsigned int vin1_data_b_pins[] = {1383 /* B */1384 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),1385 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),1386 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),1387 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),1388 /* G */1389 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),1390 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),1391 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),1392 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),1393 /* R */1394 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),1395 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),1396 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),1397 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),1398};1399static const unsigned int vin1_data_b_mux[] = {1400 /* B */1401 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,1402 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,1403 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,1404 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,1405 /* G */1406 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,1407 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,1408 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,1409 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,1410 /* R */1411 VI1_D16_R0_MARK, VI1_D17_R1_MARK,1412 VI1_D18_R2_MARK, VI1_D19_R3_MARK,1413 VI1_D20_R4_MARK, VI1_D21_R5_MARK,1414 VI1_D22_R6_MARK, VI1_D23_R7_MARK,1415};1416static const unsigned int vin1_data18_b_pins[] = {1417 /* B */1418 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),1419 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),1420 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),1421 /* G */1422 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),1423 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),1424 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),1425 /* R */1426 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),1427 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),1428 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),1429};1430static const unsigned int vin1_data18_b_mux[] = {1431 /* B */1432 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,1433 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,1434 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,1435 /* G */1436 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,1437 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,1438 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,1439 /* R */1440 VI1_D18_R2_MARK, VI1_D19_R3_MARK,1441 VI1_D20_R4_MARK, VI1_D21_R5_MARK,1442 VI1_D22_R6_MARK, VI1_D23_R7_MARK,1443};1444static const unsigned int vin1_sync_pins[] = {1445 /* HSYNC#, VSYNC# */1446 RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),1447};1448static const unsigned int vin1_sync_mux[] = {1449 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,1450};1451static const unsigned int vin1_field_pins[] = {1452 RCAR_GP_PIN(5, 16),1453};1454static const unsigned int vin1_field_mux[] = {1455 VI1_FIELD_MARK,1456};1457static const unsigned int vin1_clkenb_pins[] = {1458 RCAR_GP_PIN(5, 1),1459};1460static const unsigned int vin1_clkenb_mux[] = {1461 VI1_CLKENB_MARK,1462};1463static const unsigned int vin1_clk_pins[] = {1464 RCAR_GP_PIN(5, 0),1465};1466static const unsigned int vin1_clk_mux[] = {1467 VI1_CLK_MARK,1468};1469/* - VIN2 ------------------------------------------------------------------- */1470static const unsigned int vin2_data_pins[] = {1471 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),1472 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),1473 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),1474 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),1475 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),1476 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),1477 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),1478 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),1479};1480static const unsigned int vin2_data_mux[] = {1481 VI2_D0_C0_MARK, VI2_D1_C1_MARK,1482 VI2_D2_C2_MARK, VI2_D3_C3_MARK,1483 VI2_D4_C4_MARK, VI2_D5_C5_MARK,1484 VI2_D6_C6_MARK, VI2_D7_C7_MARK,1485 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,1486 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,1487 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,1488 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,1489};1490static const unsigned int vin2_sync_pins[] = {1491 /* HSYNC#, VSYNC# */1492 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),1493};1494static const unsigned int vin2_sync_mux[] = {1495 VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,1496};1497static const unsigned int vin2_field_pins[] = {1498 RCAR_GP_PIN(6, 16),1499};1500static const unsigned int vin2_field_mux[] = {1501 VI2_FIELD_MARK,1502};1503static const unsigned int vin2_clkenb_pins[] = {1504 RCAR_GP_PIN(6, 1),1505};1506static const unsigned int vin2_clkenb_mux[] = {1507 VI2_CLKENB_MARK,1508};1509static const unsigned int vin2_clk_pins[] = {1510 RCAR_GP_PIN(6, 0),1511};1512static const unsigned int vin2_clk_mux[] = {1513 VI2_CLK_MARK,1514};1515/* - VIN3 ------------------------------------------------------------------- */1516static const unsigned int vin3_data_pins[] = {1517 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),1518 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),1519 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),1520 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),1521 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),1522 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),1523 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),1524 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),1525};1526static const unsigned int vin3_data_mux[] = {1527 VI3_D0_C0_MARK, VI3_D1_C1_MARK,1528 VI3_D2_C2_MARK, VI3_D3_C3_MARK,1529 VI3_D4_C4_MARK, VI3_D5_C5_MARK,1530 VI3_D6_C6_MARK, VI3_D7_C7_MARK,1531 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,1532 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,1533 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,1534 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,1535};1536static const unsigned int vin3_sync_pins[] = {1537 /* HSYNC#, VSYNC# */1538 RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),1539};1540static const unsigned int vin3_sync_mux[] = {1541 VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,1542};1543static const unsigned int vin3_field_pins[] = {1544 RCAR_GP_PIN(7, 16),1545};1546static const unsigned int vin3_field_mux[] = {1547 VI3_FIELD_MARK,1548};1549static const unsigned int vin3_clkenb_pins[] = {1550 RCAR_GP_PIN(7, 1),1551};1552static const unsigned int vin3_clkenb_mux[] = {1553 VI3_CLKENB_MARK,1554};1555static const unsigned int vin3_clk_pins[] = {1556 RCAR_GP_PIN(7, 0),1557};1558static const unsigned int vin3_clk_mux[] = {1559 VI3_CLK_MARK,1560};1561/* - VIN4 ------------------------------------------------------------------- */1562static const unsigned int vin4_data_pins[] = {1563 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),1564 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),1565 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),1566 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),1567 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),1568 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),1569};1570static const unsigned int vin4_data_mux[] = {1571 VI4_D0_C0_MARK, VI4_D1_C1_MARK,1572 VI4_D2_C2_MARK, VI4_D3_C3_MARK,1573 VI4_D4_C4_MARK, VI4_D5_C5_MARK,1574 VI4_D6_C6_MARK, VI4_D7_C7_MARK,1575 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,1576 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,1577};1578static const unsigned int vin4_sync_pins[] = {1579 /* HSYNC#, VSYNC# */1580 RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),1581};1582static const unsigned int vin4_sync_mux[] = {1583 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,1584};1585static const unsigned int vin4_field_pins[] = {1586 RCAR_GP_PIN(8, 16),1587};1588static const unsigned int vin4_field_mux[] = {1589 VI4_FIELD_MARK,1590};1591static const unsigned int vin4_clkenb_pins[] = {1592 RCAR_GP_PIN(8, 1),1593};1594static const unsigned int vin4_clkenb_mux[] = {1595 VI4_CLKENB_MARK,1596};1597static const unsigned int vin4_clk_pins[] = {1598 RCAR_GP_PIN(8, 0),1599};1600static const unsigned int vin4_clk_mux[] = {1601 VI4_CLK_MARK,1602};1603/* - VIN5 ------------------------------------------------------------------- */1604static const unsigned int vin5_data_pins[] = {1605 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),1606 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),1607 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),1608 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),1609 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),1610 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),1611};1612static const unsigned int vin5_data_mux[] = {1613 VI5_D0_C0_MARK, VI5_D1_C1_MARK,1614 VI5_D2_C2_MARK, VI5_D3_C3_MARK,1615 VI5_D4_C4_MARK, VI5_D5_C5_MARK,1616 VI5_D6_C6_MARK, VI5_D7_C7_MARK,1617 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,1618 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,1619};1620static const unsigned int vin5_sync_pins[] = {1621 /* HSYNC#, VSYNC# */1622 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),1623};1624static const unsigned int vin5_sync_mux[] = {1625 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,1626};1627static const unsigned int vin5_field_pins[] = {1628 RCAR_GP_PIN(9, 16),1629};1630static const unsigned int vin5_field_mux[] = {1631 VI5_FIELD_MARK,1632};1633static const unsigned int vin5_clkenb_pins[] = {1634 RCAR_GP_PIN(9, 1),1635};1636static const unsigned int vin5_clkenb_mux[] = {1637 VI5_CLKENB_MARK,1638};1639static const unsigned int vin5_clk_pins[] = {1640 RCAR_GP_PIN(9, 0),1641};1642static const unsigned int vin5_clk_mux[] = {1643 VI5_CLK_MARK,1644};1645 1646static const struct sh_pfc_pin_group pinmux_groups[] = {1647 SH_PFC_PIN_GROUP(avb_link),1648 SH_PFC_PIN_GROUP(avb_magic),1649 SH_PFC_PIN_GROUP(avb_phy_int),1650 SH_PFC_PIN_GROUP(avb_mdio),1651 SH_PFC_PIN_GROUP(avb_mii),1652 SH_PFC_PIN_GROUP(avb_gmii),1653 SH_PFC_PIN_GROUP(avb_avtp_match),1654 SH_PFC_PIN_GROUP(can0_data),1655 SH_PFC_PIN_GROUP(can1_data),1656 SH_PFC_PIN_GROUP(can_clk),1657 SH_PFC_PIN_GROUP(du0_rgb666),1658 SH_PFC_PIN_GROUP(du0_rgb888),1659 SH_PFC_PIN_GROUP(du0_sync),1660 SH_PFC_PIN_GROUP(du0_oddf),1661 SH_PFC_PIN_GROUP(du0_disp),1662 SH_PFC_PIN_GROUP(du0_cde),1663 SH_PFC_PIN_GROUP(du1_rgb666),1664 SH_PFC_PIN_GROUP(du1_sync),1665 SH_PFC_PIN_GROUP(du1_oddf),1666 SH_PFC_PIN_GROUP(du1_disp),1667 SH_PFC_PIN_GROUP(du1_cde),1668 SH_PFC_PIN_GROUP(intc_irq0),1669 SH_PFC_PIN_GROUP(intc_irq1),1670 SH_PFC_PIN_GROUP(intc_irq2),1671 SH_PFC_PIN_GROUP(intc_irq3),1672 SH_PFC_PIN_GROUP(lbsc_cs0),1673 SH_PFC_PIN_GROUP(lbsc_cs1),1674 SH_PFC_PIN_GROUP(lbsc_ex_cs0),1675 SH_PFC_PIN_GROUP(lbsc_ex_cs1),1676 SH_PFC_PIN_GROUP(lbsc_ex_cs2),1677 SH_PFC_PIN_GROUP(lbsc_ex_cs3),1678 SH_PFC_PIN_GROUP(lbsc_ex_cs4),1679 SH_PFC_PIN_GROUP(lbsc_ex_cs5),1680 SH_PFC_PIN_GROUP(msiof0_clk),1681 SH_PFC_PIN_GROUP(msiof0_sync),1682 SH_PFC_PIN_GROUP(msiof0_rx),1683 SH_PFC_PIN_GROUP(msiof0_tx),1684 SH_PFC_PIN_GROUP(msiof1_clk),1685 SH_PFC_PIN_GROUP(msiof1_sync),1686 SH_PFC_PIN_GROUP(msiof1_rx),1687 SH_PFC_PIN_GROUP(msiof1_tx),1688 SH_PFC_PIN_GROUP(qspi_ctrl),1689 BUS_DATA_PIN_GROUP(qspi_data, 2),1690 BUS_DATA_PIN_GROUP(qspi_data, 4),1691 SH_PFC_PIN_GROUP(scif0_data),1692 SH_PFC_PIN_GROUP(scif0_clk),1693 SH_PFC_PIN_GROUP(scif0_ctrl),1694 SH_PFC_PIN_GROUP(scif1_data),1695 SH_PFC_PIN_GROUP(scif1_clk),1696 SH_PFC_PIN_GROUP(scif1_ctrl),1697 SH_PFC_PIN_GROUP(scif2_data),1698 SH_PFC_PIN_GROUP(scif2_clk),1699 SH_PFC_PIN_GROUP(scif3_data),1700 SH_PFC_PIN_GROUP(scif3_clk),1701 BUS_DATA_PIN_GROUP(sdhi0_data, 1),1702 BUS_DATA_PIN_GROUP(sdhi0_data, 4),1703 SH_PFC_PIN_GROUP(sdhi0_ctrl),1704 SH_PFC_PIN_GROUP(sdhi0_cd),1705 SH_PFC_PIN_GROUP(sdhi0_wp),1706 BUS_DATA_PIN_GROUP(vin0_data, 24),1707 BUS_DATA_PIN_GROUP(vin0_data, 20),1708 SH_PFC_PIN_GROUP(vin0_data18),1709 BUS_DATA_PIN_GROUP(vin0_data, 16),1710 BUS_DATA_PIN_GROUP(vin0_data, 12),1711 BUS_DATA_PIN_GROUP(vin0_data, 10),1712 BUS_DATA_PIN_GROUP(vin0_data, 8),1713 SH_PFC_PIN_GROUP(vin0_sync),1714 SH_PFC_PIN_GROUP(vin0_field),1715 SH_PFC_PIN_GROUP(vin0_clkenb),1716 SH_PFC_PIN_GROUP(vin0_clk),1717 BUS_DATA_PIN_GROUP(vin1_data, 24),1718 BUS_DATA_PIN_GROUP(vin1_data, 20),1719 SH_PFC_PIN_GROUP(vin1_data18),1720 BUS_DATA_PIN_GROUP(vin1_data, 16),1721 BUS_DATA_PIN_GROUP(vin1_data, 12),1722 BUS_DATA_PIN_GROUP(vin1_data, 10),1723 BUS_DATA_PIN_GROUP(vin1_data, 8),1724 BUS_DATA_PIN_GROUP(vin1_data, 24, _b),1725 BUS_DATA_PIN_GROUP(vin1_data, 20, _b),1726 SH_PFC_PIN_GROUP(vin1_data18_b),1727 BUS_DATA_PIN_GROUP(vin1_data, 16, _b),1728 SH_PFC_PIN_GROUP(vin1_sync),1729 SH_PFC_PIN_GROUP(vin1_field),1730 SH_PFC_PIN_GROUP(vin1_clkenb),1731 SH_PFC_PIN_GROUP(vin1_clk),1732 BUS_DATA_PIN_GROUP(vin2_data, 16),1733 BUS_DATA_PIN_GROUP(vin2_data, 12),1734 BUS_DATA_PIN_GROUP(vin2_data, 10),1735 BUS_DATA_PIN_GROUP(vin2_data, 8),1736 SH_PFC_PIN_GROUP(vin2_sync),1737 SH_PFC_PIN_GROUP(vin2_field),1738 SH_PFC_PIN_GROUP(vin2_clkenb),1739 SH_PFC_PIN_GROUP(vin2_clk),1740 BUS_DATA_PIN_GROUP(vin3_data, 16),1741 BUS_DATA_PIN_GROUP(vin3_data, 12),1742 BUS_DATA_PIN_GROUP(vin3_data, 10),1743 BUS_DATA_PIN_GROUP(vin3_data, 8),1744 SH_PFC_PIN_GROUP(vin3_sync),1745 SH_PFC_PIN_GROUP(vin3_field),1746 SH_PFC_PIN_GROUP(vin3_clkenb),1747 SH_PFC_PIN_GROUP(vin3_clk),1748 BUS_DATA_PIN_GROUP(vin4_data, 12),1749 BUS_DATA_PIN_GROUP(vin4_data, 10),1750 BUS_DATA_PIN_GROUP(vin4_data, 8),1751 SH_PFC_PIN_GROUP(vin4_sync),1752 SH_PFC_PIN_GROUP(vin4_field),1753 SH_PFC_PIN_GROUP(vin4_clkenb),1754 SH_PFC_PIN_GROUP(vin4_clk),1755 BUS_DATA_PIN_GROUP(vin5_data, 12),1756 BUS_DATA_PIN_GROUP(vin5_data, 10),1757 BUS_DATA_PIN_GROUP(vin5_data, 8),1758 SH_PFC_PIN_GROUP(vin5_sync),1759 SH_PFC_PIN_GROUP(vin5_field),1760 SH_PFC_PIN_GROUP(vin5_clkenb),1761 SH_PFC_PIN_GROUP(vin5_clk),1762};1763 1764static const char * const avb_groups[] = {1765 "avb_link",1766 "avb_magic",1767 "avb_phy_int",1768 "avb_mdio",1769 "avb_mii",1770 "avb_gmii",1771 "avb_avtp_match",1772};1773 1774static const char * const can0_groups[] = {1775 "can0_data",1776 "can_clk",1777};1778 1779static const char * const can1_groups[] = {1780 "can1_data",1781 "can_clk",1782};1783 1784static const char * const du0_groups[] = {1785 "du0_rgb666",1786 "du0_rgb888",1787 "du0_sync",1788 "du0_oddf",1789 "du0_disp",1790 "du0_cde",1791};1792 1793static const char * const du1_groups[] = {1794 "du1_rgb666",1795 "du1_sync",1796 "du1_oddf",1797 "du1_disp",1798 "du1_cde",1799};1800 1801static const char * const intc_groups[] = {1802 "intc_irq0",1803 "intc_irq1",1804 "intc_irq2",1805 "intc_irq3",1806};1807 1808static const char * const lbsc_groups[] = {1809 "lbsc_cs0",1810 "lbsc_cs1",1811 "lbsc_ex_cs0",1812 "lbsc_ex_cs1",1813 "lbsc_ex_cs2",1814 "lbsc_ex_cs3",1815 "lbsc_ex_cs4",1816 "lbsc_ex_cs5",1817};1818 1819static const char * const msiof0_groups[] = {1820 "msiof0_clk",1821 "msiof0_sync",1822 "msiof0_rx",1823 "msiof0_tx",1824};1825 1826static const char * const msiof1_groups[] = {1827 "msiof1_clk",1828 "msiof1_sync",1829 "msiof1_rx",1830 "msiof1_tx",1831};1832 1833static const char * const qspi_groups[] = {1834 "qspi_ctrl",1835 "qspi_data2",1836 "qspi_data4",1837};1838 1839static const char * const scif0_groups[] = {1840 "scif0_data",1841 "scif0_clk",1842 "scif0_ctrl",1843};1844 1845static const char * const scif1_groups[] = {1846 "scif1_data",1847 "scif1_clk",1848 "scif1_ctrl",1849};1850 1851static const char * const scif2_groups[] = {1852 "scif2_data",1853 "scif2_clk",1854};1855 1856static const char * const scif3_groups[] = {1857 "scif3_data",1858 "scif3_clk",1859};1860 1861static const char * const sdhi0_groups[] = {1862 "sdhi0_data1",1863 "sdhi0_data4",1864 "sdhi0_ctrl",1865 "sdhi0_cd",1866 "sdhi0_wp",1867};1868 1869static const char * const vin0_groups[] = {1870 "vin0_data24",1871 "vin0_data20",1872 "vin0_data18",1873 "vin0_data16",1874 "vin0_data12",1875 "vin0_data10",1876 "vin0_data8",1877 "vin0_sync",1878 "vin0_field",1879 "vin0_clkenb",1880 "vin0_clk",1881};1882 1883static const char * const vin1_groups[] = {1884 "vin1_data24",1885 "vin1_data20",1886 "vin1_data18",1887 "vin1_data16",1888 "vin1_data12",1889 "vin1_data10",1890 "vin1_data8",1891 "vin1_data24_b",1892 "vin1_data20_b",1893 "vin1_data18_b",1894 "vin1_data16_b",1895 "vin1_sync",1896 "vin1_field",1897 "vin1_clkenb",1898 "vin1_clk",1899};1900 1901static const char * const vin2_groups[] = {1902 "vin2_data16",1903 "vin2_data12",1904 "vin2_data10",1905 "vin2_data8",1906 "vin2_sync",1907 "vin2_field",1908 "vin2_clkenb",1909 "vin2_clk",1910};1911 1912static const char * const vin3_groups[] = {1913 "vin3_data16",1914 "vin3_data12",1915 "vin3_data10",1916 "vin3_data8",1917 "vin3_sync",1918 "vin3_field",1919 "vin3_clkenb",1920 "vin3_clk",1921};1922 1923static const char * const vin4_groups[] = {1924 "vin4_data12",1925 "vin4_data10",1926 "vin4_data8",1927 "vin4_sync",1928 "vin4_field",1929 "vin4_clkenb",1930 "vin4_clk",1931};1932 1933static const char * const vin5_groups[] = {1934 "vin5_data12",1935 "vin5_data10",1936 "vin5_data8",1937 "vin5_sync",1938 "vin5_field",1939 "vin5_clkenb",1940 "vin5_clk",1941};1942 1943static const struct sh_pfc_function pinmux_functions[] = {1944 SH_PFC_FUNCTION(avb),1945 SH_PFC_FUNCTION(can0),1946 SH_PFC_FUNCTION(can1),1947 SH_PFC_FUNCTION(du0),1948 SH_PFC_FUNCTION(du1),1949 SH_PFC_FUNCTION(intc),1950 SH_PFC_FUNCTION(lbsc),1951 SH_PFC_FUNCTION(msiof0),1952 SH_PFC_FUNCTION(msiof1),1953 SH_PFC_FUNCTION(qspi),1954 SH_PFC_FUNCTION(scif0),1955 SH_PFC_FUNCTION(scif1),1956 SH_PFC_FUNCTION(scif2),1957 SH_PFC_FUNCTION(scif3),1958 SH_PFC_FUNCTION(sdhi0),1959 SH_PFC_FUNCTION(vin0),1960 SH_PFC_FUNCTION(vin1),1961 SH_PFC_FUNCTION(vin2),1962 SH_PFC_FUNCTION(vin3),1963 SH_PFC_FUNCTION(vin4),1964 SH_PFC_FUNCTION(vin5),1965};1966 1967static const struct pinmux_cfg_reg pinmux_config_regs[] = {1968 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(1969 0, 0,1970 0, 0,1971 0, 0,1972 GP_0_28_FN, FN_IP1_4,1973 GP_0_27_FN, FN_IP1_3,1974 GP_0_26_FN, FN_IP1_2,1975 GP_0_25_FN, FN_IP1_1,1976 GP_0_24_FN, FN_IP1_0,1977 GP_0_23_FN, FN_IP0_23,1978 GP_0_22_FN, FN_IP0_22,1979 GP_0_21_FN, FN_IP0_21,1980 GP_0_20_FN, FN_IP0_20,1981 GP_0_19_FN, FN_IP0_19,1982 GP_0_18_FN, FN_IP0_18,1983 GP_0_17_FN, FN_IP0_17,1984 GP_0_16_FN, FN_IP0_16,1985 GP_0_15_FN, FN_IP0_15,1986 GP_0_14_FN, FN_IP0_14,1987 GP_0_13_FN, FN_IP0_13,1988 GP_0_12_FN, FN_IP0_12,1989 GP_0_11_FN, FN_IP0_11,1990 GP_0_10_FN, FN_IP0_10,1991 GP_0_9_FN, FN_IP0_9,1992 GP_0_8_FN, FN_IP0_8,1993 GP_0_7_FN, FN_IP0_7,1994 GP_0_6_FN, FN_IP0_6,1995 GP_0_5_FN, FN_IP0_5,1996 GP_0_4_FN, FN_IP0_4,1997 GP_0_3_FN, FN_IP0_3,1998 GP_0_2_FN, FN_IP0_2,1999 GP_0_1_FN, FN_IP0_1,2000 GP_0_0_FN, FN_IP0_0 ))2001 },2002 { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,2003 GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,2004 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),2005 GROUP(2006 /* GP1_31_23 RESERVED */2007 GP_1_22_FN, FN_DU1_CDE,2008 GP_1_21_FN, FN_DU1_DISP,2009 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,2010 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,2011 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,2012 GP_1_17_FN, FN_DU1_DB7_C5,2013 GP_1_16_FN, FN_DU1_DB6_C4,2014 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,2015 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,2016 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,2017 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,2018 GP_1_11_FN, FN_IP1_16,2019 GP_1_10_FN, FN_IP1_15,2020 GP_1_9_FN, FN_IP1_14,2021 GP_1_8_FN, FN_IP1_13,2022 GP_1_7_FN, FN_IP1_12,2023 GP_1_6_FN, FN_IP1_11,2024 GP_1_5_FN, FN_IP1_10,2025 GP_1_4_FN, FN_IP1_9,2026 GP_1_3_FN, FN_IP1_8,2027 GP_1_2_FN, FN_IP1_7,2028 GP_1_1_FN, FN_IP1_6,2029 GP_1_0_FN, FN_IP1_5, ))2030 },2031 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(2032 GP_2_31_FN, FN_A15,2033 GP_2_30_FN, FN_A14,2034 GP_2_29_FN, FN_A13,2035 GP_2_28_FN, FN_A12,2036 GP_2_27_FN, FN_A11,2037 GP_2_26_FN, FN_A10,2038 GP_2_25_FN, FN_A9,2039 GP_2_24_FN, FN_A8,2040 GP_2_23_FN, FN_A7,2041 GP_2_22_FN, FN_A6,2042 GP_2_21_FN, FN_A5,2043 GP_2_20_FN, FN_A4,2044 GP_2_19_FN, FN_A3,2045 GP_2_18_FN, FN_A2,2046 GP_2_17_FN, FN_A1,2047 GP_2_16_FN, FN_A0,2048 GP_2_15_FN, FN_D15,2049 GP_2_14_FN, FN_D14,2050 GP_2_13_FN, FN_D13,2051 GP_2_12_FN, FN_D12,2052 GP_2_11_FN, FN_D11,2053 GP_2_10_FN, FN_D10,2054 GP_2_9_FN, FN_D9,2055 GP_2_8_FN, FN_D8,2056 GP_2_7_FN, FN_D7,2057 GP_2_6_FN, FN_D6,2058 GP_2_5_FN, FN_D5,2059 GP_2_4_FN, FN_D4,2060 GP_2_3_FN, FN_D3,2061 GP_2_2_FN, FN_D2,2062 GP_2_1_FN, FN_D1,2063 GP_2_0_FN, FN_D0 ))2064 },2065 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(2066 0, 0,2067 0, 0,2068 0, 0,2069 0, 0,2070 GP_3_27_FN, FN_CS0_N,2071 GP_3_26_FN, FN_IP1_22,2072 GP_3_25_FN, FN_IP1_21,2073 GP_3_24_FN, FN_IP1_20,2074 GP_3_23_FN, FN_IP1_19,2075 GP_3_22_FN, FN_IRQ3,2076 GP_3_21_FN, FN_IRQ2,2077 GP_3_20_FN, FN_IRQ1,2078 GP_3_19_FN, FN_IRQ0,2079 GP_3_18_FN, FN_EX_WAIT0,2080 GP_3_17_FN, FN_WE1_N,2081 GP_3_16_FN, FN_WE0_N,2082 GP_3_15_FN, FN_RD_WR_N,2083 GP_3_14_FN, FN_RD_N,2084 GP_3_13_FN, FN_BS_N,2085 GP_3_12_FN, FN_EX_CS5_N,2086 GP_3_11_FN, FN_EX_CS4_N,2087 GP_3_10_FN, FN_EX_CS3_N,2088 GP_3_9_FN, FN_EX_CS2_N,2089 GP_3_8_FN, FN_EX_CS1_N,2090 GP_3_7_FN, FN_EX_CS0_N,2091 GP_3_6_FN, FN_CS1_N_A26,2092 GP_3_5_FN, FN_IP1_18,2093 GP_3_4_FN, FN_IP1_17,2094 GP_3_3_FN, FN_A19,2095 GP_3_2_FN, FN_A18,2096 GP_3_1_FN, FN_A17,2097 GP_3_0_FN, FN_A16 ))2098 },2099 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060014, 32,2100 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,2101 1, 1, 1, 1, 1, 1),2102 GROUP(2103 /* GP4_31_17 RESERVED */2104 GP_4_16_FN, FN_VI0_FIELD,2105 GP_4_15_FN, FN_VI0_D11_G3_Y3,2106 GP_4_14_FN, FN_VI0_D10_G2_Y2,2107 GP_4_13_FN, FN_VI0_D9_G1_Y1,2108 GP_4_12_FN, FN_VI0_D8_G0_Y0,2109 GP_4_11_FN, FN_VI0_D7_B7_C7,2110 GP_4_10_FN, FN_VI0_D6_B6_C6,2111 GP_4_9_FN, FN_VI0_D5_B5_C5,2112 GP_4_8_FN, FN_VI0_D4_B4_C4,2113 GP_4_7_FN, FN_VI0_D3_B3_C3,2114 GP_4_6_FN, FN_VI0_D2_B2_C2,2115 GP_4_5_FN, FN_VI0_D1_B1_C1,2116 GP_4_4_FN, FN_VI0_D0_B0_C0,2117 GP_4_3_FN, FN_VI0_VSYNC_N,2118 GP_4_2_FN, FN_VI0_HSYNC_N,2119 GP_4_1_FN, FN_VI0_CLKENB,2120 GP_4_0_FN, FN_VI0_CLK ))2121 },2122 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060018, 32,2123 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,2124 1, 1, 1, 1, 1, 1),2125 GROUP(2126 /* GP5_31_17 RESERVED */2127 GP_5_16_FN, FN_VI1_FIELD,2128 GP_5_15_FN, FN_VI1_D11_G3_Y3,2129 GP_5_14_FN, FN_VI1_D10_G2_Y2,2130 GP_5_13_FN, FN_VI1_D9_G1_Y1,2131 GP_5_12_FN, FN_VI1_D8_G0_Y0,2132 GP_5_11_FN, FN_VI1_D7_B7_C7,2133 GP_5_10_FN, FN_VI1_D6_B6_C6,2134 GP_5_9_FN, FN_VI1_D5_B5_C5,2135 GP_5_8_FN, FN_VI1_D4_B4_C4,2136 GP_5_7_FN, FN_VI1_D3_B3_C3,2137 GP_5_6_FN, FN_VI1_D2_B2_C2,2138 GP_5_5_FN, FN_VI1_D1_B1_C1,2139 GP_5_4_FN, FN_VI1_D0_B0_C0,2140 GP_5_3_FN, FN_VI1_VSYNC_N,2141 GP_5_2_FN, FN_VI1_HSYNC_N,2142 GP_5_1_FN, FN_VI1_CLKENB,2143 GP_5_0_FN, FN_VI1_CLK ))2144 },2145 { PINMUX_CFG_REG_VAR("GPSR6", 0xE606001C, 32,2146 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,2147 1, 1, 1, 1, 1, 1),2148 GROUP(2149 /* GP6_31_17 RESERVED */2150 GP_6_16_FN, FN_IP2_16,2151 GP_6_15_FN, FN_IP2_15,2152 GP_6_14_FN, FN_IP2_14,2153 GP_6_13_FN, FN_IP2_13,2154 GP_6_12_FN, FN_IP2_12,2155 GP_6_11_FN, FN_IP2_11,2156 GP_6_10_FN, FN_IP2_10,2157 GP_6_9_FN, FN_IP2_9,2158 GP_6_8_FN, FN_IP2_8,2159 GP_6_7_FN, FN_IP2_7,2160 GP_6_6_FN, FN_IP2_6,2161 GP_6_5_FN, FN_IP2_5,2162 GP_6_4_FN, FN_IP2_4,2163 GP_6_3_FN, FN_IP2_3,2164 GP_6_2_FN, FN_IP2_2,2165 GP_6_1_FN, FN_IP2_1,2166 GP_6_0_FN, FN_IP2_0 ))2167 },2168 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6060020, 32,2169 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,2170 1, 1, 1, 1, 1, 1),2171 GROUP(2172 /* GP7_31_17 RESERVED */2173 GP_7_16_FN, FN_VI3_FIELD,2174 GP_7_15_FN, FN_IP3_14,2175 GP_7_14_FN, FN_VI3_D10_Y2,2176 GP_7_13_FN, FN_IP3_13,2177 GP_7_12_FN, FN_IP3_12,2178 GP_7_11_FN, FN_IP3_11,2179 GP_7_10_FN, FN_IP3_10,2180 GP_7_9_FN, FN_IP3_9,2181 GP_7_8_FN, FN_IP3_8,2182 GP_7_7_FN, FN_IP3_7,2183 GP_7_6_FN, FN_IP3_6,2184 GP_7_5_FN, FN_IP3_5,2185 GP_7_4_FN, FN_IP3_4,2186 GP_7_3_FN, FN_IP3_3,2187 GP_7_2_FN, FN_IP3_2,2188 GP_7_1_FN, FN_IP3_1,2189 GP_7_0_FN, FN_IP3_0 ))2190 },2191 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6060024, 32,2192 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,2193 1, 1, 1, 1, 1, 1),2194 GROUP(2195 /* GP8_31_17 RESERVED */2196 GP_8_16_FN, FN_IP4_24,2197 GP_8_15_FN, FN_IP4_23,2198 GP_8_14_FN, FN_IP4_22,2199 GP_8_13_FN, FN_IP4_21,2200 GP_8_12_FN, FN_IP4_20_19,2201 GP_8_11_FN, FN_IP4_18_17,2202 GP_8_10_FN, FN_IP4_16_15,2203 GP_8_9_FN, FN_IP4_14_13,2204 GP_8_8_FN, FN_IP4_12_11,2205 GP_8_7_FN, FN_IP4_10_9,2206 GP_8_6_FN, FN_IP4_8_7,2207 GP_8_5_FN, FN_IP4_6_5,2208 GP_8_4_FN, FN_IP4_4,2209 GP_8_3_FN, FN_IP4_3_2,2210 GP_8_2_FN, FN_IP4_1,2211 GP_8_1_FN, FN_IP4_0,2212 GP_8_0_FN, FN_VI4_CLK ))2213 },2214 { PINMUX_CFG_REG_VAR("GPSR9", 0xE6060028, 32,2215 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,2216 1, 1, 1, 1, 1, 1),2217 GROUP(2218 /* GP9_31_17 RESERVED */2219 GP_9_16_FN, FN_VI5_FIELD,2220 GP_9_15_FN, FN_VI5_D11_Y3,2221 GP_9_14_FN, FN_VI5_D10_Y2,2222 GP_9_13_FN, FN_VI5_D9_Y1,2223 GP_9_12_FN, FN_IP5_11,2224 GP_9_11_FN, FN_IP5_10,2225 GP_9_10_FN, FN_IP5_9,2226 GP_9_9_FN, FN_IP5_8,2227 GP_9_8_FN, FN_IP5_7,2228 GP_9_7_FN, FN_IP5_6,2229 GP_9_6_FN, FN_IP5_5,2230 GP_9_5_FN, FN_IP5_4,2231 GP_9_4_FN, FN_IP5_3,2232 GP_9_3_FN, FN_IP5_2,2233 GP_9_2_FN, FN_IP5_1,2234 GP_9_1_FN, FN_IP5_0,2235 GP_9_0_FN, FN_VI5_CLK ))2236 },2237 { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(2238 GP_10_31_FN, FN_CAN1_RX,2239 GP_10_30_FN, FN_CAN1_TX,2240 GP_10_29_FN, FN_CAN_CLK,2241 GP_10_28_FN, FN_CAN0_RX,2242 GP_10_27_FN, FN_CAN0_TX,2243 GP_10_26_FN, FN_SCIF_CLK,2244 GP_10_25_FN, FN_IP6_18_17,2245 GP_10_24_FN, FN_IP6_16,2246 GP_10_23_FN, FN_IP6_15_14,2247 GP_10_22_FN, FN_IP6_13_12,2248 GP_10_21_FN, FN_IP6_11_10,2249 GP_10_20_FN, FN_IP6_9_8,2250 GP_10_19_FN, FN_RX1,2251 GP_10_18_FN, FN_TX1,2252 GP_10_17_FN, FN_RTS1_N,2253 GP_10_16_FN, FN_CTS1_N,2254 GP_10_15_FN, FN_SCK1,2255 GP_10_14_FN, FN_RX0,2256 GP_10_13_FN, FN_TX0,2257 GP_10_12_FN, FN_RTS0_N,2258 GP_10_11_FN, FN_CTS0_N,2259 GP_10_10_FN, FN_SCK0,2260 GP_10_9_FN, FN_IP6_7,2261 GP_10_8_FN, FN_IP6_6,2262 GP_10_7_FN, FN_HCTS1_N,2263 GP_10_6_FN, FN_IP6_5,2264 GP_10_5_FN, FN_IP6_4,2265 GP_10_4_FN, FN_IP6_3,2266 GP_10_3_FN, FN_IP6_2,2267 GP_10_2_FN, FN_HRTS0_N,2268 GP_10_1_FN, FN_IP6_1,2269 GP_10_0_FN, FN_IP6_0 ))2270 },2271 { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(2272 0, 0,2273 0, 0,2274 GP_11_29_FN, FN_AVS2,2275 GP_11_28_FN, FN_AVS1,2276 GP_11_27_FN, FN_ADICHS2,2277 GP_11_26_FN, FN_ADICHS1,2278 GP_11_25_FN, FN_ADICHS0,2279 GP_11_24_FN, FN_ADIDATA,2280 GP_11_23_FN, FN_ADICS_SAMP,2281 GP_11_22_FN, FN_ADICLK,2282 GP_11_21_FN, FN_IP7_20,2283 GP_11_20_FN, FN_IP7_19,2284 GP_11_19_FN, FN_IP7_18,2285 GP_11_18_FN, FN_IP7_17,2286 GP_11_17_FN, FN_IP7_16,2287 GP_11_16_FN, FN_IP7_15_14,2288 GP_11_15_FN, FN_IP7_13_12,2289 GP_11_14_FN, FN_IP7_11_10,2290 GP_11_13_FN, FN_IP7_9_8,2291 GP_11_12_FN, FN_SD0_WP,2292 GP_11_11_FN, FN_SD0_CD,2293 GP_11_10_FN, FN_SD0_DAT3,2294 GP_11_9_FN, FN_SD0_DAT2,2295 GP_11_8_FN, FN_SD0_DAT1,2296 GP_11_7_FN, FN_SD0_DAT0,2297 GP_11_6_FN, FN_SD0_CMD,2298 GP_11_5_FN, FN_SD0_CLK,2299 GP_11_4_FN, FN_IP7_7,2300 GP_11_3_FN, FN_IP7_6,2301 GP_11_2_FN, FN_IP7_5_4,2302 GP_11_1_FN, FN_IP7_3_2,2303 GP_11_0_FN, FN_IP7_1_0 ))2304 },2305 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,2306 GROUP(-8,2307 1, 1, 1, 1, 1, 1, 1, 1,2308 1, 1, 1, 1, 1, 1, 1, 1,2309 1, 1, 1, 1, 1, 1, 1, 1),2310 GROUP(2311 /* IP0_31_24 [8] RESERVED */2312 /* IP0_23 [1] */2313 FN_DU0_DB7_C5, 0,2314 /* IP0_22 [1] */2315 FN_DU0_DB6_C4, 0,2316 /* IP0_21 [1] */2317 FN_DU0_DB5_C3, 0,2318 /* IP0_20 [1] */2319 FN_DU0_DB4_C2, 0,2320 /* IP0_19 [1] */2321 FN_DU0_DB3_C1, 0,2322 /* IP0_18 [1] */2323 FN_DU0_DB2_C0, 0,2324 /* IP0_17 [1] */2325 FN_DU0_DB1, 0,2326 /* IP0_16 [1] */2327 FN_DU0_DB0, 0,2328 /* IP0_15 [1] */2329 FN_DU0_DG7_Y3_DATA15, 0,2330 /* IP0_14 [1] */2331 FN_DU0_DG6_Y2_DATA14, 0,2332 /* IP0_13 [1] */2333 FN_DU0_DG5_Y1_DATA13, 0,2334 /* IP0_12 [1] */2335 FN_DU0_DG4_Y0_DATA12, 0,2336 /* IP0_11 [1] */2337 FN_DU0_DG3_C7_DATA11, 0,2338 /* IP0_10 [1] */2339 FN_DU0_DG2_C6_DATA10, 0,2340 /* IP0_9 [1] */2341 FN_DU0_DG1_DATA9, 0,2342 /* IP0_8 [1] */2343 FN_DU0_DG0_DATA8, 0,2344 /* IP0_7 [1] */2345 FN_DU0_DR7_Y9_DATA7, 0,2346 /* IP0_6 [1] */2347 FN_DU0_DR6_Y8_DATA6, 0,2348 /* IP0_5 [1] */2349 FN_DU0_DR5_Y7_DATA5, 0,2350 /* IP0_4 [1] */2351 FN_DU0_DR4_Y6_DATA4, 0,2352 /* IP0_3 [1] */2353 FN_DU0_DR3_Y5_DATA3, 0,2354 /* IP0_2 [1] */2355 FN_DU0_DR2_Y4_DATA2, 0,2356 /* IP0_1 [1] */2357 FN_DU0_DR1_DATA1, 0,2358 /* IP0_0 [1] */2359 FN_DU0_DR0_DATA0, 0 ))2360 },2361 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,2362 GROUP(-9, 1, 1, 1, 1, 1, 1, 1,2363 1, 1, 1, 1, 1, 1, 1, 1,2364 1, 1, 1, 1, 1, 1, 1, 1),2365 GROUP(2366 /* IP1_31_23 [9] RESERVED */2367 /* IP1_22 [1] */2368 FN_A25, FN_SSL,2369 /* IP1_21 [1] */2370 FN_A24, FN_SPCLK,2371 /* IP1_20 [1] */2372 FN_A23, FN_IO3,2373 /* IP1_19 [1] */2374 FN_A22, FN_IO2,2375 /* IP1_18 [1] */2376 FN_A21, FN_MISO_IO1,2377 /* IP1_17 [1] */2378 FN_A20, FN_MOSI_IO0,2379 /* IP1_16 [1] */2380 FN_DU1_DG7_Y3_DATA11, 0,2381 /* IP1_15 [1] */2382 FN_DU1_DG6_Y2_DATA10, 0,2383 /* IP1_14 [1] */2384 FN_DU1_DG5_Y1_DATA9, 0,2385 /* IP1_13 [1] */2386 FN_DU1_DG4_Y0_DATA8, 0,2387 /* IP1_12 [1] */2388 FN_DU1_DG3_C7_DATA7, 0,2389 /* IP1_11 [1] */2390 FN_DU1_DG2_C6_DATA6, 0,2391 /* IP1_10 [1] */2392 FN_DU1_DR7_DATA5, 0,2393 /* IP1_9 [1] */2394 FN_DU1_DR6_DATA4, 0,2395 /* IP1_8 [1] */2396 FN_DU1_DR5_Y7_DATA3, 0,2397 /* IP1_7 [1] */2398 FN_DU1_DR4_Y6_DATA2, 0,2399 /* IP1_6 [1] */2400 FN_DU1_DR3_Y5_DATA1, 0,2401 /* IP1_5 [1] */2402 FN_DU1_DR2_Y4_DATA0, 0,2403 /* IP1_4 [1] */2404 FN_DU0_CDE, 0,2405 /* IP1_3 [1] */2406 FN_DU0_DISP, 0,2407 /* IP1_2 [1] */2408 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,2409 /* IP1_1 [1] */2410 FN_DU0_EXVSYNC_DU0_VSYNC, 0,2411 /* IP1_0 [1] */2412 FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))2413 },2414 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,2415 GROUP(-15, 1,2416 1, 1, 1, 1, 1, 1, 1, 1,2417 1, 1, 1, 1, 1, 1, 1, 1),2418 GROUP(2419 /* IP2_31_17 [15] RESERVED */2420 /* IP2_16 [1] */2421 FN_VI2_FIELD, FN_AVB_TXD2,2422 /* IP2_15 [1] */2423 FN_VI2_D11_Y3, FN_AVB_TXD1,2424 /* IP2_14 [1] */2425 FN_VI2_D10_Y2, FN_AVB_TXD0,2426 /* IP2_13 [1] */2427 FN_VI2_D9_Y1, FN_AVB_TX_EN,2428 /* IP2_12 [1] */2429 FN_VI2_D8_Y0, FN_AVB_TXD3,2430 /* IP2_11 [1] */2431 FN_VI2_D7_C7, FN_AVB_COL,2432 /* IP2_10 [1] */2433 FN_VI2_D6_C6, FN_AVB_RX_ER,2434 /* IP2_9 [1] */2435 FN_VI2_D5_C5, FN_AVB_RXD7,2436 /* IP2_8 [1] */2437 FN_VI2_D4_C4, FN_AVB_RXD6,2438 /* IP2_7 [1] */2439 FN_VI2_D3_C3, FN_AVB_RXD5,2440 /* IP2_6 [1] */2441 FN_VI2_D2_C2, FN_AVB_RXD4,2442 /* IP2_5 [1] */2443 FN_VI2_D1_C1, FN_AVB_RXD3,2444 /* IP2_4 [1] */2445 FN_VI2_D0_C0, FN_AVB_RXD2,2446 /* IP2_3 [1] */2447 FN_VI2_VSYNC_N, FN_AVB_RXD1,2448 /* IP2_2 [1] */2449 FN_VI2_HSYNC_N, FN_AVB_RXD0,2450 /* IP2_1 [1] */2451 FN_VI2_CLKENB, FN_AVB_RX_DV,2452 /* IP2_0 [1] */2453 FN_VI2_CLK, FN_AVB_RX_CLK ))2454 },2455 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,2456 GROUP(-17, 1, 1, 1, 1, 1, 1, 1,2457 1, 1, 1, 1, 1, 1, 1, 1),2458 GROUP(2459 /* IP3_31_15 [17] RESERVED */2460 /* IP3_14 [1] */2461 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,2462 /* IP3_13 [1] */2463 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,2464 /* IP3_12 [1] */2465 FN_VI3_D8_Y0, FN_AVB_CRS,2466 /* IP3_11 [1] */2467 FN_VI3_D7_C7, FN_AVB_PHY_INT,2468 /* IP3_10 [1] */2469 FN_VI3_D6_C6, FN_AVB_MAGIC,2470 /* IP3_9 [1] */2471 FN_VI3_D5_C5, FN_AVB_LINK,2472 /* IP3_8 [1] */2473 FN_VI3_D4_C4, FN_AVB_MDIO,2474 /* IP3_7 [1] */2475 FN_VI3_D3_C3, FN_AVB_MDC,2476 /* IP3_6 [1] */2477 FN_VI3_D2_C2, FN_AVB_GTX_CLK,2478 /* IP3_5 [1] */2479 FN_VI3_D1_C1, FN_AVB_TX_ER,2480 /* IP3_4 [1] */2481 FN_VI3_D0_C0, FN_AVB_TXD7,2482 /* IP3_3 [1] */2483 FN_VI3_VSYNC_N, FN_AVB_TXD6,2484 /* IP3_2 [1] */2485 FN_VI3_HSYNC_N, FN_AVB_TXD5,2486 /* IP3_1 [1] */2487 FN_VI3_CLKENB, FN_AVB_TXD4,2488 /* IP3_0 [1] */2489 FN_VI3_CLK, FN_AVB_TX_CLK ))2490 },2491 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,2492 GROUP(-7, 1, 1, 1, 1, 2, 2, 2,2493 2, 2, 2, 2, 2, 1, 2, 1, 1),2494 GROUP(2495 /* IP4_31_25 [7] RESERVED */2496 /* IP4_24 [1] */2497 FN_VI4_FIELD, FN_VI3_D15_Y7,2498 /* IP4_23 [1] */2499 FN_VI4_D11_Y3, FN_VI3_D14_Y6,2500 /* IP4_22 [1] */2501 FN_VI4_D10_Y2, FN_VI3_D13_Y5,2502 /* IP4_21 [1] */2503 FN_VI4_D9_Y1, FN_VI3_D12_Y4,2504 /* IP4_20_19 [2] */2505 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,2506 /* IP4_18_17 [2] */2507 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,2508 /* IP4_16_15 [2] */2509 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,2510 /* IP4_14_13 [2] */2511 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,2512 /* IP4_12_11 [2] */2513 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,2514 /* IP4_10_9 [2] */2515 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,2516 /* IP4_8_7 [2] */2517 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,2518 /* IP4_6_5 [2] */2519 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,2520 /* IP4_4 [1] */2521 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,2522 /* IP4_3_2 [2] */2523 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,2524 /* IP4_1 [1] */2525 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,2526 /* IP4_0 [1] */2527 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))2528 },2529 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,2530 GROUP(-20, 1, 1, 1, 1,2531 1, 1, 1, 1, 1, 1, 1, 1),2532 GROUP(2533 /* IP5_31_12 [20] RESERVED */2534 /* IP5_11 [1] */2535 FN_VI5_D8_Y0, FN_VI1_D23_R7,2536 /* IP5_10 [1] */2537 FN_VI5_D7_C7, FN_VI1_D22_R6,2538 /* IP5_9 [1] */2539 FN_VI5_D6_C6, FN_VI1_D21_R5,2540 /* IP5_8 [1] */2541 FN_VI5_D5_C5, FN_VI1_D20_R4,2542 /* IP5_7 [1] */2543 FN_VI5_D4_C4, FN_VI1_D19_R3,2544 /* IP5_6 [1] */2545 FN_VI5_D3_C3, FN_VI1_D18_R2,2546 /* IP5_5 [1] */2547 FN_VI5_D2_C2, FN_VI1_D17_R1,2548 /* IP5_4 [1] */2549 FN_VI5_D1_C1, FN_VI1_D16_R0,2550 /* IP5_3 [1] */2551 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,2552 /* IP5_2 [1] */2553 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,2554 /* IP5_1 [1] */2555 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,2556 /* IP5_0 [1] */2557 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))2558 },2559 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,2560 GROUP(-13, 2, 1, 2, 2, 2, 2,2561 1, 1, 1, 1, 1, 1, 1, 1),2562 GROUP(2563 /* IP6_31_19 [13] RESERVED */2564 /* IP6_18_17 [2] */2565 FN_DREQ1_N, FN_RX3, 0, 0,2566 /* IP6_16 [1] */2567 FN_TX3, 0,2568 /* IP6_15_14 [2] */2569 FN_DACK1, FN_SCK3, 0, 0,2570 /* IP6_13_12 [2] */2571 FN_DREQ0_N, FN_RX2, 0, 0,2572 /* IP6_11_10 [2] */2573 FN_DACK0, FN_TX2, 0, 0,2574 /* IP6_9_8 [2] */2575 FN_DRACK0, FN_SCK2, 0, 0,2576 /* IP6_7 [1] */2577 FN_MSIOF1_RXD, FN_HRX1,2578 /* IP6_6 [1] */2579 FN_MSIOF1_TXD, FN_HTX1,2580 /* IP6_5 [1] */2581 FN_MSIOF1_SYNC, FN_HRTS1_N,2582 /* IP6_4 [1] */2583 FN_MSIOF1_SCK, FN_HSCK1,2584 /* IP6_3 [1] */2585 FN_MSIOF0_RXD, FN_HRX0,2586 /* IP6_2 [1] */2587 FN_MSIOF0_TXD, FN_HTX0,2588 /* IP6_1 [1] */2589 FN_MSIOF0_SYNC, FN_HCTS0_N,2590 /* IP6_0 [1] */2591 FN_MSIOF0_SCK, FN_HSCK0 ))2592 },2593 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,2594 GROUP(-11, 1, 1, 1, 1, 1,2595 2, 2, 2, 2,2596 1, 1, 2, 2, 2),2597 GROUP(2598 /* IP7_31_21 [11] RESERVED */2599 /* IP7_20 [1] */2600 FN_AUDIO_CLKB, 0,2601 /* IP7_19 [1] */2602 FN_AUDIO_CLKA, 0,2603 /* IP7_18 [1] */2604 FN_AUDIO_CLKOUT, 0,2605 /* IP7_17 [1] */2606 FN_SSI_SDATA4, 0,2607 /* IP7_16 [1] */2608 FN_SSI_WS4, 0,2609 /* IP7_15_14 [2] */2610 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,2611 /* IP7_13_12 [2] */2612 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,2613 /* IP7_11_10 [2] */2614 FN_SSI_WS34, FN_TPU0TO1, 0, 0,2615 /* IP7_9_8 [2] */2616 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,2617 /* IP7_7 [1] */2618 FN_PWM4, 0,2619 /* IP7_6 [1] */2620 FN_PWM3, 0,2621 /* IP7_5_4 [2] */2622 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,2623 /* IP7_3_2 [2] */2624 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,2625 /* IP7_1_0 [2] */2626 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))2627 },2628 { /* sentinel */ }2629};2630 2631static const struct pinmux_bias_reg pinmux_bias_regs[] = {2632 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {2633 [ 0] = RCAR_GP_PIN(0, 0), /* DU0_DR0_DATA0 */2634 [ 1] = RCAR_GP_PIN(0, 1), /* DU0_DR1_DATA1 */2635 [ 2] = RCAR_GP_PIN(0, 2), /* DU0_DR2_Y4_DATA2 */2636 [ 3] = RCAR_GP_PIN(0, 3), /* DU0_DR3_Y5_DATA3 */2637 [ 4] = RCAR_GP_PIN(0, 4), /* DU0_DR4_Y6_DATA4 */2638 [ 5] = RCAR_GP_PIN(0, 5), /* DU0_DR5_Y7_DATA5 */2639 [ 6] = RCAR_GP_PIN(0, 6), /* DU0_DR6_Y8_DATA6 */2640 [ 7] = RCAR_GP_PIN(0, 7), /* DU0_DR7_Y9_DATA7 */2641 [ 8] = RCAR_GP_PIN(0, 8), /* DU0_DG0_DATA8 */2642 [ 9] = RCAR_GP_PIN(0, 9), /* DU0_DG1_DATA9 */2643 [10] = RCAR_GP_PIN(0, 10), /* DU0_DG2_C6_DATA10 */2644 [11] = RCAR_GP_PIN(0, 11), /* DU0_DG3_C7_DATA11 */2645 [12] = RCAR_GP_PIN(0, 12), /* DU0_DG4_Y0_DATA12 */2646 [13] = RCAR_GP_PIN(0, 13), /* DU0_DG5_Y1_DATA13 */2647 [14] = RCAR_GP_PIN(0, 14), /* DU0_DG6_Y2_DATA14 */2648 [15] = RCAR_GP_PIN(0, 15), /* DU0_DG7_Y3_DATA15 */2649 [16] = RCAR_GP_PIN(0, 16), /* DU0_DB0 */2650 [17] = RCAR_GP_PIN(0, 17), /* DU0_DB1 */2651 [18] = RCAR_GP_PIN(0, 18), /* DU0_DB2_C0 */2652 [19] = RCAR_GP_PIN(0, 19), /* DU0_DB3_C1 */2653 [20] = RCAR_GP_PIN(0, 20), /* DU0_DB4_C2 */2654 [21] = RCAR_GP_PIN(0, 21), /* DU0_DB5_C3 */2655 [22] = RCAR_GP_PIN(0, 22), /* DU0_DB6_C4 */2656 [23] = RCAR_GP_PIN(0, 23), /* DU0_DB7_C5 */2657 [24] = RCAR_GP_PIN(0, 24), /* DU0_EXHSYNC/DU0_HSYNC */2658 [25] = RCAR_GP_PIN(0, 25), /* DU0_EXVSYNC/DU0_VSYNC */2659 [26] = RCAR_GP_PIN(0, 26), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */2660 [27] = RCAR_GP_PIN(0, 27), /* DU0_DISP */2661 [28] = RCAR_GP_PIN(0, 28), /* DU0_CDE */2662 [29] = SH_PFC_PIN_NONE,2663 [30] = SH_PFC_PIN_NONE,2664 [31] = SH_PFC_PIN_NONE,2665 } },2666 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {2667 [ 0] = RCAR_GP_PIN(1, 0), /* DU1_DR2_Y4_DATA0 */2668 [ 1] = RCAR_GP_PIN(1, 1), /* DU1_DR3_Y5_DATA1 */2669 [ 2] = RCAR_GP_PIN(1, 2), /* DU1_DR4_Y6_DATA2 */2670 [ 3] = RCAR_GP_PIN(1, 3), /* DU1_DR5_Y7_DATA3 */2671 [ 4] = RCAR_GP_PIN(1, 4), /* DU1_DR6_DATA4 */2672 [ 5] = RCAR_GP_PIN(1, 5), /* DU1_DR7_DATA5 */2673 [ 6] = RCAR_GP_PIN(1, 6), /* DU1_DG2_C6_DATA6 */2674 [ 7] = RCAR_GP_PIN(1, 7), /* DU1_DG3_C7_DATA7 */2675 [ 8] = RCAR_GP_PIN(1, 8), /* DU1_DG4_Y0_DATA8 */2676 [ 9] = RCAR_GP_PIN(1, 9), /* DU1_DG5_Y1_DATA9 */2677 [10] = RCAR_GP_PIN(1, 10), /* DU1_DG6_Y2_DATA10 */2678 [11] = RCAR_GP_PIN(1, 11), /* DU1_DG7_Y3_DATA11 */2679 [12] = RCAR_GP_PIN(1, 12), /* DU1_DB2_C0_DATA12 */2680 [13] = RCAR_GP_PIN(1, 13), /* DU1_DB3_C1_DATA13 */2681 [14] = RCAR_GP_PIN(1, 14), /* DU1_DB4_C2_DATA14 */2682 [15] = RCAR_GP_PIN(1, 15), /* DU1_DB5_C3_DATA15 */2683 [16] = RCAR_GP_PIN(1, 16), /* DU1_DB6_C4 */2684 [17] = RCAR_GP_PIN(1, 17), /* DU1_DB7_C5 */2685 [18] = RCAR_GP_PIN(1, 18), /* DU1_EXHSYNC/DU1_HSYNC */2686 [19] = RCAR_GP_PIN(1, 19), /* DU1_EXVSYNC/DU1_VSYNC */2687 [20] = RCAR_GP_PIN(1, 20), /* DU1_EXODDF/DU1_ODDF_DISP_CDE */2688 [21] = RCAR_GP_PIN(1, 21), /* DU1_DISP */2689 [22] = RCAR_GP_PIN(1, 22), /* DU1_CDE */2690 [23] = SH_PFC_PIN_NONE,2691 [24] = SH_PFC_PIN_NONE,2692 [25] = SH_PFC_PIN_NONE,2693 [26] = SH_PFC_PIN_NONE,2694 [27] = SH_PFC_PIN_NONE,2695 [28] = SH_PFC_PIN_NONE,2696 [29] = SH_PFC_PIN_NONE,2697 [30] = SH_PFC_PIN_NONE,2698 [31] = SH_PFC_PIN_NONE,2699 } },2700 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {2701 [ 0] = RCAR_GP_PIN(2, 0), /* D0 */2702 [ 1] = RCAR_GP_PIN(2, 1), /* D1 */2703 [ 2] = RCAR_GP_PIN(2, 2), /* D2 */2704 [ 3] = RCAR_GP_PIN(2, 3), /* D3 */2705 [ 4] = RCAR_GP_PIN(2, 4), /* D4 */2706 [ 5] = RCAR_GP_PIN(2, 5), /* D5 */2707 [ 6] = RCAR_GP_PIN(2, 6), /* D6 */2708 [ 7] = RCAR_GP_PIN(2, 7), /* D7 */2709 [ 8] = RCAR_GP_PIN(2, 8), /* D8 */2710 [ 9] = RCAR_GP_PIN(2, 9), /* D9 */2711 [10] = RCAR_GP_PIN(2, 10), /* D10 */2712 [11] = RCAR_GP_PIN(2, 11), /* D11 */2713 [12] = RCAR_GP_PIN(2, 12), /* D12 */2714 [13] = RCAR_GP_PIN(2, 13), /* D13 */2715 [14] = RCAR_GP_PIN(2, 14), /* D14 */2716 [15] = RCAR_GP_PIN(2, 15), /* D15 */2717 [16] = RCAR_GP_PIN(2, 16), /* A0 */2718 [17] = RCAR_GP_PIN(2, 17), /* A1 */2719 [18] = RCAR_GP_PIN(2, 18), /* A2 */2720 [19] = RCAR_GP_PIN(2, 19), /* A3 */2721 [20] = RCAR_GP_PIN(2, 20), /* A4 */2722 [21] = RCAR_GP_PIN(2, 21), /* A5 */2723 [22] = RCAR_GP_PIN(2, 22), /* A6 */2724 [23] = RCAR_GP_PIN(2, 23), /* A7 */2725 [24] = RCAR_GP_PIN(2, 24), /* A8 */2726 [25] = RCAR_GP_PIN(2, 25), /* A9 */2727 [26] = RCAR_GP_PIN(2, 26), /* A10 */2728 [27] = RCAR_GP_PIN(2, 27), /* A11 */2729 [28] = RCAR_GP_PIN(2, 28), /* A12 */2730 [29] = RCAR_GP_PIN(2, 29), /* A13 */2731 [30] = RCAR_GP_PIN(2, 30), /* A14 */2732 [31] = RCAR_GP_PIN(2, 31), /* A15 */2733 } },2734 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {2735 [ 0] = RCAR_GP_PIN(3, 0), /* A16 */2736 [ 1] = RCAR_GP_PIN(3, 1), /* A17 */2737 [ 2] = RCAR_GP_PIN(3, 2), /* A18 */2738 [ 3] = RCAR_GP_PIN(3, 3), /* A19 */2739 [ 4] = RCAR_GP_PIN(3, 4), /* A20 */2740 [ 5] = RCAR_GP_PIN(3, 5), /* A21 */2741 [ 6] = RCAR_GP_PIN(3, 6), /* CS1#/A26 */2742 [ 7] = RCAR_GP_PIN(3, 7), /* EX_CS0# */2743 [ 8] = RCAR_GP_PIN(3, 8), /* EX_CS1# */2744 [ 9] = RCAR_GP_PIN(3, 9), /* EX_CS2# */2745 [10] = RCAR_GP_PIN(3, 10), /* EX_CS3# */2746 [11] = RCAR_GP_PIN(3, 11), /* EX_CS4# */2747 [12] = RCAR_GP_PIN(3, 12), /* EX_CS5# */2748 [13] = RCAR_GP_PIN(3, 13), /* BS# */2749 [14] = RCAR_GP_PIN(3, 14), /* RD# */2750 [15] = RCAR_GP_PIN(3, 15), /* RD/WR# */2751 [16] = RCAR_GP_PIN(3, 16), /* WE0# */2752 [17] = RCAR_GP_PIN(3, 17), /* WE1# */2753 [18] = RCAR_GP_PIN(3, 18), /* EX_WAIT0 */2754 [19] = RCAR_GP_PIN(3, 19), /* IRQ0 */2755 [20] = RCAR_GP_PIN(3, 20), /* IRQ1 */2756 [21] = RCAR_GP_PIN(3, 21), /* IRQ2 */2757 [22] = RCAR_GP_PIN(3, 22), /* IRQ3 */2758 [23] = RCAR_GP_PIN(3, 23), /* A22 */2759 [24] = RCAR_GP_PIN(3, 24), /* A23 */2760 [25] = RCAR_GP_PIN(3, 25), /* A24 */2761 [26] = RCAR_GP_PIN(3, 26), /* A25 */2762 [27] = RCAR_GP_PIN(3, 27), /* CS0# */2763 [28] = SH_PFC_PIN_NONE,2764 [29] = SH_PFC_PIN_NONE,2765 [30] = SH_PFC_PIN_NONE,2766 [31] = SH_PFC_PIN_NONE,2767 } },2768 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {2769 [ 0] = RCAR_GP_PIN(4, 0), /* VI0_CLK */2770 [ 1] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */2771 [ 2] = RCAR_GP_PIN(4, 2), /* VI0_HSYNC# */2772 [ 3] = RCAR_GP_PIN(4, 3), /* VI0_VSYNC# */2773 [ 4] = RCAR_GP_PIN(4, 4), /* VI0_D0_B0_C0 */2774 [ 5] = RCAR_GP_PIN(4, 5), /* VI0_D1_B1_C1 */2775 [ 6] = RCAR_GP_PIN(4, 6), /* VI0_D2_B2_C2 */2776 [ 7] = RCAR_GP_PIN(4, 7), /* VI0_D3_B3_C3 */2777 [ 8] = RCAR_GP_PIN(4, 8), /* VI0_D4_B4_C4 */2778 [ 9] = RCAR_GP_PIN(4, 9), /* VI0_D5_B5_C5 */2779 [10] = RCAR_GP_PIN(4, 10), /* VI0_D6_B6_C6 */2780 [11] = RCAR_GP_PIN(4, 11), /* VI0_D7_B7_C7 */2781 [12] = RCAR_GP_PIN(4, 12), /* VI0_D8_G0_Y0 */2782 [13] = RCAR_GP_PIN(4, 13), /* VI0_D9_G1_Y1 */2783 [14] = RCAR_GP_PIN(4, 14), /* VI0_D10_G2_Y2 */2784 [15] = RCAR_GP_PIN(4, 15), /* VI0_D11_G3_Y3 */2785 [16] = RCAR_GP_PIN(4, 16), /* VI0_FIELD */2786 [17] = SH_PFC_PIN_NONE,2787 [18] = SH_PFC_PIN_NONE,2788 [19] = SH_PFC_PIN_NONE,2789 [20] = SH_PFC_PIN_NONE,2790 [21] = SH_PFC_PIN_NONE,2791 [22] = SH_PFC_PIN_NONE,2792 [23] = SH_PFC_PIN_NONE,2793 [24] = SH_PFC_PIN_NONE,2794 [25] = SH_PFC_PIN_NONE,2795 [26] = SH_PFC_PIN_NONE,2796 [27] = SH_PFC_PIN_NONE,2797 [28] = SH_PFC_PIN_NONE,2798 [29] = SH_PFC_PIN_NONE,2799 [30] = SH_PFC_PIN_NONE,2800 [31] = SH_PFC_PIN_NONE,2801 } },2802 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {2803 [ 0] = RCAR_GP_PIN(5, 0), /* VI1_CLK */2804 [ 1] = RCAR_GP_PIN(5, 1), /* VI1_CLKENB */2805 [ 2] = RCAR_GP_PIN(5, 2), /* VI1_HSYNC# */2806 [ 3] = RCAR_GP_PIN(5, 3), /* VI1_VSYNC# */2807 [ 4] = RCAR_GP_PIN(5, 4), /* VI1_D0_B0_C0 */2808 [ 5] = RCAR_GP_PIN(5, 5), /* VI1_D1_B1_C1 */2809 [ 6] = RCAR_GP_PIN(5, 6), /* VI1_D2_B2_C2 */2810 [ 7] = RCAR_GP_PIN(5, 7), /* VI1_D3_B3_C3 */2811 [ 8] = RCAR_GP_PIN(5, 8), /* VI1_D4_B4_C4 */2812 [ 9] = RCAR_GP_PIN(5, 9), /* VI1_D5_B5_C5 */2813 [10] = RCAR_GP_PIN(5, 10), /* VI1_D6_B6_C6 */2814 [11] = RCAR_GP_PIN(5, 11), /* VI1_D7_B7_C7 */2815 [12] = RCAR_GP_PIN(5, 12), /* VI1_D8_G0_Y0 */2816 [13] = RCAR_GP_PIN(5, 13), /* VI1_D9_G1_Y1 */2817 [14] = RCAR_GP_PIN(5, 14), /* VI1_D10_G2_Y2 */2818 [15] = RCAR_GP_PIN(5, 15), /* VI1_D11_G3_Y3 */2819 [16] = RCAR_GP_PIN(5, 16), /* VI1_FIELD */2820 [17] = SH_PFC_PIN_NONE,2821 [18] = SH_PFC_PIN_NONE,2822 [19] = SH_PFC_PIN_NONE,2823 [20] = SH_PFC_PIN_NONE,2824 [21] = SH_PFC_PIN_NONE,2825 [22] = SH_PFC_PIN_NONE,2826 [23] = SH_PFC_PIN_NONE,2827 [24] = SH_PFC_PIN_NONE,2828 [25] = SH_PFC_PIN_NONE,2829 [26] = SH_PFC_PIN_NONE,2830 [27] = SH_PFC_PIN_NONE,2831 [28] = SH_PFC_PIN_NONE,2832 [29] = SH_PFC_PIN_NONE,2833 [30] = SH_PFC_PIN_NONE,2834 [31] = SH_PFC_PIN_NONE,2835 } },2836 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {2837 [ 0] = RCAR_GP_PIN(6, 0), /* VI2_CLK */2838 [ 1] = RCAR_GP_PIN(6, 1), /* VI2_CLKENB */2839 [ 2] = RCAR_GP_PIN(6, 2), /* VI2_HSYNC# */2840 [ 3] = RCAR_GP_PIN(6, 3), /* VI2_VSYNC# */2841 [ 4] = RCAR_GP_PIN(6, 4), /* VI2_D0_C0 */2842 [ 5] = RCAR_GP_PIN(6, 5), /* VI2_D1_C1 */2843 [ 6] = RCAR_GP_PIN(6, 6), /* VI2_D2_C2 */2844 [ 7] = RCAR_GP_PIN(6, 7), /* VI2_D3_C3 */2845 [ 8] = RCAR_GP_PIN(6, 8), /* VI2_D4_C4 */2846 [ 9] = RCAR_GP_PIN(6, 9), /* VI2_D5_C5 */2847 [10] = RCAR_GP_PIN(6, 10), /* VI2_D6_C6 */2848 [11] = RCAR_GP_PIN(6, 11), /* VI2_D7_C7 */2849 [12] = RCAR_GP_PIN(6, 12), /* VI2_D8_Y0 */2850 [13] = RCAR_GP_PIN(6, 13), /* VI2_D9_Y1 */2851 [14] = RCAR_GP_PIN(6, 14), /* VI2_D10_Y2 */2852 [15] = RCAR_GP_PIN(6, 15), /* VI2_D11_Y3 */2853 [16] = RCAR_GP_PIN(6, 16), /* VI2_FIELD */2854 [17] = SH_PFC_PIN_NONE,2855 [18] = SH_PFC_PIN_NONE,2856 [19] = SH_PFC_PIN_NONE,2857 [20] = SH_PFC_PIN_NONE,2858 [21] = SH_PFC_PIN_NONE,2859 [22] = SH_PFC_PIN_NONE,2860 [23] = SH_PFC_PIN_NONE,2861 [24] = SH_PFC_PIN_NONE,2862 [25] = SH_PFC_PIN_NONE,2863 [26] = SH_PFC_PIN_NONE,2864 [27] = SH_PFC_PIN_NONE,2865 [28] = SH_PFC_PIN_NONE,2866 [29] = SH_PFC_PIN_NONE,2867 [30] = SH_PFC_PIN_NONE,2868 [31] = SH_PFC_PIN_NONE,2869 } },2870 { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {2871 [ 0] = RCAR_GP_PIN(7, 0), /* VI3_CLK */2872 [ 1] = RCAR_GP_PIN(7, 1), /* VI3_CLKENB */2873 [ 2] = RCAR_GP_PIN(7, 2), /* VI3_HSYNC# */2874 [ 3] = RCAR_GP_PIN(7, 3), /* VI3_VSYNC# */2875 [ 4] = RCAR_GP_PIN(7, 4), /* VI3_D0_C0 */2876 [ 5] = RCAR_GP_PIN(7, 5), /* VI3_D1_C1 */2877 [ 6] = RCAR_GP_PIN(7, 6), /* VI3_D2_C2 */2878 [ 7] = RCAR_GP_PIN(7, 7), /* VI3_D3_C3 */2879 [ 8] = RCAR_GP_PIN(7, 8), /* VI3_D4_C4 */2880 [ 9] = RCAR_GP_PIN(7, 9), /* VI3_D5_C5 */2881 [10] = RCAR_GP_PIN(7, 10), /* VI3_D6_C6 */2882 [11] = RCAR_GP_PIN(7, 11), /* VI3_D7_C7 */2883 [12] = RCAR_GP_PIN(7, 12), /* VI3_D8_Y0 */2884 [13] = RCAR_GP_PIN(7, 13), /* VI3_D9_Y1 */2885 [14] = RCAR_GP_PIN(7, 14), /* VI3_D10_Y2 */2886 [15] = RCAR_GP_PIN(7, 15), /* VI3_D11_Y3 */2887 [16] = RCAR_GP_PIN(7, 16), /* VI3_FIELD */2888 [17] = SH_PFC_PIN_NONE,2889 [18] = SH_PFC_PIN_NONE,2890 [19] = SH_PFC_PIN_NONE,2891 [20] = SH_PFC_PIN_NONE,2892 [21] = SH_PFC_PIN_NONE,2893 [22] = SH_PFC_PIN_NONE,2894 [23] = SH_PFC_PIN_NONE,2895 [24] = SH_PFC_PIN_NONE,2896 [25] = SH_PFC_PIN_NONE,2897 [26] = SH_PFC_PIN_NONE,2898 [27] = SH_PFC_PIN_NONE,2899 [28] = SH_PFC_PIN_NONE,2900 [29] = SH_PFC_PIN_NONE,2901 [30] = SH_PFC_PIN_NONE,2902 [31] = SH_PFC_PIN_NONE,2903 } },2904 { PINMUX_BIAS_REG("PUPR8", 0xe6060120, "N/A", 0) {2905 [ 0] = RCAR_GP_PIN(8, 0), /* VI4_CLK */2906 [ 1] = RCAR_GP_PIN(8, 1), /* VI4_CLKENB */2907 [ 2] = RCAR_GP_PIN(8, 2), /* VI4_HSYNC# */2908 [ 3] = RCAR_GP_PIN(8, 3), /* VI4_VSYNC# */2909 [ 4] = RCAR_GP_PIN(8, 4), /* VI4_D0_C0 */2910 [ 5] = RCAR_GP_PIN(8, 5), /* VI4_D1_C1 */2911 [ 6] = RCAR_GP_PIN(8, 6), /* VI4_D2_C2 */2912 [ 7] = RCAR_GP_PIN(8, 7), /* VI4_D3_C3 */2913 [ 8] = RCAR_GP_PIN(8, 8), /* VI4_D4_C4 */2914 [ 9] = RCAR_GP_PIN(8, 9), /* VI4_D5_C5 */2915 [10] = RCAR_GP_PIN(8, 10), /* VI4_D6_C6 */2916 [11] = RCAR_GP_PIN(8, 11), /* VI4_D7_C7 */2917 [12] = RCAR_GP_PIN(8, 12), /* VI4_D8_Y0 */2918 [13] = RCAR_GP_PIN(8, 13), /* VI4_D9_Y1 */2919 [14] = RCAR_GP_PIN(8, 14), /* VI4_D10_Y2 */2920 [15] = RCAR_GP_PIN(8, 15), /* VI4_D11_Y3 */2921 [16] = RCAR_GP_PIN(8, 16), /* VI4_FIELD */2922 [17] = SH_PFC_PIN_NONE,2923 [18] = SH_PFC_PIN_NONE,2924 [19] = SH_PFC_PIN_NONE,2925 [20] = SH_PFC_PIN_NONE,2926 [21] = SH_PFC_PIN_NONE,2927 [22] = SH_PFC_PIN_NONE,2928 [23] = SH_PFC_PIN_NONE,2929 [24] = SH_PFC_PIN_NONE,2930 [25] = SH_PFC_PIN_NONE,2931 [26] = SH_PFC_PIN_NONE,2932 [27] = SH_PFC_PIN_NONE,2933 [28] = SH_PFC_PIN_NONE,2934 [29] = SH_PFC_PIN_NONE,2935 [30] = SH_PFC_PIN_NONE,2936 [31] = SH_PFC_PIN_NONE,2937 } },2938 { PINMUX_BIAS_REG("PUPR9", 0xe6060124, "N/A", 0) {2939 [ 0] = RCAR_GP_PIN(9, 0), /* VI5_CLK */2940 [ 1] = RCAR_GP_PIN(9, 1), /* VI5_CLKENB */2941 [ 2] = RCAR_GP_PIN(9, 2), /* VI5_HSYNC# */2942 [ 3] = RCAR_GP_PIN(9, 3), /* VI5_VSYNC# */2943 [ 4] = RCAR_GP_PIN(9, 4), /* VI5_D0_C0 */2944 [ 5] = RCAR_GP_PIN(9, 5), /* VI5_D1_C1 */2945 [ 6] = RCAR_GP_PIN(9, 6), /* VI5_D2_C2 */2946 [ 7] = RCAR_GP_PIN(9, 7), /* VI5_D3_C3 */2947 [ 8] = RCAR_GP_PIN(9, 8), /* VI5_D4_C4 */2948 [ 9] = RCAR_GP_PIN(9, 9), /* VI5_D5_C5 */2949 [10] = RCAR_GP_PIN(9, 10), /* VI5_D6_C6 */2950 [11] = RCAR_GP_PIN(9, 11), /* VI5_D7_C7 */2951 [12] = RCAR_GP_PIN(9, 12), /* VI5_D8_Y0 */2952 [13] = RCAR_GP_PIN(9, 13), /* VI5_D9_Y1 */2953 [14] = RCAR_GP_PIN(9, 14), /* VI5_D10_Y2 */2954 [15] = RCAR_GP_PIN(9, 15), /* VI5_D11_Y3 */2955 [16] = RCAR_GP_PIN(9, 16), /* VI5_FIELD */2956 [17] = SH_PFC_PIN_NONE,2957 [18] = SH_PFC_PIN_NONE,2958 [19] = SH_PFC_PIN_NONE,2959 [20] = SH_PFC_PIN_NONE,2960 [21] = SH_PFC_PIN_NONE,2961 [22] = SH_PFC_PIN_NONE,2962 [23] = SH_PFC_PIN_NONE,2963 [24] = SH_PFC_PIN_NONE,2964 [25] = SH_PFC_PIN_NONE,2965 [26] = SH_PFC_PIN_NONE,2966 [27] = SH_PFC_PIN_NONE,2967 [28] = SH_PFC_PIN_NONE,2968 [29] = SH_PFC_PIN_NONE,2969 [30] = SH_PFC_PIN_NONE,2970 [31] = SH_PFC_PIN_NONE,2971 } },2972 { PINMUX_BIAS_REG("PUPR10", 0xe6060128, "N/A", 0) {2973 [ 0] = RCAR_GP_PIN(10, 0), /* HSCK0 */2974 [ 1] = RCAR_GP_PIN(10, 1), /* HCTS0# */2975 [ 2] = RCAR_GP_PIN(10, 2), /* HRTS0# */2976 [ 3] = RCAR_GP_PIN(10, 3), /* HTX0 */2977 [ 4] = RCAR_GP_PIN(10, 4), /* HRX0 */2978 [ 5] = RCAR_GP_PIN(10, 5), /* HSCK1 */2979 [ 6] = RCAR_GP_PIN(10, 6), /* HRTS1# */2980 [ 7] = RCAR_GP_PIN(10, 7), /* HCTS1# */2981 [ 8] = RCAR_GP_PIN(10, 8), /* HTX1 */2982 [ 9] = RCAR_GP_PIN(10, 9), /* HRX1 */2983 [10] = RCAR_GP_PIN(10, 10), /* SCK0 */2984 [11] = RCAR_GP_PIN(10, 11), /* CTS0# */2985 [12] = RCAR_GP_PIN(10, 12), /* RTS0# */2986 [13] = RCAR_GP_PIN(10, 13), /* TX0 */2987 [14] = RCAR_GP_PIN(10, 14), /* RX0 */2988 [15] = RCAR_GP_PIN(10, 15), /* SCK1 */2989 [16] = RCAR_GP_PIN(10, 16), /* CTS1# */2990 [17] = RCAR_GP_PIN(10, 17), /* RTS1# */2991 [18] = RCAR_GP_PIN(10, 18), /* TX1 */2992 [19] = RCAR_GP_PIN(10, 19), /* RX1 */2993 [20] = RCAR_GP_PIN(10, 20), /* SCK2 */2994 [21] = RCAR_GP_PIN(10, 21), /* TX2 */2995 [22] = RCAR_GP_PIN(10, 22), /* RX2 */2996 [23] = RCAR_GP_PIN(10, 23), /* SCK3 */2997 [24] = RCAR_GP_PIN(10, 24), /* TX3 */2998 [25] = RCAR_GP_PIN(10, 25), /* RX3 */2999 [26] = RCAR_GP_PIN(10, 26), /* SCIF_CLK */3000 [27] = RCAR_GP_PIN(10, 27), /* CAN0_TX */3001 [28] = RCAR_GP_PIN(10, 28), /* CAN0_RX */3002 [29] = RCAR_GP_PIN(10, 29), /* CAN_CLK */3003 [30] = RCAR_GP_PIN(10, 30), /* CAN1_TX */3004 [31] = RCAR_GP_PIN(10, 31), /* CAN1_RX */3005 } },3006 { PINMUX_BIAS_REG("PUPR11", 0xe606012c, "N/A", 0) {3007 [ 0] = RCAR_GP_PIN(11, 0), /* PWM0 */3008 [ 1] = RCAR_GP_PIN(11, 1), /* PWM1 */3009 [ 2] = RCAR_GP_PIN(11, 2), /* PWM2 */3010 [ 3] = RCAR_GP_PIN(11, 3), /* PWM3 */3011 [ 4] = RCAR_GP_PIN(11, 4), /* PWM4 */3012 [ 5] = RCAR_GP_PIN(11, 5), /* SD0_CLK */3013 [ 6] = RCAR_GP_PIN(11, 6), /* SD0_CMD */3014 [ 7] = RCAR_GP_PIN(11, 7), /* SD0_DAT0 */3015 [ 8] = RCAR_GP_PIN(11, 8), /* SD0_DAT1 */3016 [ 9] = RCAR_GP_PIN(11, 9), /* SD0_DAT2 */3017 [10] = RCAR_GP_PIN(11, 10), /* SD0_DAT3 */3018 [11] = RCAR_GP_PIN(11, 11), /* SD0_CD */3019 [12] = RCAR_GP_PIN(11, 12), /* SD0_WP */3020 [13] = RCAR_GP_PIN(11, 13), /* SSI_SCK3 */3021 [14] = RCAR_GP_PIN(11, 14), /* SSI_WS3 */3022 [15] = RCAR_GP_PIN(11, 15), /* SSI_SDATA3 */3023 [16] = RCAR_GP_PIN(11, 16), /* SSI_SCK4 */3024 [17] = RCAR_GP_PIN(11, 17), /* SSI_WS4 */3025 [18] = RCAR_GP_PIN(11, 18), /* SSI_SDATA4 */3026 [19] = RCAR_GP_PIN(11, 19), /* AUDIO_CLKOUT */3027 [20] = RCAR_GP_PIN(11, 20), /* AUDIO_CLKA */3028 [21] = RCAR_GP_PIN(11, 21), /* AUDIO_CLKB */3029 [22] = RCAR_GP_PIN(11, 22), /* ADICLK */3030 [23] = RCAR_GP_PIN(11, 23), /* ADICS_SAMP */3031 [24] = RCAR_GP_PIN(11, 24), /* ADIDATA */3032 [25] = RCAR_GP_PIN(11, 25), /* ADICHS0 */3033 [26] = RCAR_GP_PIN(11, 26), /* ADICHS1 */3034 [27] = RCAR_GP_PIN(11, 27), /* ADICHS2 */3035 [28] = RCAR_GP_PIN(11, 28), /* AVS1 */3036 [29] = RCAR_GP_PIN(11, 29), /* AVS2 */3037 [30] = SH_PFC_PIN_NONE,3038 [31] = SH_PFC_PIN_NONE,3039 } },3040 { PINMUX_BIAS_REG("PUPR12", 0xe6060130, "N/A", 0) {3041 /* PUPR12 pull-up pins */3042 [ 0] = PIN_DU0_DOTCLKIN, /* DU0_DOTCLKIN */3043 [ 1] = PIN_DU0_DOTCLKOUT, /* DU0_DOTCLKOUT */3044 [ 2] = PIN_DU1_DOTCLKIN, /* DU1_DOTCLKIN */3045 [ 3] = PIN_DU1_DOTCLKOUT, /* DU1_DOTCLKOUT */3046 [ 4] = PIN_TRST_N, /* TRST# */3047 [ 5] = PIN_TCK, /* TCK */3048 [ 6] = PIN_TMS, /* TMS */3049 [ 7] = PIN_TDI, /* TDI */3050 [ 8] = SH_PFC_PIN_NONE,3051 [ 9] = SH_PFC_PIN_NONE,3052 [10] = SH_PFC_PIN_NONE,3053 [11] = SH_PFC_PIN_NONE,3054 [12] = SH_PFC_PIN_NONE,3055 [13] = SH_PFC_PIN_NONE,3056 [14] = SH_PFC_PIN_NONE,3057 [15] = SH_PFC_PIN_NONE,3058 [16] = SH_PFC_PIN_NONE,3059 [17] = SH_PFC_PIN_NONE,3060 [18] = SH_PFC_PIN_NONE,3061 [19] = SH_PFC_PIN_NONE,3062 [20] = SH_PFC_PIN_NONE,3063 [21] = SH_PFC_PIN_NONE,3064 [22] = SH_PFC_PIN_NONE,3065 [23] = SH_PFC_PIN_NONE,3066 [24] = SH_PFC_PIN_NONE,3067 [25] = SH_PFC_PIN_NONE,3068 [26] = SH_PFC_PIN_NONE,3069 [27] = SH_PFC_PIN_NONE,3070 [28] = SH_PFC_PIN_NONE,3071 [29] = SH_PFC_PIN_NONE,3072 [30] = SH_PFC_PIN_NONE,3073 [31] = SH_PFC_PIN_NONE,3074 } },3075 { PINMUX_BIAS_REG("N/A", 0, "PUPR12", 0xe6060130) {3076 /* PUPR12 pull-down pins */3077 [ 0] = SH_PFC_PIN_NONE,3078 [ 1] = SH_PFC_PIN_NONE,3079 [ 2] = SH_PFC_PIN_NONE,3080 [ 3] = SH_PFC_PIN_NONE,3081 [ 4] = SH_PFC_PIN_NONE,3082 [ 5] = SH_PFC_PIN_NONE,3083 [ 6] = SH_PFC_PIN_NONE,3084 [ 7] = SH_PFC_PIN_NONE,3085 [ 8] = PIN_EDBGREQ, /* EDBGREQ */3086 [ 9] = SH_PFC_PIN_NONE,3087 [10] = SH_PFC_PIN_NONE,3088 [11] = SH_PFC_PIN_NONE,3089 [12] = SH_PFC_PIN_NONE,3090 [13] = SH_PFC_PIN_NONE,3091 [14] = SH_PFC_PIN_NONE,3092 [15] = SH_PFC_PIN_NONE,3093 [16] = SH_PFC_PIN_NONE,3094 [17] = SH_PFC_PIN_NONE,3095 [18] = SH_PFC_PIN_NONE,3096 [19] = SH_PFC_PIN_NONE,3097 [20] = SH_PFC_PIN_NONE,3098 [21] = SH_PFC_PIN_NONE,3099 [22] = SH_PFC_PIN_NONE,3100 [23] = SH_PFC_PIN_NONE,3101 [24] = SH_PFC_PIN_NONE,3102 [25] = SH_PFC_PIN_NONE,3103 [26] = SH_PFC_PIN_NONE,3104 [27] = SH_PFC_PIN_NONE,3105 [28] = SH_PFC_PIN_NONE,3106 [29] = SH_PFC_PIN_NONE,3107 [30] = SH_PFC_PIN_NONE,3108 [31] = SH_PFC_PIN_NONE,3109 } },3110 { /* sentinel */ }3111};3112 3113static const struct sh_pfc_soc_operations r8a7792_pfc_ops = {3114 .get_bias = rcar_pinmux_get_bias,3115 .set_bias = rcar_pinmux_set_bias,3116};3117 3118const struct sh_pfc_soc_info r8a7792_pinmux_info = {3119 .name = "r8a77920_pfc",3120 .ops = &r8a7792_pfc_ops,3121 .unlock_reg = 0xe6060000, /* PMMR */3122 3123 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },3124 3125 .pins = pinmux_pins,3126 .nr_pins = ARRAY_SIZE(pinmux_pins),3127 .groups = pinmux_groups,3128 .nr_groups = ARRAY_SIZE(pinmux_groups),3129 .functions = pinmux_functions,3130 .nr_functions = ARRAY_SIZE(pinmux_functions),3131 3132 .cfg_regs = pinmux_config_regs,3133 .bias_regs = pinmux_bias_regs,3134 3135 .pinmux_data = pinmux_data,3136 .pinmux_data_size = ARRAY_SIZE(pinmux_data),3137};3138