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1// SPDX-License-Identifier: GPL-2.02/*3 * R8A779A0 processor support - PFC hardware block.4 *5 * Copyright (C) 2021 Renesas Electronics Corp.6 *7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c8 */9 10#include <linux/errno.h>11#include <linux/io.h>12#include <linux/kernel.h>13 14#include "sh_pfc.h"15 16#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)17 18#define CPU_ALL_GP(fn, sfx) \19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \20 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \21 PORT_GP_CFG_1(1, 23, fn, sfx, CFG_FLAGS), \22 PORT_GP_CFG_1(1, 24, fn, sfx, CFG_FLAGS), \23 PORT_GP_CFG_1(1, 25, fn, sfx, CFG_FLAGS), \24 PORT_GP_CFG_1(1, 26, fn, sfx, CFG_FLAGS), \25 PORT_GP_CFG_1(1, 27, fn, sfx, CFG_FLAGS), \26 PORT_GP_CFG_1(1, 28, fn, sfx, CFG_FLAGS), \27 PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \28 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \32 PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \33 PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \34 PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \35 PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \36 PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \37 PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \38 PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \39 PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \40 PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \41 PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \42 PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \43 PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \44 PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \45 PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \46 PORT_GP_CFG_25(4, fn, sfx, CFG_FLAGS), \47 PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \48 PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \49 PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \50 PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)51 52#define CPU_ALL_NOGP(fn) \53 PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \54 PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \55 PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \56 PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)57 58/* GPSR0 */59#define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)60#define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)61#define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0)62#define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28)63#define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)64#define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20)65#define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16)66#define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12)67#define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8)68#define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)69#define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)70#define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)71#define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24)72#define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20)73#define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16)74#define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12)75#define GPSR0_2 F_(GP0_02, IP0SR0_11_8)76#define GPSR0_1 F_(GP0_01, IP0SR0_7_4)77#define GPSR0_0 F_(GP0_00, IP0SR0_3_0)78 79/* GPSR1 */80#define GPSR1_28 F_(HTX3_A, IP3SR1_19_16)81#define GPSR1_27 F_(HCTS3_N_A, IP3SR1_15_12)82#define GPSR1_26 F_(HRTS3_N_A, IP3SR1_11_8)83#define GPSR1_25 F_(HSCK3_A, IP3SR1_7_4)84#define GPSR1_24 F_(HRX3_A, IP3SR1_3_0)85#define GPSR1_23 F_(GP1_23, IP2SR1_31_28)86#define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)87#define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)88#define GPSR1_20 F_(SSI_SD, IP2SR1_19_16)89#define GPSR1_19 F_(SSI_WS, IP2SR1_15_12)90#define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8)91#define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4)92#define GPSR1_16 F_(HRX0, IP2SR1_3_0)93#define GPSR1_15 F_(HSCK0, IP1SR1_31_28)94#define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24)95#define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20)96#define GPSR1_12 F_(HTX0, IP1SR1_19_16)97#define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12)98#define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8)99#define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4)100#define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0)101#define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28)102#define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24)103#define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20)104#define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16)105#define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)106#define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8)107#define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4)108#define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0)109 110/* GPSR2 */111#define GPSR2_19 F_(CANFD7_RX, IP2SR2_15_12)112#define GPSR2_18 F_(CANFD7_TX, IP2SR2_11_8)113#define GPSR2_17 F_(CANFD4_RX, IP2SR2_7_4)114#define GPSR2_16 F_(CANFD4_TX, IP2SR2_3_0)115#define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28)116#define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24)117#define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20)118#define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16)119#define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)120#define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)121#define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)122#define GPSR2_8 F_(TPU0TO0_A, IP1SR2_3_0)123#define GPSR2_7 F_(TPU0TO1_A, IP0SR2_31_28)124#define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)125#define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20)126#define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)127#define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)128#define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)129#define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4)130#define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)131 132/* GPSR3 */133#define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20)134#define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16)135#define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12)136#define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8)137#define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4)138#define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0)139#define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28)140#define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24)141#define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20)142#define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16)143#define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12)144#define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8)145#define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4)146#define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0)147#define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28)148#define GPSR3_14 F_(IPC_CLKOUT, IP1SR3_27_24)149#define GPSR3_13 F_(IPC_CLKIN, IP1SR3_23_20)150#define GPSR3_12 F_(SD_WP, IP1SR3_19_16)151#define GPSR3_11 F_(SD_CD, IP1SR3_15_12)152#define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8)153#define GPSR3_9 F_(MMC_D6, IP1SR3_7_4)154#define GPSR3_8 F_(MMC_D7, IP1SR3_3_0)155#define GPSR3_7 F_(MMC_D4, IP0SR3_31_28)156#define GPSR3_6 F_(MMC_D5, IP0SR3_27_24)157#define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20)158#define GPSR3_4 F_(MMC_DS, IP0SR3_19_16)159#define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12)160#define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8)161#define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4)162#define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)163 164/* GPSR4 */165#define GPSR4_24 F_(AVS1, IP3SR4_3_0)166#define GPSR4_23 F_(AVS0, IP2SR4_31_28)167#define GPSR4_22 F_(PCIE1_CLKREQ_N, IP2SR4_27_24)168#define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20)169#define GPSR4_20 F_(TSN0_TXCREFCLK, IP2SR4_19_16)170#define GPSR4_19 F_(TSN0_TD2, IP2SR4_15_12)171#define GPSR4_18 F_(TSN0_TD3, IP2SR4_11_8)172#define GPSR4_17 F_(TSN0_RD2, IP2SR4_7_4)173#define GPSR4_16 F_(TSN0_RD3, IP2SR4_3_0)174#define GPSR4_15 F_(TSN0_TD0, IP1SR4_31_28)175#define GPSR4_14 F_(TSN0_TD1, IP1SR4_27_24)176#define GPSR4_13 F_(TSN0_RD1, IP1SR4_23_20)177#define GPSR4_12 F_(TSN0_TXC, IP1SR4_19_16)178#define GPSR4_11 F_(TSN0_RXC, IP1SR4_15_12)179#define GPSR4_10 F_(TSN0_RD0, IP1SR4_11_8)180#define GPSR4_9 F_(TSN0_TX_CTL, IP1SR4_7_4)181#define GPSR4_8 F_(TSN0_AVTP_PPS0, IP1SR4_3_0)182#define GPSR4_7 F_(TSN0_RX_CTL, IP0SR4_31_28)183#define GPSR4_6 F_(TSN0_AVTP_CAPTURE, IP0SR4_27_24)184#define GPSR4_5 F_(TSN0_AVTP_MATCH, IP0SR4_23_20)185#define GPSR4_4 F_(TSN0_LINK, IP0SR4_19_16)186#define GPSR4_3 F_(TSN0_PHY_INT, IP0SR4_15_12)187#define GPSR4_2 F_(TSN0_AVTP_PPS1, IP0SR4_11_8)188#define GPSR4_1 F_(TSN0_MDC, IP0SR4_7_4)189#define GPSR4_0 F_(TSN0_MDIO, IP0SR4_3_0)190 191/* GPSR 5 */192#define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16)193#define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12)194#define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8)195#define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4)196#define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0)197#define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28)198#define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24)199#define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20)200#define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16)201#define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12)202#define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8)203#define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4)204#define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0)205#define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28)206#define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24)207#define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20)208#define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16)209#define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12)210#define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8)211#define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4)212#define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0)213 214/* GPSR 6 */215#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)216#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)217#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)218#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)219#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)220#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)221#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)222#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)223#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)224#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)225#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)226#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)227#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)228#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)229#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)230#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)231#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)232#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)233#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)234#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)235#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)236 237/* GPSR7 */238#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)239#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)240#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)241#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)242#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)243#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)244#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)245#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)246#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)247#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)248#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)249#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)250#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)251#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)252#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)253#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)254#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)255#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)256#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)257#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)258#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)259 260/* GPSR8 */261#define GPSR8_13 F_(GP8_13, IP1SR8_23_20)262#define GPSR8_12 F_(GP8_12, IP1SR8_19_16)263#define GPSR8_11 F_(SDA5, IP1SR8_15_12)264#define GPSR8_10 F_(SCL5, IP1SR8_11_8)265#define GPSR8_9 F_(SDA4, IP1SR8_7_4)266#define GPSR8_8 F_(SCL4, IP1SR8_3_0)267#define GPSR8_7 F_(SDA3, IP0SR8_31_28)268#define GPSR8_6 F_(SCL3, IP0SR8_27_24)269#define GPSR8_5 F_(SDA2, IP0SR8_23_20)270#define GPSR8_4 F_(SCL2, IP0SR8_19_16)271#define GPSR8_3 F_(SDA1, IP0SR8_15_12)272#define GPSR8_2 F_(SCL1, IP0SR8_11_8)273#define GPSR8_1 F_(SDA0, IP0SR8_7_4)274#define GPSR8_0 F_(SCL0, IP0SR8_3_0)275 276/* SR0 */277/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */278#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)279#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)280#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)281#define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)282#define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)283#define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)284#define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)285#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)286 287/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */288#define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)289#define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)290#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)291#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)292#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)293#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)294#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)295#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)296 297/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */298#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)299#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)300#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)301 302/* SR1 */303/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */304#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)305#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)306#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)307#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)308#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)309#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)310#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)311#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)312 313/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */314#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)315#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)316#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)317#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)318#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)319#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)320#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)321#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)322 323/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */324#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)325#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)326#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)327#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)328#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)329#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)330#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)331#define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)332 333/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */334#define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)335#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)336#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)337#define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)338#define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)339 340/* SR2 */341/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */342#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)343#define IP0SR2_7_4 FM(FXR_TXENA_N_A) FM(CANFD1_RX) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)344#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX_A) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)345#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX_A) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)346#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)347#define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)348#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)349#define IP0SR2_31_28 FM(TPU0TO1_A) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)350 351/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */352#define IP1SR2_3_0 FM(TPU0TO0_A) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)353#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)354#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)355#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)356#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)357#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)358#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)359#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)360 361/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */362#define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)363#define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)364#define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)365#define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)366 367/* SR3 */368/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */369#define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)370#define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)371#define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)372#define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)373#define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)374#define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)375#define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)376#define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)377 378/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */379#define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)380#define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)381#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)382#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)383#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)384#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)385#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)386#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)387 388/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */389#define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)390#define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)391#define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)392#define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)393#define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)394#define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)395#define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)396#define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)397 398/* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */399#define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)400#define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)401#define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)402#define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)403#define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)404#define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)405 406/* SR4 */407/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */408#define IP0SR4_3_0 FM(TSN0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)409#define IP0SR4_7_4 FM(TSN0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)410#define IP0SR4_11_8 FM(TSN0_AVTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)411#define IP0SR4_15_12 FM(TSN0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)412#define IP0SR4_19_16 FM(TSN0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)413#define IP0SR4_23_20 FM(TSN0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)414#define IP0SR4_27_24 FM(TSN0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)415#define IP0SR4_31_28 FM(TSN0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)416 417/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */418#define IP1SR4_3_0 FM(TSN0_AVTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)419#define IP1SR4_7_4 FM(TSN0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)420#define IP1SR4_11_8 FM(TSN0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)421#define IP1SR4_15_12 FM(TSN0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)422#define IP1SR4_19_16 FM(TSN0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)423#define IP1SR4_23_20 FM(TSN0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)424#define IP1SR4_27_24 FM(TSN0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)425#define IP1SR4_31_28 FM(TSN0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)426 427/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */428#define IP2SR4_3_0 FM(TSN0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)429#define IP2SR4_7_4 FM(TSN0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)430#define IP2SR4_11_8 FM(TSN0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)431#define IP2SR4_15_12 FM(TSN0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)432#define IP2SR4_19_16 FM(TSN0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)433#define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)434#define IP2SR4_27_24 FM(PCIE1_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)435#define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)436 437/* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */438#define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)439 440/* SR5 */441/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */442#define IP0SR5_3_0 FM(AVB2_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)443#define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)444#define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)445#define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)446#define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)447#define IP0SR5_23_20 FM(AVB2_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)448#define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)449#define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)450 451/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */452#define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)453#define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)454#define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)455#define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)456#define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)457#define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)458#define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)459#define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)460 461/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */462#define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)463#define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)464#define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)465#define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)466#define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)467 468/* SR6 */469/* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */470#define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)471#define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)472#define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)473#define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)474#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)475#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)476#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)477#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)478 479/* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */480#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)481#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)482#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)483#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)484#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)485#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)486#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)487#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)488 489/* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */490#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)491#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)492#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)493#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)494#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)495 496/* SR7 */497/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */498#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)499#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)500#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)501#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)502#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)503#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)504#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)505#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)506 507/* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */508#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)509#define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)510#define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)511#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)512#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)513#define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)514#define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)515#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)516 517/* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */518#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)519#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)520#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)521#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)522#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)523 524/* SR8 */525/* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */526#define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)527#define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)528#define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)529#define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)530#define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)531#define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)532#define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)533#define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)534 535/* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */536#define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)537#define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)538#define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)539#define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)540#define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)541#define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)542 543#define PINMUX_GPSR \544 GPSR3_29 \545 GPSR1_28 GPSR3_28 \546 GPSR1_27 GPSR3_27 \547 GPSR1_26 GPSR3_26 \548 GPSR1_25 GPSR3_25 \549 GPSR1_24 GPSR3_24 GPSR4_24 \550 GPSR1_23 GPSR3_23 GPSR4_23 \551 GPSR1_22 GPSR3_22 GPSR4_22 \552 GPSR1_21 GPSR3_21 GPSR4_21 \553 GPSR1_20 GPSR3_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 \554 GPSR1_19 GPSR2_19 GPSR3_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 \555GPSR0_18 GPSR1_18 GPSR2_18 GPSR3_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 \556GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 \557GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 \558GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \559GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \560GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 \561GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 \562GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 \563GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 \564GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 \565GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 \566GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 \567GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 \568GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 \569GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 \570GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 \571GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 \572GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 \573GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0574 575#define PINMUX_IPSR \576\577FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \578FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \579FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \580FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \581FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \582FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \583FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \584FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \585\586FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \587FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \588FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \589FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \590FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \591FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 \592FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \593FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \594\595FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \596FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \597FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \598FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \599FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \600FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \601FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \602FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \603\604FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \605FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \606FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \607FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \608FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \609FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \610FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 \611FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 \612\613FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \614FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \615FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \616FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \617FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \618FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \619FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \620FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \621\622FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \623FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \624FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \625FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \626FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \627FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \628FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \629FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \630\631FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \632FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \633FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \634FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \635FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \636FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \637FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \638FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \639\640FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \641FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \642FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \643FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \644FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \645FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \646FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \647FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \648\649FM(IP0SR8_3_0) IP0SR8_3_0 FM(IP1SR8_3_0) IP1SR8_3_0 \650FM(IP0SR8_7_4) IP0SR8_7_4 FM(IP1SR8_7_4) IP1SR8_7_4 \651FM(IP0SR8_11_8) IP0SR8_11_8 FM(IP1SR8_11_8) IP1SR8_11_8 \652FM(IP0SR8_15_12) IP0SR8_15_12 FM(IP1SR8_15_12) IP1SR8_15_12 \653FM(IP0SR8_19_16) IP0SR8_19_16 FM(IP1SR8_19_16) IP1SR8_19_16 \654FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \655FM(IP0SR8_27_24) IP0SR8_27_24 \656FM(IP0SR8_31_28) IP0SR8_31_28657 658/* MOD_SEL8 */ /* 0 */ /* 1 */659#define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1)660#define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1)661#define MOD_SEL8_9 FM(SEL_SDA4_0) FM(SEL_SDA4_1)662#define MOD_SEL8_8 FM(SEL_SCL4_0) FM(SEL_SCL4_1)663#define MOD_SEL8_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1)664#define MOD_SEL8_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1)665#define MOD_SEL8_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1)666#define MOD_SEL8_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1)667#define MOD_SEL8_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1)668#define MOD_SEL8_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1)669#define MOD_SEL8_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1)670#define MOD_SEL8_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1)671 672#define PINMUX_MOD_SELS \673\674MOD_SEL8_11 \675MOD_SEL8_10 \676MOD_SEL8_9 \677MOD_SEL8_8 \678MOD_SEL8_7 \679MOD_SEL8_6 \680MOD_SEL8_5 \681MOD_SEL8_4 \682MOD_SEL8_3 \683MOD_SEL8_2 \684MOD_SEL8_1 \685MOD_SEL8_0686 687enum {688 PINMUX_RESERVED = 0,689 690 PINMUX_DATA_BEGIN,691 GP_ALL(DATA),692 PINMUX_DATA_END,693 694#define F_(x, y)695#define FM(x) FN_##x,696 PINMUX_FUNCTION_BEGIN,697 GP_ALL(FN),698 PINMUX_GPSR699 PINMUX_IPSR700 PINMUX_MOD_SELS701 PINMUX_FUNCTION_END,702#undef F_703#undef FM704 705#define F_(x, y)706#define FM(x) x##_MARK,707 PINMUX_MARK_BEGIN,708 PINMUX_GPSR709 PINMUX_IPSR710 PINMUX_MOD_SELS711 PINMUX_MARK_END,712#undef F_713#undef FM714};715 716static const u16 pinmux_data[] = {717 PINMUX_DATA_GP_ALL(),718 719 /* IP0SR0 */720 PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B),721 PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B),722 723 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),724 725 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),726 727 PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A),728 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),729 730 PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A),731 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),732 733 PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A),734 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),735 736 PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A),737 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),738 739 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),740 741 /* IP1SR0 */742 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1),743 744 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC),745 746 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD),747 748 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK),749 750 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),751 752 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),753 PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A),754 PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B),755 756 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),757 PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A),758 PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A),759 760 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),761 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A),762 PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A),763 764 /* IP2SR0 */765 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),766 PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A),767 PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A),768 769 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),770 PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A),771 PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A),772 773 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),774 PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A),775 PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A),776 777 /* IP0SR1 */778 PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),779 PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B),780 PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B),781 782 PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),783 PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B),784 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B),785 786 PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),787 PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B),788 PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B),789 790 PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),791 PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),792 PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),793 794 PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),795 PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B),796 PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B),797 798 PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),799 800 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),801 PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B),802 PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B),803 804 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),805 PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B),806 PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B),807 808 /* IP1SR1 */809 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),810 PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B),811 PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B),812 PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_TX_B),813 814 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),815 PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B),816 PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B),817 PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_RX_B),818 819 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),820 PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B),821 PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B),822 823 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),824 825 PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0),826 PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0),827 828 PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),829 PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),830 PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),831 832 PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),833 PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),834 PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),835 836 PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),837 PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),838 PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),839 840 /* IP2SR1 */841 PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),842 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),843 844 PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK),845 PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),846 847 PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),848 PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B),849 850 PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),851 PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B),852 853 PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),854 PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B),855 856 PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),857 PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B),858 859 PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),860 PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A),861 862 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A),863 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),864 PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),865 866 /* IP3SR1 */867 PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A),868 PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),869 PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),870 871 PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A),872 PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),873 PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),874 PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B),875 876 PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A),877 PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),878 PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),879 PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B),880 881 PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A),882 PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),883 PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),884 885 PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A),886 PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),887 PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),888 889 /* IP0SR2 */890 PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),891 PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),892 PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B),893 894 PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A),895 PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),896 PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B),897 898 PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),899 PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX_A),900 PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),901 902 PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),903 PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX_A),904 PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),905 906 PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),907 908 PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A),909 910 PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),911 912 PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A),913 PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),914 PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C),915 916 /* IP1SR2 */917 PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A),918 PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),919 PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B),920 921 PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),922 PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B),923 924 PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),925 PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B),926 927 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),928 PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),929 930 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),931 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A),932 PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C),933 934 PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),935 PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A),936 PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),937 PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C),938 939 PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),940 PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),941 942 PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),943 PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),944 945 /* IP2SR2 */946 PINMUX_IPSR_GPSR(IP2SR2_3_0, CANFD4_TX),947 PINMUX_IPSR_GPSR(IP2SR2_3_0, PWM4),948 949 PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD4_RX),950 PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM5),951 952 PINMUX_IPSR_GPSR(IP2SR2_11_8, CANFD7_TX),953 PINMUX_IPSR_GPSR(IP2SR2_11_8, PWM6),954 955 PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD7_RX),956 PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM7),957 958 /* IP0SR3 */959 PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1),960 PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0),961 PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2),962 PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK),963 PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS),964 PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3),965 PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5),966 PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4),967 968 /* IP1SR3 */969 PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7),970 971 PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6),972 973 PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD),974 975 PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD),976 977 PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP),978 979 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),980 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),981 PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),982 PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_A),983 984 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),985 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),986 PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A),987 PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_A),988 989 PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),990 991 /* IP2SR3 */992 PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3),993 PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2),994 PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1),995 PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0),996 PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK),997 PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0),998 PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK),999 PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1),1000 1001 /* IP3SR3 */1002 PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2),1003 PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL),1004 PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3),1005 PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N),1006 PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N),1007 PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N),1008 1009 /* IP0SR4 */1010 PINMUX_IPSR_GPSR(IP0SR4_3_0, TSN0_MDIO),1011 PINMUX_IPSR_GPSR(IP0SR4_7_4, TSN0_MDC),1012 PINMUX_IPSR_GPSR(IP0SR4_11_8, TSN0_AVTP_PPS1),1013 PINMUX_IPSR_GPSR(IP0SR4_15_12, TSN0_PHY_INT),1014 PINMUX_IPSR_GPSR(IP0SR4_19_16, TSN0_LINK),1015 PINMUX_IPSR_GPSR(IP0SR4_23_20, TSN0_AVTP_MATCH),1016 PINMUX_IPSR_GPSR(IP0SR4_27_24, TSN0_AVTP_CAPTURE),1017 PINMUX_IPSR_GPSR(IP0SR4_31_28, TSN0_RX_CTL),1018 1019 /* IP1SR4 */1020 PINMUX_IPSR_GPSR(IP1SR4_3_0, TSN0_AVTP_PPS0),1021 PINMUX_IPSR_GPSR(IP1SR4_7_4, TSN0_TX_CTL),1022 PINMUX_IPSR_GPSR(IP1SR4_11_8, TSN0_RD0),1023 PINMUX_IPSR_GPSR(IP1SR4_15_12, TSN0_RXC),1024 PINMUX_IPSR_GPSR(IP1SR4_19_16, TSN0_TXC),1025 PINMUX_IPSR_GPSR(IP1SR4_23_20, TSN0_RD1),1026 PINMUX_IPSR_GPSR(IP1SR4_27_24, TSN0_TD1),1027 PINMUX_IPSR_GPSR(IP1SR4_31_28, TSN0_TD0),1028 1029 /* IP2SR4 */1030 PINMUX_IPSR_GPSR(IP2SR4_3_0, TSN0_RD3),1031 PINMUX_IPSR_GPSR(IP2SR4_7_4, TSN0_RD2),1032 PINMUX_IPSR_GPSR(IP2SR4_11_8, TSN0_TD3),1033 PINMUX_IPSR_GPSR(IP2SR4_15_12, TSN0_TD2),1034 PINMUX_IPSR_GPSR(IP2SR4_19_16, TSN0_TXCREFCLK),1035 PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N),1036 PINMUX_IPSR_GPSR(IP2SR4_27_24, PCIE1_CLKREQ_N),1037 PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0),1038 1039 /* IP3SR4 */1040 PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1),1041 1042 /* IP0SR5 */1043 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS),1044 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE),1045 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH),1046 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK),1047 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT),1048 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC),1049 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC),1050 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK),1051 1052 /* IP1SR5 */1053 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3),1054 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3),1055 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO),1056 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2),1057 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1),1058 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2),1059 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1),1060 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0),1061 1062 /* IP2SR5 */1063 PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC),1064 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0),1065 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC),1066 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL),1067 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL),1068 1069 /* IP0SR6 */1070 PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),1071 1072 PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),1073 1074 PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),1075 1076 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),1077 1078 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),1079 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),1080 1081 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),1082 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),1083 1084 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),1085 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),1086 1087 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),1088 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),1089 1090 /* IP1SR6 */1091 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),1092 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC),1093 1094 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),1095 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),1096 1097 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),1098 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),1099 1100 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),1101 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),1102 1103 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),1104 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),1105 1106 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),1107 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),1108 1109 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),1110 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),1111 1112 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0),1113 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),1114 1115 /* IP2SR6 */1116 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),1117 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),1118 1119 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),1120 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),1121 1122 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),1123 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),1124 1125 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),1126 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),1127 1128 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),1129 1130 /* IP0SR7 */1131 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),1132 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),1133 1134 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),1135 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),1136 1137 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),1138 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),1139 PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),1140 1141 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),1142 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),1143 1144 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),1145 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),1146 1147 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),1148 1149 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),1150 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),1151 1152 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),1153 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),1154 1155 /* IP1SR7 */1156 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),1157 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),1158 1159 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),1160 1161 PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),1162 1163 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),1164 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),1165 1166 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),1167 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),1168 1169 PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),1170 1171 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),1172 1173 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),1174 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),1175 1176 /* IP2SR7 */1177 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),1178 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),1179 1180 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),1181 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),1182 1183 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0),1184 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0),1185 1186 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC),1187 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC),1188 1189 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL),1190 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),1191 1192 /* IP0SR8 */1193 PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),1194 PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),1195 PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_0),1196 PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_0),1197 PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_0),1198 PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_0),1199 PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_0),1200 PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_0),1201 1202 /* IP1SR8 */1203 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_0),1204 PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0),1205 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0),1206 1207 PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_0),1208 PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0),1209 PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0),1210 1211 PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_0),1212 PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0),1213 PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0),1214 1215 PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_0),1216 PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0),1217 1218 PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N),1219 PINMUX_IPSR_GPSR(IP1SR8_19_16, TX4),1220 1221 PINMUX_IPSR_GPSR(IP1SR8_23_20, HSCK2),1222 PINMUX_IPSR_GPSR(IP1SR8_23_20, RX4),1223};1224 1225/*1226 * Pins not associated with a GPIO port.1227 */1228enum {1229 GP_ASSIGN_LAST(),1230 NOGP_ALL(),1231};1232 1233static const struct sh_pfc_pin pinmux_pins[] = {1234 PINMUX_GPIO_GP_ALL(),1235 PINMUX_NOGP_ALL(),1236};1237 1238/* - AUDIO CLOCK ----------------------------------------- */1239static const unsigned int audio_clkin_pins[] = {1240 /* CLK IN */1241 RCAR_GP_PIN(1, 22),1242};1243static const unsigned int audio_clkin_mux[] = {1244 AUDIO_CLKIN_MARK,1245};1246static const unsigned int audio_clkout_pins[] = {1247 /* CLK OUT */1248 RCAR_GP_PIN(1, 21),1249};1250static const unsigned int audio_clkout_mux[] = {1251 AUDIO_CLKOUT_MARK,1252};1253 1254/* - AVB0 ------------------------------------------------ */1255static const unsigned int avb0_link_pins[] = {1256 /* AVB0_LINK */1257 RCAR_GP_PIN(7, 4),1258};1259static const unsigned int avb0_link_mux[] = {1260 AVB0_LINK_MARK,1261};1262static const unsigned int avb0_magic_pins[] = {1263 /* AVB0_MAGIC */1264 RCAR_GP_PIN(7, 10),1265};1266static const unsigned int avb0_magic_mux[] = {1267 AVB0_MAGIC_MARK,1268};1269static const unsigned int avb0_phy_int_pins[] = {1270 /* AVB0_PHY_INT */1271 RCAR_GP_PIN(7, 5),1272};1273static const unsigned int avb0_phy_int_mux[] = {1274 AVB0_PHY_INT_MARK,1275};1276static const unsigned int avb0_mdio_pins[] = {1277 /* AVB0_MDC, AVB0_MDIO */1278 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),1279};1280static const unsigned int avb0_mdio_mux[] = {1281 AVB0_MDC_MARK, AVB0_MDIO_MARK,1282};1283static const unsigned int avb0_rgmii_pins[] = {1284 /*1285 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,1286 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,1287 */1288 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),1289 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),1290 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),1291 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),1292 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),1293 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),1294};1295static const unsigned int avb0_rgmii_mux[] = {1296 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,1297 AVB0_TD0_MARK, AVB0_TD1_MARK,1298 AVB0_TD2_MARK, AVB0_TD3_MARK,1299 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,1300 AVB0_RD0_MARK, AVB0_RD1_MARK,1301 AVB0_RD2_MARK, AVB0_RD3_MARK,1302};1303static const unsigned int avb0_txcrefclk_pins[] = {1304 /* AVB0_TXCREFCLK */1305 RCAR_GP_PIN(7, 9),1306};1307static const unsigned int avb0_txcrefclk_mux[] = {1308 AVB0_TXCREFCLK_MARK,1309};1310static const unsigned int avb0_avtp_pps_pins[] = {1311 /* AVB0_AVTP_PPS */1312 RCAR_GP_PIN(7, 0),1313};1314static const unsigned int avb0_avtp_pps_mux[] = {1315 AVB0_AVTP_PPS_MARK,1316};1317static const unsigned int avb0_avtp_capture_pins[] = {1318 /* AVB0_AVTP_CAPTURE */1319 RCAR_GP_PIN(7, 1),1320};1321static const unsigned int avb0_avtp_capture_mux[] = {1322 AVB0_AVTP_CAPTURE_MARK,1323};1324static const unsigned int avb0_avtp_match_pins[] = {1325 /* AVB0_AVTP_MATCH */1326 RCAR_GP_PIN(7, 2),1327};1328static const unsigned int avb0_avtp_match_mux[] = {1329 AVB0_AVTP_MATCH_MARK,1330};1331 1332/* - AVB1 ------------------------------------------------ */1333static const unsigned int avb1_link_pins[] = {1334 /* AVB1_LINK */1335 RCAR_GP_PIN(6, 4),1336};1337static const unsigned int avb1_link_mux[] = {1338 AVB1_LINK_MARK,1339};1340static const unsigned int avb1_magic_pins[] = {1341 /* AVB1_MAGIC */1342 RCAR_GP_PIN(6, 1),1343};1344static const unsigned int avb1_magic_mux[] = {1345 AVB1_MAGIC_MARK,1346};1347static const unsigned int avb1_phy_int_pins[] = {1348 /* AVB1_PHY_INT */1349 RCAR_GP_PIN(6, 3),1350};1351static const unsigned int avb1_phy_int_mux[] = {1352 AVB1_PHY_INT_MARK,1353};1354static const unsigned int avb1_mdio_pins[] = {1355 /* AVB1_MDC, AVB1_MDIO */1356 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),1357};1358static const unsigned int avb1_mdio_mux[] = {1359 AVB1_MDC_MARK, AVB1_MDIO_MARK,1360};1361static const unsigned int avb1_rgmii_pins[] = {1362 /*1363 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,1364 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,1365 */1366 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),1367 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),1368 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),1369 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),1370 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),1371 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),1372};1373static const unsigned int avb1_rgmii_mux[] = {1374 AVB1_TX_CTL_MARK, AVB1_TXC_MARK,1375 AVB1_TD0_MARK, AVB1_TD1_MARK,1376 AVB1_TD2_MARK, AVB1_TD3_MARK,1377 AVB1_RX_CTL_MARK, AVB1_RXC_MARK,1378 AVB1_RD0_MARK, AVB1_RD1_MARK,1379 AVB1_RD2_MARK, AVB1_RD3_MARK,1380};1381static const unsigned int avb1_txcrefclk_pins[] = {1382 /* AVB1_TXCREFCLK */1383 RCAR_GP_PIN(6, 20),1384};1385static const unsigned int avb1_txcrefclk_mux[] = {1386 AVB1_TXCREFCLK_MARK,1387};1388static const unsigned int avb1_avtp_pps_pins[] = {1389 /* AVB1_AVTP_PPS */1390 RCAR_GP_PIN(6, 10),1391};1392static const unsigned int avb1_avtp_pps_mux[] = {1393 AVB1_AVTP_PPS_MARK,1394};1395static const unsigned int avb1_avtp_capture_pins[] = {1396 /* AVB1_AVTP_CAPTURE */1397 RCAR_GP_PIN(6, 11),1398};1399static const unsigned int avb1_avtp_capture_mux[] = {1400 AVB1_AVTP_CAPTURE_MARK,1401};1402static const unsigned int avb1_avtp_match_pins[] = {1403 /* AVB1_AVTP_MATCH */1404 RCAR_GP_PIN(6, 5),1405};1406static const unsigned int avb1_avtp_match_mux[] = {1407 AVB1_AVTP_MATCH_MARK,1408};1409 1410/* - AVB2 ------------------------------------------------ */1411static const unsigned int avb2_link_pins[] = {1412 /* AVB2_LINK */1413 RCAR_GP_PIN(5, 3),1414};1415static const unsigned int avb2_link_mux[] = {1416 AVB2_LINK_MARK,1417};1418static const unsigned int avb2_magic_pins[] = {1419 /* AVB2_MAGIC */1420 RCAR_GP_PIN(5, 5),1421};1422static const unsigned int avb2_magic_mux[] = {1423 AVB2_MAGIC_MARK,1424};1425static const unsigned int avb2_phy_int_pins[] = {1426 /* AVB2_PHY_INT */1427 RCAR_GP_PIN(5, 4),1428};1429static const unsigned int avb2_phy_int_mux[] = {1430 AVB2_PHY_INT_MARK,1431};1432static const unsigned int avb2_mdio_pins[] = {1433 /* AVB2_MDC, AVB2_MDIO */1434 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),1435};1436static const unsigned int avb2_mdio_mux[] = {1437 AVB2_MDC_MARK, AVB2_MDIO_MARK,1438};1439static const unsigned int avb2_rgmii_pins[] = {1440 /*1441 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,1442 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,1443 */1444 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),1445 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),1446 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),1447 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),1448 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),1449 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),1450};1451static const unsigned int avb2_rgmii_mux[] = {1452 AVB2_TX_CTL_MARK, AVB2_TXC_MARK,1453 AVB2_TD0_MARK, AVB2_TD1_MARK,1454 AVB2_TD2_MARK, AVB2_TD3_MARK,1455 AVB2_RX_CTL_MARK, AVB2_RXC_MARK,1456 AVB2_RD0_MARK, AVB2_RD1_MARK,1457 AVB2_RD2_MARK, AVB2_RD3_MARK,1458};1459static const unsigned int avb2_txcrefclk_pins[] = {1460 /* AVB2_TXCREFCLK */1461 RCAR_GP_PIN(5, 7),1462};1463static const unsigned int avb2_txcrefclk_mux[] = {1464 AVB2_TXCREFCLK_MARK,1465};1466static const unsigned int avb2_avtp_pps_pins[] = {1467 /* AVB2_AVTP_PPS */1468 RCAR_GP_PIN(5, 0),1469};1470static const unsigned int avb2_avtp_pps_mux[] = {1471 AVB2_AVTP_PPS_MARK,1472};1473static const unsigned int avb2_avtp_capture_pins[] = {1474 /* AVB2_AVTP_CAPTURE */1475 RCAR_GP_PIN(5, 1),1476};1477static const unsigned int avb2_avtp_capture_mux[] = {1478 AVB2_AVTP_CAPTURE_MARK,1479};1480static const unsigned int avb2_avtp_match_pins[] = {1481 /* AVB2_AVTP_MATCH */1482 RCAR_GP_PIN(5, 2),1483};1484static const unsigned int avb2_avtp_match_mux[] = {1485 AVB2_AVTP_MATCH_MARK,1486};1487 1488/* - CANFD0 ----------------------------------------------------------------- */1489static const unsigned int canfd0_data_pins[] = {1490 /* CANFD0_TX, CANFD0_RX */1491 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),1492};1493static const unsigned int canfd0_data_mux[] = {1494 CANFD0_TX_MARK, CANFD0_RX_MARK,1495};1496 1497/* - CANFD1 ----------------------------------------------------------------- */1498static const unsigned int canfd1_data_pins[] = {1499 /* CANFD1_TX, CANFD1_RX */1500 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),1501};1502static const unsigned int canfd1_data_mux[] = {1503 CANFD1_TX_MARK, CANFD1_RX_MARK,1504};1505 1506/* - CANFD2 ----------------------------------------------------------------- */1507static const unsigned int canfd2_data_pins[] = {1508 /* CANFD2_TX, CANFD2_RX */1509 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),1510};1511static const unsigned int canfd2_data_mux[] = {1512 CANFD2_TX_MARK, CANFD2_RX_MARK,1513};1514 1515/* - CANFD3 ----------------------------------------------------------------- */1516static const unsigned int canfd3_data_pins[] = {1517 /* CANFD3_TX, CANFD3_RX */1518 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),1519};1520static const unsigned int canfd3_data_mux[] = {1521 CANFD3_TX_MARK, CANFD3_RX_MARK,1522};1523 1524/* - CANFD4 ----------------------------------------------------------------- */1525static const unsigned int canfd4_data_pins[] = {1526 /* CANFD4_TX, CANFD4_RX */1527 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),1528};1529static const unsigned int canfd4_data_mux[] = {1530 CANFD4_TX_MARK, CANFD4_RX_MARK,1531};1532 1533/* - CANFD5 ----------------------------------------------------------------- */1534static const unsigned int canfd5_data_a_pins[] = {1535 /* CANFD5_TX_A, CANFD5_RX_A */1536 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),1537};1538static const unsigned int canfd5_data_a_mux[] = {1539 CANFD5_TX_A_MARK, CANFD5_RX_A_MARK,1540};1541 1542static const unsigned int canfd5_data_b_pins[] = {1543 /* CANFD5_TX_B, CANFD5_RX_B */1544 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),1545};1546static const unsigned int canfd5_data_b_mux[] = {1547 CANFD5_TX_B_MARK, CANFD5_RX_B_MARK,1548};1549 1550/* - CANFD6 ----------------------------------------------------------------- */1551static const unsigned int canfd6_data_pins[] = {1552 /* CANFD6_TX, CANFD6_RX */1553 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),1554};1555static const unsigned int canfd6_data_mux[] = {1556 CANFD6_TX_MARK, CANFD6_RX_MARK,1557};1558 1559/* - CANFD7 ----------------------------------------------------------------- */1560static const unsigned int canfd7_data_pins[] = {1561 /* CANFD7_TX, CANFD7_RX */1562 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),1563};1564static const unsigned int canfd7_data_mux[] = {1565 CANFD7_TX_MARK, CANFD7_RX_MARK,1566};1567 1568/* - CANFD Clock ------------------------------------------------------------ */1569static const unsigned int can_clk_pins[] = {1570 /* CAN_CLK */1571 RCAR_GP_PIN(2, 9),1572};1573static const unsigned int can_clk_mux[] = {1574 CAN_CLK_MARK,1575};1576 1577/* - HSCIF0 ----------------------------------------------------------------- */1578static const unsigned int hscif0_data_pins[] = {1579 /* HRX0, HTX0 */1580 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),1581};1582static const unsigned int hscif0_data_mux[] = {1583 HRX0_MARK, HTX0_MARK,1584};1585static const unsigned int hscif0_clk_pins[] = {1586 /* HSCK0 */1587 RCAR_GP_PIN(1, 15),1588};1589static const unsigned int hscif0_clk_mux[] = {1590 HSCK0_MARK,1591};1592static const unsigned int hscif0_ctrl_pins[] = {1593 /* HRTS0_N, HCTS0_N */1594 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),1595};1596static const unsigned int hscif0_ctrl_mux[] = {1597 HRTS0_N_MARK, HCTS0_N_MARK,1598};1599 1600/* - HSCIF1 ----------------------------------------------------------------- */1601static const unsigned int hscif1_data_a_pins[] = {1602 /* HRX1_A, HTX1_A */1603 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),1604};1605static const unsigned int hscif1_data_a_mux[] = {1606 HRX1_A_MARK, HTX1_A_MARK,1607};1608static const unsigned int hscif1_clk_a_pins[] = {1609 /* HSCK1_A */1610 RCAR_GP_PIN(0, 18),1611};1612static const unsigned int hscif1_clk_a_mux[] = {1613 HSCK1_A_MARK,1614};1615static const unsigned int hscif1_ctrl_a_pins[] = {1616 /* HRTS1_N_A, HCTS1_N_A */1617 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),1618};1619static const unsigned int hscif1_ctrl_a_mux[] = {1620 HRTS1_N_A_MARK, HCTS1_N_A_MARK,1621};1622 1623static const unsigned int hscif1_data_b_pins[] = {1624 /* HRX1_B, HTX1_B */1625 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),1626};1627static const unsigned int hscif1_data_b_mux[] = {1628 HRX1_B_MARK, HTX1_B_MARK,1629};1630static const unsigned int hscif1_clk_b_pins[] = {1631 /* HSCK1_B */1632 RCAR_GP_PIN(1, 10),1633};1634static const unsigned int hscif1_clk_b_mux[] = {1635 HSCK1_B_MARK,1636};1637static const unsigned int hscif1_ctrl_b_pins[] = {1638 /* HRTS1_N_B, HCTS1_N_B */1639 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),1640};1641static const unsigned int hscif1_ctrl_b_mux[] = {1642 HRTS1_N_B_MARK, HCTS1_N_B_MARK,1643};1644 1645/* - HSCIF2 ----------------------------------------------------------------- */1646static const unsigned int hscif2_data_pins[] = {1647 /* HRX2, HTX2 */1648 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),1649};1650static const unsigned int hscif2_data_mux[] = {1651 HRX2_MARK, HTX2_MARK,1652};1653static const unsigned int hscif2_clk_pins[] = {1654 /* HSCK2 */1655 RCAR_GP_PIN(8, 13),1656};1657static const unsigned int hscif2_clk_mux[] = {1658 HSCK2_MARK,1659};1660static const unsigned int hscif2_ctrl_pins[] = {1661 /* HRTS2_N, HCTS2_N */1662 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),1663};1664static const unsigned int hscif2_ctrl_mux[] = {1665 HRTS2_N_MARK, HCTS2_N_MARK,1666};1667 1668/* - HSCIF3 ----------------------------------------------------------------- */1669static const unsigned int hscif3_data_a_pins[] = {1670 /* HRX3_A, HTX3_A */1671 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),1672};1673static const unsigned int hscif3_data_a_mux[] = {1674 HRX3_A_MARK, HTX3_A_MARK,1675};1676static const unsigned int hscif3_clk_a_pins[] = {1677 /* HSCK3_A */1678 RCAR_GP_PIN(1, 25),1679};1680static const unsigned int hscif3_clk_a_mux[] = {1681 HSCK3_A_MARK,1682};1683static const unsigned int hscif3_ctrl_a_pins[] = {1684 /* HRTS3_N_A, HCTS3_N_A */1685 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),1686};1687static const unsigned int hscif3_ctrl_a_mux[] = {1688 HRTS3_N_A_MARK, HCTS3_N_A_MARK,1689};1690 1691static const unsigned int hscif3_data_b_pins[] = {1692 /* HRX3_B, HTX3_B */1693 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),1694};1695static const unsigned int hscif3_data_b_mux[] = {1696 HRX3_B_MARK, HTX3_B_MARK,1697};1698static const unsigned int hscif3_clk_b_pins[] = {1699 /* HSCK3_B */1700 RCAR_GP_PIN(1, 3),1701};1702static const unsigned int hscif3_clk_b_mux[] = {1703 HSCK3_B_MARK,1704};1705static const unsigned int hscif3_ctrl_b_pins[] = {1706 /* HRTS3_N_B, HCTS3_N_B */1707 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),1708};1709static const unsigned int hscif3_ctrl_b_mux[] = {1710 HRTS3_N_B_MARK, HCTS3_N_B_MARK,1711};1712 1713/* - I2C0 ------------------------------------------------------------------- */1714static const unsigned int i2c0_pins[] = {1715 /* SDA0, SCL0 */1716 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),1717};1718static const unsigned int i2c0_mux[] = {1719 SDA0_MARK, SCL0_MARK,1720};1721 1722/* - I2C1 ------------------------------------------------------------------- */1723static const unsigned int i2c1_pins[] = {1724 /* SDA1, SCL1 */1725 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),1726};1727static const unsigned int i2c1_mux[] = {1728 SDA1_MARK, SCL1_MARK,1729};1730 1731/* - I2C2 ------------------------------------------------------------------- */1732static const unsigned int i2c2_pins[] = {1733 /* SDA2, SCL2 */1734 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),1735};1736static const unsigned int i2c2_mux[] = {1737 SDA2_MARK, SCL2_MARK,1738};1739 1740/* - I2C3 ------------------------------------------------------------------- */1741static const unsigned int i2c3_pins[] = {1742 /* SDA3, SCL3 */1743 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),1744};1745static const unsigned int i2c3_mux[] = {1746 SDA3_MARK, SCL3_MARK,1747};1748 1749/* - I2C4 ------------------------------------------------------------------- */1750static const unsigned int i2c4_pins[] = {1751 /* SDA4, SCL4 */1752 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),1753};1754static const unsigned int i2c4_mux[] = {1755 SDA4_MARK, SCL4_MARK,1756};1757 1758/* - I2C5 ------------------------------------------------------------------- */1759static const unsigned int i2c5_pins[] = {1760 /* SDA5, SCL5 */1761 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),1762};1763static const unsigned int i2c5_mux[] = {1764 SDA5_MARK, SCL5_MARK,1765};1766 1767/* - INTC-EX ---------------------------------------------------------------- */1768static const unsigned int intc_ex_irq0_a_pins[] = {1769 /* IRQ0_A */1770 RCAR_GP_PIN(0, 6),1771};1772static const unsigned int intc_ex_irq0_a_mux[] = {1773 IRQ0_A_MARK,1774};1775static const unsigned int intc_ex_irq0_b_pins[] = {1776 /* IRQ0_B */1777 RCAR_GP_PIN(1, 20),1778};1779static const unsigned int intc_ex_irq0_b_mux[] = {1780 IRQ0_B_MARK,1781};1782 1783static const unsigned int intc_ex_irq1_a_pins[] = {1784 /* IRQ1_A */1785 RCAR_GP_PIN(0, 5),1786};1787static const unsigned int intc_ex_irq1_a_mux[] = {1788 IRQ1_A_MARK,1789};1790static const unsigned int intc_ex_irq1_b_pins[] = {1791 /* IRQ1_B */1792 RCAR_GP_PIN(1, 21),1793};1794static const unsigned int intc_ex_irq1_b_mux[] = {1795 IRQ1_B_MARK,1796};1797 1798static const unsigned int intc_ex_irq2_a_pins[] = {1799 /* IRQ2_A */1800 RCAR_GP_PIN(0, 4),1801};1802static const unsigned int intc_ex_irq2_a_mux[] = {1803 IRQ2_A_MARK,1804};1805static const unsigned int intc_ex_irq2_b_pins[] = {1806 /* IRQ2_B */1807 RCAR_GP_PIN(0, 13),1808};1809static const unsigned int intc_ex_irq2_b_mux[] = {1810 IRQ2_B_MARK,1811};1812 1813static const unsigned int intc_ex_irq3_a_pins[] = {1814 /* IRQ3_A */1815 RCAR_GP_PIN(0, 3),1816};1817static const unsigned int intc_ex_irq3_a_mux[] = {1818 IRQ3_A_MARK,1819};1820static const unsigned int intc_ex_irq3_b_pins[] = {1821 /* IRQ3_B */1822 RCAR_GP_PIN(1, 23),1823};1824static const unsigned int intc_ex_irq3_b_mux[] = {1825 IRQ3_B_MARK,1826};1827 1828static const unsigned int intc_ex_irq4_a_pins[] = {1829 /* IRQ4_A */1830 RCAR_GP_PIN(1, 17),1831};1832static const unsigned int intc_ex_irq4_a_mux[] = {1833 IRQ4_A_MARK,1834};1835static const unsigned int intc_ex_irq4_b_pins[] = {1836 /* IRQ4_B */1837 RCAR_GP_PIN(2, 3),1838};1839static const unsigned int intc_ex_irq4_b_mux[] = {1840 IRQ4_B_MARK,1841};1842 1843static const unsigned int intc_ex_irq5_pins[] = {1844 /* IRQ5 */1845 RCAR_GP_PIN(2, 2),1846};1847static const unsigned int intc_ex_irq5_mux[] = {1848 IRQ5_MARK,1849};1850 1851/* - MMC -------------------------------------------------------------------- */1852static const unsigned int mmc_data_pins[] = {1853 /* MMC_SD_D[0:3], MMC_D[4:7] */1854 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),1855 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),1856 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),1857 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),1858};1859static const unsigned int mmc_data_mux[] = {1860 MMC_SD_D0_MARK, MMC_SD_D1_MARK,1861 MMC_SD_D2_MARK, MMC_SD_D3_MARK,1862 MMC_D4_MARK, MMC_D5_MARK,1863 MMC_D6_MARK, MMC_D7_MARK,1864};1865static const unsigned int mmc_ctrl_pins[] = {1866 /* MMC_SD_CLK, MMC_SD_CMD */1867 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),1868};1869static const unsigned int mmc_ctrl_mux[] = {1870 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,1871};1872static const unsigned int mmc_cd_pins[] = {1873 /* SD_CD */1874 RCAR_GP_PIN(3, 11),1875};1876static const unsigned int mmc_cd_mux[] = {1877 SD_CD_MARK,1878};1879static const unsigned int mmc_wp_pins[] = {1880 /* SD_WP */1881 RCAR_GP_PIN(3, 12),1882};1883static const unsigned int mmc_wp_mux[] = {1884 SD_WP_MARK,1885};1886static const unsigned int mmc_ds_pins[] = {1887 /* MMC_DS */1888 RCAR_GP_PIN(3, 4),1889};1890static const unsigned int mmc_ds_mux[] = {1891 MMC_DS_MARK,1892};1893 1894/* - MSIOF0 ----------------------------------------------------------------- */1895static const unsigned int msiof0_clk_pins[] = {1896 /* MSIOF0_SCK */1897 RCAR_GP_PIN(1, 10),1898};1899static const unsigned int msiof0_clk_mux[] = {1900 MSIOF0_SCK_MARK,1901};1902static const unsigned int msiof0_sync_pins[] = {1903 /* MSIOF0_SYNC */1904 RCAR_GP_PIN(1, 8),1905};1906static const unsigned int msiof0_sync_mux[] = {1907 MSIOF0_SYNC_MARK,1908};1909static const unsigned int msiof0_ss1_pins[] = {1910 /* MSIOF0_SS1 */1911 RCAR_GP_PIN(1, 7),1912};1913static const unsigned int msiof0_ss1_mux[] = {1914 MSIOF0_SS1_MARK,1915};1916static const unsigned int msiof0_ss2_pins[] = {1917 /* MSIOF0_SS2 */1918 RCAR_GP_PIN(1, 6),1919};1920static const unsigned int msiof0_ss2_mux[] = {1921 MSIOF0_SS2_MARK,1922};1923static const unsigned int msiof0_txd_pins[] = {1924 /* MSIOF0_TXD */1925 RCAR_GP_PIN(1, 9),1926};1927static const unsigned int msiof0_txd_mux[] = {1928 MSIOF0_TXD_MARK,1929};1930static const unsigned int msiof0_rxd_pins[] = {1931 /* MSIOF0_RXD */1932 RCAR_GP_PIN(1, 11),1933};1934static const unsigned int msiof0_rxd_mux[] = {1935 MSIOF0_RXD_MARK,1936};1937 1938/* - MSIOF1 ----------------------------------------------------------------- */1939static const unsigned int msiof1_clk_pins[] = {1940 /* MSIOF1_SCK */1941 RCAR_GP_PIN(1, 3),1942};1943static const unsigned int msiof1_clk_mux[] = {1944 MSIOF1_SCK_MARK,1945};1946static const unsigned int msiof1_sync_pins[] = {1947 /* MSIOF1_SYNC */1948 RCAR_GP_PIN(1, 2),1949};1950static const unsigned int msiof1_sync_mux[] = {1951 MSIOF1_SYNC_MARK,1952};1953static const unsigned int msiof1_ss1_pins[] = {1954 /* MSIOF1_SS1 */1955 RCAR_GP_PIN(1, 1),1956};1957static const unsigned int msiof1_ss1_mux[] = {1958 MSIOF1_SS1_MARK,1959};1960static const unsigned int msiof1_ss2_pins[] = {1961 /* MSIOF1_SS2 */1962 RCAR_GP_PIN(1, 0),1963};1964static const unsigned int msiof1_ss2_mux[] = {1965 MSIOF1_SS2_MARK,1966};1967static const unsigned int msiof1_txd_pins[] = {1968 /* MSIOF1_TXD */1969 RCAR_GP_PIN(1, 4),1970};1971static const unsigned int msiof1_txd_mux[] = {1972 MSIOF1_TXD_MARK,1973};1974static const unsigned int msiof1_rxd_pins[] = {1975 /* MSIOF1_RXD */1976 RCAR_GP_PIN(1, 5),1977};1978static const unsigned int msiof1_rxd_mux[] = {1979 MSIOF1_RXD_MARK,1980};1981 1982/* - MSIOF2 ----------------------------------------------------------------- */1983static const unsigned int msiof2_clk_pins[] = {1984 /* MSIOF2_SCK */1985 RCAR_GP_PIN(0, 17),1986};1987static const unsigned int msiof2_clk_mux[] = {1988 MSIOF2_SCK_MARK,1989};1990static const unsigned int msiof2_sync_pins[] = {1991 /* MSIOF2_SYNC */1992 RCAR_GP_PIN(0, 15),1993};1994static const unsigned int msiof2_sync_mux[] = {1995 MSIOF2_SYNC_MARK,1996};1997static const unsigned int msiof2_ss1_pins[] = {1998 /* MSIOF2_SS1 */1999 RCAR_GP_PIN(0, 14),2000};2001static const unsigned int msiof2_ss1_mux[] = {2002 MSIOF2_SS1_MARK,2003};2004static const unsigned int msiof2_ss2_pins[] = {2005 /* MSIOF2_SS2 */2006 RCAR_GP_PIN(0, 13),2007};2008static const unsigned int msiof2_ss2_mux[] = {2009 MSIOF2_SS2_MARK,2010};2011static const unsigned int msiof2_txd_pins[] = {2012 /* MSIOF2_TXD */2013 RCAR_GP_PIN(0, 16),2014};2015static const unsigned int msiof2_txd_mux[] = {2016 MSIOF2_TXD_MARK,2017};2018static const unsigned int msiof2_rxd_pins[] = {2019 /* MSIOF2_RXD */2020 RCAR_GP_PIN(0, 18),2021};2022static const unsigned int msiof2_rxd_mux[] = {2023 MSIOF2_RXD_MARK,2024};2025 2026/* - MSIOF3 ----------------------------------------------------------------- */2027static const unsigned int msiof3_clk_pins[] = {2028 /* MSIOF3_SCK */2029 RCAR_GP_PIN(0, 3),2030};2031static const unsigned int msiof3_clk_mux[] = {2032 MSIOF3_SCK_MARK,2033};2034static const unsigned int msiof3_sync_pins[] = {2035 /* MSIOF3_SYNC */2036 RCAR_GP_PIN(0, 6),2037};2038static const unsigned int msiof3_sync_mux[] = {2039 MSIOF3_SYNC_MARK,2040};2041static const unsigned int msiof3_ss1_pins[] = {2042 /* MSIOF3_SS1 */2043 RCAR_GP_PIN(0, 1),2044};2045static const unsigned int msiof3_ss1_mux[] = {2046 MSIOF3_SS1_MARK,2047};2048static const unsigned int msiof3_ss2_pins[] = {2049 /* MSIOF3_SS2 */2050 RCAR_GP_PIN(0, 2),2051};2052static const unsigned int msiof3_ss2_mux[] = {2053 MSIOF3_SS2_MARK,2054};2055static const unsigned int msiof3_txd_pins[] = {2056 /* MSIOF3_TXD */2057 RCAR_GP_PIN(0, 4),2058};2059static const unsigned int msiof3_txd_mux[] = {2060 MSIOF3_TXD_MARK,2061};2062static const unsigned int msiof3_rxd_pins[] = {2063 /* MSIOF3_RXD */2064 RCAR_GP_PIN(0, 5),2065};2066static const unsigned int msiof3_rxd_mux[] = {2067 MSIOF3_RXD_MARK,2068};2069 2070/* - MSIOF4 ----------------------------------------------------------------- */2071static const unsigned int msiof4_clk_pins[] = {2072 /* MSIOF4_SCK */2073 RCAR_GP_PIN(1, 25),2074};2075static const unsigned int msiof4_clk_mux[] = {2076 MSIOF4_SCK_MARK,2077};2078static const unsigned int msiof4_sync_pins[] = {2079 /* MSIOF4_SYNC */2080 RCAR_GP_PIN(1, 28),2081};2082static const unsigned int msiof4_sync_mux[] = {2083 MSIOF4_SYNC_MARK,2084};2085static const unsigned int msiof4_ss1_pins[] = {2086 /* MSIOF4_SS1 */2087 RCAR_GP_PIN(1, 23),2088};2089static const unsigned int msiof4_ss1_mux[] = {2090 MSIOF4_SS1_MARK,2091};2092static const unsigned int msiof4_ss2_pins[] = {2093 /* MSIOF4_SS2 */2094 RCAR_GP_PIN(1, 24),2095};2096static const unsigned int msiof4_ss2_mux[] = {2097 MSIOF4_SS2_MARK,2098};2099static const unsigned int msiof4_txd_pins[] = {2100 /* MSIOF4_TXD */2101 RCAR_GP_PIN(1, 26),2102};2103static const unsigned int msiof4_txd_mux[] = {2104 MSIOF4_TXD_MARK,2105};2106static const unsigned int msiof4_rxd_pins[] = {2107 /* MSIOF4_RXD */2108 RCAR_GP_PIN(1, 27),2109};2110static const unsigned int msiof4_rxd_mux[] = {2111 MSIOF4_RXD_MARK,2112};2113 2114/* - MSIOF5 ----------------------------------------------------------------- */2115static const unsigned int msiof5_clk_pins[] = {2116 /* MSIOF5_SCK */2117 RCAR_GP_PIN(0, 11),2118};2119static const unsigned int msiof5_clk_mux[] = {2120 MSIOF5_SCK_MARK,2121};2122static const unsigned int msiof5_sync_pins[] = {2123 /* MSIOF5_SYNC */2124 RCAR_GP_PIN(0, 9),2125};2126static const unsigned int msiof5_sync_mux[] = {2127 MSIOF5_SYNC_MARK,2128};2129static const unsigned int msiof5_ss1_pins[] = {2130 /* MSIOF5_SS1 */2131 RCAR_GP_PIN(0, 8),2132};2133static const unsigned int msiof5_ss1_mux[] = {2134 MSIOF5_SS1_MARK,2135};2136static const unsigned int msiof5_ss2_pins[] = {2137 /* MSIOF5_SS2 */2138 RCAR_GP_PIN(0, 7),2139};2140static const unsigned int msiof5_ss2_mux[] = {2141 MSIOF5_SS2_MARK,2142};2143static const unsigned int msiof5_txd_pins[] = {2144 /* MSIOF5_TXD */2145 RCAR_GP_PIN(0, 10),2146};2147static const unsigned int msiof5_txd_mux[] = {2148 MSIOF5_TXD_MARK,2149};2150static const unsigned int msiof5_rxd_pins[] = {2151 /* MSIOF5_RXD */2152 RCAR_GP_PIN(0, 12),2153};2154static const unsigned int msiof5_rxd_mux[] = {2155 MSIOF5_RXD_MARK,2156};2157 2158/* - PCIE ------------------------------------------------------------------- */2159static const unsigned int pcie0_clkreq_n_pins[] = {2160 /* PCIE0_CLKREQ_N */2161 RCAR_GP_PIN(4, 21),2162};2163 2164static const unsigned int pcie0_clkreq_n_mux[] = {2165 PCIE0_CLKREQ_N_MARK,2166};2167 2168static const unsigned int pcie1_clkreq_n_pins[] = {2169 /* PCIE1_CLKREQ_N */2170 RCAR_GP_PIN(4, 22),2171};2172 2173static const unsigned int pcie1_clkreq_n_mux[] = {2174 PCIE1_CLKREQ_N_MARK,2175};2176 2177/* - PWM0 ------------------------------------------------------------------- */2178static const unsigned int pwm0_pins[] = {2179 /* PWM0 */2180 RCAR_GP_PIN(1, 15),2181};2182static const unsigned int pwm0_mux[] = {2183 PWM0_MARK,2184};2185 2186/* - PWM1 ------------------------------------------------------------------- */2187static const unsigned int pwm1_a_pins[] = {2188 /* PWM1_A */2189 RCAR_GP_PIN(3, 13),2190};2191static const unsigned int pwm1_a_mux[] = {2192 PWM1_A_MARK,2193};2194 2195static const unsigned int pwm1_b_pins[] = {2196 /* PWM1_B */2197 RCAR_GP_PIN(2, 13),2198};2199static const unsigned int pwm1_b_mux[] = {2200 PWM1_B_MARK,2201};2202 2203/* - PWM2 ------------------------------------------------------------------- */2204static const unsigned int pwm2_pins[] = {2205 /* PWM2 */2206 RCAR_GP_PIN(2, 14),2207};2208static const unsigned int pwm2_mux[] = {2209 PWM2_MARK,2210};2211 2212/* - PWM3 ------------------------------------------------------------------- */2213static const unsigned int pwm3_a_pins[] = {2214 /* PWM3_A */2215 RCAR_GP_PIN(1, 22),2216};2217static const unsigned int pwm3_a_mux[] = {2218 PWM3_A_MARK,2219};2220 2221static const unsigned int pwm3_b_pins[] = {2222 /* PWM3_B */2223 RCAR_GP_PIN(2, 15),2224};2225static const unsigned int pwm3_b_mux[] = {2226 PWM3_B_MARK,2227};2228 2229/* - PWM4 ------------------------------------------------------------------- */2230static const unsigned int pwm4_pins[] = {2231 /* PWM4 */2232 RCAR_GP_PIN(2, 16),2233};2234static const unsigned int pwm4_mux[] = {2235 PWM4_MARK,2236};2237 2238/* - PWM5 ------------------------------------------------------------------- */2239static const unsigned int pwm5_pins[] = {2240 /* PWM5 */2241 RCAR_GP_PIN(2, 17),2242};2243static const unsigned int pwm5_mux[] = {2244 PWM5_MARK,2245};2246 2247/* - PWM6 ------------------------------------------------------------------- */2248static const unsigned int pwm6_pins[] = {2249 /* PWM6 */2250 RCAR_GP_PIN(2, 18),2251};2252static const unsigned int pwm6_mux[] = {2253 PWM6_MARK,2254};2255 2256/* - PWM7 ------------------------------------------------------------------- */2257static const unsigned int pwm7_pins[] = {2258 /* PWM7 */2259 RCAR_GP_PIN(2, 19),2260};2261static const unsigned int pwm7_mux[] = {2262 PWM7_MARK,2263};2264 2265/* - PWM8 ------------------------------------------------------------------- */2266static const unsigned int pwm8_pins[] = {2267 /* PWM8 */2268 RCAR_GP_PIN(1, 13),2269};2270static const unsigned int pwm8_mux[] = {2271 PWM8_MARK,2272};2273 2274/* - PWM9 ------------------------------------------------------------------- */2275static const unsigned int pwm9_pins[] = {2276 /* PWM9 */2277 RCAR_GP_PIN(1, 14),2278};2279static const unsigned int pwm9_mux[] = {2280 PWM9_MARK,2281};2282 2283/* - QSPI0 ------------------------------------------------------------------ */2284static const unsigned int qspi0_ctrl_pins[] = {2285 /* SPCLK, SSL */2286 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),2287};2288static const unsigned int qspi0_ctrl_mux[] = {2289 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,2290};2291static const unsigned int qspi0_data_pins[] = {2292 /* MOSI_IO0, MISO_IO1, IO2, IO3 */2293 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),2294 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),2295};2296static const unsigned int qspi0_data_mux[] = {2297 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,2298 QSPI0_IO2_MARK, QSPI0_IO3_MARK2299};2300 2301/* - QSPI1 ------------------------------------------------------------------ */2302static const unsigned int qspi1_ctrl_pins[] = {2303 /* SPCLK, SSL */2304 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),2305};2306static const unsigned int qspi1_ctrl_mux[] = {2307 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,2308};2309static const unsigned int qspi1_data_pins[] = {2310 /* MOSI_IO0, MISO_IO1, IO2, IO3 */2311 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),2312 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),2313};2314static const unsigned int qspi1_data_mux[] = {2315 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,2316 QSPI1_IO2_MARK, QSPI1_IO3_MARK2317};2318 2319/* - SCIF0 ------------------------------------------------------------------ */2320static const unsigned int scif0_data_pins[] = {2321 /* RX0, TX0 */2322 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),2323};2324static const unsigned int scif0_data_mux[] = {2325 RX0_MARK, TX0_MARK,2326};2327static const unsigned int scif0_clk_pins[] = {2328 /* SCK0 */2329 RCAR_GP_PIN(1, 15),2330};2331static const unsigned int scif0_clk_mux[] = {2332 SCK0_MARK,2333};2334static const unsigned int scif0_ctrl_pins[] = {2335 /* RTS0_N, CTS0_N */2336 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),2337};2338static const unsigned int scif0_ctrl_mux[] = {2339 RTS0_N_MARK, CTS0_N_MARK,2340};2341 2342/* - SCIF1 ------------------------------------------------------------------ */2343static const unsigned int scif1_data_a_pins[] = {2344 /* RX1_A, TX1_A */2345 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),2346};2347static const unsigned int scif1_data_a_mux[] = {2348 RX1_A_MARK, TX1_A_MARK,2349};2350static const unsigned int scif1_clk_a_pins[] = {2351 /* SCK1_A */2352 RCAR_GP_PIN(0, 18),2353};2354static const unsigned int scif1_clk_a_mux[] = {2355 SCK1_A_MARK,2356};2357static const unsigned int scif1_ctrl_a_pins[] = {2358 /* RTS1_N_A, CTS1_N_A */2359 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),2360};2361static const unsigned int scif1_ctrl_a_mux[] = {2362 RTS1_N_A_MARK, CTS1_N_A_MARK,2363};2364 2365static const unsigned int scif1_data_b_pins[] = {2366 /* RX1_B, TX1_B */2367 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),2368};2369static const unsigned int scif1_data_b_mux[] = {2370 RX1_B_MARK, TX1_B_MARK,2371};2372static const unsigned int scif1_clk_b_pins[] = {2373 /* SCK1_B */2374 RCAR_GP_PIN(1, 10),2375};2376static const unsigned int scif1_clk_b_mux[] = {2377 SCK1_B_MARK,2378};2379static const unsigned int scif1_ctrl_b_pins[] = {2380 /* RTS1_N_B, CTS1_N_B */2381 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),2382};2383static const unsigned int scif1_ctrl_b_mux[] = {2384 RTS1_N_B_MARK, CTS1_N_B_MARK,2385};2386 2387/* - SCIF3 ------------------------------------------------------------------ */2388static const unsigned int scif3_data_a_pins[] = {2389 /* RX3_A, TX3_A */2390 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),2391};2392static const unsigned int scif3_data_a_mux[] = {2393 RX3_A_MARK, TX3_A_MARK,2394};2395static const unsigned int scif3_clk_a_pins[] = {2396 /* SCK3_A */2397 RCAR_GP_PIN(1, 24),2398};2399static const unsigned int scif3_clk_a_mux[] = {2400 SCK3_A_MARK,2401};2402static const unsigned int scif3_ctrl_a_pins[] = {2403 /* RTS3_N_A, CTS3_N_A */2404 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),2405};2406static const unsigned int scif3_ctrl_a_mux[] = {2407 RTS3_N_A_MARK, CTS3_N_A_MARK,2408};2409 2410static const unsigned int scif3_data_b_pins[] = {2411 /* RX3_B, TX3_B */2412 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),2413};2414static const unsigned int scif3_data_b_mux[] = {2415 RX3_B_MARK, TX3_B_MARK,2416};2417static const unsigned int scif3_clk_b_pins[] = {2418 /* SCK3_B */2419 RCAR_GP_PIN(1, 4),2420};2421static const unsigned int scif3_clk_b_mux[] = {2422 SCK3_B_MARK,2423};2424static const unsigned int scif3_ctrl_b_pins[] = {2425 /* RTS3_N_B, CTS3_N_B */2426 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),2427};2428static const unsigned int scif3_ctrl_b_mux[] = {2429 RTS3_N_B_MARK, CTS3_N_B_MARK,2430};2431 2432/* - SCIF4 ------------------------------------------------------------------ */2433static const unsigned int scif4_data_pins[] = {2434 /* RX4, TX4 */2435 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),2436};2437static const unsigned int scif4_data_mux[] = {2438 RX4_MARK, TX4_MARK,2439};2440static const unsigned int scif4_clk_pins[] = {2441 /* SCK4 */2442 RCAR_GP_PIN(8, 8),2443};2444static const unsigned int scif4_clk_mux[] = {2445 SCK4_MARK,2446};2447static const unsigned int scif4_ctrl_pins[] = {2448 /* RTS4_N, CTS4_N */2449 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),2450};2451static const unsigned int scif4_ctrl_mux[] = {2452 RTS4_N_MARK, CTS4_N_MARK,2453};2454 2455/* - SCIF Clock ------------------------------------------------------------- */2456static const unsigned int scif_clk_pins[] = {2457 /* SCIF_CLK */2458 RCAR_GP_PIN(1, 17),2459};2460static const unsigned int scif_clk_mux[] = {2461 SCIF_CLK_MARK,2462};2463 2464static const unsigned int scif_clk2_pins[] = {2465 /* SCIF_CLK2 */2466 RCAR_GP_PIN(8, 11),2467};2468static const unsigned int scif_clk2_mux[] = {2469 SCIF_CLK2_MARK,2470};2471 2472/* - SSI ------------------------------------------------- */2473static const unsigned int ssi_data_pins[] = {2474 /* SSI_SD */2475 RCAR_GP_PIN(1, 20),2476};2477static const unsigned int ssi_data_mux[] = {2478 SSI_SD_MARK,2479};2480static const unsigned int ssi_ctrl_pins[] = {2481 /* SSI_SCK, SSI_WS */2482 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),2483};2484static const unsigned int ssi_ctrl_mux[] = {2485 SSI_SCK_MARK, SSI_WS_MARK,2486};2487 2488/* - TPU -------------------------------------------------------------------- */2489static const unsigned int tpu_to0_a_pins[] = {2490 /* TPU0TO0_A */2491 RCAR_GP_PIN(2, 8),2492};2493static const unsigned int tpu_to0_a_mux[] = {2494 TPU0TO0_A_MARK,2495};2496static const unsigned int tpu_to1_a_pins[] = {2497 /* TPU0TO1_A */2498 RCAR_GP_PIN(2, 7),2499};2500static const unsigned int tpu_to1_a_mux[] = {2501 TPU0TO1_A_MARK,2502};2503static const unsigned int tpu_to2_a_pins[] = {2504 /* TPU0TO2_A */2505 RCAR_GP_PIN(2, 12),2506};2507static const unsigned int tpu_to2_a_mux[] = {2508 TPU0TO2_A_MARK,2509};2510static const unsigned int tpu_to3_a_pins[] = {2511 /* TPU0TO3_A */2512 RCAR_GP_PIN(2, 13),2513};2514static const unsigned int tpu_to3_a_mux[] = {2515 TPU0TO3_A_MARK,2516};2517 2518static const unsigned int tpu_to0_b_pins[] = {2519 /* TPU0TO0_B */2520 RCAR_GP_PIN(1, 25),2521};2522static const unsigned int tpu_to0_b_mux[] = {2523 TPU0TO0_B_MARK,2524};2525static const unsigned int tpu_to1_b_pins[] = {2526 /* TPU0TO1_B */2527 RCAR_GP_PIN(1, 26),2528};2529static const unsigned int tpu_to1_b_mux[] = {2530 TPU0TO1_B_MARK,2531};2532static const unsigned int tpu_to2_b_pins[] = {2533 /* TPU0TO2_B */2534 RCAR_GP_PIN(2, 0),2535};2536static const unsigned int tpu_to2_b_mux[] = {2537 TPU0TO2_B_MARK,2538};2539static const unsigned int tpu_to3_b_pins[] = {2540 /* TPU0TO3_B */2541 RCAR_GP_PIN(2, 1),2542};2543static const unsigned int tpu_to3_b_mux[] = {2544 TPU0TO3_B_MARK,2545};2546 2547/* - TSN0 ------------------------------------------------ */2548static const unsigned int tsn0_link_pins[] = {2549 /* TSN0_LINK */2550 RCAR_GP_PIN(4, 4),2551};2552static const unsigned int tsn0_link_mux[] = {2553 TSN0_LINK_MARK,2554};2555static const unsigned int tsn0_phy_int_pins[] = {2556 /* TSN0_PHY_INT */2557 RCAR_GP_PIN(4, 3),2558};2559static const unsigned int tsn0_phy_int_mux[] = {2560 TSN0_PHY_INT_MARK,2561};2562static const unsigned int tsn0_mdio_pins[] = {2563 /* TSN0_MDC, TSN0_MDIO */2564 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),2565};2566static const unsigned int tsn0_mdio_mux[] = {2567 TSN0_MDC_MARK, TSN0_MDIO_MARK,2568};2569static const unsigned int tsn0_rgmii_pins[] = {2570 /*2571 * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,2572 * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,2573 */2574 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),2575 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),2576 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),2577 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),2578 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),2579 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),2580};2581static const unsigned int tsn0_rgmii_mux[] = {2582 TSN0_TX_CTL_MARK, TSN0_TXC_MARK,2583 TSN0_TD0_MARK, TSN0_TD1_MARK,2584 TSN0_TD2_MARK, TSN0_TD3_MARK,2585 TSN0_RX_CTL_MARK, TSN0_RXC_MARK,2586 TSN0_RD0_MARK, TSN0_RD1_MARK,2587 TSN0_RD2_MARK, TSN0_RD3_MARK,2588};2589static const unsigned int tsn0_txcrefclk_pins[] = {2590 /* TSN0_TXCREFCLK */2591 RCAR_GP_PIN(4, 20),2592};2593static const unsigned int tsn0_txcrefclk_mux[] = {2594 TSN0_TXCREFCLK_MARK,2595};2596static const unsigned int tsn0_avtp_pps_pins[] = {2597 /* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */2598 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),2599};2600static const unsigned int tsn0_avtp_pps_mux[] = {2601 TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,2602};2603static const unsigned int tsn0_avtp_capture_pins[] = {2604 /* TSN0_AVTP_CAPTURE */2605 RCAR_GP_PIN(4, 6),2606};2607static const unsigned int tsn0_avtp_capture_mux[] = {2608 TSN0_AVTP_CAPTURE_MARK,2609};2610static const unsigned int tsn0_avtp_match_pins[] = {2611 /* TSN0_AVTP_MATCH */2612 RCAR_GP_PIN(4, 5),2613};2614static const unsigned int tsn0_avtp_match_mux[] = {2615 TSN0_AVTP_MATCH_MARK,2616};2617 2618static const struct sh_pfc_pin_group pinmux_groups[] = {2619 SH_PFC_PIN_GROUP(audio_clkin),2620 SH_PFC_PIN_GROUP(audio_clkout),2621 2622 SH_PFC_PIN_GROUP(avb0_link),2623 SH_PFC_PIN_GROUP(avb0_magic),2624 SH_PFC_PIN_GROUP(avb0_phy_int),2625 SH_PFC_PIN_GROUP(avb0_mdio),2626 SH_PFC_PIN_GROUP(avb0_rgmii),2627 SH_PFC_PIN_GROUP(avb0_txcrefclk),2628 SH_PFC_PIN_GROUP(avb0_avtp_pps),2629 SH_PFC_PIN_GROUP(avb0_avtp_capture),2630 SH_PFC_PIN_GROUP(avb0_avtp_match),2631 2632 SH_PFC_PIN_GROUP(avb1_link),2633 SH_PFC_PIN_GROUP(avb1_magic),2634 SH_PFC_PIN_GROUP(avb1_phy_int),2635 SH_PFC_PIN_GROUP(avb1_mdio),2636 SH_PFC_PIN_GROUP(avb1_rgmii),2637 SH_PFC_PIN_GROUP(avb1_txcrefclk),2638 SH_PFC_PIN_GROUP(avb1_avtp_pps),2639 SH_PFC_PIN_GROUP(avb1_avtp_capture),2640 SH_PFC_PIN_GROUP(avb1_avtp_match),2641 2642 SH_PFC_PIN_GROUP(avb2_link),2643 SH_PFC_PIN_GROUP(avb2_magic),2644 SH_PFC_PIN_GROUP(avb2_phy_int),2645 SH_PFC_PIN_GROUP(avb2_mdio),2646 SH_PFC_PIN_GROUP(avb2_rgmii),2647 SH_PFC_PIN_GROUP(avb2_txcrefclk),2648 SH_PFC_PIN_GROUP(avb2_avtp_pps),2649 SH_PFC_PIN_GROUP(avb2_avtp_capture),2650 SH_PFC_PIN_GROUP(avb2_avtp_match),2651 2652 SH_PFC_PIN_GROUP(canfd0_data),2653 SH_PFC_PIN_GROUP(canfd1_data),2654 SH_PFC_PIN_GROUP(canfd2_data),2655 SH_PFC_PIN_GROUP(canfd3_data),2656 SH_PFC_PIN_GROUP(canfd4_data),2657 SH_PFC_PIN_GROUP(canfd5_data_a),2658 SH_PFC_PIN_GROUP(canfd5_data_b),2659 SH_PFC_PIN_GROUP(canfd6_data),2660 SH_PFC_PIN_GROUP(canfd7_data),2661 SH_PFC_PIN_GROUP(can_clk),2662 2663 SH_PFC_PIN_GROUP(hscif0_data),2664 SH_PFC_PIN_GROUP(hscif0_clk),2665 SH_PFC_PIN_GROUP(hscif0_ctrl),2666 SH_PFC_PIN_GROUP(hscif1_data_a),2667 SH_PFC_PIN_GROUP(hscif1_clk_a),2668 SH_PFC_PIN_GROUP(hscif1_ctrl_a),2669 SH_PFC_PIN_GROUP(hscif1_data_b),2670 SH_PFC_PIN_GROUP(hscif1_clk_b),2671 SH_PFC_PIN_GROUP(hscif1_ctrl_b),2672 SH_PFC_PIN_GROUP(hscif2_data),2673 SH_PFC_PIN_GROUP(hscif2_clk),2674 SH_PFC_PIN_GROUP(hscif2_ctrl),2675 SH_PFC_PIN_GROUP(hscif3_data_a),2676 SH_PFC_PIN_GROUP(hscif3_clk_a),2677 SH_PFC_PIN_GROUP(hscif3_ctrl_a),2678 SH_PFC_PIN_GROUP(hscif3_data_b),2679 SH_PFC_PIN_GROUP(hscif3_clk_b),2680 SH_PFC_PIN_GROUP(hscif3_ctrl_b),2681 2682 SH_PFC_PIN_GROUP(i2c0),2683 SH_PFC_PIN_GROUP(i2c1),2684 SH_PFC_PIN_GROUP(i2c2),2685 SH_PFC_PIN_GROUP(i2c3),2686 SH_PFC_PIN_GROUP(i2c4),2687 SH_PFC_PIN_GROUP(i2c5),2688 2689 SH_PFC_PIN_GROUP(intc_ex_irq0_a),2690 SH_PFC_PIN_GROUP(intc_ex_irq0_b),2691 SH_PFC_PIN_GROUP(intc_ex_irq1_a),2692 SH_PFC_PIN_GROUP(intc_ex_irq1_b),2693 SH_PFC_PIN_GROUP(intc_ex_irq2_a),2694 SH_PFC_PIN_GROUP(intc_ex_irq2_b),2695 SH_PFC_PIN_GROUP(intc_ex_irq3_a),2696 SH_PFC_PIN_GROUP(intc_ex_irq3_b),2697 SH_PFC_PIN_GROUP(intc_ex_irq4_a),2698 SH_PFC_PIN_GROUP(intc_ex_irq4_b),2699 SH_PFC_PIN_GROUP(intc_ex_irq5),2700 2701 BUS_DATA_PIN_GROUP(mmc_data, 1),2702 BUS_DATA_PIN_GROUP(mmc_data, 4),2703 BUS_DATA_PIN_GROUP(mmc_data, 8),2704 SH_PFC_PIN_GROUP(mmc_ctrl),2705 SH_PFC_PIN_GROUP(mmc_cd),2706 SH_PFC_PIN_GROUP(mmc_wp),2707 SH_PFC_PIN_GROUP(mmc_ds),2708 2709 SH_PFC_PIN_GROUP(msiof0_clk),2710 SH_PFC_PIN_GROUP(msiof0_sync),2711 SH_PFC_PIN_GROUP(msiof0_ss1),2712 SH_PFC_PIN_GROUP(msiof0_ss2),2713 SH_PFC_PIN_GROUP(msiof0_txd),2714 SH_PFC_PIN_GROUP(msiof0_rxd),2715 2716 SH_PFC_PIN_GROUP(msiof1_clk),2717 SH_PFC_PIN_GROUP(msiof1_sync),2718 SH_PFC_PIN_GROUP(msiof1_ss1),2719 SH_PFC_PIN_GROUP(msiof1_ss2),2720 SH_PFC_PIN_GROUP(msiof1_txd),2721 SH_PFC_PIN_GROUP(msiof1_rxd),2722 2723 SH_PFC_PIN_GROUP(msiof2_clk),2724 SH_PFC_PIN_GROUP(msiof2_sync),2725 SH_PFC_PIN_GROUP(msiof2_ss1),2726 SH_PFC_PIN_GROUP(msiof2_ss2),2727 SH_PFC_PIN_GROUP(msiof2_txd),2728 SH_PFC_PIN_GROUP(msiof2_rxd),2729 2730 SH_PFC_PIN_GROUP(msiof3_clk),2731 SH_PFC_PIN_GROUP(msiof3_sync),2732 SH_PFC_PIN_GROUP(msiof3_ss1),2733 SH_PFC_PIN_GROUP(msiof3_ss2),2734 SH_PFC_PIN_GROUP(msiof3_txd),2735 SH_PFC_PIN_GROUP(msiof3_rxd),2736 2737 SH_PFC_PIN_GROUP(msiof4_clk),2738 SH_PFC_PIN_GROUP(msiof4_sync),2739 SH_PFC_PIN_GROUP(msiof4_ss1),2740 SH_PFC_PIN_GROUP(msiof4_ss2),2741 SH_PFC_PIN_GROUP(msiof4_txd),2742 SH_PFC_PIN_GROUP(msiof4_rxd),2743 2744 SH_PFC_PIN_GROUP(msiof5_clk),2745 SH_PFC_PIN_GROUP(msiof5_sync),2746 SH_PFC_PIN_GROUP(msiof5_ss1),2747 SH_PFC_PIN_GROUP(msiof5_ss2),2748 SH_PFC_PIN_GROUP(msiof5_txd),2749 SH_PFC_PIN_GROUP(msiof5_rxd),2750 2751 SH_PFC_PIN_GROUP(pcie0_clkreq_n),2752 SH_PFC_PIN_GROUP(pcie1_clkreq_n),2753 2754 SH_PFC_PIN_GROUP(pwm0),2755 SH_PFC_PIN_GROUP(pwm1_a),2756 SH_PFC_PIN_GROUP(pwm1_b),2757 SH_PFC_PIN_GROUP(pwm2),2758 SH_PFC_PIN_GROUP(pwm3_a),2759 SH_PFC_PIN_GROUP(pwm3_b),2760 SH_PFC_PIN_GROUP(pwm4),2761 SH_PFC_PIN_GROUP(pwm5),2762 SH_PFC_PIN_GROUP(pwm6),2763 SH_PFC_PIN_GROUP(pwm7),2764 SH_PFC_PIN_GROUP(pwm8),2765 SH_PFC_PIN_GROUP(pwm9),2766 2767 SH_PFC_PIN_GROUP(qspi0_ctrl),2768 BUS_DATA_PIN_GROUP(qspi0_data, 2),2769 BUS_DATA_PIN_GROUP(qspi0_data, 4),2770 SH_PFC_PIN_GROUP(qspi1_ctrl),2771 BUS_DATA_PIN_GROUP(qspi1_data, 2),2772 BUS_DATA_PIN_GROUP(qspi1_data, 4),2773 2774 SH_PFC_PIN_GROUP(scif0_data),2775 SH_PFC_PIN_GROUP(scif0_clk),2776 SH_PFC_PIN_GROUP(scif0_ctrl),2777 SH_PFC_PIN_GROUP(scif1_data_a),2778 SH_PFC_PIN_GROUP(scif1_clk_a),2779 SH_PFC_PIN_GROUP(scif1_ctrl_a),2780 SH_PFC_PIN_GROUP(scif1_data_b),2781 SH_PFC_PIN_GROUP(scif1_clk_b),2782 SH_PFC_PIN_GROUP(scif1_ctrl_b),2783 SH_PFC_PIN_GROUP(scif3_data_a),2784 SH_PFC_PIN_GROUP(scif3_clk_a),2785 SH_PFC_PIN_GROUP(scif3_ctrl_a),2786 SH_PFC_PIN_GROUP(scif3_data_b),2787 SH_PFC_PIN_GROUP(scif3_clk_b),2788 SH_PFC_PIN_GROUP(scif3_ctrl_b),2789 SH_PFC_PIN_GROUP(scif4_data),2790 SH_PFC_PIN_GROUP(scif4_clk),2791 SH_PFC_PIN_GROUP(scif4_ctrl),2792 SH_PFC_PIN_GROUP(scif_clk),2793 SH_PFC_PIN_GROUP(scif_clk2),2794 2795 SH_PFC_PIN_GROUP(ssi_data),2796 SH_PFC_PIN_GROUP(ssi_ctrl),2797 2798 SH_PFC_PIN_GROUP(tpu_to0_a),2799 SH_PFC_PIN_GROUP(tpu_to0_b),2800 SH_PFC_PIN_GROUP(tpu_to1_a),2801 SH_PFC_PIN_GROUP(tpu_to1_b),2802 SH_PFC_PIN_GROUP(tpu_to2_a),2803 SH_PFC_PIN_GROUP(tpu_to2_b),2804 SH_PFC_PIN_GROUP(tpu_to3_a),2805 SH_PFC_PIN_GROUP(tpu_to3_b),2806 2807 SH_PFC_PIN_GROUP(tsn0_link),2808 SH_PFC_PIN_GROUP(tsn0_phy_int),2809 SH_PFC_PIN_GROUP(tsn0_mdio),2810 SH_PFC_PIN_GROUP(tsn0_rgmii),2811 SH_PFC_PIN_GROUP(tsn0_txcrefclk),2812 SH_PFC_PIN_GROUP(tsn0_avtp_pps),2813 SH_PFC_PIN_GROUP(tsn0_avtp_capture),2814 SH_PFC_PIN_GROUP(tsn0_avtp_match),2815};2816 2817static const char * const audio_clk_groups[] = {2818 "audio_clkin",2819 "audio_clkout",2820};2821 2822static const char * const avb0_groups[] = {2823 "avb0_link",2824 "avb0_magic",2825 "avb0_phy_int",2826 "avb0_mdio",2827 "avb0_rgmii",2828 "avb0_txcrefclk",2829 "avb0_avtp_pps",2830 "avb0_avtp_capture",2831 "avb0_avtp_match",2832};2833 2834static const char * const avb1_groups[] = {2835 "avb1_link",2836 "avb1_magic",2837 "avb1_phy_int",2838 "avb1_mdio",2839 "avb1_rgmii",2840 "avb1_txcrefclk",2841 "avb1_avtp_pps",2842 "avb1_avtp_capture",2843 "avb1_avtp_match",2844};2845 2846static const char * const avb2_groups[] = {2847 "avb2_link",2848 "avb2_magic",2849 "avb2_phy_int",2850 "avb2_mdio",2851 "avb2_rgmii",2852 "avb2_txcrefclk",2853 "avb2_avtp_pps",2854 "avb2_avtp_capture",2855 "avb2_avtp_match",2856};2857 2858static const char * const canfd0_groups[] = {2859 "canfd0_data",2860};2861 2862static const char * const canfd1_groups[] = {2863 "canfd1_data",2864};2865 2866static const char * const canfd2_groups[] = {2867 "canfd2_data",2868};2869 2870static const char * const canfd3_groups[] = {2871 "canfd3_data",2872};2873 2874static const char * const canfd4_groups[] = {2875 "canfd4_data",2876};2877 2878static const char * const canfd5_groups[] = {2879 "canfd5_data_a",2880 "canfd5_data_b",2881};2882 2883static const char * const canfd6_groups[] = {2884 "canfd6_data",2885};2886 2887static const char * const canfd7_groups[] = {2888 "canfd7_data",2889};2890 2891static const char * const can_clk_groups[] = {2892 "can_clk",2893};2894 2895static const char * const hscif0_groups[] = {2896 "hscif0_data",2897 "hscif0_clk",2898 "hscif0_ctrl",2899};2900 2901static const char * const hscif1_groups[] = {2902 "hscif1_data_a",2903 "hscif1_clk_a",2904 "hscif1_ctrl_a",2905 "hscif1_data_b",2906 "hscif1_clk_b",2907 "hscif1_ctrl_b",2908};2909 2910static const char * const hscif2_groups[] = {2911 "hscif2_data",2912 "hscif2_clk",2913 "hscif2_ctrl",2914};2915 2916static const char * const hscif3_groups[] = {2917 "hscif3_data_a",2918 "hscif3_clk_a",2919 "hscif3_ctrl_a",2920 "hscif3_data_b",2921 "hscif3_clk_b",2922 "hscif3_ctrl_b",2923};2924 2925static const char * const i2c0_groups[] = {2926 "i2c0",2927};2928 2929static const char * const i2c1_groups[] = {2930 "i2c1",2931};2932 2933static const char * const i2c2_groups[] = {2934 "i2c2",2935};2936 2937static const char * const i2c3_groups[] = {2938 "i2c3",2939};2940 2941static const char * const i2c4_groups[] = {2942 "i2c4",2943};2944 2945static const char * const i2c5_groups[] = {2946 "i2c5",2947};2948 2949static const char * const intc_ex_groups[] = {2950 "intc_ex_irq0_a",2951 "intc_ex_irq0_b",2952 "intc_ex_irq1_a",2953 "intc_ex_irq1_b",2954 "intc_ex_irq2_a",2955 "intc_ex_irq2_b",2956 "intc_ex_irq3_a",2957 "intc_ex_irq3_b",2958 "intc_ex_irq4_a",2959 "intc_ex_irq4_b",2960 "intc_ex_irq5",2961};2962 2963static const char * const mmc_groups[] = {2964 "mmc_data1",2965 "mmc_data4",2966 "mmc_data8",2967 "mmc_ctrl",2968 "mmc_cd",2969 "mmc_wp",2970 "mmc_ds",2971};2972 2973static const char * const msiof0_groups[] = {2974 "msiof0_clk",2975 "msiof0_sync",2976 "msiof0_ss1",2977 "msiof0_ss2",2978 "msiof0_txd",2979 "msiof0_rxd",2980};2981 2982static const char * const msiof1_groups[] = {2983 "msiof1_clk",2984 "msiof1_sync",2985 "msiof1_ss1",2986 "msiof1_ss2",2987 "msiof1_txd",2988 "msiof1_rxd",2989};2990 2991static const char * const msiof2_groups[] = {2992 "msiof2_clk",2993 "msiof2_sync",2994 "msiof2_ss1",2995 "msiof2_ss2",2996 "msiof2_txd",2997 "msiof2_rxd",2998};2999 3000static const char * const msiof3_groups[] = {3001 "msiof3_clk",3002 "msiof3_sync",3003 "msiof3_ss1",3004 "msiof3_ss2",3005 "msiof3_txd",3006 "msiof3_rxd",3007};3008 3009static const char * const msiof4_groups[] = {3010 "msiof4_clk",3011 "msiof4_sync",3012 "msiof4_ss1",3013 "msiof4_ss2",3014 "msiof4_txd",3015 "msiof4_rxd",3016};3017 3018static const char * const msiof5_groups[] = {3019 "msiof5_clk",3020 "msiof5_sync",3021 "msiof5_ss1",3022 "msiof5_ss2",3023 "msiof5_txd",3024 "msiof5_rxd",3025};3026 3027static const char * const pcie_groups[] = {3028 "pcie0_clkreq_n",3029 "pcie1_clkreq_n",3030};3031 3032static const char * const pwm0_groups[] = {3033 "pwm0",3034};3035 3036static const char * const pwm1_groups[] = {3037 "pwm1_a",3038 "pwm1_b",3039};3040 3041static const char * const pwm2_groups[] = {3042 "pwm2",3043};3044 3045static const char * const pwm3_groups[] = {3046 "pwm3_a",3047 "pwm3_b",3048};3049 3050static const char * const pwm4_groups[] = {3051 "pwm4",3052};3053 3054static const char * const pwm5_groups[] = {3055 "pwm5",3056};3057 3058static const char * const pwm6_groups[] = {3059 "pwm6",3060};3061 3062static const char * const pwm7_groups[] = {3063 "pwm7",3064};3065 3066static const char * const pwm8_groups[] = {3067 "pwm8",3068};3069 3070static const char * const pwm9_groups[] = {3071 "pwm9",3072};3073 3074static const char * const qspi0_groups[] = {3075 "qspi0_ctrl",3076 "qspi0_data2",3077 "qspi0_data4",3078};3079 3080static const char * const qspi1_groups[] = {3081 "qspi1_ctrl",3082 "qspi1_data2",3083 "qspi1_data4",3084};3085 3086static const char * const scif0_groups[] = {3087 "scif0_data",3088 "scif0_clk",3089 "scif0_ctrl",3090};3091 3092static const char * const scif1_groups[] = {3093 "scif1_data_a",3094 "scif1_clk_a",3095 "scif1_ctrl_a",3096 "scif1_data_b",3097 "scif1_clk_b",3098 "scif1_ctrl_b",3099};3100 3101static const char * const scif3_groups[] = {3102 "scif3_data_a",3103 "scif3_clk_a",3104 "scif3_ctrl_a",3105 "scif3_data_b",3106 "scif3_clk_b",3107 "scif3_ctrl_b",3108};3109 3110static const char * const scif4_groups[] = {3111 "scif4_data",3112 "scif4_clk",3113 "scif4_ctrl",3114};3115 3116static const char * const scif_clk_groups[] = {3117 "scif_clk",3118};3119 3120static const char * const scif_clk2_groups[] = {3121 "scif_clk2",3122};3123 3124static const char * const ssi_groups[] = {3125 "ssi_data",3126 "ssi_ctrl",3127};3128 3129static const char * const tpu_groups[] = {3130 "tpu_to0_a",3131 "tpu_to0_b",3132 "tpu_to1_a",3133 "tpu_to1_b",3134 "tpu_to2_a",3135 "tpu_to2_b",3136 "tpu_to3_a",3137 "tpu_to3_b",3138};3139 3140static const char * const tsn0_groups[] = {3141 "tsn0_link",3142 "tsn0_phy_int",3143 "tsn0_mdio",3144 "tsn0_rgmii",3145 "tsn0_txcrefclk",3146 "tsn0_avtp_pps",3147 "tsn0_avtp_capture",3148 "tsn0_avtp_match",3149};3150 3151static const struct sh_pfc_function pinmux_functions[] = {3152 SH_PFC_FUNCTION(audio_clk),3153 3154 SH_PFC_FUNCTION(avb0),3155 SH_PFC_FUNCTION(avb1),3156 SH_PFC_FUNCTION(avb2),3157 3158 SH_PFC_FUNCTION(canfd0),3159 SH_PFC_FUNCTION(canfd1),3160 SH_PFC_FUNCTION(canfd2),3161 SH_PFC_FUNCTION(canfd3),3162 SH_PFC_FUNCTION(canfd4),3163 SH_PFC_FUNCTION(canfd5),3164 SH_PFC_FUNCTION(canfd6),3165 SH_PFC_FUNCTION(canfd7),3166 SH_PFC_FUNCTION(can_clk),3167 3168 SH_PFC_FUNCTION(hscif0),3169 SH_PFC_FUNCTION(hscif1),3170 SH_PFC_FUNCTION(hscif2),3171 SH_PFC_FUNCTION(hscif3),3172 3173 SH_PFC_FUNCTION(i2c0),3174 SH_PFC_FUNCTION(i2c1),3175 SH_PFC_FUNCTION(i2c2),3176 SH_PFC_FUNCTION(i2c3),3177 SH_PFC_FUNCTION(i2c4),3178 SH_PFC_FUNCTION(i2c5),3179 3180 SH_PFC_FUNCTION(intc_ex),3181 3182 SH_PFC_FUNCTION(mmc),3183 3184 SH_PFC_FUNCTION(msiof0),3185 SH_PFC_FUNCTION(msiof1),3186 SH_PFC_FUNCTION(msiof2),3187 SH_PFC_FUNCTION(msiof3),3188 SH_PFC_FUNCTION(msiof4),3189 SH_PFC_FUNCTION(msiof5),3190 3191 SH_PFC_FUNCTION(pcie),3192 3193 SH_PFC_FUNCTION(pwm0),3194 SH_PFC_FUNCTION(pwm1),3195 SH_PFC_FUNCTION(pwm2),3196 SH_PFC_FUNCTION(pwm3),3197 SH_PFC_FUNCTION(pwm4),3198 SH_PFC_FUNCTION(pwm5),3199 SH_PFC_FUNCTION(pwm6),3200 SH_PFC_FUNCTION(pwm7),3201 SH_PFC_FUNCTION(pwm8),3202 SH_PFC_FUNCTION(pwm9),3203 3204 SH_PFC_FUNCTION(qspi0),3205 SH_PFC_FUNCTION(qspi1),3206 3207 SH_PFC_FUNCTION(scif0),3208 SH_PFC_FUNCTION(scif1),3209 SH_PFC_FUNCTION(scif3),3210 SH_PFC_FUNCTION(scif4),3211 SH_PFC_FUNCTION(scif_clk),3212 SH_PFC_FUNCTION(scif_clk2),3213 3214 SH_PFC_FUNCTION(ssi),3215 3216 SH_PFC_FUNCTION(tpu),3217 3218 SH_PFC_FUNCTION(tsn0),3219};3220 3221static const struct pinmux_cfg_reg pinmux_config_regs[] = {3222#define F_(x, y) FN_##y3223#define FM(x) FN_##x3224 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,3225 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,3226 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3227 GROUP(3228 /* GP0_31_19 RESERVED */3229 GP_0_18_FN, GPSR0_18,3230 GP_0_17_FN, GPSR0_17,3231 GP_0_16_FN, GPSR0_16,3232 GP_0_15_FN, GPSR0_15,3233 GP_0_14_FN, GPSR0_14,3234 GP_0_13_FN, GPSR0_13,3235 GP_0_12_FN, GPSR0_12,3236 GP_0_11_FN, GPSR0_11,3237 GP_0_10_FN, GPSR0_10,3238 GP_0_9_FN, GPSR0_9,3239 GP_0_8_FN, GPSR0_8,3240 GP_0_7_FN, GPSR0_7,3241 GP_0_6_FN, GPSR0_6,3242 GP_0_5_FN, GPSR0_5,3243 GP_0_4_FN, GPSR0_4,3244 GP_0_3_FN, GPSR0_3,3245 GP_0_2_FN, GPSR0_2,3246 GP_0_1_FN, GPSR0_1,3247 GP_0_0_FN, GPSR0_0, ))3248 },3249 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(3250 0, 0,3251 0, 0,3252 0, 0,3253 GP_1_28_FN, GPSR1_28,3254 GP_1_27_FN, GPSR1_27,3255 GP_1_26_FN, GPSR1_26,3256 GP_1_25_FN, GPSR1_25,3257 GP_1_24_FN, GPSR1_24,3258 GP_1_23_FN, GPSR1_23,3259 GP_1_22_FN, GPSR1_22,3260 GP_1_21_FN, GPSR1_21,3261 GP_1_20_FN, GPSR1_20,3262 GP_1_19_FN, GPSR1_19,3263 GP_1_18_FN, GPSR1_18,3264 GP_1_17_FN, GPSR1_17,3265 GP_1_16_FN, GPSR1_16,3266 GP_1_15_FN, GPSR1_15,3267 GP_1_14_FN, GPSR1_14,3268 GP_1_13_FN, GPSR1_13,3269 GP_1_12_FN, GPSR1_12,3270 GP_1_11_FN, GPSR1_11,3271 GP_1_10_FN, GPSR1_10,3272 GP_1_9_FN, GPSR1_9,3273 GP_1_8_FN, GPSR1_8,3274 GP_1_7_FN, GPSR1_7,3275 GP_1_6_FN, GPSR1_6,3276 GP_1_5_FN, GPSR1_5,3277 GP_1_4_FN, GPSR1_4,3278 GP_1_3_FN, GPSR1_3,3279 GP_1_2_FN, GPSR1_2,3280 GP_1_1_FN, GPSR1_1,3281 GP_1_0_FN, GPSR1_0, ))3282 },3283 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,3284 GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,3285 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3286 GROUP(3287 /* GP2_31_20 RESERVED */3288 GP_2_19_FN, GPSR2_19,3289 GP_2_18_FN, GPSR2_18,3290 GP_2_17_FN, GPSR2_17,3291 GP_2_16_FN, GPSR2_16,3292 GP_2_15_FN, GPSR2_15,3293 GP_2_14_FN, GPSR2_14,3294 GP_2_13_FN, GPSR2_13,3295 GP_2_12_FN, GPSR2_12,3296 GP_2_11_FN, GPSR2_11,3297 GP_2_10_FN, GPSR2_10,3298 GP_2_9_FN, GPSR2_9,3299 GP_2_8_FN, GPSR2_8,3300 GP_2_7_FN, GPSR2_7,3301 GP_2_6_FN, GPSR2_6,3302 GP_2_5_FN, GPSR2_5,3303 GP_2_4_FN, GPSR2_4,3304 GP_2_3_FN, GPSR2_3,3305 GP_2_2_FN, GPSR2_2,3306 GP_2_1_FN, GPSR2_1,3307 GP_2_0_FN, GPSR2_0, ))3308 },3309 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(3310 0, 0,3311 0, 0,3312 GP_3_29_FN, GPSR3_29,3313 GP_3_28_FN, GPSR3_28,3314 GP_3_27_FN, GPSR3_27,3315 GP_3_26_FN, GPSR3_26,3316 GP_3_25_FN, GPSR3_25,3317 GP_3_24_FN, GPSR3_24,3318 GP_3_23_FN, GPSR3_23,3319 GP_3_22_FN, GPSR3_22,3320 GP_3_21_FN, GPSR3_21,3321 GP_3_20_FN, GPSR3_20,3322 GP_3_19_FN, GPSR3_19,3323 GP_3_18_FN, GPSR3_18,3324 GP_3_17_FN, GPSR3_17,3325 GP_3_16_FN, GPSR3_16,3326 GP_3_15_FN, GPSR3_15,3327 GP_3_14_FN, GPSR3_14,3328 GP_3_13_FN, GPSR3_13,3329 GP_3_12_FN, GPSR3_12,3330 GP_3_11_FN, GPSR3_11,3331 GP_3_10_FN, GPSR3_10,3332 GP_3_9_FN, GPSR3_9,3333 GP_3_8_FN, GPSR3_8,3334 GP_3_7_FN, GPSR3_7,3335 GP_3_6_FN, GPSR3_6,3336 GP_3_5_FN, GPSR3_5,3337 GP_3_4_FN, GPSR3_4,3338 GP_3_3_FN, GPSR3_3,3339 GP_3_2_FN, GPSR3_2,3340 GP_3_1_FN, GPSR3_1,3341 GP_3_0_FN, GPSR3_0, ))3342 },3343 { PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(3344 0, 0,3345 0, 0,3346 0, 0,3347 0, 0,3348 0, 0,3349 0, 0,3350 0, 0,3351 GP_4_24_FN, GPSR4_24,3352 GP_4_23_FN, GPSR4_23,3353 GP_4_22_FN, GPSR4_22,3354 GP_4_21_FN, GPSR4_21,3355 GP_4_20_FN, GPSR4_20,3356 GP_4_19_FN, GPSR4_19,3357 GP_4_18_FN, GPSR4_18,3358 GP_4_17_FN, GPSR4_17,3359 GP_4_16_FN, GPSR4_16,3360 GP_4_15_FN, GPSR4_15,3361 GP_4_14_FN, GPSR4_14,3362 GP_4_13_FN, GPSR4_13,3363 GP_4_12_FN, GPSR4_12,3364 GP_4_11_FN, GPSR4_11,3365 GP_4_10_FN, GPSR4_10,3366 GP_4_9_FN, GPSR4_9,3367 GP_4_8_FN, GPSR4_8,3368 GP_4_7_FN, GPSR4_7,3369 GP_4_6_FN, GPSR4_6,3370 GP_4_5_FN, GPSR4_5,3371 GP_4_4_FN, GPSR4_4,3372 GP_4_3_FN, GPSR4_3,3373 GP_4_2_FN, GPSR4_2,3374 GP_4_1_FN, GPSR4_1,3375 GP_4_0_FN, GPSR4_0, ))3376 },3377 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,3378 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,3379 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3380 GROUP(3381 /* GP5_31_21 RESERVED */3382 GP_5_20_FN, GPSR5_20,3383 GP_5_19_FN, GPSR5_19,3384 GP_5_18_FN, GPSR5_18,3385 GP_5_17_FN, GPSR5_17,3386 GP_5_16_FN, GPSR5_16,3387 GP_5_15_FN, GPSR5_15,3388 GP_5_14_FN, GPSR5_14,3389 GP_5_13_FN, GPSR5_13,3390 GP_5_12_FN, GPSR5_12,3391 GP_5_11_FN, GPSR5_11,3392 GP_5_10_FN, GPSR5_10,3393 GP_5_9_FN, GPSR5_9,3394 GP_5_8_FN, GPSR5_8,3395 GP_5_7_FN, GPSR5_7,3396 GP_5_6_FN, GPSR5_6,3397 GP_5_5_FN, GPSR5_5,3398 GP_5_4_FN, GPSR5_4,3399 GP_5_3_FN, GPSR5_3,3400 GP_5_2_FN, GPSR5_2,3401 GP_5_1_FN, GPSR5_1,3402 GP_5_0_FN, GPSR5_0, ))3403 },3404 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,3405 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,3406 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3407 GROUP(3408 /* GP6_31_21 RESERVED */3409 GP_6_20_FN, GPSR6_20,3410 GP_6_19_FN, GPSR6_19,3411 GP_6_18_FN, GPSR6_18,3412 GP_6_17_FN, GPSR6_17,3413 GP_6_16_FN, GPSR6_16,3414 GP_6_15_FN, GPSR6_15,3415 GP_6_14_FN, GPSR6_14,3416 GP_6_13_FN, GPSR6_13,3417 GP_6_12_FN, GPSR6_12,3418 GP_6_11_FN, GPSR6_11,3419 GP_6_10_FN, GPSR6_10,3420 GP_6_9_FN, GPSR6_9,3421 GP_6_8_FN, GPSR6_8,3422 GP_6_7_FN, GPSR6_7,3423 GP_6_6_FN, GPSR6_6,3424 GP_6_5_FN, GPSR6_5,3425 GP_6_4_FN, GPSR6_4,3426 GP_6_3_FN, GPSR6_3,3427 GP_6_2_FN, GPSR6_2,3428 GP_6_1_FN, GPSR6_1,3429 GP_6_0_FN, GPSR6_0, ))3430 },3431 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,3432 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,3433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3434 GROUP(3435 /* GP7_31_21 RESERVED */3436 GP_7_20_FN, GPSR7_20,3437 GP_7_19_FN, GPSR7_19,3438 GP_7_18_FN, GPSR7_18,3439 GP_7_17_FN, GPSR7_17,3440 GP_7_16_FN, GPSR7_16,3441 GP_7_15_FN, GPSR7_15,3442 GP_7_14_FN, GPSR7_14,3443 GP_7_13_FN, GPSR7_13,3444 GP_7_12_FN, GPSR7_12,3445 GP_7_11_FN, GPSR7_11,3446 GP_7_10_FN, GPSR7_10,3447 GP_7_9_FN, GPSR7_9,3448 GP_7_8_FN, GPSR7_8,3449 GP_7_7_FN, GPSR7_7,3450 GP_7_6_FN, GPSR7_6,3451 GP_7_5_FN, GPSR7_5,3452 GP_7_4_FN, GPSR7_4,3453 GP_7_3_FN, GPSR7_3,3454 GP_7_2_FN, GPSR7_2,3455 GP_7_1_FN, GPSR7_1,3456 GP_7_0_FN, GPSR7_0, ))3457 },3458 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,3459 GROUP(-18, 1, 1, 1, 1,3460 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3461 GROUP(3462 /* GP8_31_14 RESERVED */3463 GP_8_13_FN, GPSR8_13,3464 GP_8_12_FN, GPSR8_12,3465 GP_8_11_FN, GPSR8_11,3466 GP_8_10_FN, GPSR8_10,3467 GP_8_9_FN, GPSR8_9,3468 GP_8_8_FN, GPSR8_8,3469 GP_8_7_FN, GPSR8_7,3470 GP_8_6_FN, GPSR8_6,3471 GP_8_5_FN, GPSR8_5,3472 GP_8_4_FN, GPSR8_4,3473 GP_8_3_FN, GPSR8_3,3474 GP_8_2_FN, GPSR8_2,3475 GP_8_1_FN, GPSR8_1,3476 GP_8_0_FN, GPSR8_0, ))3477 },3478#undef F_3479#undef FM3480 3481#define F_(x, y) x,3482#define FM(x) FN_##x,3483 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(3484 IP0SR0_31_283485 IP0SR0_27_243486 IP0SR0_23_203487 IP0SR0_19_163488 IP0SR0_15_123489 IP0SR0_11_83490 IP0SR0_7_43491 IP0SR0_3_0))3492 },3493 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(3494 IP1SR0_31_283495 IP1SR0_27_243496 IP1SR0_23_203497 IP1SR0_19_163498 IP1SR0_15_123499 IP1SR0_11_83500 IP1SR0_7_43501 IP1SR0_3_0))3502 },3503 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,3504 GROUP(-20, 4, 4, 4),3505 GROUP(3506 /* IP2SR0_31_12 RESERVED */3507 IP2SR0_11_83508 IP2SR0_7_43509 IP2SR0_3_0))3510 },3511 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(3512 IP0SR1_31_283513 IP0SR1_27_243514 IP0SR1_23_203515 IP0SR1_19_163516 IP0SR1_15_123517 IP0SR1_11_83518 IP0SR1_7_43519 IP0SR1_3_0))3520 },3521 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(3522 IP1SR1_31_283523 IP1SR1_27_243524 IP1SR1_23_203525 IP1SR1_19_163526 IP1SR1_15_123527 IP1SR1_11_83528 IP1SR1_7_43529 IP1SR1_3_0))3530 },3531 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(3532 IP2SR1_31_283533 IP2SR1_27_243534 IP2SR1_23_203535 IP2SR1_19_163536 IP2SR1_15_123537 IP2SR1_11_83538 IP2SR1_7_43539 IP2SR1_3_0))3540 },3541 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,3542 GROUP(-12, 4, 4, 4, 4, 4),3543 GROUP(3544 /* IP3SR1_31_20 RESERVED */3545 IP3SR1_19_163546 IP3SR1_15_123547 IP3SR1_11_83548 IP3SR1_7_43549 IP3SR1_3_0))3550 },3551 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(3552 IP0SR2_31_283553 IP0SR2_27_243554 IP0SR2_23_203555 IP0SR2_19_163556 IP0SR2_15_123557 IP0SR2_11_83558 IP0SR2_7_43559 IP0SR2_3_0))3560 },3561 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(3562 IP1SR2_31_283563 IP1SR2_27_243564 IP1SR2_23_203565 IP1SR2_19_163566 IP1SR2_15_123567 IP1SR2_11_83568 IP1SR2_7_43569 IP1SR2_3_0))3570 },3571 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,3572 GROUP(-16, 4, 4, 4, 4),3573 GROUP(3574 /* IP2SR2_31_16 RESERVED */3575 IP2SR2_15_123576 IP2SR2_11_83577 IP2SR2_7_43578 IP2SR2_3_0))3579 },3580 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(3581 IP0SR3_31_283582 IP0SR3_27_243583 IP0SR3_23_203584 IP0SR3_19_163585 IP0SR3_15_123586 IP0SR3_11_83587 IP0SR3_7_43588 IP0SR3_3_0))3589 },3590 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(3591 IP1SR3_31_283592 IP1SR3_27_243593 IP1SR3_23_203594 IP1SR3_19_163595 IP1SR3_15_123596 IP1SR3_11_83597 IP1SR3_7_43598 IP1SR3_3_0))3599 },3600 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(3601 IP2SR3_31_283602 IP2SR3_27_243603 IP2SR3_23_203604 IP2SR3_19_163605 IP2SR3_15_123606 IP2SR3_11_83607 IP2SR3_7_43608 IP2SR3_3_0))3609 },3610 { PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,3611 GROUP(-8, 4, 4, 4, 4, 4, 4),3612 GROUP(3613 /* IP3SR3_31_24 RESERVED */3614 IP3SR3_23_203615 IP3SR3_19_163616 IP3SR3_15_123617 IP3SR3_11_83618 IP3SR3_7_43619 IP3SR3_3_0))3620 },3621 { PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32,3622 GROUP(4, 4, 4, 4, 4, 4, 4, 4),3623 GROUP(3624 IP0SR4_31_283625 IP0SR4_27_243626 IP0SR4_23_203627 IP0SR4_19_163628 IP0SR4_15_123629 IP0SR4_11_83630 IP0SR4_7_43631 IP0SR4_3_0))3632 },3633 { PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32,3634 GROUP(4, 4, 4, 4, 4, 4, 4, 4),3635 GROUP(3636 IP1SR4_31_283637 IP1SR4_27_243638 IP1SR4_23_203639 IP1SR4_19_163640 IP1SR4_15_123641 IP1SR4_11_83642 IP1SR4_7_43643 IP1SR4_3_0))3644 },3645 { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,3646 GROUP(4, 4, 4, 4, 4, 4, 4, 4),3647 GROUP(3648 IP2SR4_31_283649 IP2SR4_27_243650 IP2SR4_23_203651 IP2SR4_19_163652 IP2SR4_15_123653 IP2SR4_11_83654 IP2SR4_7_43655 IP2SR4_3_0))3656 },3657 { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,3658 GROUP(-28, 4),3659 GROUP(3660 /* IP3SR4_31_4 RESERVED */3661 IP3SR4_3_0))3662 },3663 { PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32,3664 GROUP(4, 4, 4, 4, 4, 4, 4, 4),3665 GROUP(3666 IP0SR5_31_283667 IP0SR5_27_243668 IP0SR5_23_203669 IP0SR5_19_163670 IP0SR5_15_123671 IP0SR5_11_83672 IP0SR5_7_43673 IP0SR5_3_0))3674 },3675 { PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32,3676 GROUP(4, 4, 4, 4, 4, 4, 4, 4),3677 GROUP(3678 IP1SR5_31_283679 IP1SR5_27_243680 IP1SR5_23_203681 IP1SR5_19_163682 IP1SR5_15_123683 IP1SR5_11_83684 IP1SR5_7_43685 IP1SR5_3_0))3686 },3687 { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,3688 GROUP(-12, 4, 4, 4, 4, 4),3689 GROUP(3690 /* IP2SR5_31_20 RESERVED */3691 IP2SR5_19_163692 IP2SR5_15_123693 IP2SR5_11_83694 IP2SR5_7_43695 IP2SR5_3_0))3696 },3697 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(3698 IP0SR6_31_283699 IP0SR6_27_243700 IP0SR6_23_203701 IP0SR6_19_163702 IP0SR6_15_123703 IP0SR6_11_83704 IP0SR6_7_43705 IP0SR6_3_0))3706 },3707 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(3708 IP1SR6_31_283709 IP1SR6_27_243710 IP1SR6_23_203711 IP1SR6_19_163712 IP1SR6_15_123713 IP1SR6_11_83714 IP1SR6_7_43715 IP1SR6_3_0))3716 },3717 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,3718 GROUP(-12, 4, 4, 4, 4, 4),3719 GROUP(3720 /* IP2SR6_31_20 RESERVED */3721 IP2SR6_19_163722 IP2SR6_15_123723 IP2SR6_11_83724 IP2SR6_7_43725 IP2SR6_3_0))3726 },3727 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(3728 IP0SR7_31_283729 IP0SR7_27_243730 IP0SR7_23_203731 IP0SR7_19_163732 IP0SR7_15_123733 IP0SR7_11_83734 IP0SR7_7_43735 IP0SR7_3_0))3736 },3737 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(3738 IP1SR7_31_283739 IP1SR7_27_243740 IP1SR7_23_203741 IP1SR7_19_163742 IP1SR7_15_123743 IP1SR7_11_83744 IP1SR7_7_43745 IP1SR7_3_0))3746 },3747 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,3748 GROUP(-12, 4, 4, 4, 4, 4),3749 GROUP(3750 /* IP2SR7_31_20 RESERVED */3751 IP2SR7_19_163752 IP2SR7_15_123753 IP2SR7_11_83754 IP2SR7_7_43755 IP2SR7_3_0))3756 },3757 { PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(3758 IP0SR8_31_283759 IP0SR8_27_243760 IP0SR8_23_203761 IP0SR8_19_163762 IP0SR8_15_123763 IP0SR8_11_83764 IP0SR8_7_43765 IP0SR8_3_0))3766 },3767 { PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,3768 GROUP(-8, 4, 4, 4, 4, 4, 4),3769 GROUP(3770 /* IP1SR8_31_24 RESERVED */3771 IP1SR8_23_203772 IP1SR8_19_163773 IP1SR8_15_123774 IP1SR8_11_83775 IP1SR8_7_43776 IP1SR8_3_0))3777 },3778#undef F_3779#undef FM3780 3781#define F_(x, y) x,3782#define FM(x) FN_##x,3783 { PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,3784 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3785 GROUP(3786 /* RESERVED 31-12 */3787 MOD_SEL8_113788 MOD_SEL8_103789 MOD_SEL8_93790 MOD_SEL8_83791 MOD_SEL8_73792 MOD_SEL8_63793 MOD_SEL8_53794 MOD_SEL8_43795 MOD_SEL8_33796 MOD_SEL8_23797 MOD_SEL8_13798 MOD_SEL8_0))3799 },3800 { /* sentinel */ }3801};3802 3803static const struct pinmux_drive_reg pinmux_drive_regs[] = {3804 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {3805 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */3806 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */3807 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */3808 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */3809 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */3810 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */3811 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */3812 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */3813 } },3814 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {3815 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */3816 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */3817 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */3818 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */3819 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */3820 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */3821 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */3822 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */3823 } },3824 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {3825 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */3826 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */3827 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */3828 } },3829 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {3830 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */3831 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */3832 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */3833 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */3834 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */3835 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */3836 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */3837 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */3838 } },3839 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {3840 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */3841 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */3842 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */3843 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */3844 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */3845 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */3846 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */3847 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */3848 } },3849 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {3850 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */3851 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */3852 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */3853 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */3854 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */3855 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */3856 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */3857 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */3858 } },3859 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {3860 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */3861 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */3862 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */3863 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */3864 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */3865 } },3866 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {3867 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */3868 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */3869 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */3870 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */3871 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */3872 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */3873 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */3874 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */3875 } },3876 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {3877 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */3878 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */3879 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */3880 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */3881 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */3882 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */3883 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */3884 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */3885 } },3886 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {3887 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */3888 { RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */3889 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */3890 { RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */3891 } },3892 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {3893 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */3894 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */3895 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */3896 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */3897 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */3898 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */3899 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */3900 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */3901 } },3902 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {3903 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */3904 { RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */3905 { RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */3906 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */3907 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */3908 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */3909 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/3910 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */3911 } },3912 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {3913 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */3914 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */3915 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */3916 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */3917 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */3918 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */3919 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */3920 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */3921 } },3922 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {3923 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */3924 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */3925 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */3926 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */3927 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */3928 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */3929 } },3930 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {3931 { RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */3932 { RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */3933 { RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */3934 { RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */3935 { RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */3936 { RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */3937 { RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */3938 { RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */3939 } },3940 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {3941 { RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */3942 { RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */3943 { RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */3944 { RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */3945 { RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */3946 { RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */3947 { RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */3948 { RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */3949 } },3950 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {3951 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */3952 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */3953 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */3954 { RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */3955 { RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */3956 { RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */3957 { RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */3958 { RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */3959 } },3960 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {3961 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */3962 } },3963 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {3964 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */3965 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */3966 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */3967 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */3968 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */3969 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */3970 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */3971 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */3972 } },3973 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {3974 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */3975 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */3976 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */3977 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */3978 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */3979 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */3980 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */3981 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */3982 } },3983 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {3984 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */3985 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */3986 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */3987 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */3988 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */3989 } },3990 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {3991 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */3992 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */3993 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */3994 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */3995 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */3996 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */3997 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */3998 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */3999 } },4000 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {4001 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */4002 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */4003 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */4004 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */4005 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */4006 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */4007 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */4008 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */4009 } },4010 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {4011 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */4012 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */4013 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */4014 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */4015 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */4016 } },4017 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {4018 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */4019 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */4020 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */4021 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */4022 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */4023 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */4024 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */4025 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */4026 } },4027 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {4028 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */4029 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */4030 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */4031 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */4032 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */4033 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */4034 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */4035 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */4036 } },4037 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {4038 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */4039 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */4040 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */4041 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */4042 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */4043 } },4044 { PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {4045 { RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */4046 { RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */4047 { RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */4048 { RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */4049 { RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */4050 { RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */4051 { RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */4052 { RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */4053 } },4054 { PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {4055 { RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */4056 { RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */4057 { RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */4058 { RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */4059 { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */4060 { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */4061 } },4062 { /* sentinel */ }4063};4064 4065enum ioctrl_regs {4066 POC0,4067 POC1,4068 POC3,4069 POC4,4070 POC5,4071 POC6,4072 POC7,4073 POC8,4074};4075 4076static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {4077 [POC0] = { 0xE60500A0, },4078 [POC1] = { 0xE60508A0, },4079 [POC3] = { 0xE60588A0, },4080 [POC4] = { 0xE60600A0, },4081 [POC5] = { 0xE60608A0, },4082 [POC6] = { 0xE60610A0, },4083 [POC7] = { 0xE60618A0, },4084 [POC8] = { 0xE60680A0, },4085 { /* sentinel */ }4086};4087 4088static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)4089{4090 int bit = pin & 0x1f;4091 4092 switch (pin) {4093 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):4094 *pocctrl = pinmux_ioctrl_regs[POC0].reg;4095 return bit;4096 4097 case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):4098 *pocctrl = pinmux_ioctrl_regs[POC1].reg;4099 return bit;4100 4101 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):4102 *pocctrl = pinmux_ioctrl_regs[POC3].reg;4103 return bit;4104 4105 case PIN_VDDQ_TSN0:4106 *pocctrl = pinmux_ioctrl_regs[POC4].reg;4107 return 0;4108 4109 case PIN_VDDQ_AVB2:4110 *pocctrl = pinmux_ioctrl_regs[POC5].reg;4111 return 0;4112 4113 case PIN_VDDQ_AVB1:4114 *pocctrl = pinmux_ioctrl_regs[POC6].reg;4115 return 0;4116 4117 case PIN_VDDQ_AVB0:4118 *pocctrl = pinmux_ioctrl_regs[POC7].reg;4119 return 0;4120 4121 case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):4122 *pocctrl = pinmux_ioctrl_regs[POC8].reg;4123 return bit;4124 4125 default:4126 return -EINVAL;4127 }4128}4129 4130static const struct pinmux_bias_reg pinmux_bias_regs[] = {4131 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {4132 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */4133 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */4134 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */4135 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */4136 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */4137 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */4138 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */4139 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */4140 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */4141 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */4142 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */4143 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */4144 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */4145 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */4146 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */4147 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */4148 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */4149 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */4150 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */4151 [19] = SH_PFC_PIN_NONE,4152 [20] = SH_PFC_PIN_NONE,4153 [21] = SH_PFC_PIN_NONE,4154 [22] = SH_PFC_PIN_NONE,4155 [23] = SH_PFC_PIN_NONE,4156 [24] = SH_PFC_PIN_NONE,4157 [25] = SH_PFC_PIN_NONE,4158 [26] = SH_PFC_PIN_NONE,4159 [27] = SH_PFC_PIN_NONE,4160 [28] = SH_PFC_PIN_NONE,4161 [29] = SH_PFC_PIN_NONE,4162 [30] = SH_PFC_PIN_NONE,4163 [31] = SH_PFC_PIN_NONE,4164 } },4165 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {4166 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */4167 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */4168 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */4169 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */4170 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */4171 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */4172 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */4173 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */4174 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */4175 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */4176 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */4177 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */4178 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */4179 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */4180 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */4181 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */4182 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */4183 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */4184 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */4185 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */4186 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */4187 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */4188 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */4189 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */4190 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */4191 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */4192 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */4193 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */4194 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */4195 [29] = SH_PFC_PIN_NONE,4196 [30] = SH_PFC_PIN_NONE,4197 [31] = SH_PFC_PIN_NONE,4198 } },4199 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {4200 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */4201 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */4202 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */4203 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */4204 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */4205 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */4206 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */4207 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */4208 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */4209 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */4210 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */4211 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */4212 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */4213 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */4214 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */4215 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */4216 [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */4217 [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */4218 [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */4219 [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */4220 [20] = SH_PFC_PIN_NONE,4221 [21] = SH_PFC_PIN_NONE,4222 [22] = SH_PFC_PIN_NONE,4223 [23] = SH_PFC_PIN_NONE,4224 [24] = SH_PFC_PIN_NONE,4225 [25] = SH_PFC_PIN_NONE,4226 [26] = SH_PFC_PIN_NONE,4227 [27] = SH_PFC_PIN_NONE,4228 [28] = SH_PFC_PIN_NONE,4229 [29] = SH_PFC_PIN_NONE,4230 [30] = SH_PFC_PIN_NONE,4231 [31] = SH_PFC_PIN_NONE,4232 } },4233 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {4234 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */4235 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */4236 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */4237 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */4238 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */4239 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */4240 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */4241 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */4242 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */4243 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */4244 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */4245 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */4246 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */4247 [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */4248 [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */4249 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */4250 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */4251 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */4252 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */4253 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */4254 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */4255 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */4256 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */4257 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */4258 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */4259 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */4260 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */4261 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */4262 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */4263 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */4264 [30] = SH_PFC_PIN_NONE,4265 [31] = SH_PFC_PIN_NONE,4266 } },4267 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {4268 [ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */4269 [ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */4270 [ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */4271 [ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */4272 [ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */4273 [ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */4274 [ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */4275 [ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */4276 [ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */4277 [ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */4278 [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */4279 [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */4280 [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */4281 [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */4282 [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */4283 [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */4284 [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */4285 [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */4286 [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */4287 [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */4288 [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */4289 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */4290 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */4291 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */4292 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */4293 [25] = SH_PFC_PIN_NONE,4294 [26] = SH_PFC_PIN_NONE,4295 [27] = SH_PFC_PIN_NONE,4296 [28] = SH_PFC_PIN_NONE,4297 [29] = SH_PFC_PIN_NONE,4298 [30] = SH_PFC_PIN_NONE,4299 [31] = SH_PFC_PIN_NONE,4300 } },4301 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {4302 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */4303 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */4304 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */4305 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */4306 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */4307 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */4308 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */4309 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */4310 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */4311 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */4312 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */4313 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */4314 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */4315 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */4316 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */4317 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */4318 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */4319 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */4320 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */4321 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */4322 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */4323 [21] = SH_PFC_PIN_NONE,4324 [22] = SH_PFC_PIN_NONE,4325 [23] = SH_PFC_PIN_NONE,4326 [24] = SH_PFC_PIN_NONE,4327 [25] = SH_PFC_PIN_NONE,4328 [26] = SH_PFC_PIN_NONE,4329 [27] = SH_PFC_PIN_NONE,4330 [28] = SH_PFC_PIN_NONE,4331 [29] = SH_PFC_PIN_NONE,4332 [30] = SH_PFC_PIN_NONE,4333 [31] = SH_PFC_PIN_NONE,4334 } },4335 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {4336 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */4337 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */4338 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */4339 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */4340 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */4341 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */4342 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */4343 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */4344 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */4345 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */4346 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */4347 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */4348 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */4349 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */4350 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/4351 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */4352 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */4353 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */4354 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */4355 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */4356 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */4357 [21] = SH_PFC_PIN_NONE,4358 [22] = SH_PFC_PIN_NONE,4359 [23] = SH_PFC_PIN_NONE,4360 [24] = SH_PFC_PIN_NONE,4361 [25] = SH_PFC_PIN_NONE,4362 [26] = SH_PFC_PIN_NONE,4363 [27] = SH_PFC_PIN_NONE,4364 [28] = SH_PFC_PIN_NONE,4365 [29] = SH_PFC_PIN_NONE,4366 [30] = SH_PFC_PIN_NONE,4367 [31] = SH_PFC_PIN_NONE,4368 } },4369 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {4370 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */4371 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */4372 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */4373 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */4374 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */4375 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */4376 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */4377 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */4378 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */4379 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */4380 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */4381 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */4382 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */4383 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */4384 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */4385 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */4386 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */4387 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */4388 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */4389 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */4390 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */4391 [21] = SH_PFC_PIN_NONE,4392 [22] = SH_PFC_PIN_NONE,4393 [23] = SH_PFC_PIN_NONE,4394 [24] = SH_PFC_PIN_NONE,4395 [25] = SH_PFC_PIN_NONE,4396 [26] = SH_PFC_PIN_NONE,4397 [27] = SH_PFC_PIN_NONE,4398 [28] = SH_PFC_PIN_NONE,4399 [29] = SH_PFC_PIN_NONE,4400 [30] = SH_PFC_PIN_NONE,4401 [31] = SH_PFC_PIN_NONE,4402 } },4403 { PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {4404 [ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */4405 [ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */4406 [ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */4407 [ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */4408 [ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */4409 [ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */4410 [ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */4411 [ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */4412 [ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */4413 [ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */4414 [10] = RCAR_GP_PIN(8, 10), /* SCL5 */4415 [11] = RCAR_GP_PIN(8, 11), /* SDA5 */4416 [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */4417 [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */4418 [14] = SH_PFC_PIN_NONE,4419 [15] = SH_PFC_PIN_NONE,4420 [16] = SH_PFC_PIN_NONE,4421 [17] = SH_PFC_PIN_NONE,4422 [18] = SH_PFC_PIN_NONE,4423 [19] = SH_PFC_PIN_NONE,4424 [20] = SH_PFC_PIN_NONE,4425 [21] = SH_PFC_PIN_NONE,4426 [22] = SH_PFC_PIN_NONE,4427 [23] = SH_PFC_PIN_NONE,4428 [24] = SH_PFC_PIN_NONE,4429 [25] = SH_PFC_PIN_NONE,4430 [26] = SH_PFC_PIN_NONE,4431 [27] = SH_PFC_PIN_NONE,4432 [28] = SH_PFC_PIN_NONE,4433 [29] = SH_PFC_PIN_NONE,4434 [30] = SH_PFC_PIN_NONE,4435 [31] = SH_PFC_PIN_NONE,4436 } },4437 { /* sentinel */ }4438};4439 4440static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {4441 .pin_to_pocctrl = r8a779g0_pin_to_pocctrl,4442 .get_bias = rcar_pinmux_get_bias,4443 .set_bias = rcar_pinmux_set_bias,4444};4445 4446const struct sh_pfc_soc_info r8a779g0_pinmux_info = {4447 .name = "r8a779g0_pfc",4448 .ops = &r8a779g0_pin_ops,4449 .unlock_reg = 0x1ff, /* PMMRn mask */4450 4451 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },4452 4453 .pins = pinmux_pins,4454 .nr_pins = ARRAY_SIZE(pinmux_pins),4455 .groups = pinmux_groups,4456 .nr_groups = ARRAY_SIZE(pinmux_groups),4457 .functions = pinmux_functions,4458 .nr_functions = ARRAY_SIZE(pinmux_functions),4459 4460 .cfg_regs = pinmux_config_regs,4461 .drive_regs = pinmux_drive_regs,4462 .bias_regs = pinmux_bias_regs,4463 .ioctrl_regs = pinmux_ioctrl_regs,4464 4465 .pinmux_data = pinmux_data,4466 .pinmux_data_size = ARRAY_SIZE(pinmux_data),4467};4468