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1// SPDX-License-Identifier: GPL-2.02/*3 * R8A779H0 processor support - PFC hardware block.4 *5 * Copyright (C) 2023 Renesas Electronics Corp.6 *7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c8 */9 10#include <linux/errno.h>11#include <linux/io.h>12#include <linux/kernel.h>13 14#include "sh_pfc.h"15 16#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)17 18#define CPU_ALL_GP(fn, sfx) \19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \20 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \21 PORT_GP_CFG_1(1, 29, fn, sfx, CFG_FLAGS), \22 PORT_GP_CFG_16(2, fn, sfx, CFG_FLAGS), \23 PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \24 PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \25 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \29 PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \30 PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \31 PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \32 PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \33 PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \34 PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \35 PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \36 PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \37 PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \38 PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \39 PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \40 PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \41 PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \42 PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \43 PORT_GP_CFG_1(3, 30, fn, sfx, CFG_FLAGS), \44 PORT_GP_CFG_1(3, 31, fn, sfx, CFG_FLAGS), \45 PORT_GP_CFG_14(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \46 PORT_GP_CFG_1(4, 14, fn, sfx, CFG_FLAGS), \47 PORT_GP_CFG_1(4, 15, fn, sfx, CFG_FLAGS), \48 PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \49 PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \50 PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \51 PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \52 PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \53 PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS)54 55#define CPU_ALL_NOGP(fn) \56 PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \57 PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \58 PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)59 60/*61 * F_() : just information62 * FM() : macro for FN_xxx / xxx_MARK63 */64 65/* GPSR0 */66#define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)67#define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)68#define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0)69#define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28)70#define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)71#define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20)72#define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16)73#define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12)74#define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8)75#define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)76#define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)77#define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)78#define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24)79#define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20)80#define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16)81#define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12)82#define GPSR0_2 F_(GP0_02, IP0SR0_11_8)83#define GPSR0_1 F_(GP0_01, IP0SR0_7_4)84#define GPSR0_0 F_(GP0_00, IP0SR0_3_0)85 86/* GPSR1 */87#define GPSR1_29 F_(ERROROUTC_N_A, IP3SR1_23_20)88#define GPSR1_28 F_(HTX3, IP3SR1_19_16)89#define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)90#define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)91#define GPSR1_25 F_(HSCK3, IP3SR1_7_4)92#define GPSR1_24 F_(HRX3, IP3SR1_3_0)93#define GPSR1_23 F_(GP1_23, IP2SR1_31_28)94#define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)95#define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)96#define GPSR1_20 F_(SSI_SD, IP2SR1_19_16)97#define GPSR1_19 F_(SSI_WS, IP2SR1_15_12)98#define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8)99#define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4)100#define GPSR1_16 F_(HRX0, IP2SR1_3_0)101#define GPSR1_15 F_(HSCK0, IP1SR1_31_28)102#define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24)103#define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20)104#define GPSR1_12 F_(HTX0, IP1SR1_19_16)105#define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12)106#define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8)107#define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4)108#define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0)109#define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28)110#define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24)111#define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20)112#define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16)113#define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)114#define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8)115#define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4)116#define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0)117 118/* GPSR2 */119#define GPSR2_19 F_(CANFD1_RX, IP2SR2_15_12)120#define GPSR2_17 F_(CANFD1_TX, IP2SR2_7_4)121#define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28)122#define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24)123#define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20)124#define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16)125#define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)126#define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)127#define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)128#define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)129#define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)130#define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)131#define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20)132#define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)133#define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)134#define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)135#define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4)136#define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)137 138/* GPSR3 */139#define GPSR3_31 F_(TCLK4, IP3SR3_31_28)140#define GPSR3_30 F_(TCLK3, IP3SR3_27_24)141#define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20)142#define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16)143#define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12)144#define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8)145#define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4)146#define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0)147#define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28)148#define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24)149#define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20)150#define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16)151#define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12)152#define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8)153#define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4)154#define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0)155#define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28)156#define GPSR3_14 F_(PWM2, IP1SR3_27_24)157#define GPSR3_13 F_(PWM1, IP1SR3_23_20)158#define GPSR3_12 F_(SD_WP, IP1SR3_19_16)159#define GPSR3_11 F_(SD_CD, IP1SR3_15_12)160#define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8)161#define GPSR3_9 F_(MMC_D6, IP1SR3_7_4)162#define GPSR3_8 F_(MMC_D7, IP1SR3_3_0)163#define GPSR3_7 F_(MMC_D4, IP0SR3_31_28)164#define GPSR3_6 F_(MMC_D5, IP0SR3_27_24)165#define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20)166#define GPSR3_4 F_(MMC_DS, IP0SR3_19_16)167#define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12)168#define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8)169#define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4)170#define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)171 172/* GPSR4 */173#define GPSR4_24 F_(AVS1, IP3SR4_3_0)174#define GPSR4_23 F_(AVS0, IP2SR4_31_28)175#define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20)176#define GPSR4_15 F_(PWM4, IP1SR4_31_28)177#define GPSR4_14 F_(PWM3, IP1SR4_27_24)178#define GPSR4_13 F_(HSCK2, IP1SR4_23_20)179#define GPSR4_12 F_(HCTS2_N, IP1SR4_19_16)180#define GPSR4_11 F_(SCIF_CLK2, IP1SR4_15_12)181#define GPSR4_10 F_(HRTS2_N, IP1SR4_11_8)182#define GPSR4_9 F_(HTX2, IP1SR4_7_4)183#define GPSR4_8 F_(HRX2, IP1SR4_3_0)184#define GPSR4_7 F_(SDA3, IP0SR4_31_28)185#define GPSR4_6 F_(SCL3, IP0SR4_27_24)186#define GPSR4_5 F_(SDA2, IP0SR4_23_20)187#define GPSR4_4 F_(SCL2, IP0SR4_19_16)188#define GPSR4_3 F_(SDA1, IP0SR4_15_12)189#define GPSR4_2 F_(SCL1, IP0SR4_11_8)190#define GPSR4_1 F_(SDA0, IP0SR4_7_4)191#define GPSR4_0 F_(SCL0, IP0SR4_3_0)192 193/* GPSR 5 */194#define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16)195#define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12)196#define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8)197#define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4)198#define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0)199#define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28)200#define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24)201#define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20)202#define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16)203#define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12)204#define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8)205#define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4)206#define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0)207#define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28)208#define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24)209#define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20)210#define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16)211#define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12)212#define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8)213#define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4)214#define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0)215 216/* GPSR 6 */217#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)218#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)219#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)220#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)221#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)222#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)223#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)224#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)225#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)226#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)227#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)228#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)229#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)230#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)231#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)232#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)233#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)234#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)235#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)236#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)237#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)238 239/* GPSR7 */240#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)241#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)242#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)243#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)244#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)245#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)246#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)247#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)248#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)249#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)250#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)251#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)252#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)253#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)254#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)255#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)256#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)257#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)258#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)259#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)260#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)261 262 263/* SR0 */264/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */265#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)266#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)267#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)268#define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)269#define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)270#define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)271#define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)272#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)273 274/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */275#define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)276#define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)277#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)278#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)279#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)280#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)281#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)282#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)283 284/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */285#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)286#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)287#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)288 289/* SR1 */290/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */291#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)292#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)293#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)294#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)295#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)296#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)297#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)298#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)299 300/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */301#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)302#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)303#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)304#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)305#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)306#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)307#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)308#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)309 310/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */311#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)312#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)313#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)314#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)315#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)316#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)317#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)318#define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)319 320/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */321#define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)322#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)323#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)324#define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)325#define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)326#define IP3SR1_23_20 FM(ERROROUTC_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)327 328/* SR2 */329/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */330#define IP0SR2_3_0 FM(FXR_TXDA) F_(0, 0) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)331#define IP0SR2_7_4 FM(FXR_TXENA_N_A) F_(0, 0) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)332#define IP0SR2_11_8 FM(RXDA_EXTFXR) F_(0, 0) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)333#define IP0SR2_15_12 FM(CLK_EXTFXR) F_(0, 0) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)334#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)335#define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)336#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)337#define IP0SR2_31_28 FM(TPU0TO1_A) F_(0, 0) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)338 339/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */340#define IP1SR2_3_0 FM(TPU0TO0_A) F_(0, 0) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)341#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)342#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)343#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)344#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)345#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)346#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)347#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)348 349/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */350#define IP2SR2_7_4 FM(CANFD1_TX) F_(0, 0) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)351#define IP2SR2_15_12 FM(CANFD1_RX) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)352 353/* SR3 */354/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */355#define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)356#define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)357#define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)358#define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)359#define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)360#define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)361#define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)362#define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)363 364/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */365#define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)366#define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)367#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)368#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)369#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)370#define IP1SR3_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)371#define IP1SR3_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)372#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)373 374/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */375#define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)376#define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)377#define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)378#define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)379#define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)380#define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)381#define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)382#define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)383 384/* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */385#define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)386#define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)387#define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)388#define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)389#define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)390#define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)391#define IP3SR3_27_24 FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)392#define IP3SR3_31_28 FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)393 394/* SR4 */395/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */396#define IP0SR4_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)397#define IP0SR4_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)398#define IP0SR4_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)399#define IP0SR4_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)400#define IP0SR4_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)401#define IP0SR4_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)402#define IP0SR4_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)403#define IP0SR4_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)404 405/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */406#define IP1SR4_3_0 FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)407#define IP1SR4_7_4 FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)408#define IP1SR4_11_8 FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)409#define IP1SR4_15_12 FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)410#define IP1SR4_19_16 FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)411#define IP1SR4_23_20 FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)412#define IP1SR4_27_24 FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)413#define IP1SR4_31_28 FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)414 415/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */416#define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)417#define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)418 419/* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */420#define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)421 422/* SR5 */423/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */424#define IP0SR5_3_0 FM(AVB2_AVTP_PPS) FM(Ether_GPTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)425#define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) FM(Ether_GPTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)426#define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) FM(Ether_GPTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)427#define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)428#define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)429#define IP0SR5_23_20 FM(AVB2_MAGIC) FM(Ether_GPTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)430#define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)431#define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)432 433/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */434#define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)435#define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)436#define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)437#define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)438#define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)439#define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)440#define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)441#define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)442 443/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */444#define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)445#define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)446#define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)447#define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)448#define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)449 450/* SR6 */451/* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */452#define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)453#define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)454#define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)455#define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)456#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)457#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)458#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)459#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)460 461/* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */462#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)463#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)464#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)465#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)466#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)467#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)468#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)469#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)470 471/* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */472#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)473#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)474#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)475#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)476#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)477 478/* SR7 */479/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */480#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)481#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)482#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)483#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)484#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)485#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)486#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)487#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)488 489/* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */490#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)491#define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)492#define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)493#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)494#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)495#define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)496#define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)497#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)498 499/* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */500#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)501#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)502#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)503#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)504#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)505 506#define PINMUX_GPSR \507 GPSR3_31 \508 GPSR3_30 \509 GPSR1_29 GPSR3_29 \510 GPSR1_28 GPSR3_28 \511 GPSR1_27 GPSR3_27 \512 GPSR1_26 GPSR3_26 \513 GPSR1_25 GPSR3_25 \514 GPSR1_24 GPSR3_24 GPSR4_24 \515 GPSR1_23 GPSR3_23 GPSR4_23 \516 GPSR1_22 GPSR3_22 \517 GPSR1_21 GPSR3_21 GPSR4_21 \518 GPSR1_20 GPSR3_20 GPSR5_20 GPSR6_20 GPSR7_20 \519 GPSR1_19 GPSR2_19 GPSR3_19 GPSR5_19 GPSR6_19 GPSR7_19 \520GPSR0_18 GPSR1_18 GPSR3_18 GPSR5_18 GPSR6_18 GPSR7_18 \521GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR5_17 GPSR6_17 GPSR7_17 \522GPSR0_16 GPSR1_16 GPSR3_16 GPSR5_16 GPSR6_16 GPSR7_16 \523GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \524GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \525GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 \526GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 \527GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 \528GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 \529GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 \530GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 \531GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 \532GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 \533GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 \534GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 \535GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \536GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \537GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \538GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0539 540#define PINMUX_IPSR \541\542FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \543FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \544FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \545FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \546FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \547FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \548FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \549FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \550\551FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \552FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \553FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \554FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \555FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \556FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \557FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \558FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \559\560FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 \561FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \562FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 \563FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \564FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \565FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \566FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \567FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \568\569FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \570FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \571FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \572FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \573FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \574FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \575FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 FM(IP3SR3_27_24) IP3SR3_27_24 \576FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 FM(IP3SR3_31_28) IP3SR3_31_28 \577\578FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \579FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 \580FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 \581FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 \582FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 \583FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \584FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \585FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \586\587FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \588FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \589FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \590FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \591FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \592FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \593FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \594FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \595\596FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \597FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \598FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \599FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \600FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \601FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \602FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \603FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \604\605FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \606FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \607FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \608FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \609FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \610FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \611FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \612FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \613 614/* MOD_SEL4 */ /* 0 */ /* 1 */615#define MOD_SEL4_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1)616#define MOD_SEL4_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1)617#define MOD_SEL4_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1)618#define MOD_SEL4_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1)619#define MOD_SEL4_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1)620#define MOD_SEL4_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1)621#define MOD_SEL4_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1)622#define MOD_SEL4_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1)623 624#define PINMUX_MOD_SELS \625\626MOD_SEL4_7 \627MOD_SEL4_6 \628MOD_SEL4_5 \629MOD_SEL4_4 \630MOD_SEL4_3 \631MOD_SEL4_2 \632MOD_SEL4_1 \633MOD_SEL4_0634 635enum {636 PINMUX_RESERVED = 0,637 638 PINMUX_DATA_BEGIN,639 GP_ALL(DATA),640 PINMUX_DATA_END,641 642#define F_(x, y)643#define FM(x) FN_##x,644 PINMUX_FUNCTION_BEGIN,645 GP_ALL(FN),646 PINMUX_GPSR647 PINMUX_IPSR648 PINMUX_MOD_SELS649 PINMUX_FUNCTION_END,650#undef F_651#undef FM652 653#define F_(x, y)654#define FM(x) x##_MARK,655 PINMUX_MARK_BEGIN,656 PINMUX_GPSR657 PINMUX_IPSR658 PINMUX_MOD_SELS659 PINMUX_MARK_END,660#undef F_661#undef FM662};663 664static const u16 pinmux_data[] = {665 PINMUX_DATA_GP_ALL(),666 667 /* IP0SR0 */668 PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B),669 PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B),670 671 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),672 673 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),674 675 PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A),676 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),677 678 PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A),679 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),680 681 PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A),682 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),683 684 PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A),685 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),686 687 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),688 689 /* IP1SR0 */690 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1),691 692 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC),693 694 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD),695 696 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK),697 698 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),699 700 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),701 PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A),702 PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B),703 704 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),705 PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A),706 PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A),707 708 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),709 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A),710 PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A),711 712 /* IP2SR0 */713 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),714 PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A),715 PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A),716 717 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),718 PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A),719 PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A),720 721 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),722 PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A),723 PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A),724 725 /* IP0SR1 */726 PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),727 PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B),728 PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B),729 730 PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),731 PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B),732 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B),733 734 PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),735 PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B),736 PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B),737 738 PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),739 PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),740 PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),741 742 PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),743 PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B),744 PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B),745 746 PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),747 748 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),749 PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B),750 PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B),751 752 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),753 PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B),754 PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B),755 756 /* IP1SR1 */757 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),758 PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B),759 PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B),760 761 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),762 PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B),763 PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B),764 765 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),766 PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B),767 PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B),768 769 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),770 771 PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0),772 PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0),773 774 PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),775 PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),776 777 PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),778 PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),779 PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM0_B),780 781 PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),782 PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),783 PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),784 785 /* IP2SR1 */786 PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),787 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),788 789 PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK),790 PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),791 792 PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),793 PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B),794 795 PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),796 PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B),797 798 PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),799 PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B),800 801 PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),802 PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B),803 804 PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),805 PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_C),806 807 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A),808 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),809 PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),810 811 /* IP3SR1 */812 PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A),813 PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),814 PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),815 816 PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A),817 PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),818 PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),819 PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B),820 821 PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A),822 PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),823 PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),824 PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B),825 826 PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A),827 PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),828 PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),829 830 PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A),831 PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),832 PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),833 834 PINMUX_IPSR_GPSR(IP3SR1_23_20, ERROROUTC_N_A),835 836 /* IP0SR2 */837 PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),838 PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B),839 840 PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A),841 PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B),842 843 PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),844 PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),845 846 PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),847 PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),848 849 PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),850 851 PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A),852 853 PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),854 855 PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A),856 PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C),857 858 /* IP1SR2 */859 PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A),860 PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B),861 862 PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),863 PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B),864 865 PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),866 PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B),867 868 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),869 PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),870 871 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),872 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A),873 PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C),874 875 PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),876 PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A),877 PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),878 PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C),879 880 PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),881 PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B),882 883 PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),884 PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),885 886 /* IP2SR2 */887 PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD1_TX),888 PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM1_C),889 890 PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD1_RX),891 PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM2_C),892 893 /* IP0SR3 */894 PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1),895 896 PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0),897 898 PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2),899 900 PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK),901 902 PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS),903 904 PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3),905 906 PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5),907 908 PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4),909 910 /* IP1SR3 */911 PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7),912 913 PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6),914 915 PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD),916 917 PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD),918 919 PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP),920 921 PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),922 923 PINMUX_IPSR_GPSR(IP1SR3_27_24, PWM2_A),924 925 PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),926 927 /* IP2SR3 */928 PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3),929 930 PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2),931 932 PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1),933 934 PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0),935 936 PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK),937 938 PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0),939 940 PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK),941 942 PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1),943 944 /* IP3SR3 */945 PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2),946 947 PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL),948 949 PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3),950 951 PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N),952 953 PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N),954 955 PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N),956 957 PINMUX_IPSR_GPSR(IP3SR3_27_24, TCLK3_A),958 959 PINMUX_IPSR_GPSR(IP3SR3_31_28, TCLK4_A),960 961 /* IP0SR4 */962 PINMUX_IPSR_MSEL(IP0SR4_3_0, SCL0, SEL_SCL0_0),963 964 PINMUX_IPSR_MSEL(IP0SR4_7_4, SDA0, SEL_SDA0_0),965 966 PINMUX_IPSR_MSEL(IP0SR4_11_8, SCL1, SEL_SCL1_0),967 968 PINMUX_IPSR_MSEL(IP0SR4_15_12, SDA1, SEL_SDA1_0),969 970 PINMUX_IPSR_MSEL(IP0SR4_19_16, SCL2, SEL_SCL2_0),971 972 PINMUX_IPSR_MSEL(IP0SR4_23_20, SDA2, SEL_SDA2_0),973 974 PINMUX_IPSR_MSEL(IP0SR4_27_24, SCL3, SEL_SCL3_0),975 976 PINMUX_IPSR_MSEL(IP0SR4_31_28, SDA3, SEL_SDA3_0),977 978 /* IP1SR4 */979 PINMUX_IPSR_GPSR(IP1SR4_3_0, HRX2),980 PINMUX_IPSR_GPSR(IP1SR4_3_0, SCK4),981 982 PINMUX_IPSR_GPSR(IP1SR4_7_4, HTX2),983 PINMUX_IPSR_GPSR(IP1SR4_7_4, CTS4_N),984 985 PINMUX_IPSR_GPSR(IP1SR4_11_8, HRTS2_N),986 PINMUX_IPSR_GPSR(IP1SR4_11_8, RTS4_N),987 988 PINMUX_IPSR_GPSR(IP1SR4_15_12, SCIF_CLK2),989 990 PINMUX_IPSR_GPSR(IP1SR4_19_16, HCTS2_N),991 PINMUX_IPSR_GPSR(IP1SR4_19_16, TX4),992 993 PINMUX_IPSR_GPSR(IP1SR4_23_20, HSCK2),994 PINMUX_IPSR_GPSR(IP1SR4_23_20, RX4),995 996 PINMUX_IPSR_GPSR(IP1SR4_27_24, PWM3_A),997 998 PINMUX_IPSR_GPSR(IP1SR4_31_28, PWM4),999 1000 /* IP2SR4 */1001 PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N),1002 1003 PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0),1004 1005 /* IP3SR4 */1006 PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1),1007 1008 /* IP0SR5 */1009 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS),1010 PINMUX_IPSR_GPSR(IP0SR5_3_0, Ether_GPTP_PPS0),1011 1012 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE),1013 PINMUX_IPSR_GPSR(IP0SR5_7_4, Ether_GPTP_CAPTURE),1014 1015 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH),1016 PINMUX_IPSR_GPSR(IP0SR5_11_8, Ether_GPTP_MATCH),1017 1018 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK),1019 1020 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT),1021 1022 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC),1023 PINMUX_IPSR_GPSR(IP0SR5_23_20, Ether_GPTP_PPS1),1024 1025 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC),1026 1027 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK),1028 1029 /* IP1SR5 */1030 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3),1031 1032 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3),1033 1034 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO),1035 1036 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2),1037 1038 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1),1039 1040 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2),1041 1042 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1),1043 1044 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0),1045 1046 /* IP2SR5 */1047 PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC),1048 1049 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0),1050 1051 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC),1052 1053 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL),1054 1055 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL),1056 1057 /* IP0SR6 */1058 PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),1059 1060 PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),1061 1062 PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),1063 1064 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),1065 1066 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),1067 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),1068 1069 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),1070 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),1071 1072 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),1073 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),1074 1075 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),1076 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),1077 1078 /* IP1SR6 */1079 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),1080 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC),1081 1082 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),1083 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),1084 1085 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),1086 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),1087 1088 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),1089 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),1090 1091 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),1092 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),1093 1094 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),1095 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),1096 1097 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),1098 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),1099 1100 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0),1101 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),1102 1103 /* IP2SR6 */1104 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),1105 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),1106 1107 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),1108 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),1109 1110 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),1111 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),1112 1113 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),1114 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),1115 1116 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),1117 1118 /* IP0SR7 */1119 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),1120 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),1121 1122 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),1123 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),1124 1125 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),1126 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),1127 PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),1128 1129 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),1130 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),1131 1132 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),1133 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),1134 1135 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),1136 1137 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),1138 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),1139 1140 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),1141 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),1142 1143 /* IP1SR7 */1144 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),1145 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),1146 1147 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),1148 1149 PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),1150 1151 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),1152 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),1153 1154 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),1155 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),1156 1157 PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),1158 1159 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),1160 1161 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),1162 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),1163 1164 /* IP2SR7 */1165 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),1166 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),1167 1168 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),1169 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),1170 1171 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0),1172 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0),1173 1174 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC),1175 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC),1176 1177 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL),1178 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),1179};1180 1181/*1182 * Pins not associated with a GPIO port.1183 */1184enum {1185 GP_ASSIGN_LAST(),1186 NOGP_ALL(),1187};1188 1189static const struct sh_pfc_pin pinmux_pins[] = {1190 PINMUX_GPIO_GP_ALL(),1191 PINMUX_NOGP_ALL(),1192};1193 1194/* - AUDIO CLOCK ----------------------------------------- */1195static const unsigned int audio_clkin_pins[] = {1196 /* CLK IN */1197 RCAR_GP_PIN(1, 22),1198};1199static const unsigned int audio_clkin_mux[] = {1200 AUDIO_CLKIN_MARK,1201};1202static const unsigned int audio_clkout_pins[] = {1203 /* CLK OUT */1204 RCAR_GP_PIN(1, 21),1205};1206static const unsigned int audio_clkout_mux[] = {1207 AUDIO_CLKOUT_MARK,1208};1209 1210/* - AVB0 ------------------------------------------------ */1211static const unsigned int avb0_link_pins[] = {1212 /* AVB0_LINK */1213 RCAR_GP_PIN(7, 4),1214};1215static const unsigned int avb0_link_mux[] = {1216 AVB0_LINK_MARK,1217};1218static const unsigned int avb0_magic_pins[] = {1219 /* AVB0_MAGIC */1220 RCAR_GP_PIN(7, 10),1221};1222static const unsigned int avb0_magic_mux[] = {1223 AVB0_MAGIC_MARK,1224};1225static const unsigned int avb0_phy_int_pins[] = {1226 /* AVB0_PHY_INT */1227 RCAR_GP_PIN(7, 5),1228};1229static const unsigned int avb0_phy_int_mux[] = {1230 AVB0_PHY_INT_MARK,1231};1232static const unsigned int avb0_mdio_pins[] = {1233 /* AVB0_MDC, AVB0_MDIO */1234 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),1235};1236static const unsigned int avb0_mdio_mux[] = {1237 AVB0_MDC_MARK, AVB0_MDIO_MARK,1238};1239static const unsigned int avb0_mii_pins[] = {1240 /*1241 * AVB0_MII_TD0, AVB0_MII_TD1, AVB0_MII_TD2,1242 * AVB0_MII_TD3, AVB0_MII_RD0, AVB0_MII_RD1,1243 * AVB0_MII_RD2, AVB0_MII_RD3, AVB0_MII_TXC,1244 * AVB0_MII_TX_EN, AVB0_MII_TX_ER, AVB0_MII_RXC,1245 * AVB0_MII_RX_DV, AVB0_MII_RX_ER, AVB0_MII_CRS,1246 * AVB0_MII_COL1247 */1248 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 6),1249 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),1250 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 15),1251 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 19),1252 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 1),1253 RCAR_GP_PIN(7, 0),1254};1255static const unsigned int avb0_mii_mux[] = {1256 AVB0_MII_TD0_MARK, AVB0_MII_TD1_MARK, AVB0_MII_TD2_MARK,1257 AVB0_MII_TD3_MARK, AVB0_MII_RD0_MARK, AVB0_MII_RD1_MARK,1258 AVB0_MII_RD2_MARK, AVB0_MII_RD3_MARK, AVB0_MII_TXC_MARK,1259 AVB0_MII_TX_EN_MARK, AVB0_MII_TX_ER_MARK, AVB0_MII_RXC_MARK,1260 AVB0_MII_RX_DV_MARK, AVB0_MII_RX_ER_MARK, AVB0_MII_CRS_MARK,1261 AVB0_MII_COL_MARK,1262};1263static const unsigned int avb0_rgmii_pins[] = {1264 /*1265 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,1266 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,1267 */1268 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),1269 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),1270 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),1271 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),1272 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),1273 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),1274};1275static const unsigned int avb0_rgmii_mux[] = {1276 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,1277 AVB0_TD0_MARK, AVB0_TD1_MARK,1278 AVB0_TD2_MARK, AVB0_TD3_MARK,1279 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,1280 AVB0_RD0_MARK, AVB0_RD1_MARK,1281 AVB0_RD2_MARK, AVB0_RD3_MARK,1282};1283static const unsigned int avb0_txcrefclk_pins[] = {1284 /* AVB0_TXCREFCLK */1285 RCAR_GP_PIN(7, 9),1286};1287static const unsigned int avb0_txcrefclk_mux[] = {1288 AVB0_TXCREFCLK_MARK,1289};1290static const unsigned int avb0_avtp_pps_pins[] = {1291 /* AVB0_AVTP_PPS */1292 RCAR_GP_PIN(7, 0),1293};1294static const unsigned int avb0_avtp_pps_mux[] = {1295 AVB0_AVTP_PPS_MARK,1296};1297static const unsigned int avb0_avtp_capture_pins[] = {1298 /* AVB0_AVTP_CAPTURE */1299 RCAR_GP_PIN(7, 1),1300};1301static const unsigned int avb0_avtp_capture_mux[] = {1302 AVB0_AVTP_CAPTURE_MARK,1303};1304static const unsigned int avb0_avtp_match_pins[] = {1305 /* AVB0_AVTP_MATCH */1306 RCAR_GP_PIN(7, 2),1307};1308static const unsigned int avb0_avtp_match_mux[] = {1309 AVB0_AVTP_MATCH_MARK,1310};1311 1312/* - AVB1 ------------------------------------------------ */1313static const unsigned int avb1_link_pins[] = {1314 /* AVB1_LINK */1315 RCAR_GP_PIN(6, 4),1316};1317static const unsigned int avb1_link_mux[] = {1318 AVB1_LINK_MARK,1319};1320static const unsigned int avb1_magic_pins[] = {1321 /* AVB1_MAGIC */1322 RCAR_GP_PIN(6, 1),1323};1324static const unsigned int avb1_magic_mux[] = {1325 AVB1_MAGIC_MARK,1326};1327static const unsigned int avb1_phy_int_pins[] = {1328 /* AVB1_PHY_INT */1329 RCAR_GP_PIN(6, 3),1330};1331static const unsigned int avb1_phy_int_mux[] = {1332 AVB1_PHY_INT_MARK,1333};1334static const unsigned int avb1_mdio_pins[] = {1335 /* AVB1_MDC, AVB1_MDIO */1336 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),1337};1338static const unsigned int avb1_mdio_mux[] = {1339 AVB1_MDC_MARK, AVB1_MDIO_MARK,1340};1341static const unsigned int avb1_mii_pins[] = {1342 /*1343 * AVB1_MII_TD0, AVB1_MII_TD1, AVB1_MII_TD2,1344 * AVB1_MII_TD3, AVB1_MII_RD0, AVB1_MII_RD1,1345 * AVB1_MII_RD2, AVB1_MII_RD3, AVB1_MII_TXC,1346 * AVB1_MII_TX_EN, AVB1_MII_TX_ER, AVB1_MII_RXC,1347 * AVB1_MII_RX_DV, AVB1_MII_RX_ER, AVB1_MII_CRS,1348 * AVB1_MII_COL1349 */1350 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 16),1351 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),1352 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 6),1353 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 8),1354 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),1355 RCAR_GP_PIN(6, 10),1356};1357static const unsigned int avb1_mii_mux[] = {1358 AVB1_MII_TD0_MARK, AVB1_MII_TD1_MARK, AVB1_MII_TD2_MARK,1359 AVB1_MII_TD3_MARK, AVB1_MII_RD0_MARK, AVB1_MII_RD1_MARK,1360 AVB1_MII_RD2_MARK, AVB1_MII_RD3_MARK, AVB1_MII_TXC_MARK,1361 AVB1_MII_TX_EN_MARK, AVB1_MII_TX_ER_MARK, AVB1_MII_RXC_MARK,1362 AVB1_MII_RX_DV_MARK, AVB1_MII_RX_ER_MARK, AVB1_MII_CRS_MARK,1363 AVB1_MII_COL_MARK,1364};1365static const unsigned int avb1_rgmii_pins[] = {1366 /*1367 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,1368 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,1369 */1370 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),1371 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),1372 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),1373 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),1374 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),1375 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),1376};1377static const unsigned int avb1_rgmii_mux[] = {1378 AVB1_TX_CTL_MARK, AVB1_TXC_MARK,1379 AVB1_TD0_MARK, AVB1_TD1_MARK,1380 AVB1_TD2_MARK, AVB1_TD3_MARK,1381 AVB1_RX_CTL_MARK, AVB1_RXC_MARK,1382 AVB1_RD0_MARK, AVB1_RD1_MARK,1383 AVB1_RD2_MARK, AVB1_RD3_MARK,1384};1385static const unsigned int avb1_txcrefclk_pins[] = {1386 /* AVB1_TXCREFCLK */1387 RCAR_GP_PIN(6, 20),1388};1389static const unsigned int avb1_txcrefclk_mux[] = {1390 AVB1_TXCREFCLK_MARK,1391};1392static const unsigned int avb1_avtp_pps_pins[] = {1393 /* AVB1_AVTP_PPS */1394 RCAR_GP_PIN(6, 10),1395};1396static const unsigned int avb1_avtp_pps_mux[] = {1397 AVB1_AVTP_PPS_MARK,1398};1399static const unsigned int avb1_avtp_capture_pins[] = {1400 /* AVB1_AVTP_CAPTURE */1401 RCAR_GP_PIN(6, 11),1402};1403static const unsigned int avb1_avtp_capture_mux[] = {1404 AVB1_AVTP_CAPTURE_MARK,1405};1406static const unsigned int avb1_avtp_match_pins[] = {1407 /* AVB1_AVTP_MATCH */1408 RCAR_GP_PIN(6, 5),1409};1410static const unsigned int avb1_avtp_match_mux[] = {1411 AVB1_AVTP_MATCH_MARK,1412};1413 1414/* - AVB2 ------------------------------------------------ */1415static const unsigned int avb2_link_pins[] = {1416 /* AVB2_LINK */1417 RCAR_GP_PIN(5, 3),1418};1419static const unsigned int avb2_link_mux[] = {1420 AVB2_LINK_MARK,1421};1422static const unsigned int avb2_magic_pins[] = {1423 /* AVB2_MAGIC */1424 RCAR_GP_PIN(5, 5),1425};1426static const unsigned int avb2_magic_mux[] = {1427 AVB2_MAGIC_MARK,1428};1429static const unsigned int avb2_phy_int_pins[] = {1430 /* AVB2_PHY_INT */1431 RCAR_GP_PIN(5, 4),1432};1433static const unsigned int avb2_phy_int_mux[] = {1434 AVB2_PHY_INT_MARK,1435};1436static const unsigned int avb2_mdio_pins[] = {1437 /* AVB2_MDC, AVB2_MDIO */1438 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),1439};1440static const unsigned int avb2_mdio_mux[] = {1441 AVB2_MDC_MARK, AVB2_MDIO_MARK,1442};1443static const unsigned int avb2_rgmii_pins[] = {1444 /*1445 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,1446 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,1447 */1448 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),1449 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),1450 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),1451 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),1452 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),1453 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),1454};1455static const unsigned int avb2_rgmii_mux[] = {1456 AVB2_TX_CTL_MARK, AVB2_TXC_MARK,1457 AVB2_TD0_MARK, AVB2_TD1_MARK,1458 AVB2_TD2_MARK, AVB2_TD3_MARK,1459 AVB2_RX_CTL_MARK, AVB2_RXC_MARK,1460 AVB2_RD0_MARK, AVB2_RD1_MARK,1461 AVB2_RD2_MARK, AVB2_RD3_MARK,1462};1463static const unsigned int avb2_txcrefclk_pins[] = {1464 /* AVB2_TXCREFCLK */1465 RCAR_GP_PIN(5, 7),1466};1467static const unsigned int avb2_txcrefclk_mux[] = {1468 AVB2_TXCREFCLK_MARK,1469};1470static const unsigned int avb2_avtp_pps_pins[] = {1471 /* AVB2_AVTP_PPS */1472 RCAR_GP_PIN(5, 0),1473};1474static const unsigned int avb2_avtp_pps_mux[] = {1475 AVB2_AVTP_PPS_MARK,1476};1477static const unsigned int avb2_avtp_capture_pins[] = {1478 /* AVB2_AVTP_CAPTURE */1479 RCAR_GP_PIN(5, 1),1480};1481static const unsigned int avb2_avtp_capture_mux[] = {1482 AVB2_AVTP_CAPTURE_MARK,1483};1484static const unsigned int avb2_avtp_match_pins[] = {1485 /* AVB2_AVTP_MATCH */1486 RCAR_GP_PIN(5, 2),1487};1488static const unsigned int avb2_avtp_match_mux[] = {1489 AVB2_AVTP_MATCH_MARK,1490};1491 1492/* - CANFD0 ----------------------------------------------------------------- */1493static const unsigned int canfd0_data_pins[] = {1494 /* CANFD0_TX, CANFD0_RX */1495 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),1496};1497static const unsigned int canfd0_data_mux[] = {1498 CANFD0_TX_MARK, CANFD0_RX_MARK,1499};1500 1501/* - CANFD1 ----------------------------------------------------------------- */1502static const unsigned int canfd1_data_pins[] = {1503 /* CANFD1_TX, CANFD1_RX */1504 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 19),1505};1506static const unsigned int canfd1_data_mux[] = {1507 CANFD1_TX_MARK, CANFD1_RX_MARK,1508};1509 1510/* - CANFD2 ----------------------------------------------------------------- */1511static const unsigned int canfd2_data_pins[] = {1512 /* CANFD2_TX, CANFD2_RX */1513 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),1514};1515static const unsigned int canfd2_data_mux[] = {1516 CANFD2_TX_MARK, CANFD2_RX_MARK,1517};1518 1519/* - CANFD3 ----------------------------------------------------------------- */1520static const unsigned int canfd3_data_pins[] = {1521 /* CANFD3_TX, CANFD3_RX */1522 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),1523};1524static const unsigned int canfd3_data_mux[] = {1525 CANFD3_TX_MARK, CANFD3_RX_MARK,1526};1527 1528/* - CANFD Clock ------------------------------------------------------------ */1529static const unsigned int can_clk_pins[] = {1530 /* CAN_CLK */1531 RCAR_GP_PIN(2, 9),1532};1533static const unsigned int can_clk_mux[] = {1534 CAN_CLK_MARK,1535};1536 1537/* - HSCIF0 ----------------------------------------------------------------- */1538static const unsigned int hscif0_data_pins[] = {1539 /* HRX0, HTX0 */1540 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),1541};1542static const unsigned int hscif0_data_mux[] = {1543 HRX0_MARK, HTX0_MARK,1544};1545static const unsigned int hscif0_clk_pins[] = {1546 /* HSCK0 */1547 RCAR_GP_PIN(1, 15),1548};1549static const unsigned int hscif0_clk_mux[] = {1550 HSCK0_MARK,1551};1552static const unsigned int hscif0_ctrl_pins[] = {1553 /* HRTS0_N, HCTS0_N */1554 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),1555};1556static const unsigned int hscif0_ctrl_mux[] = {1557 HRTS0_N_MARK, HCTS0_N_MARK,1558};1559 1560/* - HSCIF1 ------------------------------------------------------------------- */1561static const unsigned int hscif1_data_a_pins[] = {1562 /* HRX1_A, HTX1_A */1563 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),1564};1565static const unsigned int hscif1_data_a_mux[] = {1566 HRX1_A_MARK, HTX1_A_MARK,1567};1568static const unsigned int hscif1_clk_a_pins[] = {1569 /* HSCK1_A */1570 RCAR_GP_PIN(0, 18),1571};1572static const unsigned int hscif1_clk_a_mux[] = {1573 HSCK1_A_MARK,1574};1575static const unsigned int hscif1_ctrl_a_pins[] = {1576 /* HRTS1_N_A, HCTS1_N_A */1577 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),1578};1579static const unsigned int hscif1_ctrl_a_mux[] = {1580 HRTS1_N_A_MARK, HCTS1_N_A_MARK,1581};1582 1583static const unsigned int hscif1_data_b_pins[] = {1584 /* HRX1_B, HTX1_B */1585 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),1586};1587static const unsigned int hscif1_data_b_mux[] = {1588 HRX1_B_MARK, HTX1_B_MARK,1589};1590static const unsigned int hscif1_clk_b_pins[] = {1591 /* HSCK1_B */1592 RCAR_GP_PIN(1, 10),1593};1594static const unsigned int hscif1_clk_b_mux[] = {1595 HSCK1_B_MARK,1596};1597static const unsigned int hscif1_ctrl_b_pins[] = {1598 /* HRTS1_N_B, HCTS1_N_B */1599 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),1600};1601static const unsigned int hscif1_ctrl_b_mux[] = {1602 HRTS1_N_B_MARK, HCTS1_N_B_MARK,1603};1604 1605/* - HSCIF2 ----------------------------------------------------------------- */1606static const unsigned int hscif2_data_pins[] = {1607 /* HRX2, HTX2 */1608 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),1609};1610static const unsigned int hscif2_data_mux[] = {1611 HRX2_MARK, HTX2_MARK,1612};1613static const unsigned int hscif2_clk_pins[] = {1614 /* HSCK2 */1615 RCAR_GP_PIN(4, 13),1616};1617static const unsigned int hscif2_clk_mux[] = {1618 HSCK2_MARK,1619};1620static const unsigned int hscif2_ctrl_pins[] = {1621 /* HRTS2_N, HCTS2_N */1622 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 12),1623};1624static const unsigned int hscif2_ctrl_mux[] = {1625 HRTS2_N_MARK, HCTS2_N_MARK,1626};1627 1628/* - HSCIF3 ------------------------------------------------------------------- */1629static const unsigned int hscif3_data_a_pins[] = {1630 /* HRX3_A, HTX3_A */1631 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),1632};1633static const unsigned int hscif3_data_a_mux[] = {1634 HRX3_A_MARK, HTX3_A_MARK,1635};1636static const unsigned int hscif3_clk_a_pins[] = {1637 /* HSCK3_A */1638 RCAR_GP_PIN(1, 25),1639};1640static const unsigned int hscif3_clk_a_mux[] = {1641 HSCK3_A_MARK,1642};1643static const unsigned int hscif3_ctrl_a_pins[] = {1644 /* HRTS3_N_A, HCTS3_N_A */1645 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),1646};1647static const unsigned int hscif3_ctrl_a_mux[] = {1648 HRTS3_N_A_MARK, HCTS3_N_A_MARK,1649};1650 1651static const unsigned int hscif3_data_b_pins[] = {1652 /* HRX3_B, HTX3_B */1653 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),1654};1655static const unsigned int hscif3_data_b_mux[] = {1656 HRX3_B_MARK, HTX3_B_MARK,1657};1658static const unsigned int hscif3_clk_b_pins[] = {1659 /* HSCK3_B */1660 RCAR_GP_PIN(1, 3),1661};1662static const unsigned int hscif3_clk_b_mux[] = {1663 HSCK3_B_MARK,1664};1665static const unsigned int hscif3_ctrl_b_pins[] = {1666 /* HRTS3_N_B, HCTS3_N_B */1667 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),1668};1669static const unsigned int hscif3_ctrl_b_mux[] = {1670 HRTS3_N_B_MARK, HCTS3_N_B_MARK,1671};1672 1673/* - I2C0 ------------------------------------------------------------------- */1674static const unsigned int i2c0_pins[] = {1675 /* SDA0, SCL0 */1676 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),1677};1678static const unsigned int i2c0_mux[] = {1679 SDA0_MARK, SCL0_MARK,1680};1681 1682/* - I2C1 ------------------------------------------------------------------- */1683static const unsigned int i2c1_pins[] = {1684 /* SDA1, SCL1 */1685 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),1686};1687static const unsigned int i2c1_mux[] = {1688 SDA1_MARK, SCL1_MARK,1689};1690 1691/* - I2C2 ------------------------------------------------------------------- */1692static const unsigned int i2c2_pins[] = {1693 /* SDA2, SCL2 */1694 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),1695};1696static const unsigned int i2c2_mux[] = {1697 SDA2_MARK, SCL2_MARK,1698};1699 1700/* - I2C3 ------------------------------------------------------------------- */1701static const unsigned int i2c3_pins[] = {1702 /* SDA3, SCL3 */1703 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),1704};1705static const unsigned int i2c3_mux[] = {1706 SDA3_MARK, SCL3_MARK,1707};1708 1709/* - INTC-EX ---------------------------------------------------------------- */1710static const unsigned int intc_ex_irq0_a_pins[] = {1711 /* IRQ0_A */1712 RCAR_GP_PIN(0, 6),1713};1714static const unsigned int intc_ex_irq0_a_mux[] = {1715 IRQ0_A_MARK,1716};1717static const unsigned int intc_ex_irq0_b_pins[] = {1718 /* IRQ0_B */1719 RCAR_GP_PIN(1, 20),1720};1721static const unsigned int intc_ex_irq0_b_mux[] = {1722 IRQ0_B_MARK,1723};1724 1725static const unsigned int intc_ex_irq1_a_pins[] = {1726 /* IRQ1_A */1727 RCAR_GP_PIN(0, 5),1728};1729static const unsigned int intc_ex_irq1_a_mux[] = {1730 IRQ1_A_MARK,1731};1732static const unsigned int intc_ex_irq1_b_pins[] = {1733 /* IRQ1_B */1734 RCAR_GP_PIN(1, 21),1735};1736static const unsigned int intc_ex_irq1_b_mux[] = {1737 IRQ1_B_MARK,1738};1739 1740static const unsigned int intc_ex_irq2_a_pins[] = {1741 /* IRQ2_A */1742 RCAR_GP_PIN(0, 4),1743};1744static const unsigned int intc_ex_irq2_a_mux[] = {1745 IRQ2_A_MARK,1746};1747static const unsigned int intc_ex_irq2_b_pins[] = {1748 /* IRQ2_B */1749 RCAR_GP_PIN(0, 13),1750};1751static const unsigned int intc_ex_irq2_b_mux[] = {1752 IRQ2_B_MARK,1753};1754 1755static const unsigned int intc_ex_irq3_a_pins[] = {1756 /* IRQ3_A */1757 RCAR_GP_PIN(0, 3),1758};1759static const unsigned int intc_ex_irq3_a_mux[] = {1760 IRQ3_A_MARK,1761};1762static const unsigned int intc_ex_irq3_b_pins[] = {1763 /* IRQ3_B */1764 RCAR_GP_PIN(1, 23),1765};1766static const unsigned int intc_ex_irq3_b_mux[] = {1767 IRQ3_B_MARK,1768};1769 1770static const unsigned int intc_ex_irq4_a_pins[] = {1771 /* IRQ4_A */1772 RCAR_GP_PIN(1, 17),1773};1774static const unsigned int intc_ex_irq4_a_mux[] = {1775 IRQ4_A_MARK,1776};1777static const unsigned int intc_ex_irq4_b_pins[] = {1778 /* IRQ4_B */1779 RCAR_GP_PIN(2, 3),1780};1781static const unsigned int intc_ex_irq4_b_mux[] = {1782 IRQ4_B_MARK,1783};1784 1785static const unsigned int intc_ex_irq5_pins[] = {1786 /* IRQ5 */1787 RCAR_GP_PIN(2, 2),1788};1789static const unsigned int intc_ex_irq5_mux[] = {1790 IRQ5_MARK,1791};1792 1793/* - MMC -------------------------------------------------------------------- */1794static const unsigned int mmc_data_pins[] = {1795 /* MMC_SD_D[0:3], MMC_D[4:7] */1796 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),1797 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),1798 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),1799 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),1800};1801static const unsigned int mmc_data_mux[] = {1802 MMC_SD_D0_MARK, MMC_SD_D1_MARK,1803 MMC_SD_D2_MARK, MMC_SD_D3_MARK,1804 MMC_D4_MARK, MMC_D5_MARK,1805 MMC_D6_MARK, MMC_D7_MARK,1806};1807static const unsigned int mmc_ctrl_pins[] = {1808 /* MMC_SD_CLK, MMC_SD_CMD */1809 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),1810};1811static const unsigned int mmc_ctrl_mux[] = {1812 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,1813};1814static const unsigned int mmc_cd_pins[] = {1815 /* SD_CD */1816 RCAR_GP_PIN(3, 11),1817};1818static const unsigned int mmc_cd_mux[] = {1819 SD_CD_MARK,1820};1821static const unsigned int mmc_wp_pins[] = {1822 /* SD_WP */1823 RCAR_GP_PIN(3, 12),1824};1825static const unsigned int mmc_wp_mux[] = {1826 SD_WP_MARK,1827};1828static const unsigned int mmc_ds_pins[] = {1829 /* MMC_DS */1830 RCAR_GP_PIN(3, 4),1831};1832static const unsigned int mmc_ds_mux[] = {1833 MMC_DS_MARK,1834};1835 1836/* - MSIOF0 ----------------------------------------------------------------- */1837static const unsigned int msiof0_clk_pins[] = {1838 /* MSIOF0_SCK */1839 RCAR_GP_PIN(1, 10),1840};1841static const unsigned int msiof0_clk_mux[] = {1842 MSIOF0_SCK_MARK,1843};1844static const unsigned int msiof0_sync_pins[] = {1845 /* MSIOF0_SYNC */1846 RCAR_GP_PIN(1, 8),1847};1848static const unsigned int msiof0_sync_mux[] = {1849 MSIOF0_SYNC_MARK,1850};1851static const unsigned int msiof0_ss1_pins[] = {1852 /* MSIOF0_SS1 */1853 RCAR_GP_PIN(1, 7),1854};1855static const unsigned int msiof0_ss1_mux[] = {1856 MSIOF0_SS1_MARK,1857};1858static const unsigned int msiof0_ss2_pins[] = {1859 /* MSIOF0_SS2 */1860 RCAR_GP_PIN(1, 6),1861};1862static const unsigned int msiof0_ss2_mux[] = {1863 MSIOF0_SS2_MARK,1864};1865static const unsigned int msiof0_txd_pins[] = {1866 /* MSIOF0_TXD */1867 RCAR_GP_PIN(1, 9),1868};1869static const unsigned int msiof0_txd_mux[] = {1870 MSIOF0_TXD_MARK,1871};1872static const unsigned int msiof0_rxd_pins[] = {1873 /* MSIOF0_RXD */1874 RCAR_GP_PIN(1, 11),1875};1876static const unsigned int msiof0_rxd_mux[] = {1877 MSIOF0_RXD_MARK,1878};1879 1880/* - MSIOF1 ----------------------------------------------------------------- */1881static const unsigned int msiof1_clk_pins[] = {1882 /* MSIOF1_SCK */1883 RCAR_GP_PIN(1, 3),1884};1885static const unsigned int msiof1_clk_mux[] = {1886 MSIOF1_SCK_MARK,1887};1888static const unsigned int msiof1_sync_pins[] = {1889 /* MSIOF1_SYNC */1890 RCAR_GP_PIN(1, 2),1891};1892static const unsigned int msiof1_sync_mux[] = {1893 MSIOF1_SYNC_MARK,1894};1895static const unsigned int msiof1_ss1_pins[] = {1896 /* MSIOF1_SS1 */1897 RCAR_GP_PIN(1, 1),1898};1899static const unsigned int msiof1_ss1_mux[] = {1900 MSIOF1_SS1_MARK,1901};1902static const unsigned int msiof1_ss2_pins[] = {1903 /* MSIOF1_SS2 */1904 RCAR_GP_PIN(1, 0),1905};1906static const unsigned int msiof1_ss2_mux[] = {1907 MSIOF1_SS2_MARK,1908};1909static const unsigned int msiof1_txd_pins[] = {1910 /* MSIOF1_TXD */1911 RCAR_GP_PIN(1, 4),1912};1913static const unsigned int msiof1_txd_mux[] = {1914 MSIOF1_TXD_MARK,1915};1916static const unsigned int msiof1_rxd_pins[] = {1917 /* MSIOF1_RXD */1918 RCAR_GP_PIN(1, 5),1919};1920static const unsigned int msiof1_rxd_mux[] = {1921 MSIOF1_RXD_MARK,1922};1923 1924/* - MSIOF2 ----------------------------------------------------------------- */1925static const unsigned int msiof2_clk_pins[] = {1926 /* MSIOF2_SCK */1927 RCAR_GP_PIN(0, 17),1928};1929static const unsigned int msiof2_clk_mux[] = {1930 MSIOF2_SCK_MARK,1931};1932static const unsigned int msiof2_sync_pins[] = {1933 /* MSIOF2_SYNC */1934 RCAR_GP_PIN(0, 15),1935};1936static const unsigned int msiof2_sync_mux[] = {1937 MSIOF2_SYNC_MARK,1938};1939static const unsigned int msiof2_ss1_pins[] = {1940 /* MSIOF2_SS1 */1941 RCAR_GP_PIN(0, 14),1942};1943static const unsigned int msiof2_ss1_mux[] = {1944 MSIOF2_SS1_MARK,1945};1946static const unsigned int msiof2_ss2_pins[] = {1947 /* MSIOF2_SS2 */1948 RCAR_GP_PIN(0, 13),1949};1950static const unsigned int msiof2_ss2_mux[] = {1951 MSIOF2_SS2_MARK,1952};1953static const unsigned int msiof2_txd_pins[] = {1954 /* MSIOF2_TXD */1955 RCAR_GP_PIN(0, 16),1956};1957static const unsigned int msiof2_txd_mux[] = {1958 MSIOF2_TXD_MARK,1959};1960static const unsigned int msiof2_rxd_pins[] = {1961 /* MSIOF2_RXD */1962 RCAR_GP_PIN(0, 18),1963};1964static const unsigned int msiof2_rxd_mux[] = {1965 MSIOF2_RXD_MARK,1966};1967 1968/* - MSIOF3 ----------------------------------------------------------------- */1969static const unsigned int msiof3_clk_pins[] = {1970 /* MSIOF3_SCK */1971 RCAR_GP_PIN(0, 3),1972};1973static const unsigned int msiof3_clk_mux[] = {1974 MSIOF3_SCK_MARK,1975};1976static const unsigned int msiof3_sync_pins[] = {1977 /* MSIOF3_SYNC */1978 RCAR_GP_PIN(0, 6),1979};1980static const unsigned int msiof3_sync_mux[] = {1981 MSIOF3_SYNC_MARK,1982};1983static const unsigned int msiof3_ss1_pins[] = {1984 /* MSIOF3_SS1 */1985 RCAR_GP_PIN(0, 1),1986};1987static const unsigned int msiof3_ss1_mux[] = {1988 MSIOF3_SS1_MARK,1989};1990static const unsigned int msiof3_ss2_pins[] = {1991 /* MSIOF3_SS2 */1992 RCAR_GP_PIN(0, 2),1993};1994static const unsigned int msiof3_ss2_mux[] = {1995 MSIOF3_SS2_MARK,1996};1997static const unsigned int msiof3_txd_pins[] = {1998 /* MSIOF3_TXD */1999 RCAR_GP_PIN(0, 4),2000};2001static const unsigned int msiof3_txd_mux[] = {2002 MSIOF3_TXD_MARK,2003};2004static const unsigned int msiof3_rxd_pins[] = {2005 /* MSIOF3_RXD */2006 RCAR_GP_PIN(0, 5),2007};2008static const unsigned int msiof3_rxd_mux[] = {2009 MSIOF3_RXD_MARK,2010};2011 2012/* - MSIOF4 ----------------------------------------------------------------- */2013static const unsigned int msiof4_clk_pins[] = {2014 /* MSIOF4_SCK */2015 RCAR_GP_PIN(1, 25),2016};2017static const unsigned int msiof4_clk_mux[] = {2018 MSIOF4_SCK_MARK,2019};2020static const unsigned int msiof4_sync_pins[] = {2021 /* MSIOF4_SYNC */2022 RCAR_GP_PIN(1, 28),2023};2024static const unsigned int msiof4_sync_mux[] = {2025 MSIOF4_SYNC_MARK,2026};2027static const unsigned int msiof4_ss1_pins[] = {2028 /* MSIOF4_SS1 */2029 RCAR_GP_PIN(1, 23),2030};2031static const unsigned int msiof4_ss1_mux[] = {2032 MSIOF4_SS1_MARK,2033};2034static const unsigned int msiof4_ss2_pins[] = {2035 /* MSIOF4_SS2 */2036 RCAR_GP_PIN(1, 24),2037};2038static const unsigned int msiof4_ss2_mux[] = {2039 MSIOF4_SS2_MARK,2040};2041static const unsigned int msiof4_txd_pins[] = {2042 /* MSIOF4_TXD */2043 RCAR_GP_PIN(1, 26),2044};2045static const unsigned int msiof4_txd_mux[] = {2046 MSIOF4_TXD_MARK,2047};2048static const unsigned int msiof4_rxd_pins[] = {2049 /* MSIOF4_RXD */2050 RCAR_GP_PIN(1, 27),2051};2052static const unsigned int msiof4_rxd_mux[] = {2053 MSIOF4_RXD_MARK,2054};2055 2056/* - MSIOF5 ----------------------------------------------------------------- */2057static const unsigned int msiof5_clk_pins[] = {2058 /* MSIOF5_SCK */2059 RCAR_GP_PIN(0, 11),2060};2061static const unsigned int msiof5_clk_mux[] = {2062 MSIOF5_SCK_MARK,2063};2064static const unsigned int msiof5_sync_pins[] = {2065 /* MSIOF5_SYNC */2066 RCAR_GP_PIN(0, 9),2067};2068static const unsigned int msiof5_sync_mux[] = {2069 MSIOF5_SYNC_MARK,2070};2071static const unsigned int msiof5_ss1_pins[] = {2072 /* MSIOF5_SS1 */2073 RCAR_GP_PIN(0, 8),2074};2075static const unsigned int msiof5_ss1_mux[] = {2076 MSIOF5_SS1_MARK,2077};2078static const unsigned int msiof5_ss2_pins[] = {2079 /* MSIOF5_SS2 */2080 RCAR_GP_PIN(0, 7),2081};2082static const unsigned int msiof5_ss2_mux[] = {2083 MSIOF5_SS2_MARK,2084};2085static const unsigned int msiof5_txd_pins[] = {2086 /* MSIOF5_TXD */2087 RCAR_GP_PIN(0, 10),2088};2089static const unsigned int msiof5_txd_mux[] = {2090 MSIOF5_TXD_MARK,2091};2092static const unsigned int msiof5_rxd_pins[] = {2093 /* MSIOF5_RXD */2094 RCAR_GP_PIN(0, 12),2095};2096static const unsigned int msiof5_rxd_mux[] = {2097 MSIOF5_RXD_MARK,2098};2099 2100/* - PCIE ------------------------------------------------------------------- */2101static const unsigned int pcie0_clkreq_n_pins[] = {2102 /* PCIE0_CLKREQ_N */2103 RCAR_GP_PIN(4, 21),2104};2105 2106static const unsigned int pcie0_clkreq_n_mux[] = {2107 PCIE0_CLKREQ_N_MARK,2108};2109 2110/* - PWM0 --------------------------------------------------------------------- */2111static const unsigned int pwm0_a_pins[] = {2112 /* PWM0_A */2113 RCAR_GP_PIN(1, 15),2114};2115static const unsigned int pwm0_a_mux[] = {2116 PWM0_A_MARK,2117};2118 2119static const unsigned int pwm0_b_pins[] = {2120 /* PWM0_B */2121 RCAR_GP_PIN(1, 14),2122};2123static const unsigned int pwm0_b_mux[] = {2124 PWM0_B_MARK,2125};2126 2127/* - PWM1 --------------------------------------------------------------------- */2128static const unsigned int pwm1_a_pins[] = {2129 /* PWM1_A */2130 RCAR_GP_PIN(3, 13),2131};2132static const unsigned int pwm1_a_mux[] = {2133 PWM1_A_MARK,2134};2135 2136static const unsigned int pwm1_b_pins[] = {2137 /* PWM1_B */2138 RCAR_GP_PIN(2, 13),2139};2140static const unsigned int pwm1_b_mux[] = {2141 PWM1_B_MARK,2142};2143 2144static const unsigned int pwm1_c_pins[] = {2145 /* PWM1_C */2146 RCAR_GP_PIN(2, 17),2147};2148static const unsigned int pwm1_c_mux[] = {2149 PWM1_C_MARK,2150};2151 2152/* - PWM2 --------------------------------------------------------------------- */2153static const unsigned int pwm2_a_pins[] = {2154 /* PWM2_A */2155 RCAR_GP_PIN(3, 14),2156};2157static const unsigned int pwm2_a_mux[] = {2158 PWM2_A_MARK,2159};2160 2161static const unsigned int pwm2_b_pins[] = {2162 /* PWM2_B */2163 RCAR_GP_PIN(2, 14),2164};2165static const unsigned int pwm2_b_mux[] = {2166 PWM2_B_MARK,2167};2168 2169static const unsigned int pwm2_c_pins[] = {2170 /* PWM2_C */2171 RCAR_GP_PIN(2, 19),2172};2173static const unsigned int pwm2_c_mux[] = {2174 PWM2_C_MARK,2175};2176 2177/* - PWM3 --------------------------------------------------------------------- */2178static const unsigned int pwm3_a_pins[] = {2179 /* PWM3_A */2180 RCAR_GP_PIN(4, 14),2181};2182static const unsigned int pwm3_a_mux[] = {2183 PWM3_A_MARK,2184};2185 2186static const unsigned int pwm3_b_pins[] = {2187 /* PWM3_B */2188 RCAR_GP_PIN(2, 15),2189};2190static const unsigned int pwm3_b_mux[] = {2191 PWM3_B_MARK,2192};2193 2194static const unsigned int pwm3_c_pins[] = {2195 /* PWM3_C */2196 RCAR_GP_PIN(1, 22),2197};2198static const unsigned int pwm3_c_mux[] = {2199 PWM3_C_MARK,2200};2201 2202/* - PWM4 ------------------------------------------------------------------- */2203static const unsigned int pwm4_pins[] = {2204 /* PWM4 */2205 RCAR_GP_PIN(4, 15),2206};2207static const unsigned int pwm4_mux[] = {2208 PWM4_MARK,2209};2210 2211/* - QSPI0 ------------------------------------------------------------------ */2212static const unsigned int qspi0_ctrl_pins[] = {2213 /* SPCLK, SSL */2214 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),2215};2216static const unsigned int qspi0_ctrl_mux[] = {2217 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,2218};2219static const unsigned int qspi0_data_pins[] = {2220 /* MOSI_IO0, MISO_IO1, IO2, IO3 */2221 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),2222 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),2223};2224static const unsigned int qspi0_data_mux[] = {2225 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,2226 QSPI0_IO2_MARK, QSPI0_IO3_MARK2227};2228 2229/* - QSPI1 ------------------------------------------------------------------ */2230static const unsigned int qspi1_ctrl_pins[] = {2231 /* SPCLK, SSL */2232 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),2233};2234static const unsigned int qspi1_ctrl_mux[] = {2235 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,2236};2237static const unsigned int qspi1_data_pins[] = {2238 /* MOSI_IO0, MISO_IO1, IO2, IO3 */2239 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),2240 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),2241};2242static const unsigned int qspi1_data_mux[] = {2243 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,2244 QSPI1_IO2_MARK, QSPI1_IO3_MARK2245};2246 2247/* - SCIF0 ------------------------------------------------------------------ */2248static const unsigned int scif0_data_pins[] = {2249 /* RX0, TX0 */2250 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),2251};2252static const unsigned int scif0_data_mux[] = {2253 RX0_MARK, TX0_MARK,2254};2255static const unsigned int scif0_clk_pins[] = {2256 /* SCK0 */2257 RCAR_GP_PIN(1, 15),2258};2259static const unsigned int scif0_clk_mux[] = {2260 SCK0_MARK,2261};2262static const unsigned int scif0_ctrl_pins[] = {2263 /* RTS0_N, CTS0_N */2264 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),2265};2266static const unsigned int scif0_ctrl_mux[] = {2267 RTS0_N_MARK, CTS0_N_MARK,2268};2269 2270/* - SCIF1 -------------------------------------------------------------------- */2271static const unsigned int scif1_data_a_pins[] = {2272 /* RX1_A, TX1_A */2273 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),2274};2275static const unsigned int scif1_data_a_mux[] = {2276 RX1_A_MARK, TX1_A_MARK,2277};2278static const unsigned int scif1_clk_a_pins[] = {2279 /* SCK1_A */2280 RCAR_GP_PIN(0, 18),2281};2282static const unsigned int scif1_clk_a_mux[] = {2283 SCK1_A_MARK,2284};2285static const unsigned int scif1_ctrl_a_pins[] = {2286 /* RTS1_N_A, CTS1_N_A */2287 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),2288};2289static const unsigned int scif1_ctrl_a_mux[] = {2290 RTS1_N_A_MARK, CTS1_N_A_MARK,2291};2292 2293static const unsigned int scif1_data_b_pins[] = {2294 /* RX1_B, TX1_B */2295 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),2296};2297static const unsigned int scif1_data_b_mux[] = {2298 RX1_B_MARK, TX1_B_MARK,2299};2300static const unsigned int scif1_clk_b_pins[] = {2301 /* SCK1_B */2302 RCAR_GP_PIN(1, 10),2303};2304static const unsigned int scif1_clk_b_mux[] = {2305 SCK1_B_MARK,2306};2307static const unsigned int scif1_ctrl_b_pins[] = {2308 /* RTS1_N_B, CTS1_N_B */2309 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),2310};2311static const unsigned int scif1_ctrl_b_mux[] = {2312 RTS1_N_B_MARK, CTS1_N_B_MARK,2313};2314 2315/* - SCIF3 -------------------------------------------------------------------- */2316static const unsigned int scif3_data_a_pins[] = {2317 /* RX3_A, TX3_A */2318 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),2319};2320static const unsigned int scif3_data_a_mux[] = {2321 RX3_A_MARK, TX3_A_MARK,2322};2323static const unsigned int scif3_clk_a_pins[] = {2324 /* SCK3_A */2325 RCAR_GP_PIN(1, 24),2326};2327static const unsigned int scif3_clk_a_mux[] = {2328 SCK3_A_MARK,2329};2330static const unsigned int scif3_ctrl_a_pins[] = {2331 /* RTS3_N_A, CTS3_N_A */2332 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),2333};2334static const unsigned int scif3_ctrl_a_mux[] = {2335 RTS3_N_A_MARK, CTS3_N_A_MARK,2336};2337 2338static const unsigned int scif3_data_b_pins[] = {2339 /* RX3_B, TX3_B */2340 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),2341};2342static const unsigned int scif3_data_b_mux[] = {2343 RX3_B_MARK, TX3_B_MARK,2344};2345static const unsigned int scif3_clk_b_pins[] = {2346 /* SCK3_B */2347 RCAR_GP_PIN(1, 4),2348};2349static const unsigned int scif3_clk_b_mux[] = {2350 SCK3_B_MARK,2351};2352static const unsigned int scif3_ctrl_b_pins[] = {2353 /* RTS3_N_B, CTS3_N_B */2354 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),2355};2356static const unsigned int scif3_ctrl_b_mux[] = {2357 RTS3_N_B_MARK, CTS3_N_B_MARK,2358};2359 2360/* - SCIF4 ------------------------------------------------------------------ */2361static const unsigned int scif4_data_pins[] = {2362 /* RX4, TX4 */2363 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),2364};2365static const unsigned int scif4_data_mux[] = {2366 RX4_MARK, TX4_MARK,2367};2368static const unsigned int scif4_clk_pins[] = {2369 /* SCK4 */2370 RCAR_GP_PIN(4, 8),2371};2372static const unsigned int scif4_clk_mux[] = {2373 SCK4_MARK,2374};2375static const unsigned int scif4_ctrl_pins[] = {2376 /* RTS4_N, CTS4_N */2377 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 9),2378};2379static const unsigned int scif4_ctrl_mux[] = {2380 RTS4_N_MARK, CTS4_N_MARK,2381};2382 2383/* - SCIF Clock ------------------------------------------------------------- */2384static const unsigned int scif_clk_pins[] = {2385 /* SCIF_CLK */2386 RCAR_GP_PIN(1, 17),2387};2388static const unsigned int scif_clk_mux[] = {2389 SCIF_CLK_MARK,2390};2391 2392static const unsigned int scif_clk2_pins[] = {2393 /* SCIF_CLK2 */2394 RCAR_GP_PIN(4, 11),2395};2396static const unsigned int scif_clk2_mux[] = {2397 SCIF_CLK2_MARK,2398};2399 2400/* - SSI ------------------------------------------------- */2401static const unsigned int ssi_data_pins[] = {2402 /* SSI_SD */2403 RCAR_GP_PIN(1, 20),2404};2405static const unsigned int ssi_data_mux[] = {2406 SSI_SD_MARK,2407};2408static const unsigned int ssi_ctrl_pins[] = {2409 /* SSI_SCK, SSI_WS */2410 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),2411};2412static const unsigned int ssi_ctrl_mux[] = {2413 SSI_SCK_MARK, SSI_WS_MARK,2414};2415 2416/* - TPU --------------------------------------------------------------------- */2417static const unsigned int tpu_to0_a_pins[] = {2418 /* TPU0TO0_A */2419 RCAR_GP_PIN(2, 8),2420};2421static const unsigned int tpu_to0_a_mux[] = {2422 TPU0TO0_A_MARK,2423};2424static const unsigned int tpu_to1_a_pins[] = {2425 /* TPU0TO1_A */2426 RCAR_GP_PIN(2, 7),2427};2428static const unsigned int tpu_to1_a_mux[] = {2429 TPU0TO1_A_MARK,2430};2431static const unsigned int tpu_to2_a_pins[] = {2432 /* TPU0TO2_A */2433 RCAR_GP_PIN(2, 12),2434};2435static const unsigned int tpu_to2_a_mux[] = {2436 TPU0TO2_A_MARK,2437};2438static const unsigned int tpu_to3_a_pins[] = {2439 /* TPU0TO3_A */2440 RCAR_GP_PIN(2, 13),2441};2442static const unsigned int tpu_to3_a_mux[] = {2443 TPU0TO3_A_MARK,2444};2445 2446static const unsigned int tpu_to0_b_pins[] = {2447 /* TPU0TO0_B */2448 RCAR_GP_PIN(1, 25),2449};2450static const unsigned int tpu_to0_b_mux[] = {2451 TPU0TO0_B_MARK,2452};2453static const unsigned int tpu_to1_b_pins[] = {2454 /* TPU0TO1_B */2455 RCAR_GP_PIN(1, 26),2456};2457static const unsigned int tpu_to1_b_mux[] = {2458 TPU0TO1_B_MARK,2459};2460static const unsigned int tpu_to2_b_pins[] = {2461 /* TPU0TO2_B */2462 RCAR_GP_PIN(2, 0),2463};2464static const unsigned int tpu_to2_b_mux[] = {2465 TPU0TO2_B_MARK,2466};2467static const unsigned int tpu_to3_b_pins[] = {2468 /* TPU0TO3_B */2469 RCAR_GP_PIN(2, 1),2470};2471static const unsigned int tpu_to3_b_mux[] = {2472 TPU0TO3_B_MARK,2473};2474 2475static const struct sh_pfc_pin_group pinmux_groups[] = {2476 SH_PFC_PIN_GROUP(audio_clkin),2477 SH_PFC_PIN_GROUP(audio_clkout),2478 2479 SH_PFC_PIN_GROUP(avb0_link),2480 SH_PFC_PIN_GROUP(avb0_magic),2481 SH_PFC_PIN_GROUP(avb0_phy_int),2482 SH_PFC_PIN_GROUP(avb0_mdio),2483 SH_PFC_PIN_GROUP(avb0_mii),2484 SH_PFC_PIN_GROUP(avb0_rgmii),2485 SH_PFC_PIN_GROUP(avb0_txcrefclk),2486 SH_PFC_PIN_GROUP(avb0_avtp_pps),2487 SH_PFC_PIN_GROUP(avb0_avtp_capture),2488 SH_PFC_PIN_GROUP(avb0_avtp_match),2489 2490 SH_PFC_PIN_GROUP(avb1_link),2491 SH_PFC_PIN_GROUP(avb1_magic),2492 SH_PFC_PIN_GROUP(avb1_phy_int),2493 SH_PFC_PIN_GROUP(avb1_mdio),2494 SH_PFC_PIN_GROUP(avb1_mii),2495 SH_PFC_PIN_GROUP(avb1_rgmii),2496 SH_PFC_PIN_GROUP(avb1_txcrefclk),2497 SH_PFC_PIN_GROUP(avb1_avtp_pps),2498 SH_PFC_PIN_GROUP(avb1_avtp_capture),2499 SH_PFC_PIN_GROUP(avb1_avtp_match),2500 2501 SH_PFC_PIN_GROUP(avb2_link),2502 SH_PFC_PIN_GROUP(avb2_magic),2503 SH_PFC_PIN_GROUP(avb2_phy_int),2504 SH_PFC_PIN_GROUP(avb2_mdio),2505 SH_PFC_PIN_GROUP(avb2_rgmii),2506 SH_PFC_PIN_GROUP(avb2_txcrefclk),2507 SH_PFC_PIN_GROUP(avb2_avtp_pps),2508 SH_PFC_PIN_GROUP(avb2_avtp_capture),2509 SH_PFC_PIN_GROUP(avb2_avtp_match),2510 2511 SH_PFC_PIN_GROUP(canfd0_data),2512 SH_PFC_PIN_GROUP(canfd1_data),2513 SH_PFC_PIN_GROUP(canfd2_data),2514 SH_PFC_PIN_GROUP(canfd3_data),2515 SH_PFC_PIN_GROUP(can_clk),2516 2517 SH_PFC_PIN_GROUP(hscif0_data),2518 SH_PFC_PIN_GROUP(hscif0_clk),2519 SH_PFC_PIN_GROUP(hscif0_ctrl),2520 SH_PFC_PIN_GROUP(hscif1_data_a),2521 SH_PFC_PIN_GROUP(hscif1_clk_a),2522 SH_PFC_PIN_GROUP(hscif1_ctrl_a),2523 SH_PFC_PIN_GROUP(hscif1_data_b),2524 SH_PFC_PIN_GROUP(hscif1_clk_b),2525 SH_PFC_PIN_GROUP(hscif1_ctrl_b),2526 SH_PFC_PIN_GROUP(hscif2_data),2527 SH_PFC_PIN_GROUP(hscif2_clk),2528 SH_PFC_PIN_GROUP(hscif2_ctrl),2529 SH_PFC_PIN_GROUP(hscif3_data_a),2530 SH_PFC_PIN_GROUP(hscif3_clk_a),2531 SH_PFC_PIN_GROUP(hscif3_ctrl_a),2532 SH_PFC_PIN_GROUP(hscif3_data_b),2533 SH_PFC_PIN_GROUP(hscif3_clk_b),2534 SH_PFC_PIN_GROUP(hscif3_ctrl_b),2535 2536 SH_PFC_PIN_GROUP(i2c0),2537 SH_PFC_PIN_GROUP(i2c1),2538 SH_PFC_PIN_GROUP(i2c2),2539 SH_PFC_PIN_GROUP(i2c3),2540 2541 SH_PFC_PIN_GROUP(intc_ex_irq0_a),2542 SH_PFC_PIN_GROUP(intc_ex_irq0_b),2543 SH_PFC_PIN_GROUP(intc_ex_irq1_a),2544 SH_PFC_PIN_GROUP(intc_ex_irq1_b),2545 SH_PFC_PIN_GROUP(intc_ex_irq2_a),2546 SH_PFC_PIN_GROUP(intc_ex_irq2_b),2547 SH_PFC_PIN_GROUP(intc_ex_irq3_a),2548 SH_PFC_PIN_GROUP(intc_ex_irq3_b),2549 SH_PFC_PIN_GROUP(intc_ex_irq4_a),2550 SH_PFC_PIN_GROUP(intc_ex_irq4_b),2551 SH_PFC_PIN_GROUP(intc_ex_irq5),2552 2553 BUS_DATA_PIN_GROUP(mmc_data, 1),2554 BUS_DATA_PIN_GROUP(mmc_data, 4),2555 BUS_DATA_PIN_GROUP(mmc_data, 8),2556 SH_PFC_PIN_GROUP(mmc_ctrl),2557 SH_PFC_PIN_GROUP(mmc_cd),2558 SH_PFC_PIN_GROUP(mmc_wp),2559 SH_PFC_PIN_GROUP(mmc_ds),2560 2561 SH_PFC_PIN_GROUP(msiof0_clk),2562 SH_PFC_PIN_GROUP(msiof0_sync),2563 SH_PFC_PIN_GROUP(msiof0_ss1),2564 SH_PFC_PIN_GROUP(msiof0_ss2),2565 SH_PFC_PIN_GROUP(msiof0_txd),2566 SH_PFC_PIN_GROUP(msiof0_rxd),2567 2568 SH_PFC_PIN_GROUP(msiof1_clk),2569 SH_PFC_PIN_GROUP(msiof1_sync),2570 SH_PFC_PIN_GROUP(msiof1_ss1),2571 SH_PFC_PIN_GROUP(msiof1_ss2),2572 SH_PFC_PIN_GROUP(msiof1_txd),2573 SH_PFC_PIN_GROUP(msiof1_rxd),2574 2575 SH_PFC_PIN_GROUP(msiof2_clk),2576 SH_PFC_PIN_GROUP(msiof2_sync),2577 SH_PFC_PIN_GROUP(msiof2_ss1),2578 SH_PFC_PIN_GROUP(msiof2_ss2),2579 SH_PFC_PIN_GROUP(msiof2_txd),2580 SH_PFC_PIN_GROUP(msiof2_rxd),2581 2582 SH_PFC_PIN_GROUP(msiof3_clk),2583 SH_PFC_PIN_GROUP(msiof3_sync),2584 SH_PFC_PIN_GROUP(msiof3_ss1),2585 SH_PFC_PIN_GROUP(msiof3_ss2),2586 SH_PFC_PIN_GROUP(msiof3_txd),2587 SH_PFC_PIN_GROUP(msiof3_rxd),2588 2589 SH_PFC_PIN_GROUP(msiof4_clk),2590 SH_PFC_PIN_GROUP(msiof4_sync),2591 SH_PFC_PIN_GROUP(msiof4_ss1),2592 SH_PFC_PIN_GROUP(msiof4_ss2),2593 SH_PFC_PIN_GROUP(msiof4_txd),2594 SH_PFC_PIN_GROUP(msiof4_rxd),2595 2596 SH_PFC_PIN_GROUP(msiof5_clk),2597 SH_PFC_PIN_GROUP(msiof5_sync),2598 SH_PFC_PIN_GROUP(msiof5_ss1),2599 SH_PFC_PIN_GROUP(msiof5_ss2),2600 SH_PFC_PIN_GROUP(msiof5_txd),2601 SH_PFC_PIN_GROUP(msiof5_rxd),2602 2603 SH_PFC_PIN_GROUP(pcie0_clkreq_n),2604 2605 SH_PFC_PIN_GROUP(pwm0_a),2606 SH_PFC_PIN_GROUP(pwm0_b),2607 SH_PFC_PIN_GROUP(pwm1_a),2608 SH_PFC_PIN_GROUP(pwm1_b),2609 SH_PFC_PIN_GROUP(pwm1_c),2610 SH_PFC_PIN_GROUP(pwm2_a),2611 SH_PFC_PIN_GROUP(pwm2_b),2612 SH_PFC_PIN_GROUP(pwm2_c),2613 SH_PFC_PIN_GROUP(pwm3_a),2614 SH_PFC_PIN_GROUP(pwm3_b),2615 SH_PFC_PIN_GROUP(pwm3_c),2616 SH_PFC_PIN_GROUP(pwm4),2617 2618 SH_PFC_PIN_GROUP(qspi0_ctrl),2619 BUS_DATA_PIN_GROUP(qspi0_data, 2),2620 BUS_DATA_PIN_GROUP(qspi0_data, 4),2621 SH_PFC_PIN_GROUP(qspi1_ctrl),2622 BUS_DATA_PIN_GROUP(qspi1_data, 2),2623 BUS_DATA_PIN_GROUP(qspi1_data, 4),2624 2625 SH_PFC_PIN_GROUP(scif0_data),2626 SH_PFC_PIN_GROUP(scif0_clk),2627 SH_PFC_PIN_GROUP(scif0_ctrl),2628 SH_PFC_PIN_GROUP(scif1_data_a),2629 SH_PFC_PIN_GROUP(scif1_clk_a),2630 SH_PFC_PIN_GROUP(scif1_ctrl_a),2631 SH_PFC_PIN_GROUP(scif1_data_b),2632 SH_PFC_PIN_GROUP(scif1_clk_b),2633 SH_PFC_PIN_GROUP(scif1_ctrl_b),2634 SH_PFC_PIN_GROUP(scif3_data_a),2635 SH_PFC_PIN_GROUP(scif3_clk_a),2636 SH_PFC_PIN_GROUP(scif3_ctrl_a),2637 SH_PFC_PIN_GROUP(scif3_data_b),2638 SH_PFC_PIN_GROUP(scif3_clk_b),2639 SH_PFC_PIN_GROUP(scif3_ctrl_b),2640 SH_PFC_PIN_GROUP(scif4_data),2641 SH_PFC_PIN_GROUP(scif4_clk),2642 SH_PFC_PIN_GROUP(scif4_ctrl),2643 SH_PFC_PIN_GROUP(scif_clk),2644 SH_PFC_PIN_GROUP(scif_clk2),2645 2646 SH_PFC_PIN_GROUP(ssi_data),2647 SH_PFC_PIN_GROUP(ssi_ctrl),2648 2649 SH_PFC_PIN_GROUP(tpu_to0_a),2650 SH_PFC_PIN_GROUP(tpu_to0_b),2651 SH_PFC_PIN_GROUP(tpu_to1_a),2652 SH_PFC_PIN_GROUP(tpu_to1_b),2653 SH_PFC_PIN_GROUP(tpu_to2_a),2654 SH_PFC_PIN_GROUP(tpu_to2_b),2655 SH_PFC_PIN_GROUP(tpu_to3_a),2656 SH_PFC_PIN_GROUP(tpu_to3_b),2657};2658 2659static const char * const audio_clk_groups[] = {2660 "audio_clkin",2661 "audio_clkout",2662};2663 2664static const char * const avb0_groups[] = {2665 "avb0_link",2666 "avb0_magic",2667 "avb0_phy_int",2668 "avb0_mdio",2669 "avb0_mii",2670 "avb0_rgmii",2671 "avb0_txcrefclk",2672 "avb0_avtp_pps",2673 "avb0_avtp_capture",2674 "avb0_avtp_match",2675};2676 2677static const char * const avb1_groups[] = {2678 "avb1_link",2679 "avb1_magic",2680 "avb1_phy_int",2681 "avb1_mdio",2682 "avb1_mii",2683 "avb1_rgmii",2684 "avb1_txcrefclk",2685 "avb1_avtp_pps",2686 "avb1_avtp_capture",2687 "avb1_avtp_match",2688};2689 2690static const char * const avb2_groups[] = {2691 "avb2_link",2692 "avb2_magic",2693 "avb2_phy_int",2694 "avb2_mdio",2695 "avb2_rgmii",2696 "avb2_txcrefclk",2697 "avb2_avtp_pps",2698 "avb2_avtp_capture",2699 "avb2_avtp_match",2700};2701 2702static const char * const canfd0_groups[] = {2703 "canfd0_data",2704};2705 2706static const char * const canfd1_groups[] = {2707 "canfd1_data",2708};2709 2710static const char * const canfd2_groups[] = {2711 "canfd2_data",2712};2713 2714static const char * const canfd3_groups[] = {2715 "canfd3_data",2716};2717 2718static const char * const can_clk_groups[] = {2719 "can_clk",2720};2721 2722static const char * const hscif0_groups[] = {2723 "hscif0_data",2724 "hscif0_clk",2725 "hscif0_ctrl",2726};2727 2728static const char * const hscif1_groups[] = {2729 "hscif1_data_a",2730 "hscif1_clk_a",2731 "hscif1_ctrl_a",2732 "hscif1_data_b",2733 "hscif1_clk_b",2734 "hscif1_ctrl_b",2735};2736 2737static const char * const hscif2_groups[] = {2738 "hscif2_data",2739 "hscif2_clk",2740 "hscif2_ctrl",2741};2742 2743static const char * const hscif3_groups[] = {2744 "hscif3_data_a",2745 "hscif3_clk_a",2746 "hscif3_ctrl_a",2747 "hscif3_data_b",2748 "hscif3_clk_b",2749 "hscif3_ctrl_b",2750};2751 2752static const char * const i2c0_groups[] = {2753 "i2c0",2754};2755 2756static const char * const i2c1_groups[] = {2757 "i2c1",2758};2759 2760static const char * const i2c2_groups[] = {2761 "i2c2",2762};2763 2764static const char * const i2c3_groups[] = {2765 "i2c3",2766};2767 2768static const char * const intc_ex_groups[] = {2769 "intc_ex_irq0_a",2770 "intc_ex_irq0_b",2771 "intc_ex_irq1_a",2772 "intc_ex_irq1_b",2773 "intc_ex_irq2_a",2774 "intc_ex_irq2_b",2775 "intc_ex_irq3_a",2776 "intc_ex_irq3_b",2777 "intc_ex_irq4_a",2778 "intc_ex_irq4_b",2779 "intc_ex_irq5",2780};2781 2782static const char * const mmc_groups[] = {2783 "mmc_data1",2784 "mmc_data4",2785 "mmc_data8",2786 "mmc_ctrl",2787 "mmc_cd",2788 "mmc_wp",2789 "mmc_ds",2790};2791 2792static const char * const msiof0_groups[] = {2793 "msiof0_clk",2794 "msiof0_sync",2795 "msiof0_ss1",2796 "msiof0_ss2",2797 "msiof0_txd",2798 "msiof0_rxd",2799};2800 2801static const char * const msiof1_groups[] = {2802 "msiof1_clk",2803 "msiof1_sync",2804 "msiof1_ss1",2805 "msiof1_ss2",2806 "msiof1_txd",2807 "msiof1_rxd",2808};2809 2810static const char * const msiof2_groups[] = {2811 "msiof2_clk",2812 "msiof2_sync",2813 "msiof2_ss1",2814 "msiof2_ss2",2815 "msiof2_txd",2816 "msiof2_rxd",2817};2818 2819static const char * const msiof3_groups[] = {2820 "msiof3_clk",2821 "msiof3_sync",2822 "msiof3_ss1",2823 "msiof3_ss2",2824 "msiof3_txd",2825 "msiof3_rxd",2826};2827 2828static const char * const msiof4_groups[] = {2829 "msiof4_clk",2830 "msiof4_sync",2831 "msiof4_ss1",2832 "msiof4_ss2",2833 "msiof4_txd",2834 "msiof4_rxd",2835};2836 2837static const char * const msiof5_groups[] = {2838 "msiof5_clk",2839 "msiof5_sync",2840 "msiof5_ss1",2841 "msiof5_ss2",2842 "msiof5_txd",2843 "msiof5_rxd",2844};2845 2846static const char * const pcie_groups[] = {2847 "pcie0_clkreq_n",2848};2849 2850static const char * const pwm0_groups[] = {2851 "pwm0_a",2852 "pwm0_b",2853};2854 2855static const char * const pwm1_groups[] = {2856 "pwm1_a",2857 "pwm1_b",2858 "pwm1_c",2859};2860 2861static const char * const pwm2_groups[] = {2862 "pwm2_a",2863 "pwm2_b",2864 "pwm2_c",2865};2866 2867static const char * const pwm3_groups[] = {2868 "pwm3_a",2869 "pwm3_b",2870 "pwm3_c",2871};2872 2873static const char * const pwm4_groups[] = {2874 "pwm4",2875};2876 2877static const char * const qspi0_groups[] = {2878 "qspi0_ctrl",2879 "qspi0_data2",2880 "qspi0_data4",2881};2882 2883static const char * const qspi1_groups[] = {2884 "qspi1_ctrl",2885 "qspi1_data2",2886 "qspi1_data4",2887};2888 2889static const char * const scif0_groups[] = {2890 "scif0_data",2891 "scif0_clk",2892 "scif0_ctrl",2893};2894 2895static const char * const scif1_groups[] = {2896 "scif1_data_a",2897 "scif1_clk_a",2898 "scif1_ctrl_a",2899 "scif1_data_b",2900 "scif1_clk_b",2901 "scif1_ctrl_b",2902};2903 2904static const char * const scif3_groups[] = {2905 "scif3_data_a",2906 "scif3_clk_a",2907 "scif3_ctrl_a",2908 "scif3_data_b",2909 "scif3_clk_b",2910 "scif3_ctrl_b",2911};2912 2913static const char * const scif4_groups[] = {2914 "scif4_data",2915 "scif4_clk",2916 "scif4_ctrl",2917};2918 2919static const char * const scif_clk_groups[] = {2920 "scif_clk",2921};2922 2923static const char * const scif_clk2_groups[] = {2924 "scif_clk2",2925};2926 2927static const char * const ssi_groups[] = {2928 "ssi_data",2929 "ssi_ctrl",2930};2931 2932static const char * const tpu_groups[] = {2933 "tpu_to0_a",2934 "tpu_to0_b",2935 "tpu_to1_a",2936 "tpu_to1_b",2937 "tpu_to2_a",2938 "tpu_to2_b",2939 "tpu_to3_a",2940 "tpu_to3_b",2941};2942 2943static const struct sh_pfc_function pinmux_functions[] = {2944 SH_PFC_FUNCTION(audio_clk),2945 2946 SH_PFC_FUNCTION(avb0),2947 SH_PFC_FUNCTION(avb1),2948 SH_PFC_FUNCTION(avb2),2949 2950 SH_PFC_FUNCTION(canfd0),2951 SH_PFC_FUNCTION(canfd1),2952 SH_PFC_FUNCTION(canfd2),2953 SH_PFC_FUNCTION(canfd3),2954 SH_PFC_FUNCTION(can_clk),2955 2956 SH_PFC_FUNCTION(hscif0),2957 SH_PFC_FUNCTION(hscif1),2958 SH_PFC_FUNCTION(hscif2),2959 SH_PFC_FUNCTION(hscif3),2960 2961 SH_PFC_FUNCTION(i2c0),2962 SH_PFC_FUNCTION(i2c1),2963 SH_PFC_FUNCTION(i2c2),2964 SH_PFC_FUNCTION(i2c3),2965 2966 SH_PFC_FUNCTION(intc_ex),2967 2968 SH_PFC_FUNCTION(mmc),2969 2970 SH_PFC_FUNCTION(msiof0),2971 SH_PFC_FUNCTION(msiof1),2972 SH_PFC_FUNCTION(msiof2),2973 SH_PFC_FUNCTION(msiof3),2974 SH_PFC_FUNCTION(msiof4),2975 SH_PFC_FUNCTION(msiof5),2976 2977 SH_PFC_FUNCTION(pcie),2978 2979 SH_PFC_FUNCTION(pwm0),2980 SH_PFC_FUNCTION(pwm1),2981 SH_PFC_FUNCTION(pwm2),2982 SH_PFC_FUNCTION(pwm3),2983 SH_PFC_FUNCTION(pwm4),2984 2985 SH_PFC_FUNCTION(qspi0),2986 SH_PFC_FUNCTION(qspi1),2987 2988 SH_PFC_FUNCTION(scif0),2989 SH_PFC_FUNCTION(scif1),2990 SH_PFC_FUNCTION(scif3),2991 SH_PFC_FUNCTION(scif4),2992 SH_PFC_FUNCTION(scif_clk),2993 SH_PFC_FUNCTION(scif_clk2),2994 2995 SH_PFC_FUNCTION(ssi),2996 2997 SH_PFC_FUNCTION(tpu),2998};2999 3000static const struct pinmux_cfg_reg pinmux_config_regs[] = {3001#define F_(x, y) FN_##y3002#define FM(x) FN_##x3003 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,3004 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,3005 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3006 GROUP(3007 /* GP0_31_19 RESERVED */3008 GP_0_18_FN, GPSR0_18,3009 GP_0_17_FN, GPSR0_17,3010 GP_0_16_FN, GPSR0_16,3011 GP_0_15_FN, GPSR0_15,3012 GP_0_14_FN, GPSR0_14,3013 GP_0_13_FN, GPSR0_13,3014 GP_0_12_FN, GPSR0_12,3015 GP_0_11_FN, GPSR0_11,3016 GP_0_10_FN, GPSR0_10,3017 GP_0_9_FN, GPSR0_9,3018 GP_0_8_FN, GPSR0_8,3019 GP_0_7_FN, GPSR0_7,3020 GP_0_6_FN, GPSR0_6,3021 GP_0_5_FN, GPSR0_5,3022 GP_0_4_FN, GPSR0_4,3023 GP_0_3_FN, GPSR0_3,3024 GP_0_2_FN, GPSR0_2,3025 GP_0_1_FN, GPSR0_1,3026 GP_0_0_FN, GPSR0_0, ))3027 },3028 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(3029 0, 0,3030 0, 0,3031 GP_1_29_FN, GPSR1_29,3032 GP_1_28_FN, GPSR1_28,3033 GP_1_27_FN, GPSR1_27,3034 GP_1_26_FN, GPSR1_26,3035 GP_1_25_FN, GPSR1_25,3036 GP_1_24_FN, GPSR1_24,3037 GP_1_23_FN, GPSR1_23,3038 GP_1_22_FN, GPSR1_22,3039 GP_1_21_FN, GPSR1_21,3040 GP_1_20_FN, GPSR1_20,3041 GP_1_19_FN, GPSR1_19,3042 GP_1_18_FN, GPSR1_18,3043 GP_1_17_FN, GPSR1_17,3044 GP_1_16_FN, GPSR1_16,3045 GP_1_15_FN, GPSR1_15,3046 GP_1_14_FN, GPSR1_14,3047 GP_1_13_FN, GPSR1_13,3048 GP_1_12_FN, GPSR1_12,3049 GP_1_11_FN, GPSR1_11,3050 GP_1_10_FN, GPSR1_10,3051 GP_1_9_FN, GPSR1_9,3052 GP_1_8_FN, GPSR1_8,3053 GP_1_7_FN, GPSR1_7,3054 GP_1_6_FN, GPSR1_6,3055 GP_1_5_FN, GPSR1_5,3056 GP_1_4_FN, GPSR1_4,3057 GP_1_3_FN, GPSR1_3,3058 GP_1_2_FN, GPSR1_2,3059 GP_1_1_FN, GPSR1_1,3060 GP_1_0_FN, GPSR1_0, ))3061 },3062 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,3063 GROUP(-12, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1,3064 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3065 GROUP(3066 /* GP2_31_20 RESERVED */3067 GP_2_19_FN, GPSR2_19,3068 /* GP2_18 RESERVED */3069 GP_2_17_FN, GPSR2_17,3070 /* GP2_16 RESERVED */3071 GP_2_15_FN, GPSR2_15,3072 GP_2_14_FN, GPSR2_14,3073 GP_2_13_FN, GPSR2_13,3074 GP_2_12_FN, GPSR2_12,3075 GP_2_11_FN, GPSR2_11,3076 GP_2_10_FN, GPSR2_10,3077 GP_2_9_FN, GPSR2_9,3078 GP_2_8_FN, GPSR2_8,3079 GP_2_7_FN, GPSR2_7,3080 GP_2_6_FN, GPSR2_6,3081 GP_2_5_FN, GPSR2_5,3082 GP_2_4_FN, GPSR2_4,3083 GP_2_3_FN, GPSR2_3,3084 GP_2_2_FN, GPSR2_2,3085 GP_2_1_FN, GPSR2_1,3086 GP_2_0_FN, GPSR2_0, ))3087 },3088 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(3089 GP_3_31_FN, GPSR3_31,3090 GP_3_30_FN, GPSR3_30,3091 GP_3_29_FN, GPSR3_29,3092 GP_3_28_FN, GPSR3_28,3093 GP_3_27_FN, GPSR3_27,3094 GP_3_26_FN, GPSR3_26,3095 GP_3_25_FN, GPSR3_25,3096 GP_3_24_FN, GPSR3_24,3097 GP_3_23_FN, GPSR3_23,3098 GP_3_22_FN, GPSR3_22,3099 GP_3_21_FN, GPSR3_21,3100 GP_3_20_FN, GPSR3_20,3101 GP_3_19_FN, GPSR3_19,3102 GP_3_18_FN, GPSR3_18,3103 GP_3_17_FN, GPSR3_17,3104 GP_3_16_FN, GPSR3_16,3105 GP_3_15_FN, GPSR3_15,3106 GP_3_14_FN, GPSR3_14,3107 GP_3_13_FN, GPSR3_13,3108 GP_3_12_FN, GPSR3_12,3109 GP_3_11_FN, GPSR3_11,3110 GP_3_10_FN, GPSR3_10,3111 GP_3_9_FN, GPSR3_9,3112 GP_3_8_FN, GPSR3_8,3113 GP_3_7_FN, GPSR3_7,3114 GP_3_6_FN, GPSR3_6,3115 GP_3_5_FN, GPSR3_5,3116 GP_3_4_FN, GPSR3_4,3117 GP_3_3_FN, GPSR3_3,3118 GP_3_2_FN, GPSR3_2,3119 GP_3_1_FN, GPSR3_1,3120 GP_3_0_FN, GPSR3_0, ))3121 },3122 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060040, 32,3123 GROUP(-7, 1, 1, -1, 1, -5, 1, 1, 1, 1, 1,3124 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3125 GROUP(3126 /* GP4_31_25 RESERVED */3127 GP_4_24_FN, GPSR4_24,3128 GP_4_23_FN, GPSR4_23,3129 /* GP4_22 RESERVED */3130 GP_4_21_FN, GPSR4_21,3131 /* GP4_20_16 RESERVED */3132 GP_4_15_FN, GPSR4_15,3133 GP_4_14_FN, GPSR4_14,3134 GP_4_13_FN, GPSR4_13,3135 GP_4_12_FN, GPSR4_12,3136 GP_4_11_FN, GPSR4_11,3137 GP_4_10_FN, GPSR4_10,3138 GP_4_9_FN, GPSR4_9,3139 GP_4_8_FN, GPSR4_8,3140 GP_4_7_FN, GPSR4_7,3141 GP_4_6_FN, GPSR4_6,3142 GP_4_5_FN, GPSR4_5,3143 GP_4_4_FN, GPSR4_4,3144 GP_4_3_FN, GPSR4_3,3145 GP_4_2_FN, GPSR4_2,3146 GP_4_1_FN, GPSR4_1,3147 GP_4_0_FN, GPSR4_0, ))3148 },3149 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,3150 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,3151 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3152 GROUP(3153 /* GP5_31_21 RESERVED */3154 GP_5_20_FN, GPSR5_20,3155 GP_5_19_FN, GPSR5_19,3156 GP_5_18_FN, GPSR5_18,3157 GP_5_17_FN, GPSR5_17,3158 GP_5_16_FN, GPSR5_16,3159 GP_5_15_FN, GPSR5_15,3160 GP_5_14_FN, GPSR5_14,3161 GP_5_13_FN, GPSR5_13,3162 GP_5_12_FN, GPSR5_12,3163 GP_5_11_FN, GPSR5_11,3164 GP_5_10_FN, GPSR5_10,3165 GP_5_9_FN, GPSR5_9,3166 GP_5_8_FN, GPSR5_8,3167 GP_5_7_FN, GPSR5_7,3168 GP_5_6_FN, GPSR5_6,3169 GP_5_5_FN, GPSR5_5,3170 GP_5_4_FN, GPSR5_4,3171 GP_5_3_FN, GPSR5_3,3172 GP_5_2_FN, GPSR5_2,3173 GP_5_1_FN, GPSR5_1,3174 GP_5_0_FN, GPSR5_0, ))3175 },3176 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,3177 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,3178 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3179 GROUP(3180 /* GP6_31_21 RESERVED */3181 GP_6_20_FN, GPSR6_20,3182 GP_6_19_FN, GPSR6_19,3183 GP_6_18_FN, GPSR6_18,3184 GP_6_17_FN, GPSR6_17,3185 GP_6_16_FN, GPSR6_16,3186 GP_6_15_FN, GPSR6_15,3187 GP_6_14_FN, GPSR6_14,3188 GP_6_13_FN, GPSR6_13,3189 GP_6_12_FN, GPSR6_12,3190 GP_6_11_FN, GPSR6_11,3191 GP_6_10_FN, GPSR6_10,3192 GP_6_9_FN, GPSR6_9,3193 GP_6_8_FN, GPSR6_8,3194 GP_6_7_FN, GPSR6_7,3195 GP_6_6_FN, GPSR6_6,3196 GP_6_5_FN, GPSR6_5,3197 GP_6_4_FN, GPSR6_4,3198 GP_6_3_FN, GPSR6_3,3199 GP_6_2_FN, GPSR6_2,3200 GP_6_1_FN, GPSR6_1,3201 GP_6_0_FN, GPSR6_0, ))3202 },3203 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,3204 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,3205 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),3206 GROUP(3207 /* GP7_31_21 RESERVED */3208 GP_7_20_FN, GPSR7_20,3209 GP_7_19_FN, GPSR7_19,3210 GP_7_18_FN, GPSR7_18,3211 GP_7_17_FN, GPSR7_17,3212 GP_7_16_FN, GPSR7_16,3213 GP_7_15_FN, GPSR7_15,3214 GP_7_14_FN, GPSR7_14,3215 GP_7_13_FN, GPSR7_13,3216 GP_7_12_FN, GPSR7_12,3217 GP_7_11_FN, GPSR7_11,3218 GP_7_10_FN, GPSR7_10,3219 GP_7_9_FN, GPSR7_9,3220 GP_7_8_FN, GPSR7_8,3221 GP_7_7_FN, GPSR7_7,3222 GP_7_6_FN, GPSR7_6,3223 GP_7_5_FN, GPSR7_5,3224 GP_7_4_FN, GPSR7_4,3225 GP_7_3_FN, GPSR7_3,3226 GP_7_2_FN, GPSR7_2,3227 GP_7_1_FN, GPSR7_1,3228 GP_7_0_FN, GPSR7_0, ))3229 },3230#undef F_3231#undef FM3232 3233#define F_(x, y) x,3234#define FM(x) FN_##x,3235 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(3236 IP0SR0_31_283237 IP0SR0_27_243238 IP0SR0_23_203239 IP0SR0_19_163240 IP0SR0_15_123241 IP0SR0_11_83242 IP0SR0_7_43243 IP0SR0_3_0))3244 },3245 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(3246 IP1SR0_31_283247 IP1SR0_27_243248 IP1SR0_23_203249 IP1SR0_19_163250 IP1SR0_15_123251 IP1SR0_11_83252 IP1SR0_7_43253 IP1SR0_3_0))3254 },3255 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,3256 GROUP(-20, 4, 4, 4),3257 GROUP(3258 /* IP2SR0_31_12 RESERVED */3259 IP2SR0_11_83260 IP2SR0_7_43261 IP2SR0_3_0))3262 },3263 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(3264 IP0SR1_31_283265 IP0SR1_27_243266 IP0SR1_23_203267 IP0SR1_19_163268 IP0SR1_15_123269 IP0SR1_11_83270 IP0SR1_7_43271 IP0SR1_3_0))3272 },3273 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(3274 IP1SR1_31_283275 IP1SR1_27_243276 IP1SR1_23_203277 IP1SR1_19_163278 IP1SR1_15_123279 IP1SR1_11_83280 IP1SR1_7_43281 IP1SR1_3_0))3282 },3283 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(3284 IP2SR1_31_283285 IP2SR1_27_243286 IP2SR1_23_203287 IP2SR1_19_163288 IP2SR1_15_123289 IP2SR1_11_83290 IP2SR1_7_43291 IP2SR1_3_0))3292 },3293 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,3294 GROUP(-8, 4, 4, 4, 4, 4, 4),3295 GROUP(3296 /* IP3SR1_31_24 RESERVED */3297 IP3SR1_23_203298 IP3SR1_19_163299 IP3SR1_15_123300 IP3SR1_11_83301 IP3SR1_7_43302 IP3SR1_3_0))3303 },3304 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(3305 IP0SR2_31_283306 IP0SR2_27_243307 IP0SR2_23_203308 IP0SR2_19_163309 IP0SR2_15_123310 IP0SR2_11_83311 IP0SR2_7_43312 IP0SR2_3_0))3313 },3314 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(3315 IP1SR2_31_283316 IP1SR2_27_243317 IP1SR2_23_203318 IP1SR2_19_163319 IP1SR2_15_123320 IP1SR2_11_83321 IP1SR2_7_43322 IP1SR2_3_0))3323 },3324 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,3325 GROUP(-16, 4, -4, 4, -4),3326 GROUP(3327 /* IP2SR2_31_16 RESERVED */3328 IP2SR2_15_123329 /* IP2SR2_11_8 RESERVED */3330 IP2SR2_7_43331 /* IP2SR2_3_0 RESERVED */))3332 },3333 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(3334 IP0SR3_31_283335 IP0SR3_27_243336 IP0SR3_23_203337 IP0SR3_19_163338 IP0SR3_15_123339 IP0SR3_11_83340 IP0SR3_7_43341 IP0SR3_3_0))3342 },3343 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(3344 IP1SR3_31_283345 IP1SR3_27_243346 IP1SR3_23_203347 IP1SR3_19_163348 IP1SR3_15_123349 IP1SR3_11_83350 IP1SR3_7_43351 IP1SR3_3_0))3352 },3353 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(3354 IP2SR3_31_283355 IP2SR3_27_243356 IP2SR3_23_203357 IP2SR3_19_163358 IP2SR3_15_123359 IP2SR3_11_83360 IP2SR3_7_43361 IP2SR3_3_0))3362 },3363 { PINMUX_CFG_REG("IP3SR3", 0xE605886C, 32, 4, GROUP(3364 IP3SR3_31_283365 IP3SR3_27_243366 IP3SR3_23_203367 IP3SR3_19_163368 IP3SR3_15_123369 IP3SR3_11_83370 IP3SR3_7_43371 IP3SR3_3_0))3372 },3373 { PINMUX_CFG_REG("IP0SR4", 0xE6060060, 32, 4, GROUP(3374 IP0SR4_31_283375 IP0SR4_27_243376 IP0SR4_23_203377 IP0SR4_19_163378 IP0SR4_15_123379 IP0SR4_11_83380 IP0SR4_7_43381 IP0SR4_3_0))3382 },3383 { PINMUX_CFG_REG("IP1SR4", 0xE6060064, 32, 4, GROUP(3384 IP1SR4_31_283385 IP1SR4_27_243386 IP1SR4_23_203387 IP1SR4_19_163388 IP1SR4_15_123389 IP1SR4_11_83390 IP1SR4_7_43391 IP1SR4_3_0))3392 },3393 { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,3394 GROUP(4, -4, 4, -20),3395 GROUP(3396 IP2SR4_31_283397 /* IP2SR4_27_24 RESERVED */3398 IP2SR4_23_203399 /* IP2SR4_19_0 RESERVED */))3400 },3401 { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,3402 GROUP(-28, 4),3403 GROUP(3404 /* IP3SR4_31_4 RESERVED */3405 IP3SR4_3_0))3406 },3407 { PINMUX_CFG_REG("IP0SR5", 0xE6060860, 32, 4, GROUP(3408 IP0SR5_31_283409 IP0SR5_27_243410 IP0SR5_23_203411 IP0SR5_19_163412 IP0SR5_15_123413 IP0SR5_11_83414 IP0SR5_7_43415 IP0SR5_3_0))3416 },3417 { PINMUX_CFG_REG("IP1SR5", 0xE6060864, 32, 4, GROUP(3418 IP1SR5_31_283419 IP1SR5_27_243420 IP1SR5_23_203421 IP1SR5_19_163422 IP1SR5_15_123423 IP1SR5_11_83424 IP1SR5_7_43425 IP1SR5_3_0))3426 },3427 { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,3428 GROUP(-12, 4, 4, 4, 4, 4),3429 GROUP(3430 /* IP2SR5_31_20 RESERVED */3431 IP2SR5_19_163432 IP2SR5_15_123433 IP2SR5_11_83434 IP2SR5_7_43435 IP2SR5_3_0))3436 },3437 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(3438 IP0SR6_31_283439 IP0SR6_27_243440 IP0SR6_23_203441 IP0SR6_19_163442 IP0SR6_15_123443 IP0SR6_11_83444 IP0SR6_7_43445 IP0SR6_3_0))3446 },3447 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(3448 IP1SR6_31_283449 IP1SR6_27_243450 IP1SR6_23_203451 IP1SR6_19_163452 IP1SR6_15_123453 IP1SR6_11_83454 IP1SR6_7_43455 IP1SR6_3_0))3456 },3457 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,3458 GROUP(-12, 4, 4, 4, 4, 4),3459 GROUP(3460 /* IP2SR6_31_20 RESERVED */3461 IP2SR6_19_163462 IP2SR6_15_123463 IP2SR6_11_83464 IP2SR6_7_43465 IP2SR6_3_0))3466 },3467 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(3468 IP0SR7_31_283469 IP0SR7_27_243470 IP0SR7_23_203471 IP0SR7_19_163472 IP0SR7_15_123473 IP0SR7_11_83474 IP0SR7_7_43475 IP0SR7_3_0))3476 },3477 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(3478 IP1SR7_31_283479 IP1SR7_27_243480 IP1SR7_23_203481 IP1SR7_19_163482 IP1SR7_15_123483 IP1SR7_11_83484 IP1SR7_7_43485 IP1SR7_3_0))3486 },3487 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,3488 GROUP(-12, 4, 4, 4, 4, 4),3489 GROUP(3490 /* IP2SR7_31_20 RESERVED */3491 IP2SR7_19_163492 IP2SR7_15_123493 IP2SR7_11_83494 IP2SR7_7_43495 IP2SR7_3_0))3496 },3497#undef F_3498#undef FM3499 3500#define F_(x, y) x,3501#define FM(x) FN_##x,3502 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32,3503 GROUP(-24, 1, 1, 1, 1, 1, 1, 1, 1),3504 GROUP(3505 /* RESERVED 31-8 */3506 MOD_SEL4_73507 MOD_SEL4_63508 MOD_SEL4_53509 MOD_SEL4_43510 MOD_SEL4_33511 MOD_SEL4_23512 MOD_SEL4_13513 MOD_SEL4_0))3514 },3515 { },3516};3517 3518static const struct pinmux_drive_reg pinmux_drive_regs[] = {3519 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {3520 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */3521 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */3522 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */3523 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */3524 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */3525 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */3526 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */3527 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */3528 } },3529 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {3530 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */3531 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */3532 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */3533 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */3534 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */3535 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */3536 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */3537 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */3538 } },3539 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {3540 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */3541 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */3542 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */3543 } },3544 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {3545 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */3546 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */3547 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */3548 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */3549 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */3550 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */3551 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */3552 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */3553 } },3554 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {3555 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */3556 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */3557 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */3558 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */3559 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */3560 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */3561 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */3562 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */3563 } },3564 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {3565 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */3566 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */3567 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */3568 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */3569 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */3570 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */3571 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */3572 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */3573 } },3574 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {3575 { RCAR_GP_PIN(1, 29), 20, 2 }, /* ERROROUTC_N */3576 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */3577 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */3578 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */3579 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */3580 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */3581 } },3582 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {3583 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */3584 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */3585 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */3586 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */3587 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */3588 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */3589 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */3590 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */3591 } },3592 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {3593 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */3594 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */3595 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */3596 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */3597 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */3598 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */3599 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */3600 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */3601 } },3602 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {3603 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD1_RX */3604 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD1_TX */3605 } },3606 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {3607 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */3608 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */3609 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */3610 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */3611 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */3612 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */3613 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */3614 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */3615 } },3616 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {3617 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */3618 { RCAR_GP_PIN(3, 14), 24, 2 }, /* PWM2 */3619 { RCAR_GP_PIN(3, 13), 20, 2 }, /* PWM1 */3620 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */3621 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */3622 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */3623 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/3624 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */3625 } },3626 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {3627 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */3628 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */3629 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */3630 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */3631 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */3632 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */3633 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */3634 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */3635 } },3636 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {3637 { RCAR_GP_PIN(3, 31), 28, 2 }, /* TCLK4 */3638 { RCAR_GP_PIN(3, 30), 24, 2 }, /* TCLK3 */3639 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */3640 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */3641 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */3642 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */3643 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */3644 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */3645 } },3646 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {3647 { RCAR_GP_PIN(4, 7), 28, 3 }, /* SDA3 */3648 { RCAR_GP_PIN(4, 6), 24, 3 }, /* SCL3 */3649 { RCAR_GP_PIN(4, 5), 20, 3 }, /* SDA2 */3650 { RCAR_GP_PIN(4, 4), 16, 3 }, /* SCL2 */3651 { RCAR_GP_PIN(4, 3), 12, 3 }, /* SDA1 */3652 { RCAR_GP_PIN(4, 2), 8, 3 }, /* SCL1 */3653 { RCAR_GP_PIN(4, 1), 4, 3 }, /* SDA0 */3654 { RCAR_GP_PIN(4, 0), 0, 3 }, /* SCL0 */3655 } },3656 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {3657 { RCAR_GP_PIN(4, 15), 28, 3 }, /* PWM4 */3658 { RCAR_GP_PIN(4, 14), 24, 3 }, /* PWM3 */3659 { RCAR_GP_PIN(4, 13), 20, 3 }, /* HSCK2 */3660 { RCAR_GP_PIN(4, 12), 16, 3 }, /* HCTS2_N */3661 { RCAR_GP_PIN(4, 11), 12, 3 }, /* SCIF_CLK2 */3662 { RCAR_GP_PIN(4, 10), 8, 3 }, /* HRTS2_N */3663 { RCAR_GP_PIN(4, 9), 4, 3 }, /* HTX2 */3664 { RCAR_GP_PIN(4, 8), 0, 3 }, /* HRX2 */3665 } },3666 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {3667 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */3668 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */3669 } },3670 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {3671 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */3672 } },3673 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {3674 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */3675 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */3676 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */3677 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */3678 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */3679 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */3680 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */3681 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */3682 } },3683 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {3684 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */3685 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */3686 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */3687 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */3688 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */3689 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */3690 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */3691 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */3692 } },3693 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {3694 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */3695 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */3696 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */3697 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */3698 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */3699 } },3700 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {3701 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */3702 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */3703 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */3704 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */3705 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */3706 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */3707 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */3708 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */3709 } },3710 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {3711 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */3712 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */3713 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */3714 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */3715 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */3716 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */3717 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */3718 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */3719 } },3720 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {3721 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */3722 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */3723 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */3724 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */3725 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */3726 } },3727 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {3728 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */3729 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */3730 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */3731 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */3732 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */3733 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */3734 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */3735 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */3736 } },3737 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {3738 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */3739 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */3740 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */3741 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */3742 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */3743 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */3744 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */3745 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */3746 } },3747 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {3748 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */3749 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */3750 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */3751 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */3752 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */3753 } },3754 { },3755};3756 3757enum ioctrl_regs {3758 POC0,3759 POC1,3760 POC3,3761 POC4,3762 POC5,3763 POC6,3764 POC7,3765};3766 3767static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {3768 [POC0] = { 0xE60500A0, },3769 [POC1] = { 0xE60508A0, },3770 [POC3] = { 0xE60588A0, },3771 [POC4] = { 0xE60600A0, },3772 [POC5] = { 0xE60608A0, },3773 [POC6] = { 0xE60610A0, },3774 [POC7] = { 0xE60618A0, },3775 { /* sentinel */ },3776};3777 3778static int r8a779h0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)3779{3780 int bit = pin & 0x1f;3781 3782 switch (pin) {3783 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):3784 *pocctrl = pinmux_ioctrl_regs[POC0].reg;3785 return bit;3786 3787 case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 28):3788 *pocctrl = pinmux_ioctrl_regs[POC1].reg;3789 return bit;3790 3791 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):3792 *pocctrl = pinmux_ioctrl_regs[POC3].reg;3793 return bit;3794 3795 case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 13):3796 *pocctrl = pinmux_ioctrl_regs[POC4].reg;3797 return bit;3798 3799 case PIN_VDDQ_AVB2:3800 *pocctrl = pinmux_ioctrl_regs[POC5].reg;3801 return 0;3802 3803 case PIN_VDDQ_AVB1:3804 *pocctrl = pinmux_ioctrl_regs[POC6].reg;3805 return 0;3806 3807 case PIN_VDDQ_AVB0:3808 *pocctrl = pinmux_ioctrl_regs[POC7].reg;3809 return 0;3810 3811 default:3812 return -EINVAL;3813 }3814}3815 3816static const struct pinmux_bias_reg pinmux_bias_regs[] = {3817 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {3818 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */3819 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */3820 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */3821 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */3822 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */3823 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */3824 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */3825 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */3826 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */3827 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */3828 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */3829 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */3830 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */3831 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */3832 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */3833 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */3834 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */3835 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */3836 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */3837 [19] = SH_PFC_PIN_NONE,3838 [20] = SH_PFC_PIN_NONE,3839 [21] = SH_PFC_PIN_NONE,3840 [22] = SH_PFC_PIN_NONE,3841 [23] = SH_PFC_PIN_NONE,3842 [24] = SH_PFC_PIN_NONE,3843 [25] = SH_PFC_PIN_NONE,3844 [26] = SH_PFC_PIN_NONE,3845 [27] = SH_PFC_PIN_NONE,3846 [28] = SH_PFC_PIN_NONE,3847 [29] = SH_PFC_PIN_NONE,3848 [30] = SH_PFC_PIN_NONE,3849 [31] = SH_PFC_PIN_NONE,3850 } },3851 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {3852 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */3853 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */3854 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */3855 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */3856 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */3857 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */3858 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */3859 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */3860 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */3861 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */3862 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */3863 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */3864 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */3865 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */3866 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */3867 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */3868 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */3869 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */3870 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */3871 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */3872 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */3873 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */3874 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */3875 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */3876 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */3877 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */3878 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */3879 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */3880 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */3881 [29] = RCAR_GP_PIN(1, 29), /* ERROROUTC_N */3882 [30] = SH_PFC_PIN_NONE,3883 [31] = SH_PFC_PIN_NONE,3884 } },3885 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {3886 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */3887 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */3888 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */3889 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */3890 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */3891 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */3892 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */3893 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */3894 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */3895 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */3896 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */3897 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */3898 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */3899 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */3900 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */3901 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */3902 [16] = SH_PFC_PIN_NONE,3903 [17] = RCAR_GP_PIN(2, 17), /* CANFD1_TX */3904 [18] = SH_PFC_PIN_NONE,3905 [19] = RCAR_GP_PIN(2, 19), /* CANFD1_RX */3906 [20] = SH_PFC_PIN_NONE,3907 [21] = SH_PFC_PIN_NONE,3908 [22] = SH_PFC_PIN_NONE,3909 [23] = SH_PFC_PIN_NONE,3910 [24] = SH_PFC_PIN_NONE,3911 [25] = SH_PFC_PIN_NONE,3912 [26] = SH_PFC_PIN_NONE,3913 [27] = SH_PFC_PIN_NONE,3914 [28] = SH_PFC_PIN_NONE,3915 [29] = SH_PFC_PIN_NONE,3916 [30] = SH_PFC_PIN_NONE,3917 [31] = SH_PFC_PIN_NONE,3918 } },3919 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {3920 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */3921 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */3922 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */3923 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */3924 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */3925 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */3926 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */3927 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */3928 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */3929 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */3930 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */3931 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */3932 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */3933 [13] = RCAR_GP_PIN(3, 13), /* PWM1 */3934 [14] = RCAR_GP_PIN(3, 14), /* PWM2 */3935 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */3936 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */3937 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */3938 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */3939 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */3940 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */3941 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */3942 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */3943 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */3944 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */3945 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */3946 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */3947 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */3948 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */3949 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */3950 [30] = RCAR_GP_PIN(3, 30), /* TCLK3 */3951 [31] = RCAR_GP_PIN(3, 31), /* TCLK4 */3952 } },3953 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {3954 [ 0] = RCAR_GP_PIN(4, 0), /* SCL0 */3955 [ 1] = RCAR_GP_PIN(4, 1), /* SDA0 */3956 [ 2] = RCAR_GP_PIN(4, 2), /* SCL1 */3957 [ 3] = RCAR_GP_PIN(4, 3), /* SDA1 */3958 [ 4] = RCAR_GP_PIN(4, 4), /* SCL2 */3959 [ 5] = RCAR_GP_PIN(4, 5), /* SDA2 */3960 [ 6] = RCAR_GP_PIN(4, 6), /* SCL3 */3961 [ 7] = RCAR_GP_PIN(4, 7), /* SDA3 */3962 [ 8] = RCAR_GP_PIN(4, 8), /* HRX2 */3963 [ 9] = RCAR_GP_PIN(4, 9), /* HTX2 */3964 [10] = RCAR_GP_PIN(4, 10), /* HRTS2_N */3965 [11] = RCAR_GP_PIN(4, 11), /* SCIF_CLK2 */3966 [12] = RCAR_GP_PIN(4, 12), /* HCTS2_N */3967 [13] = RCAR_GP_PIN(4, 13), /* HSCK2 */3968 [14] = RCAR_GP_PIN(4, 14), /* PWM3 */3969 [15] = RCAR_GP_PIN(4, 15), /* PWM4 */3970 [16] = SH_PFC_PIN_NONE,3971 [17] = SH_PFC_PIN_NONE,3972 [18] = SH_PFC_PIN_NONE,3973 [19] = SH_PFC_PIN_NONE,3974 [20] = SH_PFC_PIN_NONE,3975 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */3976 [22] = SH_PFC_PIN_NONE,3977 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */3978 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */3979 [25] = SH_PFC_PIN_NONE,3980 [26] = SH_PFC_PIN_NONE,3981 [27] = SH_PFC_PIN_NONE,3982 [28] = SH_PFC_PIN_NONE,3983 [29] = SH_PFC_PIN_NONE,3984 [30] = SH_PFC_PIN_NONE,3985 [31] = SH_PFC_PIN_NONE,3986 } },3987 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {3988 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */3989 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */3990 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */3991 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */3992 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */3993 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */3994 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */3995 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */3996 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */3997 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */3998 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */3999 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */4000 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */4001 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */4002 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */4003 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */4004 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */4005 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */4006 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */4007 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */4008 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */4009 [21] = SH_PFC_PIN_NONE,4010 [22] = SH_PFC_PIN_NONE,4011 [23] = SH_PFC_PIN_NONE,4012 [24] = SH_PFC_PIN_NONE,4013 [25] = SH_PFC_PIN_NONE,4014 [26] = SH_PFC_PIN_NONE,4015 [27] = SH_PFC_PIN_NONE,4016 [28] = SH_PFC_PIN_NONE,4017 [29] = SH_PFC_PIN_NONE,4018 [30] = SH_PFC_PIN_NONE,4019 [31] = SH_PFC_PIN_NONE,4020 } },4021 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {4022 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */4023 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */4024 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */4025 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */4026 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */4027 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */4028 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */4029 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */4030 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */4031 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */4032 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */4033 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */4034 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */4035 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */4036 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/4037 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */4038 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */4039 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */4040 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */4041 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */4042 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */4043 [21] = SH_PFC_PIN_NONE,4044 [22] = SH_PFC_PIN_NONE,4045 [23] = SH_PFC_PIN_NONE,4046 [24] = SH_PFC_PIN_NONE,4047 [25] = SH_PFC_PIN_NONE,4048 [26] = SH_PFC_PIN_NONE,4049 [27] = SH_PFC_PIN_NONE,4050 [28] = SH_PFC_PIN_NONE,4051 [29] = SH_PFC_PIN_NONE,4052 [30] = SH_PFC_PIN_NONE,4053 [31] = SH_PFC_PIN_NONE,4054 } },4055 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {4056 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */4057 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */4058 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */4059 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */4060 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */4061 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */4062 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */4063 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */4064 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */4065 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */4066 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */4067 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */4068 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */4069 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */4070 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */4071 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */4072 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */4073 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */4074 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */4075 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */4076 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */4077 [21] = SH_PFC_PIN_NONE,4078 [22] = SH_PFC_PIN_NONE,4079 [23] = SH_PFC_PIN_NONE,4080 [24] = SH_PFC_PIN_NONE,4081 [25] = SH_PFC_PIN_NONE,4082 [26] = SH_PFC_PIN_NONE,4083 [27] = SH_PFC_PIN_NONE,4084 [28] = SH_PFC_PIN_NONE,4085 [29] = SH_PFC_PIN_NONE,4086 [30] = SH_PFC_PIN_NONE,4087 [31] = SH_PFC_PIN_NONE,4088 } },4089 { /* sentinel */ },4090};4091 4092static const struct sh_pfc_soc_operations r8a779h0_pin_ops = {4093 .pin_to_pocctrl = r8a779h0_pin_to_pocctrl,4094 .get_bias = rcar_pinmux_get_bias,4095 .set_bias = rcar_pinmux_set_bias,4096};4097 4098const struct sh_pfc_soc_info r8a779h0_pinmux_info = {4099 .name = "r8a779h0_pfc",4100 .ops = &r8a779h0_pin_ops,4101 .unlock_reg = 0x1ff, /* PMMRn mask */4102 4103 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },4104 4105 .pins = pinmux_pins,4106 .nr_pins = ARRAY_SIZE(pinmux_pins),4107 .groups = pinmux_groups,4108 .nr_groups = ARRAY_SIZE(pinmux_groups),4109 .functions = pinmux_functions,4110 .nr_functions = ARRAY_SIZE(pinmux_functions),4111 4112 .cfg_regs = pinmux_config_regs,4113 .drive_regs = pinmux_drive_regs,4114 .bias_regs = pinmux_bias_regs,4115 .ioctrl_regs = pinmux_ioctrl_regs,4116 4117 .pinmux_data = pinmux_data,4118 .pinmux_data_size = ARRAY_SIZE(pinmux_data),4119};4120