1403 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC4 *5 * Copyright (C) 2017 Jacopo Mondi6 */7 8/*9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A110 * family.11 * This includes SoCs which are sub- or super- sets of this particular line,12 * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).13 */14 15#include <linux/bitops.h>16#include <linux/err.h>17#include <linux/gpio/driver.h>18#include <linux/init.h>19#include <linux/ioport.h>20#include <linux/module.h>21#include <linux/of.h>22#include <linux/pinctrl/pinconf-generic.h>23#include <linux/pinctrl/pinctrl.h>24#include <linux/pinctrl/pinmux.h>25#include <linux/platform_device.h>26#include <linux/property.h>27#include <linux/slab.h>28 29#include "../core.h"30#include "../devicetree.h"31#include "../pinconf.h"32#include "../pinmux.h"33 34#define DRIVER_NAME "pinctrl-rza1"35 36#define RZA1_P_REG 0x000037#define RZA1_PPR_REG 0x020038#define RZA1_PM_REG 0x030039#define RZA1_PMC_REG 0x040040#define RZA1_PFC_REG 0x050041#define RZA1_PFCE_REG 0x060042#define RZA1_PFCEA_REG 0x0a0043#define RZA1_PIBC_REG 0x400044#define RZA1_PBDC_REG 0x410045#define RZA1_PIPC_REG 0x420046 47#define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4))48 49#define RZA1_NPORTS 1250#define RZA1_PINS_PER_PORT 1651#define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS)52#define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT)53#define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT)54 55/*56 * Use 16 lower bits [15:0] for pin identifier57 * Use 16 higher bits [31:16] for pin mux function58 */59#define MUX_PIN_ID_MASK GENMASK(15, 0)60#define MUX_FUNC_MASK GENMASK(31, 16)61 62#define MUX_FUNC_OFFS 1663#define MUX_FUNC(pinconf) \64 ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)65#define MUX_FUNC_PFC_MASK BIT(0)66#define MUX_FUNC_PFCE_MASK BIT(1)67#define MUX_FUNC_PFCEA_MASK BIT(2)68 69/* Pin mux flags */70#define MUX_FLAGS_BIDIR BIT(0)71#define MUX_FLAGS_SWIO_INPUT BIT(1)72#define MUX_FLAGS_SWIO_OUTPUT BIT(2)73 74/* ----------------------------------------------------------------------------75 * RZ/A1 pinmux flags76 */77 78/*79 * rza1_bidir_pin - describe a single pin that needs bidir flag applied.80 */81struct rza1_bidir_pin {82 u8 pin: 4;83 u8 func: 4;84};85 86/*87 * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.88 * Each struct rza1_bidir_entry describes a port.89 */90struct rza1_bidir_entry {91 const unsigned int npins;92 const struct rza1_bidir_pin *pins;93};94 95/*96 * rza1_swio_pin - describe a single pin that needs swio flag applied.97 */98struct rza1_swio_pin {99 u16 pin: 4;100 u16 port: 4;101 u16 func: 4;102 u16 input: 1;103};104 105/*106 * rza1_swio_entry - describe a list of pins that needs swio flag applied107 */108struct rza1_swio_entry {109 const unsigned int npins;110 const struct rza1_swio_pin *pins;111};112 113/*114 * rza1_pinmux_conf - group together bidir and swio pinmux flag tables115 */116struct rza1_pinmux_conf {117 const struct rza1_bidir_entry *bidir_entries;118 const struct rza1_swio_entry *swio_entries;119};120 121/* ----------------------------------------------------------------------------122 * RZ/A1H (r7s72100) pinmux flags123 */124 125static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {126 { .pin = 0, .func = 1 },127 { .pin = 1, .func = 1 },128 { .pin = 2, .func = 1 },129 { .pin = 3, .func = 1 },130 { .pin = 4, .func = 1 },131 { .pin = 5, .func = 1 },132 { .pin = 6, .func = 1 },133 { .pin = 7, .func = 1 },134};135 136static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {137 { .pin = 0, .func = 1 },138 { .pin = 1, .func = 1 },139 { .pin = 2, .func = 1 },140 { .pin = 3, .func = 1 },141 { .pin = 4, .func = 1 },142 { .pin = 0, .func = 4 },143 { .pin = 1, .func = 4 },144 { .pin = 2, .func = 4 },145 { .pin = 3, .func = 4 },146 { .pin = 5, .func = 1 },147 { .pin = 6, .func = 1 },148 { .pin = 7, .func = 1 },149 { .pin = 8, .func = 1 },150 { .pin = 9, .func = 1 },151 { .pin = 10, .func = 1 },152 { .pin = 11, .func = 1 },153 { .pin = 12, .func = 1 },154 { .pin = 13, .func = 1 },155 { .pin = 14, .func = 1 },156 { .pin = 15, .func = 1 },157 { .pin = 12, .func = 4 },158 { .pin = 13, .func = 4 },159 { .pin = 14, .func = 4 },160 { .pin = 15, .func = 4 },161};162 163static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {164 { .pin = 3, .func = 2 },165 { .pin = 10, .func = 7 },166 { .pin = 11, .func = 7 },167 { .pin = 13, .func = 7 },168 { .pin = 14, .func = 7 },169 { .pin = 15, .func = 7 },170 { .pin = 10, .func = 8 },171 { .pin = 11, .func = 8 },172 { .pin = 13, .func = 8 },173 { .pin = 14, .func = 8 },174 { .pin = 15, .func = 8 },175};176 177static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {178 { .pin = 0, .func = 8 },179 { .pin = 1, .func = 8 },180 { .pin = 2, .func = 8 },181 { .pin = 3, .func = 8 },182 { .pin = 10, .func = 3 },183 { .pin = 11, .func = 3 },184 { .pin = 13, .func = 3 },185 { .pin = 14, .func = 3 },186 { .pin = 15, .func = 3 },187 { .pin = 10, .func = 4 },188 { .pin = 11, .func = 4 },189 { .pin = 13, .func = 4 },190 { .pin = 14, .func = 4 },191 { .pin = 15, .func = 4 },192 { .pin = 12, .func = 5 },193 { .pin = 13, .func = 5 },194 { .pin = 14, .func = 5 },195 { .pin = 15, .func = 5 },196};197 198static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {199 { .pin = 0, .func = 1 },200 { .pin = 1, .func = 1 },201 { .pin = 2, .func = 1 },202 { .pin = 3, .func = 1 },203 { .pin = 4, .func = 1 },204 { .pin = 5, .func = 1 },205 { .pin = 6, .func = 1 },206 { .pin = 7, .func = 1 },207 { .pin = 8, .func = 1 },208 { .pin = 9, .func = 1 },209 { .pin = 10, .func = 1 },210 { .pin = 11, .func = 1 },211 { .pin = 12, .func = 1 },212 { .pin = 13, .func = 1 },213 { .pin = 14, .func = 1 },214 { .pin = 15, .func = 1 },215};216 217static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {218 { .pin = 13, .func = 3 },219};220 221static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {222 { .pin = 8, .func = 3 },223 { .pin = 9, .func = 3 },224 { .pin = 10, .func = 3 },225 { .pin = 11, .func = 3 },226 { .pin = 14, .func = 2 },227 { .pin = 15, .func = 2 },228 { .pin = 14, .func = 3 },229 { .pin = 15, .func = 3 },230};231 232static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {233 { .pin = 0, .func = 2 },234 { .pin = 1, .func = 2 },235 { .pin = 4, .func = 2 },236 { .pin = 5, .func = 2 },237 { .pin = 6, .func = 2 },238 { .pin = 7, .func = 2 },239};240 241static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {242 { .pin = 6, .func = 2 },243 { .pin = 7, .func = 2 },244 { .pin = 9, .func = 2 },245 { .pin = 6, .func = 4 },246 { .pin = 7, .func = 4 },247 { .pin = 9, .func = 4 },248 { .pin = 10, .func = 2 },249 { .pin = 11, .func = 2 },250 { .pin = 10, .func = 4 },251 { .pin = 11, .func = 4 },252 { .pin = 12, .func = 4 },253 { .pin = 13, .func = 4 },254 { .pin = 14, .func = 4 },255 { .pin = 15, .func = 4 },256};257 258static const struct rza1_swio_pin rza1h_swio_pins[] = {259 { .port = 2, .pin = 7, .func = 4, .input = 0 },260 { .port = 2, .pin = 11, .func = 4, .input = 0 },261 { .port = 3, .pin = 7, .func = 3, .input = 0 },262 { .port = 3, .pin = 7, .func = 8, .input = 0 },263 { .port = 4, .pin = 7, .func = 5, .input = 0 },264 { .port = 4, .pin = 7, .func = 11, .input = 0 },265 { .port = 4, .pin = 15, .func = 6, .input = 0 },266 { .port = 5, .pin = 0, .func = 1, .input = 1 },267 { .port = 5, .pin = 1, .func = 1, .input = 1 },268 { .port = 5, .pin = 2, .func = 1, .input = 1 },269 { .port = 5, .pin = 3, .func = 1, .input = 1 },270 { .port = 5, .pin = 4, .func = 1, .input = 1 },271 { .port = 5, .pin = 5, .func = 1, .input = 1 },272 { .port = 5, .pin = 6, .func = 1, .input = 1 },273 { .port = 5, .pin = 7, .func = 1, .input = 1 },274 { .port = 7, .pin = 4, .func = 6, .input = 0 },275 { .port = 7, .pin = 11, .func = 2, .input = 0 },276 { .port = 8, .pin = 10, .func = 8, .input = 0 },277 { .port = 10, .pin = 15, .func = 2, .input = 0 },278};279 280static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {281 [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },282 [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },283 [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },284 [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },285 [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },286 [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },287 [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },288 [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },289 [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },290};291 292static const struct rza1_swio_entry rza1h_swio_entries[] = {293 [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },294};295 296/* RZ/A1H (r7s72100x) pinmux flags table */297static const struct rza1_pinmux_conf rza1h_pmx_conf = {298 .bidir_entries = rza1h_bidir_entries,299 .swio_entries = rza1h_swio_entries,300};301 302/* ----------------------------------------------------------------------------303 * RZ/A1L (r7s72102) pinmux flags304 */305 306static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {307 { .pin = 0, .func = 1 },308 { .pin = 1, .func = 1 },309 { .pin = 2, .func = 1 },310 { .pin = 3, .func = 1 },311 { .pin = 4, .func = 1 },312 { .pin = 5, .func = 1 },313 { .pin = 6, .func = 1 },314 { .pin = 7, .func = 1 },315};316 317static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {318 { .pin = 0, .func = 2 },319 { .pin = 1, .func = 2 },320 { .pin = 2, .func = 2 },321 { .pin = 4, .func = 2 },322 { .pin = 5, .func = 2 },323 { .pin = 10, .func = 2 },324 { .pin = 11, .func = 2 },325 { .pin = 12, .func = 2 },326 { .pin = 13, .func = 2 },327};328 329static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {330 { .pin = 1, .func = 4 },331 { .pin = 2, .func = 2 },332 { .pin = 3, .func = 2 },333 { .pin = 6, .func = 2 },334 { .pin = 7, .func = 2 },335};336 337static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {338 { .pin = 0, .func = 1 },339 { .pin = 1, .func = 1 },340 { .pin = 2, .func = 1 },341 { .pin = 3, .func = 1 },342 { .pin = 4, .func = 1 },343 { .pin = 5, .func = 1 },344 { .pin = 6, .func = 1 },345 { .pin = 7, .func = 1 },346 { .pin = 8, .func = 1 },347 { .pin = 9, .func = 1 },348 { .pin = 10, .func = 1 },349 { .pin = 11, .func = 1 },350 { .pin = 12, .func = 1 },351 { .pin = 13, .func = 1 },352 { .pin = 14, .func = 1 },353 { .pin = 15, .func = 1 },354 { .pin = 0, .func = 2 },355 { .pin = 1, .func = 2 },356 { .pin = 2, .func = 2 },357 { .pin = 3, .func = 2 },358};359 360static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {361 { .pin = 0, .func = 1 },362 { .pin = 1, .func = 1 },363 { .pin = 2, .func = 1 },364 { .pin = 3, .func = 1 },365 { .pin = 4, .func = 1 },366 { .pin = 5, .func = 1 },367 { .pin = 6, .func = 1 },368 { .pin = 7, .func = 1 },369 { .pin = 8, .func = 1 },370 { .pin = 9, .func = 1 },371 { .pin = 10, .func = 1 },372 { .pin = 11, .func = 1 },373 { .pin = 12, .func = 1 },374 { .pin = 13, .func = 1 },375 { .pin = 14, .func = 1 },376 { .pin = 15, .func = 1 },377};378 379static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {380 { .pin = 2, .func = 2 },381 { .pin = 3, .func = 2 },382 { .pin = 5, .func = 2 },383 { .pin = 6, .func = 2 },384 { .pin = 7, .func = 2 },385 { .pin = 2, .func = 3 },386 { .pin = 3, .func = 3 },387 { .pin = 5, .func = 3 },388 { .pin = 6, .func = 3 },389 { .pin = 7, .func = 3 },390};391 392static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {393 { .pin = 1, .func = 2 },394 { .pin = 0, .func = 3 },395 { .pin = 1, .func = 3 },396 { .pin = 3, .func = 3 },397 { .pin = 4, .func = 3 },398 { .pin = 5, .func = 3 },399};400 401static const struct rza1_swio_pin rza1l_swio_pins[] = {402 { .port = 2, .pin = 8, .func = 2, .input = 0 },403 { .port = 5, .pin = 6, .func = 3, .input = 0 },404 { .port = 6, .pin = 6, .func = 3, .input = 0 },405 { .port = 6, .pin = 10, .func = 3, .input = 0 },406 { .port = 7, .pin = 10, .func = 2, .input = 0 },407 { .port = 8, .pin = 2, .func = 3, .input = 0 },408};409 410static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {411 [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },412 [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },413 [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },414 [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },415 [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },416 [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },417 [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },418};419 420static const struct rza1_swio_entry rza1l_swio_entries[] = {421 [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins },422};423 424/* RZ/A1L (r7s72102x) pinmux flags table */425static const struct rza1_pinmux_conf rza1l_pmx_conf = {426 .bidir_entries = rza1l_bidir_entries,427 .swio_entries = rza1l_swio_entries,428};429 430/* ----------------------------------------------------------------------------431 * RZ/A1 types432 */433/**434 * struct rza1_mux_conf - describes a pin multiplexing operation435 *436 * @id: the pin identifier from 0 to RZA1_NPINS437 * @port: the port where pin sits on438 * @pin: pin id439 * @mux_func: alternate function id number440 * @mux_flags: alternate function flags441 * @value: output value to set the pin to442 */443struct rza1_mux_conf {444 u16 id;445 u8 port;446 u8 pin;447 u8 mux_func;448 u8 mux_flags;449 u8 value;450};451 452/**453 * struct rza1_port - describes a pin port454 *455 * This is mostly useful to lock register writes per-bank and not globally.456 *457 * @lock: protect access to HW registers458 * @id: port number459 * @base: logical address base460 * @pins: pins sitting on this port461 */462struct rza1_port {463 spinlock_t lock;464 unsigned int id;465 void __iomem *base;466 struct pinctrl_pin_desc *pins;467};468 469/**470 * struct rza1_pinctrl - RZ pincontroller device471 *472 * @dev: parent device structure473 * @mutex: protect [pinctrl|pinmux]_generic functions474 * @base: logical address base475 * @nport: number of pin controller ports476 * @ports: pin controller banks477 * @pins: pin array for pinctrl core478 * @desc: pincontroller desc for pinctrl core479 * @pctl: pinctrl device480 * @data: device specific data481 */482struct rza1_pinctrl {483 struct device *dev;484 485 struct mutex mutex;486 487 void __iomem *base;488 489 unsigned int nport;490 struct rza1_port *ports;491 492 struct pinctrl_pin_desc *pins;493 struct pinctrl_desc desc;494 struct pinctrl_dev *pctl;495 496 const void *data;497};498 499/* ----------------------------------------------------------------------------500 * RZ/A1 pinmux flags501 */502static inline bool rza1_pinmux_get_bidir(unsigned int port,503 unsigned int pin,504 unsigned int func,505 const struct rza1_bidir_entry *table)506{507 const struct rza1_bidir_entry *entry = &table[port];508 const struct rza1_bidir_pin *bidir_pin;509 unsigned int i;510 511 for (i = 0; i < entry->npins; ++i) {512 bidir_pin = &entry->pins[i];513 if (bidir_pin->pin == pin && bidir_pin->func == func)514 return true;515 }516 517 return false;518}519 520static inline int rza1_pinmux_get_swio(unsigned int port,521 unsigned int pin,522 unsigned int func,523 const struct rza1_swio_entry *table)524{525 const struct rza1_swio_pin *swio_pin;526 unsigned int i;527 528 529 for (i = 0; i < table->npins; ++i) {530 swio_pin = &table->pins[i];531 if (swio_pin->port == port && swio_pin->pin == pin &&532 swio_pin->func == func)533 return swio_pin->input;534 }535 536 return -ENOENT;537}538 539/*540 * rza1_pinmux_get_flags() - return pinmux flags associated to a pin541 */542static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,543 unsigned int func,544 struct rza1_pinctrl *rza1_pctl)545 546{547 const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;548 const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;549 const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;550 unsigned int pmx_flags = 0;551 int ret;552 553 if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))554 pmx_flags |= MUX_FLAGS_BIDIR;555 556 ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);557 if (ret == 0)558 pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;559 else if (ret > 0)560 pmx_flags |= MUX_FLAGS_SWIO_INPUT;561 562 return pmx_flags;563}564 565/* ----------------------------------------------------------------------------566 * RZ/A1 SoC operations567 */568 569/*570 * rza1_set_bit() - un-locked set/clear a single bit in pin configuration571 * registers572 */573static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,574 unsigned int bit, bool set)575{576 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);577 u16 val = ioread16(mem);578 579 if (set)580 val |= BIT(bit);581 else582 val &= ~BIT(bit);583 584 iowrite16(val, mem);585}586 587static inline unsigned int rza1_get_bit(struct rza1_port *port,588 unsigned int reg, unsigned int bit)589{590 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);591 592 return ioread16(mem) & BIT(bit);593}594 595/**596 * rza1_pin_reset() - reset a pin to default initial state597 *598 * Reset pin state disabling input buffer and bi-directional control,599 * and configure it as input port.600 * Note that pin is now configured with direction as input but with input601 * buffer disabled. This implies the pin value cannot be read in this state.602 *603 * @port: port where pin sits on604 * @pin: pin offset605 */606static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)607{608 unsigned long irqflags;609 610 spin_lock_irqsave(&port->lock, irqflags);611 rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);612 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);613 614 rza1_set_bit(port, RZA1_PM_REG, pin, 1);615 rza1_set_bit(port, RZA1_PMC_REG, pin, 0);616 rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);617 spin_unlock_irqrestore(&port->lock, irqflags);618}619 620/**621 * rza1_pin_set_direction() - set I/O direction on a pin in port mode622 *623 * When running in output port mode keep PBDC enabled to allow reading the624 * pin value from PPR.625 *626 * @port: port where pin sits on627 * @pin: pin offset628 * @input: input enable/disable flag629 */630static inline void rza1_pin_set_direction(struct rza1_port *port,631 unsigned int pin, bool input)632{633 unsigned long irqflags;634 635 spin_lock_irqsave(&port->lock, irqflags);636 637 rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);638 if (input) {639 rza1_set_bit(port, RZA1_PM_REG, pin, 1);640 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);641 } else {642 rza1_set_bit(port, RZA1_PM_REG, pin, 0);643 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);644 }645 646 spin_unlock_irqrestore(&port->lock, irqflags);647}648 649static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,650 unsigned int value)651{652 unsigned long irqflags;653 654 spin_lock_irqsave(&port->lock, irqflags);655 rza1_set_bit(port, RZA1_P_REG, pin, !!value);656 spin_unlock_irqrestore(&port->lock, irqflags);657}658 659static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)660{661 return rza1_get_bit(port, RZA1_PPR_REG, pin);662}663 664/**665 * rza1_pin_mux_single() - configure pin multiplexing on a single pin666 *667 * @rza1_pctl: RZ/A1 pin controller device668 * @mux_conf: pin multiplexing descriptor669 */670static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,671 struct rza1_mux_conf *mux_conf)672{673 struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];674 unsigned int pin = mux_conf->pin;675 u8 mux_func = mux_conf->mux_func;676 u8 mux_flags = mux_conf->mux_flags;677 u8 mux_flags_from_table;678 679 rza1_pin_reset(port, pin);680 681 /* SWIO pinmux flags coming from DT are high precedence */682 mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,683 rza1_pctl);684 if (mux_flags)685 mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);686 else687 mux_flags = mux_flags_from_table;688 689 if (mux_flags & MUX_FLAGS_BIDIR)690 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);691 692 /*693 * Enable alternate function mode and select it.694 *695 * Be careful here: the pin mux sub-nodes in device tree696 * enumerate alternate functions from 1 to 8;697 * subtract 1 before using macros to match registers configuration698 * which expects numbers from 0 to 7 instead.699 *700 * ----------------------------------------------------701 * Alternate mode selection table:702 *703 * PMC PFC PFCE PFCAE (mux_func - 1)704 * 1 0 0 0 0705 * 1 1 0 0 1706 * 1 0 1 0 2707 * 1 1 1 0 3708 * 1 0 0 1 4709 * 1 1 0 1 5710 * 1 0 1 1 6711 * 1 1 1 1 7712 * ----------------------------------------------------713 */714 mux_func -= 1;715 rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);716 rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);717 rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);718 719 /*720 * All alternate functions except a few need PIPCn = 1.721 * If PIPCn has to stay disabled (SW IO mode), configure PMn according722 * to I/O direction specified by pin configuration -after- PMC has been723 * set to one.724 */725 if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))726 rza1_set_bit(port, RZA1_PM_REG, pin,727 mux_flags & MUX_FLAGS_SWIO_INPUT);728 else729 rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);730 731 rza1_set_bit(port, RZA1_PMC_REG, pin, 1);732 733 return 0;734}735 736/* ----------------------------------------------------------------------------737 * gpio operations738 */739 740/**741 * rza1_gpio_request() - configure pin in port mode742 *743 * Configure a pin as gpio (port mode).744 * After reset, the pin is in input mode with input buffer disabled.745 * To use the pin as input or output, set_direction shall be called first746 *747 * @chip: gpio chip where the gpio sits on748 * @gpio: gpio offset749 */750static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)751{752 struct rza1_port *port = gpiochip_get_data(chip);753 754 rza1_pin_reset(port, gpio);755 756 return 0;757}758 759/**760 * rza1_gpio_free() - reset a pin761 *762 * Surprisingly, freeing a gpio is equivalent to requesting it.763 * Reset pin to port mode, with input buffer disabled. This overwrites all764 * port direction settings applied with set_direction765 *766 * @chip: gpio chip where the gpio sits on767 * @gpio: gpio offset768 */769static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)770{771 struct rza1_port *port = gpiochip_get_data(chip);772 773 rza1_pin_reset(port, gpio);774}775 776static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)777{778 struct rza1_port *port = gpiochip_get_data(chip);779 780 if (rza1_get_bit(port, RZA1_PM_REG, gpio))781 return GPIO_LINE_DIRECTION_IN;782 783 return GPIO_LINE_DIRECTION_OUT;784}785 786static int rza1_gpio_direction_input(struct gpio_chip *chip,787 unsigned int gpio)788{789 struct rza1_port *port = gpiochip_get_data(chip);790 791 rza1_pin_set_direction(port, gpio, true);792 793 return 0;794}795 796static int rza1_gpio_direction_output(struct gpio_chip *chip,797 unsigned int gpio,798 int value)799{800 struct rza1_port *port = gpiochip_get_data(chip);801 802 /* Set value before driving pin direction */803 rza1_pin_set(port, gpio, value);804 rza1_pin_set_direction(port, gpio, false);805 806 return 0;807}808 809/**810 * rza1_gpio_get() - read a gpio pin value811 *812 * Read gpio pin value through PPR register.813 * Requires bi-directional mode to work when reading the value of a pin814 * in output mode815 *816 * @chip: gpio chip where the gpio sits on817 * @gpio: gpio offset818 */819static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)820{821 struct rza1_port *port = gpiochip_get_data(chip);822 823 return rza1_pin_get(port, gpio);824}825 826static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,827 int value)828{829 struct rza1_port *port = gpiochip_get_data(chip);830 831 rza1_pin_set(port, gpio, value);832}833 834static const struct gpio_chip rza1_gpiochip_template = {835 .request = rza1_gpio_request,836 .free = rza1_gpio_free,837 .get_direction = rza1_gpio_get_direction,838 .direction_input = rza1_gpio_direction_input,839 .direction_output = rza1_gpio_direction_output,840 .get = rza1_gpio_get,841 .set = rza1_gpio_set,842};843/* ----------------------------------------------------------------------------844 * pinctrl operations845 */846 847/**848 * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its849 * children sub-nodes850 *851 * @np: device tree node to parse852 */853static int rza1_dt_node_pin_count(struct device_node *np)854{855 struct property *of_pins;856 unsigned int npins;857 858 of_pins = of_find_property(np, "pinmux", NULL);859 if (of_pins)860 return of_pins->length / sizeof(u32);861 862 npins = 0;863 for_each_child_of_node_scoped(np, child) {864 of_pins = of_find_property(child, "pinmux", NULL);865 if (!of_pins)866 return -EINVAL;867 868 npins += of_pins->length / sizeof(u32);869 }870 871 return npins;872}873 874/**875 * rza1_parse_pinmux_node() - parse a pin mux sub-node876 *877 * @rza1_pctl: RZ/A1 pin controller device878 * @np: of pmx sub-node879 * @mux_confs: array of pin mux configurations to fill with parsed info880 * @grpins: array of pin ids to mux881 */882static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,883 struct device_node *np,884 struct rza1_mux_conf *mux_confs,885 unsigned int *grpins)886{887 struct pinctrl_dev *pctldev = rza1_pctl->pctl;888 char const *prop_name = "pinmux";889 unsigned long *pin_configs;890 unsigned int npin_configs;891 struct property *of_pins;892 unsigned int npins;893 u8 pinmux_flags;894 unsigned int i;895 int ret;896 897 of_pins = of_find_property(np, prop_name, NULL);898 if (!of_pins) {899 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);900 return -ENOENT;901 }902 npins = of_pins->length / sizeof(u32);903 904 /*905 * Collect pin configuration properties: they apply to all pins in906 * this sub-node907 */908 ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,909 &npin_configs);910 if (ret) {911 dev_err(rza1_pctl->dev,912 "Unable to parse pin configuration options for %pOFn\n",913 np);914 return ret;915 }916 917 /*918 * Create a mask with pinmux flags from pin configuration;919 * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction920 * specified in device tree.921 */922 pinmux_flags = 0;923 for (i = 0; i < npin_configs && pinmux_flags == 0; i++)924 switch (pinconf_to_config_param(pin_configs[i])) {925 case PIN_CONFIG_INPUT_ENABLE:926 pinmux_flags |= MUX_FLAGS_SWIO_INPUT;927 break;928 case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */929 case PIN_CONFIG_OUTPUT_ENABLE:930 pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;931 break;932 default:933 break;934 935 }936 937 kfree(pin_configs);938 939 /* Collect pin positions and their mux settings. */940 for (i = 0; i < npins; ++i) {941 u32 of_pinconf;942 struct rza1_mux_conf *mux_conf = &mux_confs[i];943 944 ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);945 if (ret)946 return ret;947 948 mux_conf->id = of_pinconf & MUX_PIN_ID_MASK;949 mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id);950 mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id);951 mux_conf->mux_func = MUX_FUNC(of_pinconf);952 mux_conf->mux_flags = pinmux_flags;953 954 if (mux_conf->port >= RZA1_NPORTS ||955 mux_conf->pin >= RZA1_PINS_PER_PORT) {956 dev_err(rza1_pctl->dev,957 "Wrong port %u pin %u for %s property\n",958 mux_conf->port, mux_conf->pin, prop_name);959 return -EINVAL;960 }961 962 grpins[i] = mux_conf->id;963 }964 965 return npins;966}967 968/**969 * rza1_dt_node_to_map() - map a pin mux node to a function/group970 *971 * Parse and register a pin mux function.972 *973 * @pctldev: pin controller device974 * @np: device tree node to parse975 * @map: pointer to pin map (output)976 * @num_maps: number of collected maps (output)977 */978static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,979 struct device_node *np,980 struct pinctrl_map **map,981 unsigned int *num_maps)982{983 struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);984 struct rza1_mux_conf *mux_confs, *mux_conf;985 unsigned int *grpins, *grpin;986 const char *grpname;987 const char **fngrps;988 int ret, npins;989 int gsel, fsel;990 991 npins = rza1_dt_node_pin_count(np);992 if (npins < 0) {993 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");994 return -EINVAL;995 }996 997 /*998 * Functions are made of 1 group only;999 * in fact, functions and groups are identical for this pin controller1000 * except that functions carry an array of per-pin mux configuration1001 * settings.1002 */1003 mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),1004 GFP_KERNEL);1005 grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),1006 GFP_KERNEL);1007 fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);1008 1009 if (!mux_confs || !grpins || !fngrps)1010 return -ENOMEM;1011 1012 /*1013 * Parse the pinmux node.1014 * If the node does not contain "pinmux" property (-ENOENT)1015 * that property shall be specified in all its children sub-nodes.1016 */1017 mux_conf = &mux_confs[0];1018 grpin = &grpins[0];1019 1020 ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);1021 if (ret == -ENOENT)1022 for_each_child_of_node_scoped(np, child) {1023 ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,1024 grpin);1025 if (ret < 0)1026 return ret;1027 1028 grpin += ret;1029 mux_conf += ret;1030 }1031 else if (ret < 0)1032 return ret;1033 1034 /* Register pin group and function name to pinctrl_generic */1035 grpname = np->name;1036 fngrps[0] = grpname;1037 1038 mutex_lock(&rza1_pctl->mutex);1039 gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,1040 NULL);1041 if (gsel < 0) {1042 mutex_unlock(&rza1_pctl->mutex);1043 return gsel;1044 }1045 1046 fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,1047 mux_confs);1048 if (fsel < 0) {1049 ret = fsel;1050 goto remove_group;1051 }1052 1053 dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",1054 grpname, npins);1055 1056 /* Create map where to retrieve function and mux settings from */1057 *num_maps = 0;1058 *map = kzalloc(sizeof(**map), GFP_KERNEL);1059 if (!*map) {1060 ret = -ENOMEM;1061 goto remove_function;1062 }1063 1064 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;1065 (*map)->data.mux.group = np->name;1066 (*map)->data.mux.function = np->name;1067 *num_maps = 1;1068 mutex_unlock(&rza1_pctl->mutex);1069 1070 return 0;1071 1072remove_function:1073 pinmux_generic_remove_function(pctldev, fsel);1074 1075remove_group:1076 pinctrl_generic_remove_group(pctldev, gsel);1077 mutex_unlock(&rza1_pctl->mutex);1078 1079 dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",1080 grpname);1081 1082 return ret;1083}1084 1085static void rza1_dt_free_map(struct pinctrl_dev *pctldev,1086 struct pinctrl_map *map, unsigned int num_maps)1087{1088 kfree(map);1089}1090 1091static const struct pinctrl_ops rza1_pinctrl_ops = {1092 .get_groups_count = pinctrl_generic_get_group_count,1093 .get_group_name = pinctrl_generic_get_group_name,1094 .get_group_pins = pinctrl_generic_get_group_pins,1095 .dt_node_to_map = rza1_dt_node_to_map,1096 .dt_free_map = rza1_dt_free_map,1097};1098 1099/* ----------------------------------------------------------------------------1100 * pinmux operations1101 */1102 1103/**1104 * rza1_set_mux() - retrieve pins from a group and apply their mux settings1105 *1106 * @pctldev: pin controller device1107 * @selector: function selector1108 * @group: group selector1109 */1110static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,1111 unsigned int group)1112{1113 struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);1114 struct rza1_mux_conf *mux_confs;1115 struct function_desc *func;1116 struct group_desc *grp;1117 int i;1118 1119 grp = pinctrl_generic_get_group(pctldev, group);1120 if (!grp)1121 return -EINVAL;1122 1123 func = pinmux_generic_get_function(pctldev, selector);1124 if (!func)1125 return -EINVAL;1126 1127 mux_confs = (struct rza1_mux_conf *)func->data;1128 for (i = 0; i < grp->grp.npins; ++i) {1129 int ret;1130 1131 ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);1132 if (ret)1133 return ret;1134 }1135 1136 return 0;1137}1138 1139static const struct pinmux_ops rza1_pinmux_ops = {1140 .get_functions_count = pinmux_generic_get_function_count,1141 .get_function_name = pinmux_generic_get_function_name,1142 .get_function_groups = pinmux_generic_get_function_groups,1143 .set_mux = rza1_set_mux,1144 .strict = true,1145};1146 1147/* ----------------------------------------------------------------------------1148 * RZ/A1 pin controller driver operations1149 */1150 1151/**1152 * rza1_parse_gpiochip() - parse and register a gpio chip and pin range1153 *1154 * The gpio controller subnode shall provide a "gpio-ranges" list property as1155 * defined by gpio device tree binding documentation.1156 *1157 * @rza1_pctl: RZ/A1 pin controller device1158 * @fwnode: gpio-controller firmware node1159 * @chip: gpio chip to register to gpiolib1160 * @range: pin range to register to pinctrl core1161 */1162static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,1163 struct fwnode_handle *fwnode,1164 struct gpio_chip *chip,1165 struct pinctrl_gpio_range *range)1166{1167 const char *list_name = "gpio-ranges";1168 struct fwnode_reference_args args;1169 unsigned int gpioport;1170 u32 pinctrl_base;1171 int ret;1172 1173 ret = fwnode_property_get_reference_args(fwnode, list_name, NULL, 3, 0, &args);1174 if (ret) {1175 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",1176 list_name);1177 return ret;1178 }1179 1180 /*1181 * Find out on which port this gpio-chip maps to by inspecting the1182 * second argument of the "gpio-ranges" property.1183 */1184 pinctrl_base = args.args[1];1185 gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);1186 if (gpioport >= RZA1_NPORTS) {1187 dev_err(rza1_pctl->dev,1188 "Invalid values in property %s\n", list_name);1189 return -EINVAL;1190 }1191 1192 *chip = rza1_gpiochip_template;1193 chip->base = -1;1194 chip->ngpio = args.args[2];1195 chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pfwP", fwnode);1196 if (!chip->label)1197 return -ENOMEM;1198 1199 chip->fwnode = fwnode;1200 chip->parent = rza1_pctl->dev;1201 1202 range->id = gpioport;1203 range->name = chip->label;1204 range->pin_base = range->base = pinctrl_base;1205 range->npins = args.args[2];1206 range->gc = chip;1207 1208 ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,1209 &rza1_pctl->ports[gpioport]);1210 if (ret)1211 return ret;1212 1213 pinctrl_add_gpio_range(rza1_pctl->pctl, range);1214 1215 dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",1216 chip->label, chip->ngpio);1217 1218 return 0;1219}1220 1221/**1222 * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges1223 *1224 * @rza1_pctl: RZ/A1 pin controller device1225 */1226static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)1227{1228 struct pinctrl_gpio_range *gpio_ranges;1229 struct gpio_chip *gpio_chips;1230 struct fwnode_handle *child;1231 unsigned int ngpiochips;1232 unsigned int i;1233 int ret;1234 1235 ngpiochips = gpiochip_node_count(rza1_pctl->dev);1236 if (ngpiochips == 0) {1237 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");1238 return 0;1239 }1240 1241 gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,1242 sizeof(*gpio_chips), GFP_KERNEL);1243 gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,1244 sizeof(*gpio_ranges), GFP_KERNEL);1245 if (!gpio_chips || !gpio_ranges)1246 return -ENOMEM;1247 1248 i = 0;1249 for_each_gpiochip_node(rza1_pctl->dev, child) {1250 ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],1251 &gpio_ranges[i]);1252 if (ret) {1253 fwnode_handle_put(child);1254 return ret;1255 }1256 1257 ++i;1258 }1259 1260 dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);1261 1262 return 0;1263}1264 1265/**1266 * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register1267 * them to pinctrl and gpio cores.1268 *1269 * @rza1_pctl: RZ/A1 pin controller device1270 */1271static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)1272{1273 struct pinctrl_pin_desc *pins;1274 struct rza1_port *ports;1275 unsigned int i;1276 int ret;1277 1278 pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),1279 GFP_KERNEL);1280 ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),1281 GFP_KERNEL);1282 if (!pins || !ports)1283 return -ENOMEM;1284 1285 rza1_pctl->pins = pins;1286 rza1_pctl->desc.pins = pins;1287 rza1_pctl->desc.npins = RZA1_NPINS;1288 rza1_pctl->ports = ports;1289 1290 for (i = 0; i < RZA1_NPINS; ++i) {1291 unsigned int pin = RZA1_PIN_ID_TO_PIN(i);1292 unsigned int port = RZA1_PIN_ID_TO_PORT(i);1293 1294 pins[i].number = i;1295 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,1296 "P%u-%u", port, pin);1297 if (!pins[i].name)1298 return -ENOMEM;1299 1300 if (i % RZA1_PINS_PER_PORT == 0) {1301 /*1302 * Setup ports;1303 * they provide per-port lock and logical base address.1304 */1305 unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);1306 1307 ports[port_id].id = port_id;1308 ports[port_id].base = rza1_pctl->base;1309 ports[port_id].pins = &pins[i];1310 spin_lock_init(&ports[port_id].lock);1311 }1312 }1313 1314 ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,1315 rza1_pctl, &rza1_pctl->pctl);1316 if (ret) {1317 dev_err(rza1_pctl->dev,1318 "RZ/A1 pin controller registration failed\n");1319 return ret;1320 }1321 1322 ret = pinctrl_enable(rza1_pctl->pctl);1323 if (ret) {1324 dev_err(rza1_pctl->dev,1325 "RZ/A1 pin controller failed to start\n");1326 return ret;1327 }1328 1329 ret = rza1_gpio_register(rza1_pctl);1330 if (ret) {1331 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");1332 return ret;1333 }1334 1335 return 0;1336}1337 1338static int rza1_pinctrl_probe(struct platform_device *pdev)1339{1340 struct rza1_pinctrl *rza1_pctl;1341 int ret;1342 1343 rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);1344 if (!rza1_pctl)1345 return -ENOMEM;1346 1347 rza1_pctl->dev = &pdev->dev;1348 1349 rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0);1350 if (IS_ERR(rza1_pctl->base))1351 return PTR_ERR(rza1_pctl->base);1352 1353 mutex_init(&rza1_pctl->mutex);1354 1355 platform_set_drvdata(pdev, rza1_pctl);1356 1357 rza1_pctl->desc.name = DRIVER_NAME;1358 rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;1359 rza1_pctl->desc.pmxops = &rza1_pinmux_ops;1360 rza1_pctl->desc.owner = THIS_MODULE;1361 rza1_pctl->data = of_device_get_match_data(&pdev->dev);1362 1363 ret = rza1_pinctrl_register(rza1_pctl);1364 if (ret)1365 return ret;1366 1367 dev_info(&pdev->dev,1368 "RZ/A1 pin controller and gpio successfully registered\n");1369 1370 return 0;1371}1372 1373static const struct of_device_id rza1_pinctrl_of_match[] = {1374 {1375 /* RZ/A1H, RZ/A1M */1376 .compatible = "renesas,r7s72100-ports",1377 .data = &rza1h_pmx_conf,1378 },1379 {1380 /* RZ/A1L */1381 .compatible = "renesas,r7s72102-ports",1382 .data = &rza1l_pmx_conf,1383 },1384 { /* sentinel */ }1385};1386 1387static struct platform_driver rza1_pinctrl_driver = {1388 .driver = {1389 .name = DRIVER_NAME,1390 .of_match_table = rza1_pinctrl_of_match,1391 },1392 .probe = rza1_pinctrl_probe,1393};1394 1395static int __init rza1_pinctrl_init(void)1396{1397 return platform_driver_register(&rza1_pinctrl_driver);1398}1399core_initcall(rza1_pinctrl_init);1400 1401MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");1402MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");1403