brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.02/*3 * Renesas RZ/G2L Pin Control and GPIO driver core4 *5 * Copyright (C) 2021 Renesas Electronics Corporation.6 */7 8#include <linux/bitfield.h>9#include <linux/bitops.h>10#include <linux/clk.h>11#include <linux/gpio/driver.h>12#include <linux/interrupt.h>13#include <linux/io.h>14#include <linux/module.h>15#include <linux/mutex.h>16#include <linux/of.h>17#include <linux/of_irq.h>18#include <linux/platform_device.h>19#include <linux/property.h>20#include <linux/seq_file.h>21#include <linux/spinlock.h>22 23#include <linux/pinctrl/consumer.h>24#include <linux/pinctrl/pinconf-generic.h>25#include <linux/pinctrl/pinconf.h>26#include <linux/pinctrl/pinctrl.h>27#include <linux/pinctrl/pinmux.h>28 29#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>30 31#include "../core.h"32#include "../pinconf.h"33#include "../pinmux.h"34 35#define DRV_NAME	"pinctrl-rzg2l"36 37/*38 * Use 16 lower bits [15:0] for pin identifier39 * Use 16 higher bits [31:16] for pin mux function40 */41#define MUX_PIN_ID_MASK		GENMASK(15, 0)42#define MUX_FUNC_MASK		GENMASK(31, 16)43 44/* PIN capabilities */45#define PIN_CFG_IOLH_A			BIT(0)46#define PIN_CFG_IOLH_B			BIT(1)47#define PIN_CFG_SR			BIT(2)48#define PIN_CFG_IEN			BIT(3)49#define PIN_CFG_PUPD			BIT(4)50#define PIN_CFG_IO_VMC_SD0		BIT(5)51#define PIN_CFG_IO_VMC_SD1		BIT(6)52#define PIN_CFG_IO_VMC_QSPI		BIT(7)53#define PIN_CFG_IO_VMC_ETH0		BIT(8)54#define PIN_CFG_IO_VMC_ETH1		BIT(9)55#define PIN_CFG_NF			BIT(10)	/* Digital noise filter */56#define PIN_CFG_IOLH_C			BIT(11)57#define PIN_CFG_SOFT_PS			BIT(12)58#define PIN_CFG_OEN			BIT(13)59#define PIN_CFG_NOGPIO_INT		BIT(14)60#define PIN_CFG_NOD			BIT(15)	/* N-ch Open Drain */61#define PIN_CFG_SMT			BIT(16)	/* Schmitt-trigger input control */62#define PIN_CFG_ELC			BIT(17)63#define PIN_CFG_IOLH_RZV2H		BIT(18)64 65#define RZG2L_SINGLE_PIN		BIT_ULL(63)	/* Dedicated pin */66#define RZG2L_VARIABLE_CFG		BIT_ULL(62)	/* Variable cfg for port pins */67 68#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \69					(PIN_CFG_IOLH_##group | \70					 PIN_CFG_PUPD | \71					 PIN_CFG_NF)72 73#define RZG2L_MPXED_PIN_FUNCS		(RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \74					 PIN_CFG_SR)75 76#define RZG3S_MPXED_PIN_FUNCS(group)	(RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \77					 PIN_CFG_SOFT_PS)78 79#define RZV2H_MPXED_PIN_FUNCS		(RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \80					 PIN_CFG_NOD | \81					 PIN_CFG_SR | \82					 PIN_CFG_SMT)83 84#define RZG2L_MPXED_ETH_PIN_FUNCS(x)	((x) | PIN_CFG_NF)85 86#define PIN_CFG_PIN_MAP_MASK		GENMASK_ULL(61, 54)87#define PIN_CFG_PIN_REG_MASK		GENMASK_ULL(53, 46)88#define PIN_CFG_MASK			GENMASK_ULL(31, 0)89 90/*91 * m indicates the bitmap of supported pins, a is the register index92 * and f is pin configuration capabilities supported.93 */94#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f)	(FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \95						 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \96						 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))97#define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a)	\98						(RZG2L_VARIABLE_CFG | \99						 RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0))100 101/*102 * n indicates number of pins in the port, a is the register index103 * and f is pin configuration capabilities supported.104 */105#define RZG2L_GPIO_PORT_PACK(n, a, f)	RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))106#define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a)	(RZG2L_VARIABLE_CFG | \107						 RZG2L_GPIO_PORT_PACK(n, a, 0))108 109#define RZG2L_SINGLE_PIN_INDEX_MASK	GENMASK_ULL(62, 56)110#define RZG2L_SINGLE_PIN_BITS_MASK	GENMASK_ULL(55, 53)111/*112 * p is the register index while referencing to SR/IEN/IOLH/FILxx113 * registers, b is the register bits (b * 8) and f is the pin114 * configuration capabilities supported.115 */116#define RZG2L_SINGLE_PIN_PACK(p, b, f)	(RZG2L_SINGLE_PIN | \117					 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \118					 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \119					 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))120 121#define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg)	((cfg) & RZG2L_SINGLE_PIN ? \122						 FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \123						 FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg)))124 125#define VARIABLE_PIN_CFG_PIN_MASK		GENMASK_ULL(54, 52)126#define VARIABLE_PIN_CFG_PORT_MASK		GENMASK_ULL(51, 47)127#define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \128	(FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \129	 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \130	 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))131 132#define P(off)			(0x0000 + (off))133#define PM(off)			(0x0100 + (off) * 2)134#define PMC(off)		(0x0200 + (off))135#define PFC(off)		(0x0400 + (off) * 4)136#define PIN(off)		(0x0800 + (off))137#define IOLH(off)		(0x1000 + (off) * 8)138#define SR(off)			(0x1400 + (off) * 8)139#define IEN(off)		(0x1800 + (off) * 8)140#define PUPD(off)		(0x1C00 + (off) * 8)141#define ISEL(off)		(0x2C00 + (off) * 8)142#define SD_CH(off, ch)		((off) + (ch) * 4)143#define ETH_POC(off, ch)	((off) + (ch) * 4)144#define QSPI			(0x3008)145#define ETH_MODE		(0x3018)146#define PFC_OEN			(0x3C40) /* known on RZ/V2H(P) only */147 148#define PVDD_2500		2	/* I/O domain voltage 2.5V */149#define PVDD_1800		1	/* I/O domain voltage <= 1.8V */150#define PVDD_3300		0	/* I/O domain voltage >= 3.3V */151 152#define PWPR_B0WI		BIT(7)	/* Bit Write Disable */153#define PWPR_PFCWE		BIT(6)	/* PFC Register Write Enable */154#define PWPR_REGWE_A		BIT(6)	/* PFC and PMC Register Write Enable on RZ/V2H(P) */155#define PWPR_REGWE_B		BIT(5)	/* OEN Register Write Enable, known only in RZ/V2H(P) */156 157#define PM_MASK			0x03158#define PFC_MASK		0x07159#define IEN_MASK		0x01160#define IOLH_MASK		0x03161#define SR_MASK			0x01162#define PUPD_MASK		0x03163 164#define PM_INPUT		0x1165#define PM_OUTPUT		0x2166 167#define RZG2L_PIN_ID_TO_PORT(id)	((id) / RZG2L_PINS_PER_PORT)168#define RZG2L_PIN_ID_TO_PIN(id)		((id) % RZG2L_PINS_PER_PORT)169 170#define RZG2L_TINT_MAX_INTERRUPT	32171#define RZG2L_TINT_IRQ_START_INDEX	9172#define RZG2L_PACK_HWIRQ(t, i)		(((t) << 16) | (i))173 174/* Custom pinconf parameters */175#define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE	(PIN_CONFIG_END + 1)176 177static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = {178	{ "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },179};180 181#ifdef CONFIG_DEBUG_FS182static const struct pin_config_item renesas_rzv2h_conf_items[] = {183	PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),184};185#endif186 187/* Read/write 8 bits register */188#define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val)	\189	do {						\190		if (_read)				\191			_val = readb(_addr);		\192		else					\193			writeb(_val, _addr);		\194	} while (0)195 196/* Read/write 16 bits register */197#define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val)	\198	do {						\199		if (_read)				\200			_val = readw(_addr);		\201		else					\202			writew(_val, _addr);		\203	} while (0)204 205/* Read/write 32 bits register */206#define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val)	\207	do {						\208		if (_read)				\209			_val = readl(_addr);		\210		else					\211			writel(_val, _addr);		\212	} while (0)213 214/**215 * struct rzg2l_register_offsets - specific register offsets216 * @pwpr: PWPR register offset217 * @sd_ch: SD_CH register offset218 * @eth_poc: ETH_POC register offset219 */220struct rzg2l_register_offsets {221	u16 pwpr;222	u16 sd_ch;223	u16 eth_poc;224};225 226/**227 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays228 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source229 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source230 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source231 * @RZG2L_IOLH_IDX_MAX: maximum index232 */233enum rzg2l_iolh_index {234	RZG2L_IOLH_IDX_1V8 = 0,235	RZG2L_IOLH_IDX_2V5 = 4,236	RZG2L_IOLH_IDX_3V3 = 8,237	RZG2L_IOLH_IDX_MAX = 12,238};239 240/* Maximum number of driver strength entries per power source. */241#define RZG2L_IOLH_MAX_DS_ENTRIES	(4)242 243/**244 * struct rzg2l_hwcfg - hardware configuration data structure245 * @regs: hardware specific register offsets246 * @iolh_groupa_ua: IOLH group A uA specific values247 * @iolh_groupb_ua: IOLH group B uA specific values248 * @iolh_groupc_ua: IOLH group C uA specific values249 * @iolh_groupb_oi: IOLH group B output impedance specific values250 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)251 * @func_base: base number for port function (see register PFC)252 * @oen_max_pin: the maximum pin number supporting output enable253 * @oen_max_port: the maximum port number supporting output enable254 */255struct rzg2l_hwcfg {256	const struct rzg2l_register_offsets regs;257	u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX];258	u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];259	u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];260	u16 iolh_groupb_oi[4];261	bool drive_strength_ua;262	u8 func_base;263	u8 oen_max_pin;264	u8 oen_max_port;265};266 267struct rzg2l_dedicated_configs {268	const char *name;269	u64 config;270};271 272struct rzg2l_pinctrl;273 274struct rzg2l_pinctrl_data {275	const char * const *port_pins;276	const u64 *port_pin_configs;277	unsigned int n_ports;278	const struct rzg2l_dedicated_configs *dedicated_pins;279	unsigned int n_port_pins;280	unsigned int n_dedicated_pins;281	const struct rzg2l_hwcfg *hwcfg;282	const u64 *variable_pin_cfg;283	unsigned int n_variable_pin_cfg;284	unsigned int num_custom_params;285	const struct pinconf_generic_params *custom_params;286#ifdef CONFIG_DEBUG_FS287	const struct pin_config_item *custom_conf_items;288#endif289	void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);290	void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);291	u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);292	int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);293	int (*hw_to_bias_param)(unsigned int val);294	int (*bias_param_to_hw)(enum pin_config_param param);295};296 297/**298 * struct rzg2l_pinctrl_pin_settings - pin data299 * @power_source: power source300 * @drive_strength_ua: drive strength (in micro amps)301 */302struct rzg2l_pinctrl_pin_settings {303	u16 power_source;304	u16 drive_strength_ua;305};306 307/**308 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume)309 * @p: P registers cache310 * @pm: PM registers cache311 * @pmc: PMC registers cache312 * @pfc: PFC registers cache313 * @iolh: IOLH registers cache314 * @ien: IEN registers cache315 * @sd_ch: SD_CH registers cache316 * @eth_poc: ET_POC registers cache317 * @eth_mode: ETH_MODE register cache318 * @qspi: QSPI registers cache319 */320struct rzg2l_pinctrl_reg_cache {321	u8	*p;322	u16	*pm;323	u8	*pmc;324	u32	*pfc;325	u32	*iolh[2];326	u32	*ien[2];327	u8	sd_ch[2];328	u8	eth_poc[2];329	u8	eth_mode;330	u8	qspi;331};332 333struct rzg2l_pinctrl {334	struct pinctrl_dev		*pctl;335	struct pinctrl_desc		desc;336	struct pinctrl_pin_desc		*pins;337 338	const struct rzg2l_pinctrl_data	*data;339	void __iomem			*base;340	struct device			*dev;341 342	struct clk			*clk;343 344	struct gpio_chip		gpio_chip;345	struct pinctrl_gpio_range	gpio_range;346	DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);347	spinlock_t			bitmap_lock; /* protect tint_slot bitmap */348	unsigned int			hwirq[RZG2L_TINT_MAX_INTERRUPT];349 350	spinlock_t			lock; /* lock read/write registers */351	struct mutex			mutex; /* serialize adding groups and functions */352 353	struct rzg2l_pinctrl_pin_settings *settings;354	struct rzg2l_pinctrl_reg_cache	*cache;355	struct rzg2l_pinctrl_reg_cache	*dedicated_cache;356	atomic_t			wakeup_path;357};358 359static const u16 available_ps[] = { 1800, 2500, 3300 };360 361static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,362					      u64 pincfg,363					      unsigned int port,364					      u8 pin)365{366	unsigned int i;367 368	for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {369		u64 cfg = pctrl->data->variable_pin_cfg[i];370 371		if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&372		    FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin)373			return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg);374	}375 376	return 0;377}378 379static const u64 r9a09g057_variable_pin_cfg[] = {380	RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS),381	RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),382	RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),383	RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),384	RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),385	RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),386};387 388#ifdef CONFIG_RISCV389static const u64 r9a07g043f_variable_pin_cfg[] = {390	RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |391					   PIN_CFG_NF |392					   PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),393	RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |394					   PIN_CFG_NF |395					   PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),396	RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |397					   PIN_CFG_NF |398					   PIN_CFG_IEN  | PIN_CFG_NOGPIO_INT),399	RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |400					   PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),401	RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |402					   PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),403	RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |404					   PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),405	RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |406					   PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),407	RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |408					   PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),409	RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |410					   PIN_CFG_NOGPIO_INT),411	RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |412					   PIN_CFG_NOGPIO_INT),413	RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |414					   PIN_CFG_NOGPIO_INT),415	RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |416					   PIN_CFG_NOGPIO_INT),417	RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),418	RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),419	RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |420					   PIN_CFG_NOGPIO_INT),421	RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |422					   PIN_CFG_NOGPIO_INT),423	RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |424					   PIN_CFG_NOGPIO_INT),425	RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |426					   PIN_CFG_NOGPIO_INT),427	RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |428					   PIN_CFG_NF |429					   PIN_CFG_NOGPIO_INT),430};431#endif432 433static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)434{435	writeb(val, pctrl->base + offset);436}437 438static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)439{440	const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;441	u8 pwpr;442 443	pwpr = readb(pctrl->base + regs->pwpr);444	writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr);445	writeb(val, pctrl->base + offset);446	writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);447}448 449static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,450				       u8 pin, u8 off, u8 func)451{452	unsigned long flags;453	u32 reg;454 455	spin_lock_irqsave(&pctrl->lock, flags);456 457	/* Set pin to 'Non-use (Hi-Z input protection)'  */458	reg = readw(pctrl->base + PM(off));459	reg &= ~(PM_MASK << (pin * 2));460	writew(reg, pctrl->base + PM(off));461 462	pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);463 464	/* Temporarily switch to GPIO mode with PMC register */465	reg = readb(pctrl->base + PMC(off));466	writeb(reg & ~BIT(pin), pctrl->base + PMC(off));467 468	/* Select Pin function mode with PFC register */469	reg = readl(pctrl->base + PFC(off));470	reg &= ~(PFC_MASK << (pin * 4));471	writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));472 473	/* Switch to Peripheral pin function with PMC register */474	reg = readb(pctrl->base + PMC(off));475	writeb(reg | BIT(pin), pctrl->base + PMC(off));476 477	pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);478 479	spin_unlock_irqrestore(&pctrl->lock, flags);480};481 482static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,483				 unsigned int func_selector,484				 unsigned int group_selector)485{486	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);487	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;488	struct function_desc *func;489	unsigned int i, *psel_val;490	struct group_desc *group;491	const unsigned int *pins;492 493	func = pinmux_generic_get_function(pctldev, func_selector);494	if (!func)495		return -EINVAL;496	group = pinctrl_generic_get_group(pctldev, group_selector);497	if (!group)498		return -EINVAL;499 500	psel_val = func->data;501	pins = group->grp.pins;502 503	for (i = 0; i < group->grp.npins; i++) {504		u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data;505		u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);506		u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);507 508		dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",509			RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);510 511		rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base);512	}513 514	return 0;515};516 517static int rzg2l_map_add_config(struct pinctrl_map *map,518				const char *group_or_pin,519				enum pinctrl_map_type type,520				unsigned long *configs,521				unsigned int num_configs)522{523	unsigned long *cfgs;524 525	cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);526	if (!cfgs)527		return -ENOMEM;528 529	map->type = type;530	map->data.configs.group_or_pin = group_or_pin;531	map->data.configs.configs = cfgs;532	map->data.configs.num_configs = num_configs;533 534	return 0;535}536 537static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,538				   struct device_node *np,539				   struct device_node *parent,540				   struct pinctrl_map **map,541				   unsigned int *num_maps,542				   unsigned int *index)543{544	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);545	struct pinctrl_map *maps = *map;546	unsigned int nmaps = *num_maps;547	unsigned long *configs = NULL;548	unsigned int *pins, *psel_val;549	unsigned int num_pinmux = 0;550	unsigned int idx = *index;551	unsigned int num_pins, i;552	unsigned int num_configs;553	struct property *pinmux;554	struct property *prop;555	int ret, gsel, fsel;556	const char **pin_fn;557	const char *name;558	const char *pin;559 560	pinmux = of_find_property(np, "pinmux", NULL);561	if (pinmux)562		num_pinmux = pinmux->length / sizeof(u32);563 564	ret = of_property_count_strings(np, "pins");565	if (ret == -EINVAL) {566		num_pins = 0;567	} else if (ret < 0) {568		dev_err(pctrl->dev, "Invalid pins list in DT\n");569		return ret;570	} else {571		num_pins = ret;572	}573 574	if (!num_pinmux && !num_pins)575		return 0;576 577	if (num_pinmux && num_pins) {578		dev_err(pctrl->dev,579			"DT node must contain either a pinmux or pins and not both\n");580		return -EINVAL;581	}582 583	ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);584	if (ret < 0)585		return ret;586 587	if (num_pins && !num_configs) {588		dev_err(pctrl->dev, "DT node must contain a config\n");589		ret = -ENODEV;590		goto done;591	}592 593	if (num_pinmux) {594		nmaps += 1;595		if (num_configs)596			nmaps += 1;597	}598 599	if (num_pins)600		nmaps += num_pins;601 602	maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);603	if (!maps) {604		ret = -ENOMEM;605		goto done;606	}607 608	*map = maps;609	*num_maps = nmaps;610	if (num_pins) {611		of_property_for_each_string(np, "pins", prop, pin) {612			ret = rzg2l_map_add_config(&maps[idx], pin,613						   PIN_MAP_TYPE_CONFIGS_PIN,614						   configs, num_configs);615			if (ret < 0)616				goto done;617 618			idx++;619		}620		ret = 0;621		goto done;622	}623 624	pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);625	psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),626				GFP_KERNEL);627	pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);628	if (!pins || !psel_val || !pin_fn) {629		ret = -ENOMEM;630		goto done;631	}632 633	/* Collect pin locations and mux settings from DT properties */634	for (i = 0; i < num_pinmux; ++i) {635		u32 value;636 637		ret = of_property_read_u32_index(np, "pinmux", i, &value);638		if (ret)639			goto done;640		pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value);641		psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value);642	}643 644	if (parent) {645		name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",646				      parent, np);647		if (!name) {648			ret = -ENOMEM;649			goto done;650		}651	} else {652		name = np->name;653	}654 655	if (num_configs) {656		ret = rzg2l_map_add_config(&maps[idx], name,657					   PIN_MAP_TYPE_CONFIGS_GROUP,658					   configs, num_configs);659		if (ret < 0)660			goto done;661 662		idx++;663	}664 665	mutex_lock(&pctrl->mutex);666 667	/* Register a single pin group listing all the pins we read from DT */668	gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);669	if (gsel < 0) {670		ret = gsel;671		goto unlock;672	}673 674	/*675	 * Register a single group function where the 'data' is an array PSEL676	 * register values read from DT.677	 */678	pin_fn[0] = name;679	fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);680	if (fsel < 0) {681		ret = fsel;682		goto remove_group;683	}684 685	mutex_unlock(&pctrl->mutex);686 687	maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;688	maps[idx].data.mux.group = name;689	maps[idx].data.mux.function = name;690	idx++;691 692	dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);693	ret = 0;694	goto done;695 696remove_group:697	pinctrl_generic_remove_group(pctldev, gsel);698unlock:699	mutex_unlock(&pctrl->mutex);700done:701	*index = idx;702	kfree(configs);703	return ret;704}705 706static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev,707			      struct pinctrl_map *map,708			      unsigned int num_maps)709{710	unsigned int i;711 712	if (!map)713		return;714 715	for (i = 0; i < num_maps; ++i) {716		if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||717		    map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)718			kfree(map[i].data.configs.configs);719	}720	kfree(map);721}722 723static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,724				struct device_node *np,725				struct pinctrl_map **map,726				unsigned int *num_maps)727{728	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);729	unsigned int index;730	int ret;731 732	*map = NULL;733	*num_maps = 0;734	index = 0;735 736	for_each_child_of_node_scoped(np, child) {737		ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map,738					      num_maps, &index);739		if (ret < 0)740			goto done;741	}742 743	if (*num_maps == 0) {744		ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map,745					      num_maps, &index);746		if (ret < 0)747			goto done;748	}749 750	if (*num_maps)751		return 0;752 753	dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);754	ret = -EINVAL;755 756done:757	rzg2l_dt_free_map(pctldev, *map, *num_maps);758 759	return ret;760}761 762static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,763				   u64 cfg, u32 port, u8 bit)764{765	u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);766	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);767	u64 data;768 769	if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)770		return -EINVAL;771 772	data = pctrl->data->port_pin_configs[port];773	if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))774		return -EINVAL;775 776	return 0;777}778 779static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,780				 u8 bit, u32 mask)781{782	void __iomem *addr = pctrl->base + offset;783 784	/* handle _L/_H for 32-bit register read/write */785	if (bit >= 4) {786		bit -= 4;787		addr += 4;788	}789 790	return (readl(addr) >> (bit * 8)) & mask;791}792 793static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,794				 u8 bit, u32 mask, u32 val)795{796	void __iomem *addr = pctrl->base + offset;797	unsigned long flags;798	u32 reg;799 800	/* handle _L/_H for 32-bit register read/write */801	if (bit >= 4) {802		bit -= 4;803		addr += 4;804	}805 806	spin_lock_irqsave(&pctrl->lock, flags);807	reg = readl(addr) & ~(mask << (bit * 8));808	writel(reg | (val << (bit * 8)), addr);809	spin_unlock_irqrestore(&pctrl->lock, flags);810}811 812static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps)813{814	if (caps & PIN_CFG_IO_VMC_SD0)815		return SD_CH(regs->sd_ch, 0);816	if (caps & PIN_CFG_IO_VMC_SD1)817		return SD_CH(regs->sd_ch, 1);818	if (caps & PIN_CFG_IO_VMC_ETH0)819		return ETH_POC(regs->eth_poc, 0);820	if (caps & PIN_CFG_IO_VMC_ETH1)821		return ETH_POC(regs->eth_poc, 1);822	if (caps & PIN_CFG_IO_VMC_QSPI)823		return QSPI;824 825	return -EINVAL;826}827 828static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps)829{830	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;831	const struct rzg2l_register_offsets *regs = &hwcfg->regs;832	int pwr_reg;833	u8 val;834 835	if (caps & PIN_CFG_SOFT_PS)836		return pctrl->settings[pin].power_source;837 838	pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);839	if (pwr_reg < 0)840		return pwr_reg;841 842	val = readb(pctrl->base + pwr_reg);843	switch (val) {844	case PVDD_1800:845		return 1800;846	case PVDD_2500:847		return 2500;848	case PVDD_3300:849		return 3300;850	default:851		/* Should not happen. */852		return -EINVAL;853	}854}855 856static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)857{858	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;859	const struct rzg2l_register_offsets *regs = &hwcfg->regs;860	int pwr_reg;861	u8 val;862 863	if (caps & PIN_CFG_SOFT_PS) {864		pctrl->settings[pin].power_source = ps;865		return 0;866	}867 868	switch (ps) {869	case 1800:870		val = PVDD_1800;871		break;872	case 2500:873		if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))874			return -EINVAL;875		val = PVDD_2500;876		break;877	case 3300:878		val = PVDD_3300;879		break;880	default:881		return -EINVAL;882	}883 884	pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);885	if (pwr_reg < 0)886		return pwr_reg;887 888	writeb(val, pctrl->base + pwr_reg);889	pctrl->settings[pin].power_source = ps;890 891	return 0;892}893 894static bool rzg2l_ps_is_supported(u16 ps)895{896	unsigned int i;897 898	for (i = 0; i < ARRAY_SIZE(available_ps); i++) {899		if (available_ps[i] == ps)900			return true;901	}902 903	return false;904}905 906static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps)907{908	unsigned int i;909 910	for (i = 0; i < ARRAY_SIZE(available_ps); i++) {911		if (available_ps[i] == ps)912			break;913	}914 915	/*916	 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have917	 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source918	 */919	return i * RZG2L_IOLH_MAX_DS_ENTRIES;920}921 922static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val)923{924	if (caps & PIN_CFG_IOLH_A)925		return hwcfg->iolh_groupa_ua[val];926 927	if (caps & PIN_CFG_IOLH_B)928		return hwcfg->iolh_groupb_ua[val];929 930	if (caps & PIN_CFG_IOLH_C)931		return hwcfg->iolh_groupc_ua[val];932 933	/* Should not happen. */934	return 0;935}936 937static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps,938				enum rzg2l_iolh_index ps_index, u16 ua)939{940	const u16 *array = NULL;941	unsigned int i;942 943	if (caps & PIN_CFG_IOLH_A)944		array = &hwcfg->iolh_groupa_ua[ps_index];945 946	if (caps & PIN_CFG_IOLH_B)947		array = &hwcfg->iolh_groupb_ua[ps_index];948 949	if (caps & PIN_CFG_IOLH_C)950		array = &hwcfg->iolh_groupc_ua[ps_index];951 952	if (!array)953		return -EINVAL;954 955	for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {956		if (array[i] == ua)957			return i;958	}959 960	return -EINVAL;961}962 963static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,964				  enum rzg2l_iolh_index iolh_idx,965				  u16 ds)966{967	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;968	const u16 *array = NULL;969	unsigned int i;970 971	if (caps & PIN_CFG_IOLH_A)972		array = hwcfg->iolh_groupa_ua;973 974	if (caps & PIN_CFG_IOLH_B)975		array = hwcfg->iolh_groupb_ua;976 977	if (caps & PIN_CFG_IOLH_C)978		array = hwcfg->iolh_groupc_ua;979 980	/* Should not happen. */981	if (!array)982		return false;983 984	if (!array[iolh_idx])985		return false;986 987	for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {988		if (array[iolh_idx + i] == ds)989			return true;990	}991 992	return false;993}994 995static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)996{997	u64 *pin_data = pctrl->desc.pins[_pin].drv_data;998	u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);999	u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);1000 1001	if (pin > pctrl->data->hwcfg->oen_max_pin)1002		return -EINVAL;1003 1004	/*1005	 * We can determine which Ethernet interface we're dealing with from1006	 * the caps.1007	 */1008	if (caps & PIN_CFG_IO_VMC_ETH0)1009		return 0;1010	if (caps & PIN_CFG_IO_VMC_ETH1)1011		return 1;1012 1013	return -EINVAL;1014}1015 1016static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)1017{1018	int bit;1019 1020	bit = rzg2l_pin_to_oen_bit(pctrl, _pin);1021	if (bit < 0)1022		return 0;1023 1024	return !(readb(pctrl->base + ETH_MODE) & BIT(bit));1025}1026 1027static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)1028{1029	unsigned long flags;1030	int bit;1031	u8 val;1032 1033	bit = rzg2l_pin_to_oen_bit(pctrl, _pin);1034	if (bit < 0)1035		return bit;1036 1037	spin_lock_irqsave(&pctrl->lock, flags);1038	val = readb(pctrl->base + ETH_MODE);1039	if (oen)1040		val &= ~BIT(bit);1041	else1042		val |= BIT(bit);1043	writeb(val, pctrl->base + ETH_MODE);1044	spin_unlock_irqrestore(&pctrl->lock, flags);1045 1046	return 0;1047}1048 1049static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)1050{1051	u64 *pin_data = pctrl->desc.pins[_pin].drv_data;1052	u8 port, pin, bit;1053 1054	if (*pin_data & RZG2L_SINGLE_PIN)1055		return -EINVAL;1056 1057	port = RZG2L_PIN_ID_TO_PORT(_pin);1058	pin = RZG2L_PIN_ID_TO_PIN(_pin);1059	if (pin > pctrl->data->hwcfg->oen_max_pin)1060		return -EINVAL;1061 1062	bit = pin * 2;1063	if (port == pctrl->data->hwcfg->oen_max_port)1064		bit += 1;1065 1066	return bit;1067}1068 1069static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)1070{1071	int bit;1072 1073	bit = rzg3s_pin_to_oen_bit(pctrl, _pin);1074	if (bit < 0)1075		return bit;1076 1077	return !(readb(pctrl->base + ETH_MODE) & BIT(bit));1078}1079 1080static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)1081{1082	unsigned long flags;1083	int bit;1084	u8 val;1085 1086	bit = rzg3s_pin_to_oen_bit(pctrl, _pin);1087	if (bit < 0)1088		return bit;1089 1090	spin_lock_irqsave(&pctrl->lock, flags);1091	val = readb(pctrl->base + ETH_MODE);1092	if (oen)1093		val &= ~BIT(bit);1094	else1095		val |= BIT(bit);1096	writeb(val, pctrl->base + ETH_MODE);1097	spin_unlock_irqrestore(&pctrl->lock, flags);1098 1099	return 0;1100}1101 1102static int rzg2l_hw_to_bias_param(unsigned int bias)1103{1104	switch (bias) {1105	case 0:1106		return PIN_CONFIG_BIAS_DISABLE;1107	case 1:1108		return PIN_CONFIG_BIAS_PULL_UP;1109	case 2:1110		return PIN_CONFIG_BIAS_PULL_DOWN;1111	default:1112		break;1113	}1114 1115	return -EINVAL;1116}1117 1118static int rzg2l_bias_param_to_hw(enum pin_config_param param)1119{1120	switch (param) {1121	case PIN_CONFIG_BIAS_DISABLE:1122		return 0;1123	case PIN_CONFIG_BIAS_PULL_UP:1124		return 1;1125	case PIN_CONFIG_BIAS_PULL_DOWN:1126		return 2;1127	default:1128		break;1129	}1130 1131	return -EINVAL;1132}1133 1134static int rzv2h_hw_to_bias_param(unsigned int bias)1135{1136	switch (bias) {1137	case 0:1138	case 1:1139		return PIN_CONFIG_BIAS_DISABLE;1140	case 2:1141		return PIN_CONFIG_BIAS_PULL_DOWN;1142	case 3:1143		return PIN_CONFIG_BIAS_PULL_UP;1144	default:1145		break;1146	}1147 1148	return -EINVAL;1149}1150 1151static int rzv2h_bias_param_to_hw(enum pin_config_param param)1152{1153	switch (param) {1154	case PIN_CONFIG_BIAS_DISABLE:1155		return 0;1156	case PIN_CONFIG_BIAS_PULL_DOWN:1157		return 2;1158	case PIN_CONFIG_BIAS_PULL_UP:1159		return 3;1160	default:1161		break;1162	}1163 1164	return -EINVAL;1165}1166 1167static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)1168{1169	static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",1170						  "XSPI0_RESET0N", "XSPI0_CS0N",1171						  "XSPI0_CKN", "XSPI0_CKP" };1172	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];1173	unsigned int i;1174 1175	for (i = 0; i < ARRAY_SIZE(pin_names); i++) {1176		if (!strcmp(pin_desc->name, pin_names[i]))1177			return i;1178	}1179 1180	/* Should not happen. */1181	return 0;1182}1183 1184static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)1185{1186	u8 bit;1187 1188	bit = rzv2h_pin_to_oen_bit(pctrl, _pin);1189 1190	return !(readb(pctrl->base + PFC_OEN) & BIT(bit));1191}1192 1193static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)1194{1195	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;1196	const struct rzg2l_register_offsets *regs = &hwcfg->regs;1197	unsigned long flags;1198	u8 val, bit;1199	u8 pwpr;1200 1201	bit = rzv2h_pin_to_oen_bit(pctrl, _pin);1202	spin_lock_irqsave(&pctrl->lock, flags);1203	val = readb(pctrl->base + PFC_OEN);1204	if (oen)1205		val &= ~BIT(bit);1206	else1207		val |= BIT(bit);1208 1209	pwpr = readb(pctrl->base + regs->pwpr);1210	writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);1211	writeb(val, pctrl->base + PFC_OEN);1212	writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);1213	spin_unlock_irqrestore(&pctrl->lock, flags);1214 1215	return 0;1216}1217 1218static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,1219				     unsigned int _pin,1220				     unsigned long *config)1221{1222	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);1223	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;1224	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];1225	u32 param = pinconf_to_config_param(*config);1226	u64 *pin_data = pin->drv_data;1227	unsigned int arg = 0;1228	u32 off;1229	u32 cfg;1230	int ret;1231	u8 bit;1232 1233	if (!pin_data)1234		return -EINVAL;1235 1236	off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);1237	cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);1238	if (*pin_data & RZG2L_SINGLE_PIN) {1239		bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);1240	} else {1241		bit = RZG2L_PIN_ID_TO_PIN(_pin);1242 1243		if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))1244			return -EINVAL;1245	}1246 1247	switch (param) {1248	case PIN_CONFIG_INPUT_ENABLE:1249		if (!(cfg & PIN_CFG_IEN))1250			return -EINVAL;1251		arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK);1252		if (!arg)1253			return -EINVAL;1254		break;1255 1256	case PIN_CONFIG_OUTPUT_ENABLE:1257		if (!(cfg & PIN_CFG_OEN))1258			return -EINVAL;1259		if (!pctrl->data->oen_read)1260			return -EOPNOTSUPP;1261		arg = pctrl->data->oen_read(pctrl, _pin);1262		if (!arg)1263			return -EINVAL;1264		break;1265 1266	case PIN_CONFIG_POWER_SOURCE:1267		ret = rzg2l_get_power_source(pctrl, _pin, cfg);1268		if (ret < 0)1269			return ret;1270		arg = ret;1271		break;1272 1273	case PIN_CONFIG_SLEW_RATE:1274		if (!(cfg & PIN_CFG_SR))1275			return -EINVAL;1276 1277		arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK);1278		break;1279 1280	case PIN_CONFIG_BIAS_DISABLE:1281	case PIN_CONFIG_BIAS_PULL_UP:1282	case PIN_CONFIG_BIAS_PULL_DOWN:1283		if (!(cfg & PIN_CFG_PUPD))1284			return -EINVAL;1285 1286		arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK);1287		ret = pctrl->data->hw_to_bias_param(arg);1288		if (ret < 0)1289			return ret;1290 1291		if (ret != param)1292			return -EINVAL;1293		/* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */1294		arg = 1;1295		break;1296 1297	case PIN_CONFIG_DRIVE_STRENGTH: {1298		unsigned int index;1299 1300		if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)1301			return -EINVAL;1302 1303		index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);1304		/*1305		 * Drive strenght mA is supported only by group A and only1306		 * for 3V3 port source.1307		 */1308		arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000;1309		break;1310	}1311 1312	case PIN_CONFIG_DRIVE_STRENGTH_UA: {1313		enum rzg2l_iolh_index iolh_idx;1314		u8 val;1315 1316		if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||1317		    !hwcfg->drive_strength_ua)1318			return -EINVAL;1319 1320		ret = rzg2l_get_power_source(pctrl, _pin, cfg);1321		if (ret < 0)1322			return ret;1323		iolh_idx = rzg2l_ps_to_iolh_idx(ret);1324		val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);1325		arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val);1326		break;1327	}1328 1329	case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {1330		unsigned int index;1331 1332		if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])1333			return -EINVAL;1334 1335		index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);1336		arg = hwcfg->iolh_groupb_oi[index];1337		break;1338	}1339 1340	case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:1341		if (!(cfg & PIN_CFG_IOLH_RZV2H))1342			return -EINVAL;1343 1344		arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);1345		break;1346 1347	default:1348		return -ENOTSUPP;1349	}1350 1351	*config = pinconf_to_config_packed(param, arg);1352 1353	return 0;1354};1355 1356static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,1357				     unsigned int _pin,1358				     unsigned long *_configs,1359				     unsigned int num_configs)1360{1361	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);1362	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];1363	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;1364	struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];1365	u64 *pin_data = pin->drv_data;1366	unsigned int i, arg, index;1367	u32 off, param;1368	u32 cfg;1369	int ret;1370	u8 bit;1371 1372	if (!pin_data)1373		return -EINVAL;1374 1375	off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);1376	cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);1377	if (*pin_data & RZG2L_SINGLE_PIN) {1378		bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);1379	} else {1380		bit = RZG2L_PIN_ID_TO_PIN(_pin);1381 1382		if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))1383			return -EINVAL;1384	}1385 1386	for (i = 0; i < num_configs; i++) {1387		param = pinconf_to_config_param(_configs[i]);1388		arg = pinconf_to_config_argument(_configs[i]);1389		switch (param) {1390		case PIN_CONFIG_INPUT_ENABLE:1391 1392			if (!(cfg & PIN_CFG_IEN))1393				return -EINVAL;1394 1395			rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg);1396			break;1397 1398		case PIN_CONFIG_OUTPUT_ENABLE:1399			if (!(cfg & PIN_CFG_OEN))1400				return -EINVAL;1401			if (!pctrl->data->oen_write)1402				return -EOPNOTSUPP;1403			ret = pctrl->data->oen_write(pctrl, _pin, !!arg);1404			if (ret)1405				return ret;1406			break;1407 1408		case PIN_CONFIG_POWER_SOURCE:1409			settings.power_source = arg;1410			break;1411 1412		case PIN_CONFIG_SLEW_RATE:1413			if (!(cfg & PIN_CFG_SR) || arg > 1)1414				return -EINVAL;1415 1416			rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg);1417			break;1418 1419		case PIN_CONFIG_BIAS_DISABLE:1420		case PIN_CONFIG_BIAS_PULL_UP:1421		case PIN_CONFIG_BIAS_PULL_DOWN:1422			if (!(cfg & PIN_CFG_PUPD))1423				return -EINVAL;1424 1425			ret = pctrl->data->bias_param_to_hw(param);1426			if (ret < 0)1427				return ret;1428 1429			rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret);1430			break;1431 1432		case PIN_CONFIG_DRIVE_STRENGTH:1433			if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)1434				return -EINVAL;1435 1436			for (index = RZG2L_IOLH_IDX_3V3;1437			     index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) {1438				if (arg == (hwcfg->iolh_groupa_ua[index] / 1000))1439					break;1440			}1441			if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES))1442				return -EINVAL;1443 1444			rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);1445			break;1446 1447		case PIN_CONFIG_DRIVE_STRENGTH_UA:1448			if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||1449			    !hwcfg->drive_strength_ua)1450				return -EINVAL;1451 1452			settings.drive_strength_ua = arg;1453			break;1454 1455		case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:1456			if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])1457				return -EINVAL;1458 1459			for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) {1460				if (arg == hwcfg->iolh_groupb_oi[index])1461					break;1462			}1463			if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi))1464				return -EINVAL;1465 1466			rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);1467			break;1468 1469		case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:1470			if (!(cfg & PIN_CFG_IOLH_RZV2H))1471				return -EINVAL;1472 1473			if (arg > 3)1474				return -EINVAL;1475			rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg);1476			break;1477 1478		default:1479			return -EOPNOTSUPP;1480		}1481	}1482 1483	/* Apply power source. */1484	if (settings.power_source != pctrl->settings[_pin].power_source) {1485		ret = rzg2l_ps_is_supported(settings.power_source);1486		if (!ret)1487			return -EINVAL;1488 1489		/* Apply power source. */1490		ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source);1491		if (ret)1492			return ret;1493	}1494 1495	/* Apply drive strength. */1496	if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) {1497		enum rzg2l_iolh_index iolh_idx;1498		int val;1499 1500		iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source);1501		ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx,1502					    settings.drive_strength_ua);1503		if (!ret)1504			return -EINVAL;1505 1506		/* Get register value for this PS/DS tuple. */1507		val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua);1508		if (val < 0)1509			return val;1510 1511		/* Apply drive strength. */1512		rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val);1513		pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua;1514	}1515 1516	return 0;1517}1518 1519static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,1520					   unsigned int group,1521					   unsigned long *configs,1522					   unsigned int num_configs)1523{1524	const unsigned int *pins;1525	unsigned int i, npins;1526	int ret;1527 1528	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);1529	if (ret)1530		return ret;1531 1532	for (i = 0; i < npins; i++) {1533		ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs,1534						num_configs);1535		if (ret)1536			return ret;1537	}1538 1539	return 0;1540};1541 1542static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,1543					   unsigned int group,1544					   unsigned long *config)1545{1546	const unsigned int *pins;1547	unsigned int i, npins, prev_config = 0;1548	int ret;1549 1550	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);1551	if (ret)1552		return ret;1553 1554	for (i = 0; i < npins; i++) {1555		ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config);1556		if (ret)1557			return ret;1558 1559		/* Check config matching between to pin  */1560		if (i && prev_config != *config)1561			return -EOPNOTSUPP;1562 1563		prev_config = *config;1564	}1565 1566	return 0;1567};1568 1569static const struct pinctrl_ops rzg2l_pinctrl_pctlops = {1570	.get_groups_count = pinctrl_generic_get_group_count,1571	.get_group_name = pinctrl_generic_get_group_name,1572	.get_group_pins = pinctrl_generic_get_group_pins,1573	.dt_node_to_map = rzg2l_dt_node_to_map,1574	.dt_free_map = rzg2l_dt_free_map,1575};1576 1577static const struct pinmux_ops rzg2l_pinctrl_pmxops = {1578	.get_functions_count = pinmux_generic_get_function_count,1579	.get_function_name = pinmux_generic_get_function_name,1580	.get_function_groups = pinmux_generic_get_function_groups,1581	.set_mux = rzg2l_pinctrl_set_mux,1582	.strict = true,1583};1584 1585static const struct pinconf_ops rzg2l_pinctrl_confops = {1586	.is_generic = true,1587	.pin_config_get = rzg2l_pinctrl_pinconf_get,1588	.pin_config_set = rzg2l_pinctrl_pinconf_set,1589	.pin_config_group_set = rzg2l_pinctrl_pinconf_group_set,1590	.pin_config_group_get = rzg2l_pinctrl_pinconf_group_get,1591	.pin_config_config_dbg_show = pinconf_generic_dump_config,1592};1593 1594static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)1595{1596	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);1597	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];1598	u64 *pin_data = pin_desc->drv_data;1599	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);1600	u32 port = RZG2L_PIN_ID_TO_PORT(offset);1601	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);1602	unsigned long flags;1603	u8 reg8;1604	int ret;1605 1606	ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);1607	if (ret)1608		return ret;1609 1610	ret = pinctrl_gpio_request(chip, offset);1611	if (ret)1612		return ret;1613 1614	spin_lock_irqsave(&pctrl->lock, flags);1615 1616	/* Select GPIO mode in PMC Register */1617	reg8 = readb(pctrl->base + PMC(off));1618	reg8 &= ~BIT(bit);1619	pctrl->data->pmc_writeb(pctrl, reg8, PMC(off));1620 1621	spin_unlock_irqrestore(&pctrl->lock, flags);1622 1623	return 0;1624}1625 1626static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,1627				     bool output)1628{1629	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];1630	u64 *pin_data = pin_desc->drv_data;1631	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);1632	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);1633	unsigned long flags;1634	u16 reg16;1635 1636	spin_lock_irqsave(&pctrl->lock, flags);1637 1638	reg16 = readw(pctrl->base + PM(off));1639	reg16 &= ~(PM_MASK << (bit * 2));1640 1641	reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);1642	writew(reg16, pctrl->base + PM(off));1643 1644	spin_unlock_irqrestore(&pctrl->lock, flags);1645}1646 1647static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)1648{1649	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);1650	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];1651	u64 *pin_data = pin_desc->drv_data;1652	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);1653	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);1654 1655	if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) {1656		u16 reg16;1657 1658		reg16 = readw(pctrl->base + PM(off));1659		reg16 = (reg16 >> (bit * 2)) & PM_MASK;1660		if (reg16 == PM_OUTPUT)1661			return GPIO_LINE_DIRECTION_OUT;1662	}1663 1664	return GPIO_LINE_DIRECTION_IN;1665}1666 1667static int rzg2l_gpio_direction_input(struct gpio_chip *chip,1668				      unsigned int offset)1669{1670	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);1671 1672	rzg2l_gpio_set_direction(pctrl, offset, false);1673 1674	return 0;1675}1676 1677static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,1678			   int value)1679{1680	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);1681	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];1682	u64 *pin_data = pin_desc->drv_data;1683	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);1684	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);1685	unsigned long flags;1686	u8 reg8;1687 1688	spin_lock_irqsave(&pctrl->lock, flags);1689 1690	reg8 = readb(pctrl->base + P(off));1691 1692	if (value)1693		writeb(reg8 | BIT(bit), pctrl->base + P(off));1694	else1695		writeb(reg8 & ~BIT(bit), pctrl->base + P(off));1696 1697	spin_unlock_irqrestore(&pctrl->lock, flags);1698}1699 1700static int rzg2l_gpio_direction_output(struct gpio_chip *chip,1701				       unsigned int offset, int value)1702{1703	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);1704 1705	rzg2l_gpio_set(chip, offset, value);1706	rzg2l_gpio_set_direction(pctrl, offset, true);1707 1708	return 0;1709}1710 1711static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)1712{1713	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);1714	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];1715	u64 *pin_data = pin_desc->drv_data;1716	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);1717	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);1718	u16 reg16;1719 1720	reg16 = readw(pctrl->base + PM(off));1721	reg16 = (reg16 >> (bit * 2)) & PM_MASK;1722 1723	if (reg16 == PM_INPUT)1724		return !!(readb(pctrl->base + PIN(off)) & BIT(bit));1725	else if (reg16 == PM_OUTPUT)1726		return !!(readb(pctrl->base + P(off)) & BIT(bit));1727	else1728		return -EINVAL;1729}1730 1731static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)1732{1733	unsigned int virq;1734 1735	pinctrl_gpio_free(chip, offset);1736 1737	virq = irq_find_mapping(chip->irq.domain, offset);1738	if (virq)1739		irq_dispose_mapping(virq);1740 1741	/*1742	 * Set the GPIO as an input to ensure that the next GPIO request won't1743	 * drive the GPIO pin as an output.1744	 */1745	rzg2l_gpio_direction_input(chip, offset);1746}1747 1748static const char * const rzg2l_gpio_names[] = {1749	"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",1750	"P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",1751	"P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",1752	"P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",1753	"P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",1754	"P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",1755	"P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",1756	"P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",1757	"P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",1758	"P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",1759	"P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",1760	"P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",1761	"P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",1762	"P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",1763	"P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",1764	"P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",1765	"P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",1766	"P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",1767	"P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",1768	"P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",1769	"P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",1770	"P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",1771	"P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",1772	"P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",1773	"P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",1774	"P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",1775	"P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",1776	"P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",1777	"P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",1778	"P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",1779	"P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",1780	"P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",1781	"P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",1782	"P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",1783	"P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",1784	"P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",1785	"P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7",1786	"P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7",1787	"P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7",1788	"P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7",1789	"P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7",1790	"P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7",1791	"P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7",1792	"P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7",1793	"P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7",1794	"P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7",1795	"P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7",1796	"P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7",1797	"P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",1798};1799 1800static const u64 r9a07g044_gpio_configs[] = {1801	RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),1802	RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),1803	RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),1804	RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),1805	RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),1806	RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),1807	RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),1808	RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),1809	RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),1810	RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),1811	RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),1812	RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),1813	RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),1814	RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),1815	RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),1816	RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),1817	RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),1818	RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),1819	RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),1820	RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),1821	RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),1822	RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1823	RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1824	RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1825	RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1826	RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1827	RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1828	RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1829	RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1830	RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),1831	RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1832	RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1833	RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1834	RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1835	RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1836	RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1837	RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1838	RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1839	RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),1840	RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),1841	RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),1842	RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),1843	RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),1844	RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),1845	RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),1846	RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),1847	RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),1848	RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),1849	RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),1850};1851 1852static const u64 r9a07g043_gpio_configs[] = {1853	RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),1854	RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),1855	RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1856	RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1857	RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),1858	RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),1859	RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),1860	RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),1861	RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1862	RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1863	RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),1864	RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),1865	RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),1866	RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),1867	RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),1868	RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),1869	RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),1870	RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),1871	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),1872#ifdef CONFIG_RISCV1873	/* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */1874	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |1875				    PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),	/* P19 */1876	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07),						/* P20 */1877	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |1878				    PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),			/* P21 */1879	RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |1880			     PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),				/* P22 */1881	RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a),				/* P23 */1882	RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b),						/* P24 */1883	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF |1884				    PIN_CFG_NOGPIO_INT),				/* P25 */1885	0x0,										/* P26 */1886	0x0,										/* P27 */1887	RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT),	/* P28 */1888#endif1889};1890 1891static const u64 r9a08g045_gpio_configs[] = {1892	RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)),			/* P0  */1893	RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |1894								PIN_CFG_IO_VMC_ETH0)) |1895				      PIN_CFG_OEN | PIN_CFG_IEN,			/* P1 */1896	RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |1897								PIN_CFG_IO_VMC_ETH0)),	/* P2 */1898	RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |1899								PIN_CFG_IO_VMC_ETH0)),	/* P3 */1900	RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |1901								PIN_CFG_IO_VMC_ETH0)),	/* P4 */1902	RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)),			/* P5  */1903	RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)),			/* P6  */1904	RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |1905								PIN_CFG_IO_VMC_ETH1)) |1906				      PIN_CFG_OEN | PIN_CFG_IEN,			/* P7 */1907	RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |1908								PIN_CFG_IO_VMC_ETH1)),	/* P8 */1909	RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |1910								PIN_CFG_IO_VMC_ETH1)),	/* P9 */1911	RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |1912								PIN_CFG_IO_VMC_ETH1)),	/* P10 */1913	RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),		/* P11  */1914	RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),		/* P12  */1915	RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)),			/* P13  */1916	RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)),			/* P14  */1917	RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)),			/* P15  */1918	RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)),			/* P16  */1919	RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)),			/* P17  */1920	RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)),			/* P18 */1921};1922 1923static const char * const rzv2h_gpio_names[] = {1924	"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",1925	"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",1926	"P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",1927	"P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",1928	"P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",1929	"P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",1930	"P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",1931	"P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",1932	"P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",1933	"P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97",1934	"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",1935	"PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",1936};1937 1938static const u64 r9a09g057_gpio_configs[] = {1939	RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS),	/* P0 */1940	RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS),	/* P1 */1941	RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |1942				      PIN_CFG_NOD),		/* P2 */1943	RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS),	/* P3 */1944	RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS),	/* P4 */1945	RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS),	/* P5 */1946	RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS |1947				      PIN_CFG_ELC),		/* P6 */1948	RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS),	/* P7 */1949	RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS |1950				      PIN_CFG_ELC),		/* P8 */1951	RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS),	/* P9 */1952	RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS),	/* PA */1953	RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b),			/* PB */1954};1955 1956static const struct {1957	struct rzg2l_dedicated_configs common[35];1958	struct rzg2l_dedicated_configs rzg2l_pins[7];1959} rzg2l_dedicated_pins = {1960	.common = {1961		{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },1962		{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,1963		 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },1964		{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,1965		 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },1966		{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },1967		{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },1968		{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,1969		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },1970		{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,1971		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },1972		{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,1973		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },1974		{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,1975		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },1976		{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,1977		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },1978		{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,1979		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },1980		{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,1981		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },1982		{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,1983		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },1984		{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,1985		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },1986		{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,1987		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },1988		{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,1989		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },1990		{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,1991		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },1992		{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,1993		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },1994		{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,1995		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },1996		{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,1997		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },1998		{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,1999		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },2000		{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,2001		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },2002		{ "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,2003		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2004		{ "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,2005		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2006		{ "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,2007		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2008		{ "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,2009		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2010		{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,2011		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2012		{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,2013		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2014		{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,2015		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2016		{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,2017		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2018		{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },2019		{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },2020		{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },2021		{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },2022		{ "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },2023	},2024	.rzg2l_pins = {2025		{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2026		{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,2027		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2028		{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,2029		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2030		{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,2031		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2032		{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,2033		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2034		{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,2035		 (PIN_CFG_IOLH_B | PIN_CFG_SR  | PIN_CFG_IO_VMC_QSPI)) },2036		{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,2037		 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },2038	}2039};2040 2041static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {2042	{ "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) },2043	{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |2044						      PIN_CFG_SOFT_PS)) },2045	{ "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },2046	{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },2047	{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },2048	{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2049						     PIN_CFG_IO_VMC_SD0)) },2050	{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },2051	{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2052						       PIN_CFG_IO_VMC_SD0)) },2053	{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2054						       PIN_CFG_IO_VMC_SD0)) },2055	{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2056						       PIN_CFG_IO_VMC_SD0)) },2057	{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2058						       PIN_CFG_IO_VMC_SD0)) },2059	{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2060						       PIN_CFG_IO_VMC_SD0)) },2061	{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2062						       PIN_CFG_IO_VMC_SD0)) },2063	{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2064						       PIN_CFG_IO_VMC_SD0)) },2065	{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2066						       PIN_CFG_IO_VMC_SD0)) },2067	{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },2068	{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2069						     PIN_CFG_IO_VMC_SD1)) },2070	{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2071						       PIN_CFG_IO_VMC_SD1)) },2072	{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2073						       PIN_CFG_IO_VMC_SD1)) },2074	{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2075						       PIN_CFG_IO_VMC_SD1)) },2076	{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |2077						       PIN_CFG_IO_VMC_SD1)) },2078};2079 2080static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {2081	{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },2082	{ "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2083						      PIN_CFG_IEN)) },2084	{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },2085	{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2086						     PIN_CFG_PUPD | PIN_CFG_NOD)) },2087	{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2088						     PIN_CFG_PUPD | PIN_CFG_NOD)) },2089	{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2090						     PIN_CFG_PUPD)) },2091	{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2092						     PIN_CFG_PUPD)) },2093	{ "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2094						      PIN_CFG_PUPD | PIN_CFG_OEN)) },2095	{ "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2096						      PIN_CFG_PUPD | PIN_CFG_OEN)) },2097	{ "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2098						       PIN_CFG_PUPD | PIN_CFG_OEN)) },2099	{ "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2100						     PIN_CFG_PUPD)) },2101	{ "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2102							  PIN_CFG_PUPD | PIN_CFG_OEN)) },2103	{ "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },2104	{ "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },2105	{ "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },2106	{ "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2107						      PIN_CFG_PUPD)) },2108	{ "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2109						      PIN_CFG_PUPD)) },2110	{ "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2111						      PIN_CFG_PUPD)) },2112	{ "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2113						      PIN_CFG_PUPD)) },2114	{ "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2115						      PIN_CFG_PUPD)) },2116	{ "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2117						      PIN_CFG_PUPD)) },2118	{ "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2119						      PIN_CFG_PUPD)) },2120	{ "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2121						      PIN_CFG_PUPD)) },2122	{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },2123	{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2124						   PIN_CFG_IEN | PIN_CFG_PUPD)) },2125	{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },2126	{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2127						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2128	{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2129						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2130	{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2131						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2132	{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2133						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2134	{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2135						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2136	{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2137						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2138	{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2139						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2140	{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2141						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2142	{ "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },2143	{ "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2144						   PIN_CFG_IEN | PIN_CFG_PUPD)) },2145	{ "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2146						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2147	{ "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2148						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2149	{ "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2150						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2151	{ "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2152						    PIN_CFG_IEN | PIN_CFG_PUPD)) },2153	{ "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },2154	{ "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },2155	{ "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2156						     PIN_CFG_IEN | PIN_CFG_PUPD)) },2157	{ "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2158						    PIN_CFG_PUPD)) },2159	{ "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },2160	{ "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2161							    PIN_CFG_PUPD)) },2162	{ "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2163						      PIN_CFG_PUPD)) },2164	{ "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },2165	{ "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },2166	{ "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2167							   PIN_CFG_PUPD | PIN_CFG_OEN)) },2168	{ "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },2169	{ "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },2170	{ "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2171						      PIN_CFG_PUPD)) },2172	{ "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2173						      PIN_CFG_PUPD)) },2174	{ "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2175						      PIN_CFG_PUPD)) },2176	{ "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2177						      PIN_CFG_PUPD)) },2178	{ "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },2179	{ "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },2180	{ "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },2181	{ "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },2182	{ "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2183						      PIN_CFG_IEN | PIN_CFG_PUPD)) },2184	{ "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2185						     PIN_CFG_PUPD)) },2186	{ "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },2187	{ "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2188							    PIN_CFG_PUPD)) },2189	{ "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2190						       PIN_CFG_PUPD)) },2191	{ "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },2192	{ "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },2193	{ "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2194							   PIN_CFG_PUPD | PIN_CFG_OEN)) },2195	{ "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },2196	{ "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },2197	{ "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2198						      PIN_CFG_PUPD)) },2199	{ "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2200						      PIN_CFG_PUPD)) },2201	{ "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2202						      PIN_CFG_PUPD)) },2203	{ "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |2204						      PIN_CFG_PUPD)) },2205	{ "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },2206	{ "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },2207	{ "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },2208	{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },2209};2210 2211static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)2212{2213	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];2214	const struct rzg2l_pinctrl_data *data = pctrl->data;2215	u64 *pin_data = pin_desc->drv_data;2216	unsigned int gpioint;2217	unsigned int i;2218	u32 port, bit;2219 2220	if (*pin_data & PIN_CFG_NOGPIO_INT)2221		return -EINVAL;2222 2223	port = virq / 8;2224	bit = virq % 8;2225 2226	if (port >= data->n_ports ||2227	    bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port])))2228		return -EINVAL;2229 2230	gpioint = bit;2231	for (i = 0; i < port; i++)2232		gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i]));2233 2234	return gpioint;2235}2236 2237static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl,2238				     unsigned int hwirq, bool enable)2239{2240	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];2241	u64 *pin_data = pin_desc->drv_data;2242	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);2243	u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);2244	unsigned long flags;2245	void __iomem *addr;2246 2247	addr = pctrl->base + ISEL(off);2248	if (bit >= 4) {2249		bit -= 4;2250		addr += 4;2251	}2252 2253	spin_lock_irqsave(&pctrl->lock, flags);2254	if (enable)2255		writel(readl(addr) | BIT(bit * 8), addr);2256	else2257		writel(readl(addr) & ~BIT(bit * 8), addr);2258	spin_unlock_irqrestore(&pctrl->lock, flags);2259}2260 2261static void rzg2l_gpio_irq_disable(struct irq_data *d)2262{2263	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);2264	unsigned int hwirq = irqd_to_hwirq(d);2265 2266	irq_chip_disable_parent(d);2267	gpiochip_disable_irq(gc, hwirq);2268}2269 2270static void rzg2l_gpio_irq_enable(struct irq_data *d)2271{2272	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);2273	unsigned int hwirq = irqd_to_hwirq(d);2274 2275	gpiochip_enable_irq(gc, hwirq);2276	irq_chip_enable_parent(d);2277}2278 2279static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type)2280{2281	return irq_chip_set_type_parent(d, type);2282}2283 2284static void rzg2l_gpio_irqc_eoi(struct irq_data *d)2285{2286	irq_chip_eoi_parent(d);2287}2288 2289static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)2290{2291	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);2292 2293	seq_printf(p, dev_name(gc->parent));2294}2295 2296static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on)2297{2298	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);2299	struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);2300	int ret;2301 2302	/* It should not happen. */2303	if (!data->parent_data)2304		return -EOPNOTSUPP;2305 2306	ret = irq_chip_set_wake_parent(data, on);2307	if (ret)2308		return ret;2309 2310	if (on)2311		atomic_inc(&pctrl->wakeup_path);2312	else2313		atomic_dec(&pctrl->wakeup_path);2314 2315	return 0;2316}2317 2318static const struct irq_chip rzg2l_gpio_irqchip = {2319	.name = "rzg2l-gpio",2320	.irq_disable = rzg2l_gpio_irq_disable,2321	.irq_enable = rzg2l_gpio_irq_enable,2322	.irq_mask = irq_chip_mask_parent,2323	.irq_unmask = irq_chip_unmask_parent,2324	.irq_set_type = rzg2l_gpio_irq_set_type,2325	.irq_eoi = rzg2l_gpio_irqc_eoi,2326	.irq_print_chip = rzg2l_gpio_irq_print_chip,2327	.irq_set_affinity = irq_chip_set_affinity_parent,2328	.irq_set_wake = rzg2l_gpio_irq_set_wake,2329	.flags = IRQCHIP_IMMUTABLE,2330	GPIOCHIP_IRQ_RESOURCE_HELPERS,2331};2332 2333static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset)2334{2335	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);2336	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];2337	u64 *pin_data = pin_desc->drv_data;2338	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);2339	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);2340	u8 reg8;2341	int ret;2342 2343	reg8 = readb(pctrl->base + PMC(off));2344	if (reg8 & BIT(bit)) {2345		ret = rzg2l_gpio_request(chip, offset);2346		if (ret)2347			return ret;2348	}2349 2350	return rzg2l_gpio_direction_input(chip, offset);2351}2352 2353static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,2354					    unsigned int child,2355					    unsigned int child_type,2356					    unsigned int *parent,2357					    unsigned int *parent_type)2358{2359	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);2360	unsigned long flags;2361	int gpioint, irq;2362	int ret;2363 2364	gpioint = rzg2l_gpio_get_gpioint(child, pctrl);2365	if (gpioint < 0)2366		return gpioint;2367 2368	ret = rzg2l_gpio_interrupt_input_mode(gc, child);2369	if (ret)2370		return ret;2371 2372	spin_lock_irqsave(&pctrl->bitmap_lock, flags);2373	irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1));2374	spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);2375	if (irq < 0) {2376		ret = -ENOSPC;2377		goto err;2378	}2379 2380	rzg2l_gpio_irq_endisable(pctrl, child, true);2381	pctrl->hwirq[irq] = child;2382	irq += RZG2L_TINT_IRQ_START_INDEX;2383 2384	/* All these interrupts are level high in the CPU */2385	*parent_type = IRQ_TYPE_LEVEL_HIGH;2386	*parent = RZG2L_PACK_HWIRQ(gpioint, irq);2387	return 0;2388 2389err:2390	rzg2l_gpio_free(gc, child);2391	return ret;2392}2393 2394static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip,2395					     union gpio_irq_fwspec *gfwspec,2396					     unsigned int parent_hwirq,2397					     unsigned int parent_type)2398{2399	struct irq_fwspec *fwspec = &gfwspec->fwspec;2400 2401	fwspec->fwnode = chip->irq.parent_domain->fwnode;2402	fwspec->param_count = 2;2403	fwspec->param[0] = parent_hwirq;2404	fwspec->param[1] = parent_type;2405 2406	return 0;2407}2408 2409static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl)2410{2411	struct irq_domain *domain = pctrl->gpio_chip.irq.domain;2412 2413	for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {2414		struct irq_data *data;2415		unsigned long flags;2416		unsigned int virq;2417		int ret;2418 2419		if (!pctrl->hwirq[i])2420			continue;2421 2422		virq = irq_find_mapping(domain, pctrl->hwirq[i]);2423		if (!virq) {2424			dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n",2425				 pctrl->hwirq[i]);2426			continue;2427		}2428 2429		data = irq_domain_get_irq_data(domain, virq);2430		if (!data) {2431			dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq);2432			continue;2433		}2434 2435		/*2436		 * This has to be atomically executed to protect against a concurrent2437		 * interrupt.2438		 */2439		spin_lock_irqsave(&pctrl->lock, flags);2440		ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data));2441		if (!ret && !irqd_irq_disabled(data))2442			rzg2l_gpio_irq_enable(data);2443		spin_unlock_irqrestore(&pctrl->lock, flags);2444 2445		if (ret)2446			dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq);2447	}2448}2449 2450static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,2451				       unsigned int nr_irqs)2452{2453	struct irq_data *d;2454 2455	d = irq_domain_get_irq_data(domain, virq);2456	if (d) {2457		struct gpio_chip *gc = irq_data_get_irq_chip_data(d);2458		struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);2459		irq_hw_number_t hwirq = irqd_to_hwirq(d);2460		unsigned long flags;2461		unsigned int i;2462 2463		for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {2464			if (pctrl->hwirq[i] == hwirq) {2465				rzg2l_gpio_irq_endisable(pctrl, hwirq, false);2466				rzg2l_gpio_free(gc, hwirq);2467				spin_lock_irqsave(&pctrl->bitmap_lock, flags);2468				bitmap_release_region(pctrl->tint_slot, i, get_order(1));2469				spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);2470				pctrl->hwirq[i] = 0;2471				break;2472			}2473		}2474	}2475	irq_domain_free_irqs_common(domain, virq, nr_irqs);2476}2477 2478static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,2479				      unsigned long *valid_mask,2480				      unsigned int ngpios)2481{2482	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);2483	struct gpio_chip *chip = &pctrl->gpio_chip;2484	unsigned int offset;2485 2486	/* Forbid unused lines to be mapped as IRQs */2487	for (offset = 0; offset < chip->ngpio; offset++) {2488		u32 port, bit;2489 2490		port = offset / 8;2491		bit = offset % 8;2492 2493		if (port >= pctrl->data->n_ports ||2494		    bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK,2495					      pctrl->data->port_pin_configs[port])))2496			clear_bit(offset, valid_mask);2497	}2498}2499 2500static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)2501{2502	u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;2503	struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache;2504 2505	cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL);2506	if (!cache)2507		return -ENOMEM;2508 2509	dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL);2510	if (!dedicated_cache)2511		return -ENOMEM;2512 2513	cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL);2514	if (!cache->p)2515		return -ENOMEM;2516 2517	cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL);2518	if (!cache->pm)2519		return -ENOMEM;2520 2521	cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL);2522	if (!cache->pmc)2523		return -ENOMEM;2524 2525	cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL);2526	if (!cache->pfc)2527		return -ENOMEM;2528 2529	for (u8 i = 0; i < 2; i++) {2530		u32 n_dedicated_pins = pctrl->data->n_dedicated_pins;2531 2532		cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]),2533					      GFP_KERNEL);2534		if (!cache->iolh[i])2535			return -ENOMEM;2536 2537		cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]),2538					     GFP_KERNEL);2539		if (!cache->ien[i])2540			return -ENOMEM;2541 2542		/* Allocate dedicated cache. */2543		dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,2544							sizeof(*dedicated_cache->iolh[i]),2545							GFP_KERNEL);2546		if (!dedicated_cache->iolh[i])2547			return -ENOMEM;2548 2549		dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,2550						       sizeof(*dedicated_cache->ien[i]),2551						       GFP_KERNEL);2552		if (!dedicated_cache->ien[i])2553			return -ENOMEM;2554	}2555 2556	pctrl->cache = cache;2557	pctrl->dedicated_cache = dedicated_cache;2558 2559	return 0;2560}2561 2562static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)2563{2564	struct device_node *np = pctrl->dev->of_node;2565	struct gpio_chip *chip = &pctrl->gpio_chip;2566	const char *name = dev_name(pctrl->dev);2567	struct irq_domain *parent_domain;2568	struct of_phandle_args of_args;2569	struct device_node *parent_np;2570	struct gpio_irq_chip *girq;2571	int ret;2572 2573	parent_np = of_irq_find_parent(np);2574	if (!parent_np)2575		return -ENXIO;2576 2577	parent_domain = irq_find_host(parent_np);2578	of_node_put(parent_np);2579	if (!parent_domain)2580		return -EPROBE_DEFER;2581 2582	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);2583	if (ret)2584		return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n");2585 2586	if (of_args.args[0] != 0 || of_args.args[1] != 0 ||2587	    of_args.args[2] != pctrl->data->n_port_pins)2588		return dev_err_probe(pctrl->dev, -EINVAL,2589				     "gpio-ranges does not match selected SOC\n");2590 2591	chip->names = pctrl->data->port_pins;2592	chip->request = rzg2l_gpio_request;2593	chip->free = rzg2l_gpio_free;2594	chip->get_direction = rzg2l_gpio_get_direction;2595	chip->direction_input = rzg2l_gpio_direction_input;2596	chip->direction_output = rzg2l_gpio_direction_output;2597	chip->get = rzg2l_gpio_get;2598	chip->set = rzg2l_gpio_set;2599	chip->label = name;2600	chip->parent = pctrl->dev;2601	chip->owner = THIS_MODULE;2602	chip->base = -1;2603	chip->ngpio = of_args.args[2];2604 2605	girq = &chip->irq;2606	gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip);2607	girq->fwnode = dev_fwnode(pctrl->dev);2608	girq->parent_domain = parent_domain;2609	girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;2610	girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;2611	girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;2612	girq->init_valid_mask = rzg2l_init_irq_valid_mask;2613 2614	pctrl->gpio_range.id = 0;2615	pctrl->gpio_range.pin_base = 0;2616	pctrl->gpio_range.base = 0;2617	pctrl->gpio_range.npins = chip->ngpio;2618	pctrl->gpio_range.name = chip->label;2619	pctrl->gpio_range.gc = chip;2620	ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);2621	if (ret)2622		return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n");2623 2624	dev_dbg(pctrl->dev, "Registered gpio controller\n");2625 2626	return 0;2627}2628 2629static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)2630{2631	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;2632	struct pinctrl_pin_desc *pins;2633	unsigned int i, j;2634	u64 *pin_data;2635	int ret;2636 2637	pctrl->desc.name = DRV_NAME;2638	pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;2639	pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;2640	pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;2641	pctrl->desc.confops = &rzg2l_pinctrl_confops;2642	pctrl->desc.owner = THIS_MODULE;2643	if (pctrl->data->num_custom_params) {2644		pctrl->desc.num_custom_params = pctrl->data->num_custom_params;2645		pctrl->desc.custom_params = pctrl->data->custom_params;2646#ifdef CONFIG_DEBUG_FS2647		pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items;2648#endif2649	}2650 2651	pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);2652	if (!pins)2653		return -ENOMEM;2654 2655	pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,2656				sizeof(*pin_data), GFP_KERNEL);2657	if (!pin_data)2658		return -ENOMEM;2659 2660	pctrl->pins = pins;2661	pctrl->desc.pins = pins;2662 2663	for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {2664		pins[i].number = i;2665		pins[i].name = pctrl->data->port_pins[i];2666		if (i && !(i % RZG2L_PINS_PER_PORT))2667			j++;2668		pin_data[i] = pctrl->data->port_pin_configs[j];2669		if (pin_data[i] & RZG2L_VARIABLE_CFG)2670			pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,2671									 pin_data[i],2672									 j,2673									 i % RZG2L_PINS_PER_PORT);2674		pins[i].drv_data = &pin_data[i];2675	}2676 2677	for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {2678		unsigned int index = pctrl->data->n_port_pins + i;2679 2680		pins[index].number = index;2681		pins[index].name = pctrl->data->dedicated_pins[i].name;2682		pin_data[index] = pctrl->data->dedicated_pins[i].config;2683		pins[index].drv_data = &pin_data[index];2684	}2685 2686	pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings),2687				       GFP_KERNEL);2688	if (!pctrl->settings)2689		return -ENOMEM;2690 2691	for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) {2692		if (pin_data[i] & PIN_CFG_SOFT_PS) {2693			pctrl->settings[i].power_source = 3300;2694		} else {2695			ret = rzg2l_get_power_source(pctrl, i, pin_data[i]);2696			if (ret < 0)2697				continue;2698			pctrl->settings[i].power_source = ret;2699		}2700	}2701 2702	ret = rzg2l_pinctrl_reg_cache_alloc(pctrl);2703	if (ret)2704		return ret;2705 2706	ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,2707					     &pctrl->pctl);2708	if (ret)2709		return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n");2710 2711	ret = pinctrl_enable(pctrl->pctl);2712	if (ret)2713		dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n");2714 2715	ret = rzg2l_gpio_register(pctrl);2716	if (ret)2717		return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n");2718 2719	return 0;2720}2721 2722static int rzg2l_pinctrl_probe(struct platform_device *pdev)2723{2724	struct rzg2l_pinctrl *pctrl;2725	int ret;2726 2727	BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT >2728		     ARRAY_SIZE(rzg2l_gpio_names));2729 2730	BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >2731		     ARRAY_SIZE(rzg2l_gpio_names));2732 2733	BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >2734		     ARRAY_SIZE(rzg2l_gpio_names));2735 2736	BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >2737		     ARRAY_SIZE(rzv2h_gpio_names));2738 2739	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);2740	if (!pctrl)2741		return -ENOMEM;2742 2743	pctrl->dev = &pdev->dev;2744 2745	pctrl->data = of_device_get_match_data(&pdev->dev);2746	if (!pctrl->data)2747		return -EINVAL;2748 2749	pctrl->base = devm_platform_ioremap_resource(pdev, 0);2750	if (IS_ERR(pctrl->base))2751		return PTR_ERR(pctrl->base);2752 2753	pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL);2754	if (IS_ERR(pctrl->clk)) {2755		return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk),2756				     "failed to enable GPIO clk\n");2757	}2758 2759	spin_lock_init(&pctrl->lock);2760	spin_lock_init(&pctrl->bitmap_lock);2761	mutex_init(&pctrl->mutex);2762	atomic_set(&pctrl->wakeup_path, 0);2763 2764	platform_set_drvdata(pdev, pctrl);2765 2766	ret = rzg2l_pinctrl_register(pctrl);2767	if (ret)2768		return ret;2769 2770	dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);2771	return 0;2772}2773 2774static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend)2775{2776	u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;2777	struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;2778 2779	for (u32 port = 0; port < nports; port++) {2780		bool has_iolh, has_ien;2781		u32 off, caps;2782		u8 pincnt;2783		u64 cfg;2784 2785		cfg = pctrl->data->port_pin_configs[port];2786		off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);2787		pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg));2788 2789		caps = FIELD_GET(PIN_CFG_MASK, cfg);2790		has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));2791		has_ien = !!(caps & PIN_CFG_IEN);2792 2793		if (suspend)2794			RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);2795 2796		/*2797		 * Now cache the registers or set them in the order suggested by2798		 * HW manual (section "Operation for GPIO Function").2799		 */2800		RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]);2801		if (has_iolh) {2802			RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off),2803						 cache->iolh[0][port]);2804			if (pincnt >= 4) {2805				RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4,2806							 cache->iolh[1][port]);2807			}2808		}2809 2810		RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]);2811		RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]);2812 2813		if (has_ien) {2814			RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),2815						 cache->ien[0][port]);2816			if (pincnt >= 4) {2817				RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4,2818							 cache->ien[1][port]);2819			}2820		}2821	}2822}2823 2824static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend)2825{2826	struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache;2827	u32 caps;2828	u32 i;2829 2830	/*2831	 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same2832	 * port offset are close together.2833	 */2834	for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {2835		bool has_iolh, has_ien;2836		u32 off, next_off = 0;2837		u64 cfg, next_cfg;2838		u8 pincnt;2839 2840		cfg = pctrl->data->dedicated_pins[i].config;2841		off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);2842		if (i + 1 < pctrl->data->n_dedicated_pins) {2843			next_cfg = pctrl->data->dedicated_pins[i + 1].config;2844			next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg);2845		}2846 2847		if (off == next_off) {2848			/* Gather caps of all port pins. */2849			caps |= FIELD_GET(PIN_CFG_MASK, cfg);2850			continue;2851		}2852 2853		/* And apply them in a single shot. */2854		has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));2855		has_ien = !!(caps & PIN_CFG_IEN);2856		pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));2857 2858		if (has_iolh) {2859			RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off),2860						 cache->iolh[0][i]);2861		}2862		if (has_ien) {2863			RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),2864						 cache->ien[0][i]);2865		}2866 2867		if (pincnt >= 4) {2868			if (has_iolh) {2869				RZG2L_PCTRL_REG_ACCESS32(suspend,2870							 pctrl->base + IOLH(off) + 4,2871							 cache->iolh[1][i]);2872			}2873			if (has_ien) {2874				RZG2L_PCTRL_REG_ACCESS32(suspend,2875							 pctrl->base + IEN(off) + 4,2876							 cache->ien[1][i]);2877			}2878		}2879		caps = 0;2880	}2881}2882 2883static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)2884{2885	u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;2886	unsigned long flags;2887 2888	spin_lock_irqsave(&pctrl->lock, flags);2889	pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);2890 2891	/* Restore port registers. */2892	for (u32 port = 0; port < nports; port++) {2893		unsigned long pinmap;2894		u8 pmc = 0, max_pin;2895		u32 off, pfc = 0;2896		u64 cfg;2897		u16 pm;2898		u8 pin;2899 2900		cfg = pctrl->data->port_pin_configs[port];2901		off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);2902		pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);2903		max_pin = fls(pinmap);2904 2905		pm = readw(pctrl->base + PM(off));2906		for_each_set_bit(pin, &pinmap, max_pin) {2907			struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;2908 2909			/* Nothing to do if PFC was not configured before. */2910			if (!(cache->pmc[port] & BIT(pin)))2911				continue;2912 2913			/* Set pin to 'Non-use (Hi-Z input protection)' */2914			pm &= ~(PM_MASK << (pin * 2));2915			writew(pm, pctrl->base + PM(off));2916 2917			/* Temporarily switch to GPIO mode with PMC register */2918			pmc &= ~BIT(pin);2919			writeb(pmc, pctrl->base + PMC(off));2920 2921			/* Select Pin function mode. */2922			pfc &= ~(PFC_MASK << (pin * 4));2923			pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));2924			writel(pfc, pctrl->base + PFC(off));2925 2926			/* Switch to Peripheral pin function. */2927			pmc |= BIT(pin);2928			writeb(pmc, pctrl->base + PMC(off));2929		}2930	}2931 2932	pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);2933	spin_unlock_irqrestore(&pctrl->lock, flags);2934}2935 2936static int rzg2l_pinctrl_suspend_noirq(struct device *dev)2937{2938	struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev);2939	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;2940	const struct rzg2l_register_offsets *regs = &hwcfg->regs;2941	struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;2942 2943	rzg2l_pinctrl_pm_setup_regs(pctrl, true);2944	rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true);2945 2946	for (u8 i = 0; i < 2; i++) {2947		if (regs->sd_ch)2948			cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i));2949		if (regs->eth_poc)2950			cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));2951	}2952 2953	cache->qspi = readb(pctrl->base + QSPI);2954	cache->eth_mode = readb(pctrl->base + ETH_MODE);2955 2956	if (!atomic_read(&pctrl->wakeup_path))2957		clk_disable_unprepare(pctrl->clk);2958	else2959		device_set_wakeup_path(dev);2960 2961	return 0;2962}2963 2964static int rzg2l_pinctrl_resume_noirq(struct device *dev)2965{2966	struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev);2967	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;2968	const struct rzg2l_register_offsets *regs = &hwcfg->regs;2969	struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;2970	int ret;2971 2972	if (!atomic_read(&pctrl->wakeup_path)) {2973		ret = clk_prepare_enable(pctrl->clk);2974		if (ret)2975			return ret;2976	}2977 2978	writeb(cache->qspi, pctrl->base + QSPI);2979	writeb(cache->eth_mode, pctrl->base + ETH_MODE);2980	for (u8 i = 0; i < 2; i++) {2981		if (regs->sd_ch)2982			writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));2983		if (regs->eth_poc)2984			writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i));2985	}2986 2987	rzg2l_pinctrl_pm_setup_pfc(pctrl);2988	rzg2l_pinctrl_pm_setup_regs(pctrl, false);2989	rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false);2990	rzg2l_gpio_irq_restore(pctrl);2991 2992	return 0;2993}2994 2995static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)2996{2997	const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;2998 2999	if (lock) {3000		/* Set the PWPR register to be write-protected */3001		writel(0x0, pctrl->base + regs->pwpr);		/* B0WI=0, PFCWE=0 */3002		writel(PWPR_B0WI, pctrl->base + regs->pwpr);	/* B0WI=1, PFCWE=0 */3003	} else {3004		/* Set the PWPR register to allow PFC register to write */3005		writel(0x0, pctrl->base + regs->pwpr);		/* B0WI=0, PFCWE=0 */3006		writel(PWPR_PFCWE, pctrl->base + regs->pwpr);	/* B0WI=0, PFCWE=1 */3007	}3008}3009 3010static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)3011{3012	const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;3013	u8 pwpr;3014 3015	if (lock) {3016		/* Set the PWPR register to be write-protected */3017		pwpr = readb(pctrl->base + regs->pwpr);3018		writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);3019	} else {3020		/* Set the PWPR register to allow PFC and PMC register to write */3021		pwpr = readb(pctrl->base + regs->pwpr);3022		writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr);3023	}3024}3025 3026static const struct rzg2l_hwcfg rzg2l_hwcfg = {3027	.regs = {3028		.pwpr = 0x3014,3029		.sd_ch = 0x3000,3030		.eth_poc = 0x300c,3031	},3032	.iolh_groupa_ua = {3033		/* 3v3 power source */3034		[RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,3035	},3036	.iolh_groupb_oi = { 100, 66, 50, 33, },3037	.oen_max_pin = 0,3038};3039 3040static const struct rzg2l_hwcfg rzg3s_hwcfg = {3041	.regs = {3042		.pwpr = 0x3000,3043		.sd_ch = 0x3004,3044		.eth_poc = 0x3010,3045	},3046	.iolh_groupa_ua = {3047		/* 1v8 power source */3048		[RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,3049		/* 3v3 power source */3050		[RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,3051	},3052	.iolh_groupb_ua = {3053		/* 1v8 power source */3054		[RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,3055		/* 3v3 power source */3056		[RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,3057	},3058	.iolh_groupc_ua = {3059		/* 1v8 power source */3060		[RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,3061		/* 2v5 source */3062		[RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,3063		/* 3v3 power source */3064		[RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,3065	},3066	.drive_strength_ua = true,3067	.func_base = 1,3068	.oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */3069	.oen_max_port = 7, /* P7_1 is the maximum OEN port. */3070};3071 3072static const struct rzg2l_hwcfg rzv2h_hwcfg = {3073	.regs = {3074		.pwpr = 0x3c04,3075	},3076};3077 3078static struct rzg2l_pinctrl_data r9a07g043_data = {3079	.port_pins = rzg2l_gpio_names,3080	.port_pin_configs = r9a07g043_gpio_configs,3081	.n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),3082	.dedicated_pins = rzg2l_dedicated_pins.common,3083	.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,3084	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),3085	.hwcfg = &rzg2l_hwcfg,3086#ifdef CONFIG_RISCV3087	.variable_pin_cfg = r9a07g043f_variable_pin_cfg,3088	.n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),3089#endif3090	.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,3091	.pmc_writeb = &rzg2l_pmc_writeb,3092	.oen_read = &rzg2l_read_oen,3093	.oen_write = &rzg2l_write_oen,3094	.hw_to_bias_param = &rzg2l_hw_to_bias_param,3095	.bias_param_to_hw = &rzg2l_bias_param_to_hw,3096};3097 3098static struct rzg2l_pinctrl_data r9a07g044_data = {3099	.port_pins = rzg2l_gpio_names,3100	.port_pin_configs = r9a07g044_gpio_configs,3101	.n_ports = ARRAY_SIZE(r9a07g044_gpio_configs),3102	.dedicated_pins = rzg2l_dedicated_pins.common,3103	.n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT,3104	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +3105		ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),3106	.hwcfg = &rzg2l_hwcfg,3107	.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,3108	.pmc_writeb = &rzg2l_pmc_writeb,3109	.oen_read = &rzg2l_read_oen,3110	.oen_write = &rzg2l_write_oen,3111	.hw_to_bias_param = &rzg2l_hw_to_bias_param,3112	.bias_param_to_hw = &rzg2l_bias_param_to_hw,3113};3114 3115static struct rzg2l_pinctrl_data r9a08g045_data = {3116	.port_pins = rzg2l_gpio_names,3117	.port_pin_configs = r9a08g045_gpio_configs,3118	.n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),3119	.dedicated_pins = rzg3s_dedicated_pins,3120	.n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,3121	.n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),3122	.hwcfg = &rzg3s_hwcfg,3123	.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,3124	.pmc_writeb = &rzg2l_pmc_writeb,3125	.oen_read = &rzg3s_oen_read,3126	.oen_write = &rzg3s_oen_write,3127	.hw_to_bias_param = &rzg2l_hw_to_bias_param,3128	.bias_param_to_hw = &rzg2l_bias_param_to_hw,3129};3130 3131static struct rzg2l_pinctrl_data r9a09g057_data = {3132	.port_pins = rzv2h_gpio_names,3133	.port_pin_configs = r9a09g057_gpio_configs,3134	.n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),3135	.dedicated_pins = rzv2h_dedicated_pins,3136	.n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,3137	.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins),3138	.hwcfg = &rzv2h_hwcfg,3139	.variable_pin_cfg = r9a09g057_variable_pin_cfg,3140	.n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),3141	.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),3142	.custom_params = renesas_rzv2h_custom_bindings,3143#ifdef CONFIG_DEBUG_FS3144	.custom_conf_items = renesas_rzv2h_conf_items,3145#endif3146	.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,3147	.pmc_writeb = &rzv2h_pmc_writeb,3148	.oen_read = &rzv2h_oen_read,3149	.oen_write = &rzv2h_oen_write,3150	.hw_to_bias_param = &rzv2h_hw_to_bias_param,3151	.bias_param_to_hw = &rzv2h_bias_param_to_hw,3152};3153 3154static const struct of_device_id rzg2l_pinctrl_of_table[] = {3155	{3156		.compatible = "renesas,r9a07g043-pinctrl",3157		.data = &r9a07g043_data,3158	},3159	{3160		.compatible = "renesas,r9a07g044-pinctrl",3161		.data = &r9a07g044_data,3162	},3163	{3164		.compatible = "renesas,r9a08g045-pinctrl",3165		.data = &r9a08g045_data,3166	},3167	{3168		.compatible = "renesas,r9a09g057-pinctrl",3169		.data = &r9a09g057_data,3170	},3171	{ /* sentinel */ }3172};3173 3174static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = {3175	NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq)3176};3177 3178static struct platform_driver rzg2l_pinctrl_driver = {3179	.driver = {3180		.name = DRV_NAME,3181		.of_match_table = of_match_ptr(rzg2l_pinctrl_of_table),3182		.pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops),3183	},3184	.probe = rzg2l_pinctrl_probe,3185};3186 3187static int __init rzg2l_pinctrl_init(void)3188{3189	return platform_driver_register(&rzg2l_pinctrl_driver);3190}3191core_initcall(rzg2l_pinctrl_init);3192 3193MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");3194MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");3195