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1// SPDX-License-Identifier: GPL-2.0+2//3// Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.4//5// Copyright (c) 2012 Samsung Electronics Co., Ltd.6// http://www.samsung.com7// Copyright (c) 2012 Linaro Ltd8// http://www.linaro.org9//10// Author: Thomas Abraham <thomas.ab@samsung.com>11//12// This file contains the Samsung Exynos specific information required by the13// the Samsung pinctrl/gpiolib driver. It also includes the implementation of14// external gpio and wakeup interrupt support.15 16#include <linux/device.h>17#include <linux/of_address.h>18#include <linux/slab.h>19#include <linux/err.h>20#include <linux/soc/samsung/exynos-regs-pmu.h>21 22#include "pinctrl-samsung.h"23#include "pinctrl-exynos.h"24 25static const struct samsung_pin_bank_type bank_type_off = {26 .fld_width = { 4, 1, 2, 2, 2, 2, },27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },28};29 30static const struct samsung_pin_bank_type bank_type_alive = {31 .fld_width = { 4, 1, 2, 2, },32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },33};34 35/* Retention control for S5PV210 are located at the end of clock controller */36#define S5P_OTHERS 0xE00037 38#define S5P_OTHERS_RET_IO (1 << 31)39#define S5P_OTHERS_RET_CF (1 << 30)40#define S5P_OTHERS_RET_MMC (1 << 29)41#define S5P_OTHERS_RET_UART (1 << 28)42 43#define S5P_PIN_PULL_DISABLE 044#define S5P_PIN_PULL_DOWN 145#define S5P_PIN_PULL_UP 246 47static void s5pv210_pud_value_init(struct samsung_pinctrl_drv_data *drvdata)48{49 unsigned int *pud_val = drvdata->pud_val;50 51 pud_val[PUD_PULL_DISABLE] = S5P_PIN_PULL_DISABLE;52 pud_val[PUD_PULL_DOWN] = S5P_PIN_PULL_DOWN;53 pud_val[PUD_PULL_UP] = S5P_PIN_PULL_UP;54}55 56static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)57{58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;59 u32 tmp;60 61 tmp = __raw_readl(clk_base + S5P_OTHERS);62 tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC |63 S5P_OTHERS_RET_UART);64 __raw_writel(tmp, clk_base + S5P_OTHERS);65}66 67static struct samsung_retention_ctrl *68s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,69 const struct samsung_retention_data *data)70{71 struct samsung_retention_ctrl *ctrl;72 struct device_node *np;73 void __iomem *clk_base;74 75 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);76 if (!ctrl)77 return ERR_PTR(-ENOMEM);78 79 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");80 if (!np) {81 pr_err("%s: failed to find clock controller DT node\n",82 __func__);83 return ERR_PTR(-ENODEV);84 }85 86 clk_base = of_iomap(np, 0);87 of_node_put(np);88 if (!clk_base) {89 pr_err("%s: failed to map clock registers\n", __func__);90 return ERR_PTR(-EINVAL);91 }92 93 ctrl->priv = (void __force *)clk_base;94 ctrl->disable = s5pv210_retention_disable;95 96 return ctrl;97}98 99static const struct samsung_retention_data s5pv210_retention_data __initconst = {100 .init = s5pv210_retention_init,101};102 103/* pin banks of s5pv210 pin-controller */104static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {105 /* Must start with EINTG banks, ordered by EINT group number. */106 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),107 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),108 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),109 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),110 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),111 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),112 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),113 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),114 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),115 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),116 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),117 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),118 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),119 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),120 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),121 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),122 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),123 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),124 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),125 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),126 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),127 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),128 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),129 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),130 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),131 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),132 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),133 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),134 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),135 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),136 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),137 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),138 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),139 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),140};141 142static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {143 {144 /* pin-controller instance 0 data */145 .pin_banks = s5pv210_pin_bank,146 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),147 .eint_gpio_init = exynos_eint_gpio_init,148 .eint_wkup_init = exynos_eint_wkup_init,149 .pud_value_init = s5pv210_pud_value_init,150 .suspend = exynos_pinctrl_suspend,151 .resume = exynos_pinctrl_resume,152 .retention_data = &s5pv210_retention_data,153 },154};155 156const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = {157 .ctrl = s5pv210_pin_ctrl,158 .num_ctrl = ARRAY_SIZE(s5pv210_pin_ctrl),159};160 161/* Pad retention control code for accessing PMU regmap */162static atomic_t exynos_shared_retention_refcnt;163 164/* pin banks of exynos3250 pin-controller 0 */165static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {166 /* Must start with EINTG banks, ordered by EINT group number. */167 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),168 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),169 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),170 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),171 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),172 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),173 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),174};175 176/* pin banks of exynos3250 pin-controller 1 */177static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {178 /* Must start with EINTG banks, ordered by EINT group number. */179 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),180 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),181 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),182 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),183 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),184 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),185 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),186 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),187 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),188 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),189 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),190 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),191 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),192 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),193 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),194 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),195};196 197/*198 * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle199 * them all together200 */201static const u32 exynos3250_retention_regs[] = {202 S5P_PAD_RET_MAUDIO_OPTION,203 S5P_PAD_RET_GPIO_OPTION,204 S5P_PAD_RET_UART_OPTION,205 S5P_PAD_RET_MMCA_OPTION,206 S5P_PAD_RET_MMCB_OPTION,207 S5P_PAD_RET_EBIA_OPTION,208 S5P_PAD_RET_EBIB_OPTION,209 S5P_PAD_RET_MMC2_OPTION,210 S5P_PAD_RET_SPI_OPTION,211};212 213static const struct samsung_retention_data exynos3250_retention_data __initconst = {214 .regs = exynos3250_retention_regs,215 .nr_regs = ARRAY_SIZE(exynos3250_retention_regs),216 .value = EXYNOS_WAKEUP_FROM_LOWPWR,217 .refcnt = &exynos_shared_retention_refcnt,218 .init = exynos_retention_init,219};220 221/*222 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes223 * two gpio/pin-mux/pinconfig controllers.224 */225static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {226 {227 /* pin-controller instance 0 data */228 .pin_banks = exynos3250_pin_banks0,229 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),230 .eint_gpio_init = exynos_eint_gpio_init,231 .suspend = exynos_pinctrl_suspend,232 .resume = exynos_pinctrl_resume,233 .retention_data = &exynos3250_retention_data,234 }, {235 /* pin-controller instance 1 data */236 .pin_banks = exynos3250_pin_banks1,237 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),238 .eint_gpio_init = exynos_eint_gpio_init,239 .eint_wkup_init = exynos_eint_wkup_init,240 .suspend = exynos_pinctrl_suspend,241 .resume = exynos_pinctrl_resume,242 .retention_data = &exynos3250_retention_data,243 },244};245 246const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = {247 .ctrl = exynos3250_pin_ctrl,248 .num_ctrl = ARRAY_SIZE(exynos3250_pin_ctrl),249};250 251/* pin banks of exynos4210 pin-controller 0 */252static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {253 /* Must start with EINTG banks, ordered by EINT group number. */254 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),255 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),256 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),257 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),258 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),259 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),260 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),261 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),262 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),263 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),264 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),265 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),266 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),267 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),268 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),269 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),270};271 272/* pin banks of exynos4210 pin-controller 1 */273static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {274 /* Must start with EINTG banks, ordered by EINT group number. */275 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),276 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),277 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),278 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),279 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),280 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),281 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),282 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),283 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),284 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),285 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),286 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),287 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),288 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),289 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),290 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),291 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),292 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),293 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),294 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),295};296 297/* pin banks of exynos4210 pin-controller 2 */298static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {299 /* Must start with EINTG banks, ordered by EINT group number. */300 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),301};302 303/* PMU pad retention groups registers for Exynos4 (without audio) */304static const u32 exynos4_retention_regs[] = {305 S5P_PAD_RET_GPIO_OPTION,306 S5P_PAD_RET_UART_OPTION,307 S5P_PAD_RET_MMCA_OPTION,308 S5P_PAD_RET_MMCB_OPTION,309 S5P_PAD_RET_EBIA_OPTION,310 S5P_PAD_RET_EBIB_OPTION,311};312 313static const struct samsung_retention_data exynos4_retention_data __initconst = {314 .regs = exynos4_retention_regs,315 .nr_regs = ARRAY_SIZE(exynos4_retention_regs),316 .value = EXYNOS_WAKEUP_FROM_LOWPWR,317 .refcnt = &exynos_shared_retention_refcnt,318 .init = exynos_retention_init,319};320 321/* PMU retention control for audio pins can be tied to audio pin bank */322static const u32 exynos4_audio_retention_regs[] = {323 S5P_PAD_RET_MAUDIO_OPTION,324};325 326static const struct samsung_retention_data exynos4_audio_retention_data __initconst = {327 .regs = exynos4_audio_retention_regs,328 .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs),329 .value = EXYNOS_WAKEUP_FROM_LOWPWR,330 .init = exynos_retention_init,331};332 333/*334 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes335 * three gpio/pin-mux/pinconfig controllers.336 */337static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {338 {339 /* pin-controller instance 0 data */340 .pin_banks = exynos4210_pin_banks0,341 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),342 .eint_gpio_init = exynos_eint_gpio_init,343 .suspend = exynos_pinctrl_suspend,344 .resume = exynos_pinctrl_resume,345 .retention_data = &exynos4_retention_data,346 }, {347 /* pin-controller instance 1 data */348 .pin_banks = exynos4210_pin_banks1,349 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),350 .eint_gpio_init = exynos_eint_gpio_init,351 .eint_wkup_init = exynos_eint_wkup_init,352 .suspend = exynos_pinctrl_suspend,353 .resume = exynos_pinctrl_resume,354 .retention_data = &exynos4_retention_data,355 }, {356 /* pin-controller instance 2 data */357 .pin_banks = exynos4210_pin_banks2,358 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),359 .retention_data = &exynos4_audio_retention_data,360 },361};362 363const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = {364 .ctrl = exynos4210_pin_ctrl,365 .num_ctrl = ARRAY_SIZE(exynos4210_pin_ctrl),366};367 368/* pin banks of exynos4x12 pin-controller 0 */369static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {370 /* Must start with EINTG banks, ordered by EINT group number. */371 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),372 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),373 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),374 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),375 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),376 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),377 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),378 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),379 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),380 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),381 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),382 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),383 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),384};385 386/* pin banks of exynos4x12 pin-controller 1 */387static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {388 /* Must start with EINTG banks, ordered by EINT group number. */389 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),390 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),391 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),392 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),393 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),394 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),395 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),396 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),397 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),398 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),399 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),400 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),401 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),402 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),403 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),404 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),405 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),406 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),407 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),408 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),409 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),410 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),411 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),412};413 414/* pin banks of exynos4x12 pin-controller 2 */415static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {416 /* Must start with EINTG banks, ordered by EINT group number. */417 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),418};419 420/* pin banks of exynos4x12 pin-controller 3 */421static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {422 /* Must start with EINTG banks, ordered by EINT group number. */423 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),424 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),425 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),426 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),427 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),428};429 430/*431 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes432 * four gpio/pin-mux/pinconfig controllers.433 */434static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {435 {436 /* pin-controller instance 0 data */437 .pin_banks = exynos4x12_pin_banks0,438 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),439 .eint_gpio_init = exynos_eint_gpio_init,440 .suspend = exynos_pinctrl_suspend,441 .resume = exynos_pinctrl_resume,442 .retention_data = &exynos4_retention_data,443 }, {444 /* pin-controller instance 1 data */445 .pin_banks = exynos4x12_pin_banks1,446 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),447 .eint_gpio_init = exynos_eint_gpio_init,448 .eint_wkup_init = exynos_eint_wkup_init,449 .suspend = exynos_pinctrl_suspend,450 .resume = exynos_pinctrl_resume,451 .retention_data = &exynos4_retention_data,452 }, {453 /* pin-controller instance 2 data */454 .pin_banks = exynos4x12_pin_banks2,455 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),456 .eint_gpio_init = exynos_eint_gpio_init,457 .suspend = exynos_pinctrl_suspend,458 .resume = exynos_pinctrl_resume,459 .retention_data = &exynos4_audio_retention_data,460 }, {461 /* pin-controller instance 3 data */462 .pin_banks = exynos4x12_pin_banks3,463 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),464 .eint_gpio_init = exynos_eint_gpio_init,465 .suspend = exynos_pinctrl_suspend,466 .resume = exynos_pinctrl_resume,467 },468};469 470const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = {471 .ctrl = exynos4x12_pin_ctrl,472 .num_ctrl = ARRAY_SIZE(exynos4x12_pin_ctrl),473};474 475/* pin banks of exynos5250 pin-controller 0 */476static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {477 /* Must start with EINTG banks, ordered by EINT group number. */478 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),479 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),480 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),481 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),482 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),483 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),484 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),485 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),486 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),487 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),488 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),489 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),490 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),491 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),492 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),493 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),494 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),495 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),496 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),497 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),498 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),499 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),500 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),501 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),502 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),503};504 505/* pin banks of exynos5250 pin-controller 1 */506static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {507 /* Must start with EINTG banks, ordered by EINT group number. */508 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),509 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),510 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),511 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),512 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),513 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),514 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),515 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),516 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),517};518 519/* pin banks of exynos5250 pin-controller 2 */520static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {521 /* Must start with EINTG banks, ordered by EINT group number. */522 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),523 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),524 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),525 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),526 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),527};528 529/* pin banks of exynos5250 pin-controller 3 */530static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {531 /* Must start with EINTG banks, ordered by EINT group number. */532 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),533};534 535/*536 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes537 * four gpio/pin-mux/pinconfig controllers.538 */539static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {540 {541 /* pin-controller instance 0 data */542 .pin_banks = exynos5250_pin_banks0,543 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),544 .eint_gpio_init = exynos_eint_gpio_init,545 .eint_wkup_init = exynos_eint_wkup_init,546 .suspend = exynos_pinctrl_suspend,547 .resume = exynos_pinctrl_resume,548 .retention_data = &exynos4_retention_data,549 }, {550 /* pin-controller instance 1 data */551 .pin_banks = exynos5250_pin_banks1,552 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),553 .eint_gpio_init = exynos_eint_gpio_init,554 .suspend = exynos_pinctrl_suspend,555 .resume = exynos_pinctrl_resume,556 .retention_data = &exynos4_retention_data,557 }, {558 /* pin-controller instance 2 data */559 .pin_banks = exynos5250_pin_banks2,560 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),561 .eint_gpio_init = exynos_eint_gpio_init,562 .suspend = exynos_pinctrl_suspend,563 .resume = exynos_pinctrl_resume,564 }, {565 /* pin-controller instance 3 data */566 .pin_banks = exynos5250_pin_banks3,567 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),568 .eint_gpio_init = exynos_eint_gpio_init,569 .suspend = exynos_pinctrl_suspend,570 .resume = exynos_pinctrl_resume,571 .retention_data = &exynos4_audio_retention_data,572 },573};574 575const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = {576 .ctrl = exynos5250_pin_ctrl,577 .num_ctrl = ARRAY_SIZE(exynos5250_pin_ctrl),578};579 580/* pin banks of exynos5260 pin-controller 0 */581static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {582 /* Must start with EINTG banks, ordered by EINT group number. */583 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),584 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),585 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),586 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),587 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),588 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),589 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),590 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),591 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),592 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),593 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),594 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),595 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),596 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),597 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),598 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),599 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),600 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),601 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),602 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),603 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),604};605 606/* pin banks of exynos5260 pin-controller 1 */607static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {608 /* Must start with EINTG banks, ordered by EINT group number. */609 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),610 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),611 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),612 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),613 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),614};615 616/* pin banks of exynos5260 pin-controller 2 */617static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {618 /* Must start with EINTG banks, ordered by EINT group number. */619 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),620 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),621};622 623/*624 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes625 * three gpio/pin-mux/pinconfig controllers.626 */627static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {628 {629 /* pin-controller instance 0 data */630 .pin_banks = exynos5260_pin_banks0,631 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),632 .eint_gpio_init = exynos_eint_gpio_init,633 .eint_wkup_init = exynos_eint_wkup_init,634 .suspend = exynos_pinctrl_suspend,635 .resume = exynos_pinctrl_resume,636 }, {637 /* pin-controller instance 1 data */638 .pin_banks = exynos5260_pin_banks1,639 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),640 .eint_gpio_init = exynos_eint_gpio_init,641 .suspend = exynos_pinctrl_suspend,642 .resume = exynos_pinctrl_resume,643 }, {644 /* pin-controller instance 2 data */645 .pin_banks = exynos5260_pin_banks2,646 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),647 .eint_gpio_init = exynos_eint_gpio_init,648 .suspend = exynos_pinctrl_suspend,649 .resume = exynos_pinctrl_resume,650 },651};652 653const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = {654 .ctrl = exynos5260_pin_ctrl,655 .num_ctrl = ARRAY_SIZE(exynos5260_pin_ctrl),656};657 658/* pin banks of exynos5410 pin-controller 0 */659static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {660 /* Must start with EINTG banks, ordered by EINT group number. */661 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),662 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),663 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),664 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),665 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),666 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),667 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),668 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),669 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),670 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),671 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),672 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),673 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),674 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),675 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),676 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),677 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),678 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),679 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),680 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),681 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),682 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),683 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),684 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),685 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),686 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),687 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),688 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),689 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),690 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),691 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),692 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),693 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),694 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),695 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),696};697 698/* pin banks of exynos5410 pin-controller 1 */699static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {700 /* Must start with EINTG banks, ordered by EINT group number. */701 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),702 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),703 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),704 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),705 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),706 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),707 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),708 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),709 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),710};711 712/* pin banks of exynos5410 pin-controller 2 */713static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {714 /* Must start with EINTG banks, ordered by EINT group number. */715 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),716 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),717 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),718 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),719 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),720};721 722/* pin banks of exynos5410 pin-controller 3 */723static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {724 /* Must start with EINTG banks, ordered by EINT group number. */725 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),726};727 728/*729 * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes730 * four gpio/pin-mux/pinconfig controllers.731 */732static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {733 {734 /* pin-controller instance 0 data */735 .pin_banks = exynos5410_pin_banks0,736 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),737 .eint_gpio_init = exynos_eint_gpio_init,738 .eint_wkup_init = exynos_eint_wkup_init,739 .suspend = exynos_pinctrl_suspend,740 .resume = exynos_pinctrl_resume,741 }, {742 /* pin-controller instance 1 data */743 .pin_banks = exynos5410_pin_banks1,744 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),745 .eint_gpio_init = exynos_eint_gpio_init,746 .suspend = exynos_pinctrl_suspend,747 .resume = exynos_pinctrl_resume,748 }, {749 /* pin-controller instance 2 data */750 .pin_banks = exynos5410_pin_banks2,751 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),752 .eint_gpio_init = exynos_eint_gpio_init,753 .suspend = exynos_pinctrl_suspend,754 .resume = exynos_pinctrl_resume,755 }, {756 /* pin-controller instance 3 data */757 .pin_banks = exynos5410_pin_banks3,758 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),759 .eint_gpio_init = exynos_eint_gpio_init,760 .suspend = exynos_pinctrl_suspend,761 .resume = exynos_pinctrl_resume,762 },763};764 765const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = {766 .ctrl = exynos5410_pin_ctrl,767 .num_ctrl = ARRAY_SIZE(exynos5410_pin_ctrl),768};769 770/* pin banks of exynos5420 pin-controller 0 */771static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {772 /* Must start with EINTG banks, ordered by EINT group number. */773 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),774 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),775 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),776 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),777 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),778};779 780/* pin banks of exynos5420 pin-controller 1 */781static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {782 /* Must start with EINTG banks, ordered by EINT group number. */783 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),784 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),785 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),786 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),787 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),788 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),789 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),790 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),791 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),792 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),793 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),794 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),795 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),796};797 798/* pin banks of exynos5420 pin-controller 2 */799static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {800 /* Must start with EINTG banks, ordered by EINT group number. */801 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),802 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),803 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),804 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),805 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),806 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),807 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),808 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),809};810 811/* pin banks of exynos5420 pin-controller 3 */812static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {813 /* Must start with EINTG banks, ordered by EINT group number. */814 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),815 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),816 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),817 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),818 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),819 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),820 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),821 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),822 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),823};824 825/* pin banks of exynos5420 pin-controller 4 */826static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {827 /* Must start with EINTG banks, ordered by EINT group number. */828 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),829};830 831/* PMU pad retention groups registers for Exynos5420 (without audio) */832static const u32 exynos5420_retention_regs[] = {833 EXYNOS_PAD_RET_DRAM_OPTION,834 EXYNOS_PAD_RET_JTAG_OPTION,835 EXYNOS5420_PAD_RET_GPIO_OPTION,836 EXYNOS5420_PAD_RET_UART_OPTION,837 EXYNOS5420_PAD_RET_MMCA_OPTION,838 EXYNOS5420_PAD_RET_MMCB_OPTION,839 EXYNOS5420_PAD_RET_MMCC_OPTION,840 EXYNOS5420_PAD_RET_HSI_OPTION,841 EXYNOS_PAD_RET_EBIA_OPTION,842 EXYNOS_PAD_RET_EBIB_OPTION,843 EXYNOS5420_PAD_RET_SPI_OPTION,844 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,845};846 847static const struct samsung_retention_data exynos5420_retention_data __initconst = {848 .regs = exynos5420_retention_regs,849 .nr_regs = ARRAY_SIZE(exynos5420_retention_regs),850 .value = EXYNOS_WAKEUP_FROM_LOWPWR,851 .refcnt = &exynos_shared_retention_refcnt,852 .init = exynos_retention_init,853};854 855/*856 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes857 * four gpio/pin-mux/pinconfig controllers.858 */859static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {860 {861 /* pin-controller instance 0 data */862 .pin_banks = exynos5420_pin_banks0,863 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),864 .eint_gpio_init = exynos_eint_gpio_init,865 .eint_wkup_init = exynos_eint_wkup_init,866 .suspend = exynos_pinctrl_suspend,867 .resume = exynos_pinctrl_resume,868 .retention_data = &exynos5420_retention_data,869 }, {870 /* pin-controller instance 1 data */871 .pin_banks = exynos5420_pin_banks1,872 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),873 .eint_gpio_init = exynos_eint_gpio_init,874 .suspend = exynos_pinctrl_suspend,875 .resume = exynos_pinctrl_resume,876 .retention_data = &exynos5420_retention_data,877 }, {878 /* pin-controller instance 2 data */879 .pin_banks = exynos5420_pin_banks2,880 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),881 .eint_gpio_init = exynos_eint_gpio_init,882 .suspend = exynos_pinctrl_suspend,883 .resume = exynos_pinctrl_resume,884 .retention_data = &exynos5420_retention_data,885 }, {886 /* pin-controller instance 3 data */887 .pin_banks = exynos5420_pin_banks3,888 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),889 .eint_gpio_init = exynos_eint_gpio_init,890 .suspend = exynos_pinctrl_suspend,891 .resume = exynos_pinctrl_resume,892 .retention_data = &exynos5420_retention_data,893 }, {894 /* pin-controller instance 4 data */895 .pin_banks = exynos5420_pin_banks4,896 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),897 .eint_gpio_init = exynos_eint_gpio_init,898 .suspend = exynos_pinctrl_suspend,899 .resume = exynos_pinctrl_resume,900 .retention_data = &exynos4_audio_retention_data,901 },902};903 904const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = {905 .ctrl = exynos5420_pin_ctrl,906 .num_ctrl = ARRAY_SIZE(exynos5420_pin_ctrl),907};908