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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.4 *5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.6 * http://www.samsung.com7 * Copyright (c) 2012 Linaro Ltd8 * http://www.linaro.org9 *10 * Author: Thomas Abraham <thomas.ab@samsung.com>11 */12 13#ifndef __PINCTRL_SAMSUNG_H14#define __PINCTRL_SAMSUNG_H15 16#include <linux/pinctrl/pinctrl.h>17#include <linux/pinctrl/pinmux.h>18#include <linux/pinctrl/pinconf.h>19#include <linux/pinctrl/consumer.h>20#include <linux/pinctrl/machine.h>21 22#include <linux/gpio/driver.h>23 24/**25 * enum pincfg_type - possible pin configuration types supported.26 * @PINCFG_TYPE_FUNC: Function configuration.27 * @PINCFG_TYPE_DAT: Pin value configuration.28 * @PINCFG_TYPE_PUD: Pull up/down configuration.29 * @PINCFG_TYPE_DRV: Drive strength configuration.30 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.31 * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.32 */33enum pincfg_type {34 PINCFG_TYPE_FUNC,35 PINCFG_TYPE_DAT,36 PINCFG_TYPE_PUD,37 PINCFG_TYPE_DRV,38 PINCFG_TYPE_CON_PDN,39 PINCFG_TYPE_PUD_PDN,40 41 PINCFG_TYPE_NUM42};43 44/*45 * pin configuration (pull up/down and drive strength) type and its value are46 * packed together into a 16-bits. The upper 8-bits represent the configuration47 * type and the lower 8-bits hold the value of the configuration type.48 */49#define PINCFG_TYPE_MASK 0xFF50#define PINCFG_VALUE_SHIFT 851#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)52#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)53#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)54#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \55 PINCFG_VALUE_SHIFT)56/*57 * Values for the pin CON register, choosing pin function.58 * The basic set (input and output) are same between: S3C24xx, S3C64xx, S5PV210,59 * Exynos ARMv7, Exynos ARMv8, Tesla FSD.60 */61#define PIN_CON_FUNC_INPUT 0x062#define PIN_CON_FUNC_OUTPUT 0x163 64/* Values for the pin PUD register */65#define EXYNOS_PIN_PUD_PULL_DISABLE 0x066#define EXYNOS_PIN_PID_PULL_DOWN 0x167#define EXYNOS_PIN_PID_PULL_UP 0x368 69/*70 * enum pud_index - Possible index values to access the pud_val array.71 * @PUD_PULL_DISABLE: Index for the value of pud disable72 * @PUD_PULL_DOWN: Index for the value of pull down enable73 * @PUD_PULL_UP: Index for the value of pull up enable74 * @PUD_MAX: Maximum value of the index75 */76enum pud_index {77 PUD_PULL_DISABLE,78 PUD_PULL_DOWN,79 PUD_PULL_UP,80 PUD_MAX,81};82 83/**84 * enum eint_type - possible external interrupt types.85 * @EINT_TYPE_NONE: bank does not support external interrupts86 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts87 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts88 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts89 *90 * Samsung GPIO controller groups all the available pins into banks. The pins91 * in a pin bank can support external gpio interrupts or external wakeup92 * interrupts or no interrupts at all. From a software perspective, the only93 * difference between external gpio and external wakeup interrupts is that94 * the wakeup interrupts can additionally wakeup the system if it is in95 * suspended state.96 */97enum eint_type {98 EINT_TYPE_NONE,99 EINT_TYPE_GPIO,100 EINT_TYPE_WKUP,101 EINT_TYPE_WKUP_MUX,102};103 104/* maximum length of a pin in pin descriptor (example: "gpa0-0") */105#define PIN_NAME_LENGTH 10106 107#define PIN_GROUP(n, p, f) \108 { \109 .name = n, \110 .pins = p, \111 .num_pins = ARRAY_SIZE(p), \112 .func = f \113 }114 115#define PMX_FUNC(n, g) \116 { \117 .name = n, \118 .groups = g, \119 .num_groups = ARRAY_SIZE(g), \120 }121 122struct samsung_pinctrl_drv_data;123 124/**125 * struct samsung_pin_bank_type: pin bank type description126 * @fld_width: widths of configuration bitfields (0 if unavailable)127 * @reg_offset: offsets of configuration registers (don't care of width is 0)128 */129struct samsung_pin_bank_type {130 u8 fld_width[PINCFG_TYPE_NUM];131 u8 reg_offset[PINCFG_TYPE_NUM];132};133 134/**135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).136 * @type: type of the bank (register offsets and bitfield widths)137 * @pctl_offset: starting offset of the pin-bank registers.138 * @pctl_res_idx: index of base address for pin-bank registers.139 * @nr_pins: number of pins included in this bank.140 * @eint_func: function to set in CON register to configure pin as EINT.141 * @eint_type: type of the external interrupt supported by the bank.142 * @eint_mask: bit mask of pins which support EINT function.143 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.144 * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.145 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.146 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.147 * @name: name to be prefixed for each pin in this pin bank.148 */149struct samsung_pin_bank_data {150 const struct samsung_pin_bank_type *type;151 u32 pctl_offset;152 u8 pctl_res_idx;153 u8 nr_pins;154 u8 eint_func;155 enum eint_type eint_type;156 u32 eint_mask;157 u32 eint_offset;158 u32 eint_con_offset;159 u32 eint_mask_offset;160 u32 eint_pend_offset;161 const char *name;162};163 164/**165 * struct samsung_pin_bank: represent a controller pin-bank.166 * @type: type of the bank (register offsets and bitfield widths)167 * @pctl_base: base address of the pin-bank registers168 * @pctl_offset: starting offset of the pin-bank registers.169 * @nr_pins: number of pins included in this bank.170 * @eint_base: base address of the pin-bank EINT registers.171 * @eint_func: function to set in CON register to configure pin as EINT.172 * @eint_type: type of the external interrupt supported by the bank.173 * @eint_mask: bit mask of pins which support EINT function.174 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.175 * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.176 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.177 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.178 * @name: name to be prefixed for each pin in this pin bank.179 * @id: id of the bank, propagated to the pin range.180 * @pin_base: starting pin number of the bank.181 * @soc_priv: per-bank private data for SoC-specific code.182 * @of_node: OF node of the bank.183 * @drvdata: link to controller driver data184 * @irq_domain: IRQ domain of the bank.185 * @gpio_chip: GPIO chip of the bank.186 * @grange: linux gpio pin range supported by this bank.187 * @irq_chip: link to irq chip for external gpio and wakeup interrupts.188 * @slock: spinlock protecting bank registers189 * @pm_save: saved register values during suspend190 */191struct samsung_pin_bank {192 const struct samsung_pin_bank_type *type;193 void __iomem *pctl_base;194 u32 pctl_offset;195 u8 nr_pins;196 void __iomem *eint_base;197 u8 eint_func;198 enum eint_type eint_type;199 u32 eint_mask;200 u32 eint_offset;201 u32 eint_con_offset;202 u32 eint_mask_offset;203 u32 eint_pend_offset;204 const char *name;205 u32 id;206 207 u32 pin_base;208 void *soc_priv;209 struct fwnode_handle *fwnode;210 struct samsung_pinctrl_drv_data *drvdata;211 struct irq_domain *irq_domain;212 struct gpio_chip gpio_chip;213 struct pinctrl_gpio_range grange;214 struct exynos_irq_chip *irq_chip;215 raw_spinlock_t slock;216 217 u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/218};219 220/**221 * struct samsung_retention_data: runtime pin-bank retention control data.222 * @regs: array of PMU registers to control pad retention.223 * @nr_regs: number of registers in @regs array.224 * @value: value to store to registers to turn off retention.225 * @refcnt: atomic counter if retention control affects more than one bank.226 * @priv: retention control code private data227 * @enable: platform specific callback to enter retention mode.228 * @disable: platform specific callback to exit retention mode.229 **/230struct samsung_retention_ctrl {231 const u32 *regs;232 int nr_regs;233 u32 value;234 atomic_t *refcnt;235 void *priv;236 void (*enable)(struct samsung_pinctrl_drv_data *);237 void (*disable)(struct samsung_pinctrl_drv_data *);238};239 240/**241 * struct samsung_retention_data: represent a pin-bank retention control data.242 * @regs: array of PMU registers to control pad retention.243 * @nr_regs: number of registers in @regs array.244 * @value: value to store to registers to turn off retention.245 * @refcnt: atomic counter if retention control affects more than one bank.246 * @init: platform specific callback to initialize retention control.247 **/248struct samsung_retention_data {249 const u32 *regs;250 int nr_regs;251 u32 value;252 atomic_t *refcnt;253 struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *,254 const struct samsung_retention_data *);255};256 257/**258 * struct samsung_pin_ctrl: represent a pin controller.259 * @pin_banks: list of pin banks included in this controller.260 * @nr_banks: number of pin banks.261 * @nr_ext_resources: number of the extra base address for pin banks.262 * @retention_data: configuration data for retention control.263 * @eint_gpio_init: platform specific callback to setup the external gpio264 * interrupts for the controller.265 * @eint_wkup_init: platform specific callback to setup the external wakeup266 * interrupts for the controller.267 * @suspend: platform specific suspend callback, executed during pin controller268 * device suspend, see samsung_pinctrl_suspend()269 * @resume: platform specific resume callback, executed during pin controller270 * device suspend, see samsung_pinctrl_resume()271 *272 * External wakeup interrupts must define at least eint_wkup_init,273 * retention_data and suspend in order for proper suspend/resume to work.274 */275struct samsung_pin_ctrl {276 const struct samsung_pin_bank_data *pin_banks;277 unsigned int nr_banks;278 unsigned int nr_ext_resources;279 const struct samsung_retention_data *retention_data;280 281 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);282 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);283 void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata);284 void (*suspend)(struct samsung_pinctrl_drv_data *);285 void (*resume)(struct samsung_pinctrl_drv_data *);286};287 288/**289 * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.290 * @node: global list node291 * @virt_base: register base address of the controller; this will be equal292 * to each bank samsung_pin_bank->pctl_base and used on legacy293 * platforms (like S3C24XX or S3C64XX) which has to access the base294 * through samsung_pinctrl_drv_data, not samsung_pin_bank).295 * @dev: device instance representing the controller.296 * @irq: interrpt number used by the controller to notify gpio interrupts.297 * @pclk: optional bus clock if required for accessing registers298 * @ctrl: pin controller instance managed by the driver.299 * @pctl: pin controller descriptor registered with the pinctrl subsystem.300 * @pctl_dev: cookie representing pinctrl device instance.301 * @pin_groups: list of pin groups available to the driver.302 * @nr_groups: number of such pin groups.303 * @pmx_functions: list of pin functions available to the driver.304 * @nr_function: number of such pin functions.305 * @nr_pins: number of pins supported by the controller.306 * @retention_ctrl: retention control runtime data.307 * @suspend: platform specific suspend callback, executed during pin controller308 * device suspend, see samsung_pinctrl_suspend()309 * @resume: platform specific resume callback, executed during pin controller310 * device suspend, see samsung_pinctrl_resume()311 */312struct samsung_pinctrl_drv_data {313 struct list_head node;314 void __iomem *virt_base;315 struct device *dev;316 int irq;317 struct clk *pclk;318 319 struct pinctrl_desc pctl;320 struct pinctrl_dev *pctl_dev;321 322 const struct samsung_pin_group *pin_groups;323 unsigned int nr_groups;324 const struct samsung_pmx_func *pmx_functions;325 unsigned int nr_functions;326 327 struct samsung_pin_bank *pin_banks;328 unsigned int nr_banks;329 unsigned int nr_pins;330 unsigned int pud_val[PUD_MAX];331 332 struct samsung_retention_ctrl *retention_ctrl;333 334 void (*suspend)(struct samsung_pinctrl_drv_data *);335 void (*resume)(struct samsung_pinctrl_drv_data *);336};337 338/**339 * struct samsung_pinctrl_of_match_data: OF match device specific configuration data.340 * @ctrl: array of pin controller data.341 * @num_ctrl: size of array @ctrl.342 */343struct samsung_pinctrl_of_match_data {344 const struct samsung_pin_ctrl *ctrl;345 unsigned int num_ctrl;346};347 348/**349 * struct samsung_pin_group: represent group of pins of a pinmux function.350 * @name: name of the pin group, used to lookup the group.351 * @pins: the pins included in this group.352 * @num_pins: number of pins included in this group.353 * @func: the function number to be programmed when selected.354 */355struct samsung_pin_group {356 const char *name;357 const unsigned int *pins;358 u8 num_pins;359 u8 func;360};361 362/**363 * struct samsung_pmx_func: represent a pin function.364 * @name: name of the pin function, used to lookup the function.365 * @groups: one or more names of pin groups that provide this function.366 * @num_groups: number of groups included in @groups.367 */368struct samsung_pmx_func {369 const char *name;370 const char **groups;371 u8 num_groups;372 u32 val;373};374 375/* list of all exported SoC specific data */376extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;377extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;378extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data;379extern const struct samsung_pinctrl_of_match_data exynos5250_of_data;380extern const struct samsung_pinctrl_of_match_data exynos5260_of_data;381extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;382extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;383extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;384extern const struct samsung_pinctrl_of_match_data exynos7_of_data;385extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;386extern const struct samsung_pinctrl_of_match_data exynos850_of_data;387extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;388extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;389extern const struct samsung_pinctrl_of_match_data fsd_of_data;390extern const struct samsung_pinctrl_of_match_data gs101_of_data;391extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;392extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;393extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;394extern const struct samsung_pinctrl_of_match_data s3c2440_of_data;395extern const struct samsung_pinctrl_of_match_data s3c2450_of_data;396extern const struct samsung_pinctrl_of_match_data s5pv210_of_data;397 398#endif /* __PINCTRL_SAMSUNG_H */399