1353 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Pinctrl / GPIO driver for StarFive JH7100 SoC4 *5 * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd.6 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>7 */8 9#include <linux/bits.h>10#include <linux/clk.h>11#include <linux/gpio/driver.h>12#include <linux/io.h>13#include <linux/mod_devicetable.h>14#include <linux/module.h>15#include <linux/of.h>16#include <linux/platform_device.h>17#include <linux/reset.h>18#include <linux/seq_file.h>19#include <linux/spinlock.h>20 21#include <linux/pinctrl/consumer.h>22#include <linux/pinctrl/pinconf.h>23#include <linux/pinctrl/pinctrl.h>24#include <linux/pinctrl/pinmux.h>25 26#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>27 28#include "../core.h"29#include "../pinctrl-utils.h"30#include "../pinmux.h"31#include "../pinconf.h"32 33#define DRIVER_NAME "pinctrl-starfive"34 35/*36 * Refer to Section 12. GPIO Registers in the JH7100 data sheet:37 * https://github.com/starfive-tech/JH7100_Docs38 */39#define NR_GPIOS 6440 41/*42 * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts43 * are enabled. If set to 0 the GPIO interrupts are disabled.44 */45#define GPIOEN 0x00046 47/*48 * The following 32-bit registers come in pairs, but only the offset of the49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and50 * the second GPIO 32-63.51 */52 53/*54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the55 * interrupt is level-triggered.56 */57#define GPIOIS 0x01058 59/*60 * Edge-Trigger Interrupt Type. If set to 1 the interrupt gets triggered on61 * both positive and negative edges. If set to 0 the interrupt is triggered by a62 * single edge.63 */64#define GPIOIBE 0x01865 66/*67 * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a68 * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the69 * interrupt is triggered on a falling edge (edge-triggered) or low level70 * (level-triggered).71 */72#define GPIOIEV 0x02073 74/*75 * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 076 * the interrupt is disabled (masked). Note that the current documentation is77 * wrong and says the exct opposite of this.78 */79#define GPIOIE 0x02880 81/*82 * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered83 * interrupt.84 */85#define GPIOIC 0x03086 87/*88 * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.89 */90#define GPIORIS 0x03891 92/*93 * Interrupt Status after Masking. A 1 means the configured edge or level was94 * detected and not masked.95 */96#define GPIOMIS 0x04097 98/*99 * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is100 * a digital 1 and if 0 the pin is a digital 0.101 */102#define GPIODIN 0x048103 104/*105 * From the data sheet section 12.2, there are 64 32-bit output data registers106 * and 64 output enable registers. Output data and output enable registers for107 * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is108 * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c. The stride109 * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n110 * and GPOn_DOEN_CFG is 0x54 + 8n.111 */112#define GPON_DOUT_CFG 0x050113#define GPON_DOEN_CFG 0x054114 115/*116 * From Section 12.3, there are 75 input signal configuration registers which117 * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with118 * GPI_USB_OVER_CURRENT_CFG 0x378119 */120#define GPI_CFG_OFFSET 0x250121 122/*123 * Pad Control Bits. There are 16 pad control bits for each pin located in 103124 * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by125 * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16126 * bit of each register.127 */128#define PAD_SLEW_RATE_MASK GENMASK(11, 9)129#define PAD_SLEW_RATE_POS 9130#define PAD_BIAS_STRONG_PULL_UP BIT(8)131#define PAD_INPUT_ENABLE BIT(7)132#define PAD_INPUT_SCHMITT_ENABLE BIT(6)133#define PAD_BIAS_DISABLE BIT(5)134#define PAD_BIAS_PULL_DOWN BIT(4)135#define PAD_BIAS_MASK \136 (PAD_BIAS_STRONG_PULL_UP | \137 PAD_BIAS_DISABLE | \138 PAD_BIAS_PULL_DOWN)139#define PAD_DRIVE_STRENGTH_MASK GENMASK(3, 0)140#define PAD_DRIVE_STRENGTH_POS 0141 142/*143 * From Section 11, the IO_PADSHARE_SEL register can be programmed to select144 * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and145 * PAD_GPIO pads. This is a global setting.146 */147#define IO_PADSHARE_SEL 0x1a0148 149/*150 * This just needs to be some number such that when151 * sfp->gpio.pin_base = PAD_INVALID_GPIO then152 * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.153 * That is it should underflow and return something >= NR_GPIOS.154 */155#define PAD_INVALID_GPIO 0x10000156 157/*158 * The packed pinmux values from the device tree look like this:159 *160 * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 |161 * | dout | doen | din | dout rev | doen rev | gpio nr |162 *163 * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this:164 *165 * | 31 | 30 - 8 | 7 - 0 |166 * | dout/doen rev | unused | dout/doen |167 */168static unsigned int starfive_pinmux_to_gpio(u32 v)169{170 return v & (NR_GPIOS - 1);171}172 173static u32 starfive_pinmux_to_dout(u32 v)174{175 return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));176}177 178static u32 starfive_pinmux_to_doen(u32 v)179{180 return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));181}182 183static u32 starfive_pinmux_to_din(u32 v)184{185 return (v >> 8) & GENMASK(7, 0);186}187 188/*189 * The maximum GPIO output current depends on the chosen drive strength:190 *191 * DS: 0 1 2 3 4 5 6 7192 * mA: 14.2 21.2 28.2 35.2 42.2 49.1 56.0 62.8193 *194 * After rounding that is 7*DS + 14 mA195 */196static u32 starfive_drive_strength_to_max_mA(u16 ds)197{198 return 7 * ds + 14;199}200 201static u16 starfive_drive_strength_from_max_mA(u32 i)202{203 return (clamp(i, 14U, 63U) - 14) / 7;204}205 206struct starfive_pinctrl {207 struct gpio_chip gc;208 struct pinctrl_gpio_range gpios;209 raw_spinlock_t lock;210 void __iomem *base;211 void __iomem *padctl;212 struct pinctrl_dev *pctl;213 struct mutex mutex; /* serialize adding groups and functions */214};215 216static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,217 unsigned int pin)218{219 return pin - sfp->gpios.pin_base;220}221 222static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,223 unsigned int gpio)224{225 return sfp->gpios.pin_base + gpio;226}227 228static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)229{230 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);231 232 return container_of(gc, struct starfive_pinctrl, gc);233}234 235static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)236{237 struct gpio_chip *gc = irq_desc_get_handler_data(desc);238 239 return container_of(gc, struct starfive_pinctrl, gc);240}241 242static const struct pinctrl_pin_desc starfive_pins[] = {243 PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"),244 PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"),245 PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"),246 PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"),247 PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"),248 PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"),249 PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"),250 PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"),251 PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"),252 PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"),253 PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"),254 PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"),255 PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"),256 PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"),257 PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"),258 PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"),259 PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"),260 PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"),261 PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"),262 PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"),263 PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"),264 PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"),265 PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"),266 PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"),267 PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"),268 PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"),269 PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"),270 PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"),271 PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"),272 PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"),273 PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"),274 PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"),275 PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"),276 PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"),277 PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"),278 PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"),279 PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"),280 PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"),281 PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"),282 PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"),283 PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"),284 PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"),285 PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"),286 PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"),287 PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"),288 PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"),289 PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"),290 PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"),291 PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"),292 PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"),293 PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"),294 PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"),295 PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"),296 PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"),297 PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"),298 PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"),299 PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"),300 PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"),301 PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"),302 PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"),303 PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"),304 PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"),305 PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"),306 PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"),307 PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"),308 PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"),309 PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"),310 PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"),311 PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"),312 PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"),313 PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"),314 PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"),315 PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"),316 PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"),317 PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"),318 PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"),319 PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"),320 PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"),321 PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"),322 PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"),323 PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"),324 PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"),325 PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"),326 PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"),327 PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"),328 PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"),329 PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"),330 PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"),331 PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"),332 PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"),333 PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"),334 PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"),335 PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"),336 PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"),337 PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"),338 PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"),339 PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"),340 PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"),341 PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"),342 PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"),343 PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"),344 PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"),345 PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"),346 PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"),347 PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"),348 PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"),349 PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"),350 PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"),351 PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"),352 PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"),353 PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"),354 PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"),355 PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"),356 PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"),357 PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"),358 PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"),359 PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"),360 PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"),361 PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"),362 PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"),363 PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"),364 PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"),365 PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"),366 PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"),367 PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"),368 PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"),369 PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"),370 PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"),371 PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"),372 PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"),373 PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"),374 PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"),375 PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"),376 PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"),377 PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"),378 PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"),379 PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"),380 PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"),381 PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"),382 PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"),383 PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"),384 PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"),385 PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"),386 PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"),387 PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"),388 PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"),389 PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"),390 PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"),391 PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"),392 PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"),393 PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"),394 PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"),395 PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"),396 PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"),397 PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"),398 PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"),399 PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"),400 PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"),401 PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"),402 PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"),403 PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"),404 PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"),405 PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"),406 PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"),407 PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"),408 PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"),409 PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"),410 PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"),411 PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"),412 PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"),413 PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"),414 PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"),415 PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"),416 PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"),417 PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"),418 PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"),419 PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"),420 PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"),421 PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"),422 PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"),423 PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"),424 PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"),425 PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"),426 PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"),427 PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"),428 PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"),429 PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"),430 PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"),431 PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"),432 PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"),433 PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"),434 PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"),435 PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"),436 PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"),437 PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"),438 PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"),439 PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"),440 PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"),441 PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"),442 PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"),443 PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"),444 PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"),445 PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"),446 PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"),447 PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"),448 PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"),449};450 451#ifdef CONFIG_DEBUG_FS452static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,453 struct seq_file *s,454 unsigned int pin)455{456 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);457 unsigned int gpio = starfive_pin_to_gpio(sfp, pin);458 void __iomem *reg;459 u32 dout, doen;460 461 if (gpio >= NR_GPIOS)462 return;463 464 reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;465 dout = readl_relaxed(reg + 0x000);466 doen = readl_relaxed(reg + 0x004);467 468 seq_printf(s, "dout=%lu%s doen=%lu%s",469 dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "",470 doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : "");471}472#else473#define starfive_pin_dbg_show NULL474#endif475 476static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,477 struct device_node *np,478 struct pinctrl_map **maps,479 unsigned int *num_maps)480{481 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);482 struct device *dev = sfp->gc.parent;483 struct pinctrl_map *map;484 const char **pgnames;485 const char *grpname;486 u32 *pinmux;487 int ngroups;488 int *pins;489 int nmaps;490 int ret;491 492 nmaps = 0;493 ngroups = 0;494 for_each_available_child_of_node_scoped(np, child) {495 int npinmux = of_property_count_u32_elems(child, "pinmux");496 int npins = of_property_count_u32_elems(child, "pins");497 498 if (npinmux > 0 && npins > 0) {499 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",500 np, child);501 return -EINVAL;502 }503 if (npinmux == 0 && npins == 0) {504 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",505 np, child);506 return -EINVAL;507 }508 509 if (npinmux > 0)510 nmaps += 2;511 else512 nmaps += 1;513 ngroups += 1;514 }515 516 pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);517 if (!pgnames)518 return -ENOMEM;519 520 map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);521 if (!map)522 return -ENOMEM;523 524 nmaps = 0;525 ngroups = 0;526 mutex_lock(&sfp->mutex);527 for_each_available_child_of_node_scoped(np, child) {528 int npins;529 int i;530 531 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);532 if (!grpname) {533 ret = -ENOMEM;534 goto free_map;535 }536 537 pgnames[ngroups++] = grpname;538 539 if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) {540 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);541 if (!pins) {542 ret = -ENOMEM;543 goto free_map;544 }545 546 pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);547 if (!pinmux) {548 ret = -ENOMEM;549 goto free_map;550 }551 552 ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);553 if (ret)554 goto free_map;555 556 for (i = 0; i < npins; i++) {557 unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);558 559 pins[i] = starfive_gpio_to_pin(sfp, gpio);560 }561 562 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;563 map[nmaps].data.mux.function = np->name;564 map[nmaps].data.mux.group = grpname;565 nmaps += 1;566 } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) {567 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);568 if (!pins) {569 ret = -ENOMEM;570 goto free_map;571 }572 573 pinmux = NULL;574 575 for (i = 0; i < npins; i++) {576 u32 v;577 578 ret = of_property_read_u32_index(child, "pins", i, &v);579 if (ret)580 goto free_map;581 pins[i] = v;582 }583 } else {584 ret = -EINVAL;585 goto free_map;586 }587 588 ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);589 if (ret < 0) {590 dev_err(dev, "error adding group %s: %d\n", grpname, ret);591 goto free_map;592 }593 594 ret = pinconf_generic_parse_dt_config(child, pctldev,595 &map[nmaps].data.configs.configs,596 &map[nmaps].data.configs.num_configs);597 if (ret) {598 dev_err(dev, "error parsing pin config of group %s: %d\n",599 grpname, ret);600 goto free_map;601 }602 603 /* don't create a map if there are no pinconf settings */604 if (map[nmaps].data.configs.num_configs == 0)605 continue;606 607 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;608 map[nmaps].data.configs.group_or_pin = grpname;609 nmaps += 1;610 }611 612 ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);613 if (ret < 0) {614 dev_err(dev, "error adding function %s: %d\n", np->name, ret);615 goto free_map;616 }617 618 *maps = map;619 *num_maps = nmaps;620 mutex_unlock(&sfp->mutex);621 return 0;622 623free_map:624 pinctrl_utils_free_map(pctldev, map, nmaps);625 mutex_unlock(&sfp->mutex);626 return ret;627}628 629static const struct pinctrl_ops starfive_pinctrl_ops = {630 .get_groups_count = pinctrl_generic_get_group_count,631 .get_group_name = pinctrl_generic_get_group_name,632 .get_group_pins = pinctrl_generic_get_group_pins,633 .pin_dbg_show = starfive_pin_dbg_show,634 .dt_node_to_map = starfive_dt_node_to_map,635 .dt_free_map = pinctrl_utils_free_map,636};637 638static int starfive_set_mux(struct pinctrl_dev *pctldev,639 unsigned int fsel, unsigned int gsel)640{641 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);642 struct device *dev = sfp->gc.parent;643 const struct group_desc *group;644 const u32 *pinmux;645 unsigned int i;646 647 group = pinctrl_generic_get_group(pctldev, gsel);648 if (!group)649 return -EINVAL;650 651 pinmux = group->data;652 for (i = 0; i < group->grp.npins; i++) {653 u32 v = pinmux[i];654 unsigned int gpio = starfive_pinmux_to_gpio(v);655 u32 dout = starfive_pinmux_to_dout(v);656 u32 doen = starfive_pinmux_to_doen(v);657 u32 din = starfive_pinmux_to_din(v);658 void __iomem *reg_dout;659 void __iomem *reg_doen;660 void __iomem *reg_din;661 unsigned long flags;662 663 dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n",664 gpio, dout, doen, din);665 666 reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;667 reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;668 if (din != GPI_NONE)669 reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;670 else671 reg_din = NULL;672 673 raw_spin_lock_irqsave(&sfp->lock, flags);674 writel_relaxed(dout, reg_dout);675 writel_relaxed(doen, reg_doen);676 if (reg_din)677 writel_relaxed(gpio + 2, reg_din);678 raw_spin_unlock_irqrestore(&sfp->lock, flags);679 }680 681 return 0;682}683 684static const struct pinmux_ops starfive_pinmux_ops = {685 .get_functions_count = pinmux_generic_get_function_count,686 .get_function_name = pinmux_generic_get_function_name,687 .get_function_groups = pinmux_generic_get_function_groups,688 .set_mux = starfive_set_mux,689 .strict = true,690};691 692static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,693 unsigned int pin)694{695 void __iomem *reg = sfp->padctl + 4 * (pin / 2);696 int shift = 16 * (pin % 2);697 698 return readl_relaxed(reg) >> shift;699}700 701static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,702 unsigned int pin,703 u16 _mask, u16 _value)704{705 void __iomem *reg = sfp->padctl + 4 * (pin / 2);706 int shift = 16 * (pin % 2);707 u32 mask = (u32)_mask << shift;708 u32 value = (u32)_value << shift;709 unsigned long flags;710 711 dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);712 713 raw_spin_lock_irqsave(&sfp->lock, flags);714 value |= readl_relaxed(reg) & ~mask;715 writel_relaxed(value, reg);716 raw_spin_unlock_irqrestore(&sfp->lock, flags);717}718 719#define PIN_CONFIG_STARFIVE_STRONG_PULL_UP (PIN_CONFIG_END + 1)720 721static const struct pinconf_generic_params starfive_pinconf_custom_params[] = {722 { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },723};724 725#ifdef CONFIG_DEBUG_FS726static const struct pin_config_item starfive_pinconf_custom_conf_items[] = {727 PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),728};729 730static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) ==731 ARRAY_SIZE(starfive_pinconf_custom_params));732#else733#define starfive_pinconf_custom_conf_items NULL734#endif735 736static int starfive_pinconf_get(struct pinctrl_dev *pctldev,737 unsigned int pin, unsigned long *config)738{739 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);740 int param = pinconf_to_config_param(*config);741 u16 value = starfive_padctl_get(sfp, pin);742 bool enabled;743 u32 arg;744 745 switch (param) {746 case PIN_CONFIG_BIAS_DISABLE:747 enabled = value & PAD_BIAS_DISABLE;748 arg = 0;749 break;750 case PIN_CONFIG_BIAS_PULL_DOWN:751 enabled = value & PAD_BIAS_PULL_DOWN;752 arg = 1;753 break;754 case PIN_CONFIG_BIAS_PULL_UP:755 enabled = !(value & PAD_BIAS_MASK);756 arg = 1;757 break;758 case PIN_CONFIG_DRIVE_STRENGTH:759 enabled = value & PAD_DRIVE_STRENGTH_MASK;760 arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK);761 break;762 case PIN_CONFIG_INPUT_ENABLE:763 enabled = value & PAD_INPUT_ENABLE;764 arg = enabled;765 break;766 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:767 enabled = value & PAD_INPUT_SCHMITT_ENABLE;768 arg = enabled;769 break;770 case PIN_CONFIG_SLEW_RATE:771 enabled = value & PAD_SLEW_RATE_MASK;772 arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS;773 break;774 case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:775 enabled = value & PAD_BIAS_STRONG_PULL_UP;776 arg = enabled;777 break;778 default:779 return -ENOTSUPP;780 }781 782 *config = pinconf_to_config_packed(param, arg);783 return enabled ? 0 : -EINVAL;784}785 786static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,787 unsigned int gsel, unsigned long *config)788{789 const struct group_desc *group;790 791 group = pinctrl_generic_get_group(pctldev, gsel);792 if (!group)793 return -EINVAL;794 795 return starfive_pinconf_get(pctldev, group->grp.pins[0], config);796}797 798static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,799 unsigned int gsel,800 unsigned long *configs,801 unsigned int num_configs)802{803 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);804 const struct group_desc *group;805 u16 mask, value;806 int i;807 808 group = pinctrl_generic_get_group(pctldev, gsel);809 if (!group)810 return -EINVAL;811 812 mask = 0;813 value = 0;814 for (i = 0; i < num_configs; i++) {815 int param = pinconf_to_config_param(configs[i]);816 u32 arg = pinconf_to_config_argument(configs[i]);817 818 switch (param) {819 case PIN_CONFIG_BIAS_DISABLE:820 mask |= PAD_BIAS_MASK;821 value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE;822 break;823 case PIN_CONFIG_BIAS_PULL_DOWN:824 if (arg == 0)825 return -ENOTSUPP;826 mask |= PAD_BIAS_MASK;827 value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN;828 break;829 case PIN_CONFIG_BIAS_PULL_UP:830 if (arg == 0)831 return -ENOTSUPP;832 mask |= PAD_BIAS_MASK;833 value = value & ~PAD_BIAS_MASK;834 break;835 case PIN_CONFIG_DRIVE_STRENGTH:836 mask |= PAD_DRIVE_STRENGTH_MASK;837 value = (value & ~PAD_DRIVE_STRENGTH_MASK) |838 starfive_drive_strength_from_max_mA(arg);839 break;840 case PIN_CONFIG_INPUT_ENABLE:841 mask |= PAD_INPUT_ENABLE;842 if (arg)843 value |= PAD_INPUT_ENABLE;844 else845 value &= ~PAD_INPUT_ENABLE;846 break;847 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:848 mask |= PAD_INPUT_SCHMITT_ENABLE;849 if (arg)850 value |= PAD_INPUT_SCHMITT_ENABLE;851 else852 value &= ~PAD_INPUT_SCHMITT_ENABLE;853 break;854 case PIN_CONFIG_SLEW_RATE:855 mask |= PAD_SLEW_RATE_MASK;856 value = (value & ~PAD_SLEW_RATE_MASK) |857 ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK);858 break;859 case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:860 if (arg) {861 mask |= PAD_BIAS_MASK;862 value = (value & ~PAD_BIAS_MASK) |863 PAD_BIAS_STRONG_PULL_UP;864 } else {865 mask |= PAD_BIAS_STRONG_PULL_UP;866 value = value & ~PAD_BIAS_STRONG_PULL_UP;867 }868 break;869 default:870 return -ENOTSUPP;871 }872 }873 874 for (i = 0; i < group->grp.npins; i++)875 starfive_padctl_rmw(sfp, group->grp.pins[i], mask, value);876 877 return 0;878}879 880#ifdef CONFIG_DEBUG_FS881static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,882 struct seq_file *s, unsigned int pin)883{884 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);885 u16 value = starfive_padctl_get(sfp, pin);886 887 seq_printf(s, " (0x%03x)", value);888}889#else890#define starfive_pinconf_dbg_show NULL891#endif892 893static const struct pinconf_ops starfive_pinconf_ops = {894 .pin_config_get = starfive_pinconf_get,895 .pin_config_group_get = starfive_pinconf_group_get,896 .pin_config_group_set = starfive_pinconf_group_set,897 .pin_config_dbg_show = starfive_pinconf_dbg_show,898 .is_generic = true,899};900 901static struct pinctrl_desc starfive_desc = {902 .name = DRIVER_NAME,903 .pins = starfive_pins,904 .npins = ARRAY_SIZE(starfive_pins),905 .pctlops = &starfive_pinctrl_ops,906 .pmxops = &starfive_pinmux_ops,907 .confops = &starfive_pinconf_ops,908 .owner = THIS_MODULE,909 .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params),910 .custom_params = starfive_pinconf_custom_params,911 .custom_conf_items = starfive_pinconf_custom_conf_items,912};913 914static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)915{916 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);917 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;918 919 if (readl_relaxed(doen) == GPO_ENABLE)920 return GPIO_LINE_DIRECTION_OUT;921 922 return GPIO_LINE_DIRECTION_IN;923}924 925static int starfive_gpio_direction_input(struct gpio_chip *gc,926 unsigned int gpio)927{928 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);929 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;930 unsigned long flags;931 932 /* enable input and schmitt trigger */933 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),934 PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,935 PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE);936 937 raw_spin_lock_irqsave(&sfp->lock, flags);938 writel_relaxed(GPO_DISABLE, doen);939 raw_spin_unlock_irqrestore(&sfp->lock, flags);940 return 0;941}942 943static int starfive_gpio_direction_output(struct gpio_chip *gc,944 unsigned int gpio, int value)945{946 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);947 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;948 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;949 unsigned long flags;950 951 raw_spin_lock_irqsave(&sfp->lock, flags);952 writel_relaxed(value, dout);953 writel_relaxed(GPO_ENABLE, doen);954 raw_spin_unlock_irqrestore(&sfp->lock, flags);955 956 /* disable input, schmitt trigger and bias */957 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),958 PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,959 PAD_BIAS_DISABLE);960 961 return 0;962}963 964static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)965{966 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);967 void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);968 969 return !!(readl_relaxed(din) & BIT(gpio % 32));970}971 972static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,973 int value)974{975 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);976 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;977 unsigned long flags;978 979 raw_spin_lock_irqsave(&sfp->lock, flags);980 writel_relaxed(value, dout);981 raw_spin_unlock_irqrestore(&sfp->lock, flags);982}983 984static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,985 unsigned long config)986{987 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);988 u32 arg = pinconf_to_config_argument(config);989 u16 value;990 u16 mask;991 992 switch (pinconf_to_config_param(config)) {993 case PIN_CONFIG_BIAS_DISABLE:994 mask = PAD_BIAS_MASK;995 value = PAD_BIAS_DISABLE;996 break;997 case PIN_CONFIG_BIAS_PULL_DOWN:998 if (arg == 0)999 return -ENOTSUPP;1000 mask = PAD_BIAS_MASK;1001 value = PAD_BIAS_PULL_DOWN;1002 break;1003 case PIN_CONFIG_BIAS_PULL_UP:1004 if (arg == 0)1005 return -ENOTSUPP;1006 mask = PAD_BIAS_MASK;1007 value = 0;1008 break;1009 case PIN_CONFIG_DRIVE_PUSH_PULL:1010 return 0;1011 case PIN_CONFIG_INPUT_ENABLE:1012 mask = PAD_INPUT_ENABLE;1013 value = arg ? PAD_INPUT_ENABLE : 0;1014 break;1015 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:1016 mask = PAD_INPUT_SCHMITT_ENABLE;1017 value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0;1018 break;1019 default:1020 return -ENOTSUPP;1021 }1022 1023 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);1024 return 0;1025}1026 1027static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)1028{1029 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);1030 1031 sfp->gpios.name = sfp->gc.label;1032 sfp->gpios.base = sfp->gc.base;1033 /*1034 * sfp->gpios.pin_base depends on the chosen signal group1035 * and is set in starfive_probe()1036 */1037 sfp->gpios.npins = NR_GPIOS;1038 sfp->gpios.gc = &sfp->gc;1039 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);1040 return 0;1041}1042 1043static void starfive_irq_ack(struct irq_data *d)1044{1045 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);1046 irq_hw_number_t gpio = irqd_to_hwirq(d);1047 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);1048 u32 mask = BIT(gpio % 32);1049 unsigned long flags;1050 1051 raw_spin_lock_irqsave(&sfp->lock, flags);1052 writel_relaxed(mask, ic);1053 raw_spin_unlock_irqrestore(&sfp->lock, flags);1054}1055 1056static void starfive_irq_mask(struct irq_data *d)1057{1058 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);1059 irq_hw_number_t gpio = irqd_to_hwirq(d);1060 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);1061 u32 mask = BIT(gpio % 32);1062 unsigned long flags;1063 u32 value;1064 1065 raw_spin_lock_irqsave(&sfp->lock, flags);1066 value = readl_relaxed(ie) & ~mask;1067 writel_relaxed(value, ie);1068 raw_spin_unlock_irqrestore(&sfp->lock, flags);1069 1070 gpiochip_disable_irq(&sfp->gc, gpio);1071}1072 1073static void starfive_irq_mask_ack(struct irq_data *d)1074{1075 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);1076 irq_hw_number_t gpio = irqd_to_hwirq(d);1077 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);1078 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);1079 u32 mask = BIT(gpio % 32);1080 unsigned long flags;1081 u32 value;1082 1083 raw_spin_lock_irqsave(&sfp->lock, flags);1084 value = readl_relaxed(ie) & ~mask;1085 writel_relaxed(value, ie);1086 writel_relaxed(mask, ic);1087 raw_spin_unlock_irqrestore(&sfp->lock, flags);1088}1089 1090static void starfive_irq_unmask(struct irq_data *d)1091{1092 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);1093 irq_hw_number_t gpio = irqd_to_hwirq(d);1094 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);1095 u32 mask = BIT(gpio % 32);1096 unsigned long flags;1097 u32 value;1098 1099 gpiochip_enable_irq(&sfp->gc, gpio);1100 1101 raw_spin_lock_irqsave(&sfp->lock, flags);1102 value = readl_relaxed(ie) | mask;1103 writel_relaxed(value, ie);1104 raw_spin_unlock_irqrestore(&sfp->lock, flags);1105}1106 1107static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)1108{1109 struct starfive_pinctrl *sfp = starfive_from_irq_data(d);1110 irq_hw_number_t gpio = irqd_to_hwirq(d);1111 void __iomem *base = sfp->base + 4 * (gpio / 32);1112 u32 mask = BIT(gpio % 32);1113 u32 irq_type, edge_both, polarity;1114 unsigned long flags;1115 1116 switch (trigger) {1117 case IRQ_TYPE_EDGE_RISING:1118 irq_type = mask; /* 1: edge triggered */1119 edge_both = 0; /* 0: single edge */1120 polarity = mask; /* 1: rising edge */1121 break;1122 case IRQ_TYPE_EDGE_FALLING:1123 irq_type = mask; /* 1: edge triggered */1124 edge_both = 0; /* 0: single edge */1125 polarity = 0; /* 0: falling edge */1126 break;1127 case IRQ_TYPE_EDGE_BOTH:1128 irq_type = mask; /* 1: edge triggered */1129 edge_both = mask; /* 1: both edges */1130 polarity = 0; /* 0: ignored */1131 break;1132 case IRQ_TYPE_LEVEL_HIGH:1133 irq_type = 0; /* 0: level triggered */1134 edge_both = 0; /* 0: ignored */1135 polarity = mask; /* 1: high level */1136 break;1137 case IRQ_TYPE_LEVEL_LOW:1138 irq_type = 0; /* 0: level triggered */1139 edge_both = 0; /* 0: ignored */1140 polarity = 0; /* 0: low level */1141 break;1142 default:1143 return -EINVAL;1144 }1145 1146 if (trigger & IRQ_TYPE_EDGE_BOTH)1147 irq_set_handler_locked(d, handle_edge_irq);1148 else1149 irq_set_handler_locked(d, handle_level_irq);1150 1151 raw_spin_lock_irqsave(&sfp->lock, flags);1152 irq_type |= readl_relaxed(base + GPIOIS) & ~mask;1153 writel_relaxed(irq_type, base + GPIOIS);1154 edge_both |= readl_relaxed(base + GPIOIBE) & ~mask;1155 writel_relaxed(edge_both, base + GPIOIBE);1156 polarity |= readl_relaxed(base + GPIOIEV) & ~mask;1157 writel_relaxed(polarity, base + GPIOIEV);1158 raw_spin_unlock_irqrestore(&sfp->lock, flags);1159 return 0;1160}1161 1162static const struct irq_chip starfive_irq_chip = {1163 .name = "StarFive GPIO",1164 .irq_ack = starfive_irq_ack,1165 .irq_mask = starfive_irq_mask,1166 .irq_mask_ack = starfive_irq_mask_ack,1167 .irq_unmask = starfive_irq_unmask,1168 .irq_set_type = starfive_irq_set_type,1169 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,1170 GPIOCHIP_IRQ_RESOURCE_HELPERS,1171};1172 1173static void starfive_gpio_irq_handler(struct irq_desc *desc)1174{1175 struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);1176 struct irq_chip *chip = irq_desc_get_chip(desc);1177 unsigned long mis;1178 unsigned int pin;1179 1180 chained_irq_enter(chip, desc);1181 1182 mis = readl_relaxed(sfp->base + GPIOMIS + 0);1183 for_each_set_bit(pin, &mis, 32)1184 generic_handle_domain_irq(sfp->gc.irq.domain, pin);1185 1186 mis = readl_relaxed(sfp->base + GPIOMIS + 4);1187 for_each_set_bit(pin, &mis, 32)1188 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);1189 1190 chained_irq_exit(chip, desc);1191}1192 1193static int starfive_gpio_init_hw(struct gpio_chip *gc)1194{1195 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);1196 1197 /* mask all GPIO interrupts */1198 writel(0, sfp->base + GPIOIE + 0);1199 writel(0, sfp->base + GPIOIE + 4);1200 /* clear edge interrupt flags */1201 writel(~0U, sfp->base + GPIOIC + 0);1202 writel(~0U, sfp->base + GPIOIC + 4);1203 /* enable GPIO interrupts */1204 writel(1, sfp->base + GPIOEN);1205 return 0;1206}1207 1208static void starfive_disable_clock(void *data)1209{1210 clk_disable_unprepare(data);1211}1212 1213static int starfive_probe(struct platform_device *pdev)1214{1215 struct device *dev = &pdev->dev;1216 struct starfive_pinctrl *sfp;1217 struct reset_control *rst;1218 struct clk *clk;1219 u32 value;1220 int ret;1221 1222 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);1223 if (!sfp)1224 return -ENOMEM;1225 1226 sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");1227 if (IS_ERR(sfp->base))1228 return PTR_ERR(sfp->base);1229 1230 sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");1231 if (IS_ERR(sfp->padctl))1232 return PTR_ERR(sfp->padctl);1233 1234 clk = devm_clk_get(dev, NULL);1235 if (IS_ERR(clk))1236 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");1237 1238 rst = devm_reset_control_get_exclusive(dev, NULL);1239 if (IS_ERR(rst))1240 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");1241 1242 ret = clk_prepare_enable(clk);1243 if (ret)1244 return dev_err_probe(dev, ret, "could not enable clock\n");1245 1246 ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);1247 if (ret)1248 return ret;1249 1250 /*1251 * We don't want to assert reset and risk undoing pin muxing for the1252 * early boot serial console, but let's make sure the reset line is1253 * deasserted in case someone runs a really minimal bootloader.1254 */1255 ret = reset_control_deassert(rst);1256 if (ret)1257 return dev_err_probe(dev, ret, "could not deassert reset\n");1258 1259 platform_set_drvdata(pdev, sfp);1260 sfp->gc.parent = dev;1261 raw_spin_lock_init(&sfp->lock);1262 mutex_init(&sfp->mutex);1263 1264 ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);1265 if (ret)1266 return dev_err_probe(dev, ret, "could not register pinctrl driver\n");1267 1268 if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {1269 if (value > 6)1270 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);1271 writel(value, sfp->padctl + IO_PADSHARE_SEL);1272 }1273 1274 value = readl(sfp->padctl + IO_PADSHARE_SEL);1275 switch (value) {1276 case 0:1277 sfp->gpios.pin_base = PAD_INVALID_GPIO;1278 goto out_pinctrl_enable;1279 case 1:1280 sfp->gpios.pin_base = PAD_GPIO(0);1281 break;1282 case 2:1283 sfp->gpios.pin_base = PAD_FUNC_SHARE(72);1284 break;1285 case 3:1286 sfp->gpios.pin_base = PAD_FUNC_SHARE(70);1287 break;1288 case 4: case 5: case 6:1289 sfp->gpios.pin_base = PAD_FUNC_SHARE(0);1290 break;1291 default:1292 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);1293 }1294 1295 sfp->gc.label = dev_name(dev);1296 sfp->gc.owner = THIS_MODULE;1297 sfp->gc.request = pinctrl_gpio_request;1298 sfp->gc.free = pinctrl_gpio_free;1299 sfp->gc.get_direction = starfive_gpio_get_direction;1300 sfp->gc.direction_input = starfive_gpio_direction_input;1301 sfp->gc.direction_output = starfive_gpio_direction_output;1302 sfp->gc.get = starfive_gpio_get;1303 sfp->gc.set = starfive_gpio_set;1304 sfp->gc.set_config = starfive_gpio_set_config;1305 sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;1306 sfp->gc.base = -1;1307 sfp->gc.ngpio = NR_GPIOS;1308 1309 gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);1310 sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;1311 sfp->gc.irq.num_parents = 1;1312 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,1313 sizeof(*sfp->gc.irq.parents), GFP_KERNEL);1314 if (!sfp->gc.irq.parents)1315 return -ENOMEM;1316 sfp->gc.irq.default_type = IRQ_TYPE_NONE;1317 sfp->gc.irq.handler = handle_bad_irq;1318 sfp->gc.irq.init_hw = starfive_gpio_init_hw;1319 1320 ret = platform_get_irq(pdev, 0);1321 if (ret < 0)1322 return ret;1323 sfp->gc.irq.parents[0] = ret;1324 1325 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);1326 if (ret)1327 return dev_err_probe(dev, ret, "could not register gpiochip\n");1328 1329 irq_domain_set_pm_device(sfp->gc.irq.domain, dev);1330 1331out_pinctrl_enable:1332 return pinctrl_enable(sfp->pctl);1333}1334 1335static const struct of_device_id starfive_of_match[] = {1336 { .compatible = "starfive,jh7100-pinctrl" },1337 { /* sentinel */ }1338};1339MODULE_DEVICE_TABLE(of, starfive_of_match);1340 1341static struct platform_driver starfive_pinctrl_driver = {1342 .probe = starfive_probe,1343 .driver = {1344 .name = DRIVER_NAME,1345 .of_match_table = starfive_of_match,1346 },1347};1348module_platform_driver(starfive_pinctrl_driver);1349 1350MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs");1351MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");1352MODULE_LICENSE("GPL v2");1353