1008 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Pinctrl / GPIO driver for StarFive JH7110 SoC4 *5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>6 * Copyright (C) 2022 StarFive Technology Co., Ltd.7 */8 9#include <linux/bits.h>10#include <linux/clk.h>11#include <linux/gpio/driver.h>12#include <linux/io.h>13#include <linux/mod_devicetable.h>14#include <linux/module.h>15#include <linux/mutex.h>16#include <linux/of.h>17#include <linux/platform_device.h>18#include <linux/reset.h>19#include <linux/seq_file.h>20#include <linux/spinlock.h>21 22#include <linux/pinctrl/consumer.h>23#include <linux/pinctrl/pinconf.h>24#include <linux/pinctrl/pinctrl.h>25#include <linux/pinctrl/pinmux.h>26 27#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>28 29#include "../core.h"30#include "../pinctrl-utils.h"31#include "../pinmux.h"32#include "../pinconf.h"33#include "pinctrl-starfive-jh7110.h"34 35/* pad control bits */36#define JH7110_PADCFG_POS BIT(7)37#define JH7110_PADCFG_SMT BIT(6)38#define JH7110_PADCFG_SLEW BIT(5)39#define JH7110_PADCFG_PD BIT(4)40#define JH7110_PADCFG_PU BIT(3)41#define JH7110_PADCFG_BIAS (JH7110_PADCFG_PD | JH7110_PADCFG_PU)42#define JH7110_PADCFG_DS_MASK GENMASK(2, 1)43#define JH7110_PADCFG_DS_2MA (0U << 1)44#define JH7110_PADCFG_DS_4MA BIT(1)45#define JH7110_PADCFG_DS_8MA (2U << 1)46#define JH7110_PADCFG_DS_12MA (3U << 1)47#define JH7110_PADCFG_IE BIT(0)48 49/*50 * The packed pinmux values from the device tree look like this:51 *52 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |53 * | din | dout | doen | function | pin |54 */55static unsigned int jh7110_pinmux_din(u32 v)56{57 return (v & GENMASK(31, 24)) >> 24;58}59 60static u32 jh7110_pinmux_dout(u32 v)61{62 return (v & GENMASK(23, 16)) >> 16;63}64 65static u32 jh7110_pinmux_doen(u32 v)66{67 return (v & GENMASK(15, 10)) >> 10;68}69 70static u32 jh7110_pinmux_function(u32 v)71{72 return (v & GENMASK(9, 8)) >> 8;73}74 75static unsigned int jh7110_pinmux_pin(u32 v)76{77 return v & GENMASK(7, 0);78}79 80static struct jh7110_pinctrl *jh7110_from_irq_data(struct irq_data *d)81{82 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);83 84 return container_of(gc, struct jh7110_pinctrl, gc);85}86 87struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc)88{89 struct gpio_chip *gc = irq_desc_get_handler_data(desc);90 91 return container_of(gc, struct jh7110_pinctrl, gc);92}93EXPORT_SYMBOL_GPL(jh7110_from_irq_desc);94 95#ifdef CONFIG_DEBUG_FS96static void jh7110_pin_dbg_show(struct pinctrl_dev *pctldev,97 struct seq_file *s, unsigned int pin)98{99 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);100 const struct jh7110_pinctrl_soc_info *info = sfp->info;101 102 seq_printf(s, "%s", dev_name(pctldev->dev));103 104 if (pin < sfp->gc.ngpio) {105 unsigned int offset = 4 * (pin / 4);106 unsigned int shift = 8 * (pin % 4);107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset);108 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);109 u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset);110 111 dout = (dout >> shift) & info->dout_mask;112 doen = (doen >> shift) & info->doen_mask;113 gpi = ((gpi >> shift) - 2) & info->gpi_mask;114 115 seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi);116 }117}118#else119#define jh7110_pin_dbg_show NULL120#endif121 122static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,123 struct device_node *np,124 struct pinctrl_map **maps,125 unsigned int *num_maps)126{127 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);128 struct device *dev = sfp->gc.parent;129 struct device_node *child;130 struct pinctrl_map *map;131 const char **pgnames;132 const char *grpname;133 int ngroups;134 int nmaps;135 int ret;136 137 ngroups = 0;138 for_each_available_child_of_node(np, child)139 ngroups += 1;140 nmaps = 2 * ngroups;141 142 pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);143 if (!pgnames)144 return -ENOMEM;145 146 map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);147 if (!map)148 return -ENOMEM;149 150 nmaps = 0;151 ngroups = 0;152 mutex_lock(&sfp->mutex);153 for_each_available_child_of_node_scoped(np, child) {154 int npins = of_property_count_u32_elems(child, "pinmux");155 int *pins;156 u32 *pinmux;157 int i;158 159 if (npins < 1) {160 dev_err(dev,161 "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n",162 np, child);163 ret = -EINVAL;164 goto free_map;165 }166 167 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);168 if (!grpname) {169 ret = -ENOMEM;170 goto free_map;171 }172 173 pgnames[ngroups++] = grpname;174 175 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);176 if (!pins) {177 ret = -ENOMEM;178 goto free_map;179 }180 181 pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);182 if (!pinmux) {183 ret = -ENOMEM;184 goto free_map;185 }186 187 ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);188 if (ret)189 goto free_map;190 191 for (i = 0; i < npins; i++)192 pins[i] = jh7110_pinmux_pin(pinmux[i]);193 194 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;195 map[nmaps].data.mux.function = np->name;196 map[nmaps].data.mux.group = grpname;197 nmaps += 1;198 199 ret = pinctrl_generic_add_group(pctldev, grpname,200 pins, npins, pinmux);201 if (ret < 0) {202 dev_err(dev, "error adding group %s: %d\n", grpname, ret);203 goto free_map;204 }205 206 ret = pinconf_generic_parse_dt_config(child, pctldev,207 &map[nmaps].data.configs.configs,208 &map[nmaps].data.configs.num_configs);209 if (ret) {210 dev_err(dev, "error parsing pin config of group %s: %d\n",211 grpname, ret);212 goto free_map;213 }214 215 /* don't create a map if there are no pinconf settings */216 if (map[nmaps].data.configs.num_configs == 0)217 continue;218 219 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;220 map[nmaps].data.configs.group_or_pin = grpname;221 nmaps += 1;222 }223 224 ret = pinmux_generic_add_function(pctldev, np->name,225 pgnames, ngroups, NULL);226 if (ret < 0) {227 dev_err(dev, "error adding function %s: %d\n", np->name, ret);228 goto free_map;229 }230 mutex_unlock(&sfp->mutex);231 232 *maps = map;233 *num_maps = nmaps;234 return 0;235 236free_map:237 pinctrl_utils_free_map(pctldev, map, nmaps);238 mutex_unlock(&sfp->mutex);239 return ret;240}241 242static const struct pinctrl_ops jh7110_pinctrl_ops = {243 .get_groups_count = pinctrl_generic_get_group_count,244 .get_group_name = pinctrl_generic_get_group_name,245 .get_group_pins = pinctrl_generic_get_group_pins,246 .pin_dbg_show = jh7110_pin_dbg_show,247 .dt_node_to_map = jh7110_dt_node_to_map,248 .dt_free_map = pinctrl_utils_free_map,249};250 251void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,252 unsigned int din, u32 dout, u32 doen)253{254 const struct jh7110_pinctrl_soc_info *info = sfp->info;255 256 unsigned int offset = 4 * (pin / 4);257 unsigned int shift = 8 * (pin % 4);258 u32 dout_mask = info->dout_mask << shift;259 u32 done_mask = info->doen_mask << shift;260 u32 ival, imask;261 void __iomem *reg_dout;262 void __iomem *reg_doen;263 void __iomem *reg_din;264 unsigned long flags;265 266 reg_dout = sfp->base + info->dout_reg_base + offset;267 reg_doen = sfp->base + info->doen_reg_base + offset;268 dout <<= shift;269 doen <<= shift;270 if (din != GPI_NONE) {271 unsigned int ioffset = 4 * (din / 4);272 unsigned int ishift = 8 * (din % 4);273 274 reg_din = sfp->base + info->gpi_reg_base + ioffset;275 ival = (pin + 2) << ishift;276 imask = info->gpi_mask << ishift;277 } else {278 reg_din = NULL;279 }280 281 raw_spin_lock_irqsave(&sfp->lock, flags);282 dout |= readl_relaxed(reg_dout) & ~dout_mask;283 writel_relaxed(dout, reg_dout);284 doen |= readl_relaxed(reg_doen) & ~done_mask;285 writel_relaxed(doen, reg_doen);286 if (reg_din) {287 ival |= readl_relaxed(reg_din) & ~imask;288 writel_relaxed(ival, reg_din);289 }290 raw_spin_unlock_irqrestore(&sfp->lock, flags);291}292EXPORT_SYMBOL_GPL(jh7110_set_gpiomux);293 294static int jh7110_set_mux(struct pinctrl_dev *pctldev,295 unsigned int fsel, unsigned int gsel)296{297 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);298 const struct jh7110_pinctrl_soc_info *info = sfp->info;299 const struct group_desc *group;300 const u32 *pinmux;301 unsigned int i;302 303 group = pinctrl_generic_get_group(pctldev, gsel);304 if (!group)305 return -EINVAL;306 307 pinmux = group->data;308 for (i = 0; i < group->grp.npins; i++) {309 u32 v = pinmux[i];310 311 if (info->jh7110_set_one_pin_mux)312 info->jh7110_set_one_pin_mux(sfp,313 jh7110_pinmux_pin(v),314 jh7110_pinmux_din(v),315 jh7110_pinmux_dout(v),316 jh7110_pinmux_doen(v),317 jh7110_pinmux_function(v));318 }319 320 return 0;321}322 323static const struct pinmux_ops jh7110_pinmux_ops = {324 .get_functions_count = pinmux_generic_get_function_count,325 .get_function_name = pinmux_generic_get_function_name,326 .get_function_groups = pinmux_generic_get_function_groups,327 .set_mux = jh7110_set_mux,328 .strict = true,329};330 331static const u8 jh7110_drive_strength_mA[4] = { 2, 4, 8, 12 };332 333static u32 jh7110_padcfg_ds_to_mA(u32 padcfg)334{335 return jh7110_drive_strength_mA[(padcfg >> 1) & 3U];336}337 338static u32 jh7110_padcfg_ds_from_mA(u32 v)339{340 int i;341 342 for (i = 0; i < 3; i++) {343 if (v <= jh7110_drive_strength_mA[i])344 break;345 }346 return i << 1;347}348 349static void jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp,350 unsigned int pin, u32 mask, u32 value)351{352 const struct jh7110_pinctrl_soc_info *info = sfp->info;353 void __iomem *reg;354 unsigned long flags;355 int padcfg_base;356 357 if (!info->jh7110_get_padcfg_base)358 return;359 360 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);361 if (padcfg_base < 0)362 return;363 364 reg = sfp->base + padcfg_base + 4 * pin;365 value &= mask;366 367 raw_spin_lock_irqsave(&sfp->lock, flags);368 value |= readl_relaxed(reg) & ~mask;369 writel_relaxed(value, reg);370 raw_spin_unlock_irqrestore(&sfp->lock, flags);371}372 373static int jh7110_pinconf_get(struct pinctrl_dev *pctldev,374 unsigned int pin, unsigned long *config)375{376 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);377 const struct jh7110_pinctrl_soc_info *info = sfp->info;378 int param = pinconf_to_config_param(*config);379 u32 padcfg, arg;380 bool enabled;381 int padcfg_base;382 383 if (!info->jh7110_get_padcfg_base)384 return 0;385 386 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);387 if (padcfg_base < 0)388 return 0;389 390 padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin);391 switch (param) {392 case PIN_CONFIG_BIAS_DISABLE:393 enabled = !(padcfg & JH7110_PADCFG_BIAS);394 arg = 0;395 break;396 case PIN_CONFIG_BIAS_PULL_DOWN:397 enabled = padcfg & JH7110_PADCFG_PD;398 arg = 1;399 break;400 case PIN_CONFIG_BIAS_PULL_UP:401 enabled = padcfg & JH7110_PADCFG_PU;402 arg = 1;403 break;404 case PIN_CONFIG_DRIVE_STRENGTH:405 enabled = true;406 arg = jh7110_padcfg_ds_to_mA(padcfg);407 break;408 case PIN_CONFIG_INPUT_ENABLE:409 enabled = padcfg & JH7110_PADCFG_IE;410 arg = enabled;411 break;412 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:413 enabled = padcfg & JH7110_PADCFG_SMT;414 arg = enabled;415 break;416 case PIN_CONFIG_SLEW_RATE:417 enabled = true;418 arg = !!(padcfg & JH7110_PADCFG_SLEW);419 break;420 default:421 return -ENOTSUPP;422 }423 424 *config = pinconf_to_config_packed(param, arg);425 return enabled ? 0 : -EINVAL;426}427 428static int jh7110_pinconf_group_get(struct pinctrl_dev *pctldev,429 unsigned int gsel,430 unsigned long *config)431{432 const struct group_desc *group;433 434 group = pinctrl_generic_get_group(pctldev, gsel);435 if (!group)436 return -EINVAL;437 438 return jh7110_pinconf_get(pctldev, group->grp.pins[0], config);439}440 441static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev,442 unsigned int gsel,443 unsigned long *configs,444 unsigned int num_configs)445{446 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);447 const struct group_desc *group;448 u16 mask, value;449 int i;450 451 group = pinctrl_generic_get_group(pctldev, gsel);452 if (!group)453 return -EINVAL;454 455 mask = 0;456 value = 0;457 for (i = 0; i < num_configs; i++) {458 int param = pinconf_to_config_param(configs[i]);459 u32 arg = pinconf_to_config_argument(configs[i]);460 461 switch (param) {462 case PIN_CONFIG_BIAS_DISABLE:463 mask |= JH7110_PADCFG_BIAS;464 value &= ~JH7110_PADCFG_BIAS;465 break;466 case PIN_CONFIG_BIAS_PULL_DOWN:467 if (arg == 0)468 return -ENOTSUPP;469 mask |= JH7110_PADCFG_BIAS;470 value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PD;471 break;472 case PIN_CONFIG_BIAS_PULL_UP:473 if (arg == 0)474 return -ENOTSUPP;475 mask |= JH7110_PADCFG_BIAS;476 value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PU;477 break;478 case PIN_CONFIG_DRIVE_STRENGTH:479 mask |= JH7110_PADCFG_DS_MASK;480 value = (value & ~JH7110_PADCFG_DS_MASK) |481 jh7110_padcfg_ds_from_mA(arg);482 break;483 case PIN_CONFIG_INPUT_ENABLE:484 mask |= JH7110_PADCFG_IE;485 if (arg)486 value |= JH7110_PADCFG_IE;487 else488 value &= ~JH7110_PADCFG_IE;489 break;490 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:491 mask |= JH7110_PADCFG_SMT;492 if (arg)493 value |= JH7110_PADCFG_SMT;494 else495 value &= ~JH7110_PADCFG_SMT;496 break;497 case PIN_CONFIG_SLEW_RATE:498 mask |= JH7110_PADCFG_SLEW;499 if (arg)500 value |= JH7110_PADCFG_SLEW;501 else502 value &= ~JH7110_PADCFG_SLEW;503 break;504 default:505 return -ENOTSUPP;506 }507 }508 509 for (i = 0; i < group->grp.npins; i++)510 jh7110_padcfg_rmw(sfp, group->grp.pins[i], mask, value);511 512 return 0;513}514 515#ifdef CONFIG_DEBUG_FS516static void jh7110_pinconf_dbg_show(struct pinctrl_dev *pctldev,517 struct seq_file *s, unsigned int pin)518{519 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);520 const struct jh7110_pinctrl_soc_info *info = sfp->info;521 u32 value;522 int padcfg_base;523 524 if (!info->jh7110_get_padcfg_base)525 return;526 527 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);528 if (padcfg_base < 0)529 return;530 531 value = readl_relaxed(sfp->base + padcfg_base + 4 * pin);532 seq_printf(s, " (0x%02x)", value);533}534#else535#define jh7110_pinconf_dbg_show NULL536#endif537 538static const struct pinconf_ops jh7110_pinconf_ops = {539 .pin_config_get = jh7110_pinconf_get,540 .pin_config_group_get = jh7110_pinconf_group_get,541 .pin_config_group_set = jh7110_pinconf_group_set,542 .pin_config_dbg_show = jh7110_pinconf_dbg_show,543 .is_generic = true,544};545 546static int jh7110_gpio_get_direction(struct gpio_chip *gc,547 unsigned int gpio)548{549 struct jh7110_pinctrl *sfp = container_of(gc,550 struct jh7110_pinctrl, gc);551 const struct jh7110_pinctrl_soc_info *info = sfp->info;552 unsigned int offset = 4 * (gpio / 4);553 unsigned int shift = 8 * (gpio % 4);554 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);555 556 doen = (doen >> shift) & info->doen_mask;557 558 return doen == GPOEN_ENABLE ?559 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;560}561 562static int jh7110_gpio_direction_input(struct gpio_chip *gc,563 unsigned int gpio)564{565 struct jh7110_pinctrl *sfp = container_of(gc,566 struct jh7110_pinctrl, gc);567 const struct jh7110_pinctrl_soc_info *info = sfp->info;568 569 /* enable input and schmitt trigger */570 jh7110_padcfg_rmw(sfp, gpio,571 JH7110_PADCFG_IE | JH7110_PADCFG_SMT,572 JH7110_PADCFG_IE | JH7110_PADCFG_SMT);573 574 if (info->jh7110_set_one_pin_mux)575 info->jh7110_set_one_pin_mux(sfp, gpio,576 GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0);577 578 return 0;579}580 581static int jh7110_gpio_direction_output(struct gpio_chip *gc,582 unsigned int gpio, int value)583{584 struct jh7110_pinctrl *sfp = container_of(gc,585 struct jh7110_pinctrl, gc);586 const struct jh7110_pinctrl_soc_info *info = sfp->info;587 588 if (info->jh7110_set_one_pin_mux)589 info->jh7110_set_one_pin_mux(sfp, gpio,590 GPI_NONE, value ? GPOUT_HIGH : GPOUT_LOW,591 GPOEN_ENABLE, 0);592 593 /* disable input, schmitt trigger and bias */594 jh7110_padcfg_rmw(sfp, gpio,595 JH7110_PADCFG_IE | JH7110_PADCFG_SMT |596 JH7110_PADCFG_BIAS, 0);597 return 0;598}599 600static int jh7110_gpio_get(struct gpio_chip *gc, unsigned int gpio)601{602 struct jh7110_pinctrl *sfp = container_of(gc,603 struct jh7110_pinctrl, gc);604 const struct jh7110_pinctrl_soc_info *info = sfp->info;605 void __iomem *reg = sfp->base + info->gpioin_reg_base606 + 4 * (gpio / 32);607 608 return !!(readl_relaxed(reg) & BIT(gpio % 32));609}610 611static void jh7110_gpio_set(struct gpio_chip *gc,612 unsigned int gpio, int value)613{614 struct jh7110_pinctrl *sfp = container_of(gc,615 struct jh7110_pinctrl, gc);616 const struct jh7110_pinctrl_soc_info *info = sfp->info;617 unsigned int offset = 4 * (gpio / 4);618 unsigned int shift = 8 * (gpio % 4);619 void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset;620 u32 dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift;621 u32 mask = info->dout_mask << shift;622 unsigned long flags;623 624 raw_spin_lock_irqsave(&sfp->lock, flags);625 dout |= readl_relaxed(reg_dout) & ~mask;626 writel_relaxed(dout, reg_dout);627 raw_spin_unlock_irqrestore(&sfp->lock, flags);628}629 630static int jh7110_gpio_set_config(struct gpio_chip *gc,631 unsigned int gpio, unsigned long config)632{633 struct jh7110_pinctrl *sfp = container_of(gc,634 struct jh7110_pinctrl, gc);635 u32 arg = pinconf_to_config_argument(config);636 u32 value;637 u32 mask;638 639 switch (pinconf_to_config_param(config)) {640 case PIN_CONFIG_BIAS_DISABLE:641 mask = JH7110_PADCFG_BIAS;642 value = 0;643 break;644 case PIN_CONFIG_BIAS_PULL_DOWN:645 if (arg == 0)646 return -ENOTSUPP;647 mask = JH7110_PADCFG_BIAS;648 value = JH7110_PADCFG_PD;649 break;650 case PIN_CONFIG_BIAS_PULL_UP:651 if (arg == 0)652 return -ENOTSUPP;653 mask = JH7110_PADCFG_BIAS;654 value = JH7110_PADCFG_PU;655 break;656 case PIN_CONFIG_DRIVE_PUSH_PULL:657 return 0;658 case PIN_CONFIG_INPUT_ENABLE:659 mask = JH7110_PADCFG_IE;660 value = arg ? JH7110_PADCFG_IE : 0;661 break;662 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:663 mask = JH7110_PADCFG_SMT;664 value = arg ? JH7110_PADCFG_SMT : 0;665 break;666 default:667 return -ENOTSUPP;668 }669 670 jh7110_padcfg_rmw(sfp, gpio, mask, value);671 return 0;672}673 674static int jh7110_gpio_add_pin_ranges(struct gpio_chip *gc)675{676 struct jh7110_pinctrl *sfp = container_of(gc,677 struct jh7110_pinctrl, gc);678 679 sfp->gpios.name = sfp->gc.label;680 sfp->gpios.base = sfp->gc.base;681 sfp->gpios.pin_base = 0;682 sfp->gpios.npins = sfp->gc.ngpio;683 sfp->gpios.gc = &sfp->gc;684 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);685 return 0;686}687 688static void jh7110_irq_ack(struct irq_data *d)689{690 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);691 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;692 irq_hw_number_t gpio = irqd_to_hwirq(d);693 void __iomem *ic = sfp->base + irq_reg->ic_reg_base694 + 4 * (gpio / 32);695 u32 mask = BIT(gpio % 32);696 unsigned long flags;697 u32 value;698 699 raw_spin_lock_irqsave(&sfp->lock, flags);700 value = readl_relaxed(ic) & ~mask;701 writel_relaxed(value, ic);702 writel_relaxed(value | mask, ic);703 raw_spin_unlock_irqrestore(&sfp->lock, flags);704}705 706static void jh7110_irq_mask(struct irq_data *d)707{708 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);709 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;710 irq_hw_number_t gpio = irqd_to_hwirq(d);711 void __iomem *ie = sfp->base + irq_reg->ie_reg_base712 + 4 * (gpio / 32);713 u32 mask = BIT(gpio % 32);714 unsigned long flags;715 u32 value;716 717 raw_spin_lock_irqsave(&sfp->lock, flags);718 value = readl_relaxed(ie) & ~mask;719 writel_relaxed(value, ie);720 raw_spin_unlock_irqrestore(&sfp->lock, flags);721 722 gpiochip_disable_irq(&sfp->gc, d->hwirq);723}724 725static void jh7110_irq_mask_ack(struct irq_data *d)726{727 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);728 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;729 irq_hw_number_t gpio = irqd_to_hwirq(d);730 void __iomem *ie = sfp->base + irq_reg->ie_reg_base731 + 4 * (gpio / 32);732 void __iomem *ic = sfp->base + irq_reg->ic_reg_base733 + 4 * (gpio / 32);734 u32 mask = BIT(gpio % 32);735 unsigned long flags;736 u32 value;737 738 raw_spin_lock_irqsave(&sfp->lock, flags);739 value = readl_relaxed(ie) & ~mask;740 writel_relaxed(value, ie);741 742 value = readl_relaxed(ic) & ~mask;743 writel_relaxed(value, ic);744 writel_relaxed(value | mask, ic);745 raw_spin_unlock_irqrestore(&sfp->lock, flags);746}747 748static void jh7110_irq_unmask(struct irq_data *d)749{750 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);751 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;752 irq_hw_number_t gpio = irqd_to_hwirq(d);753 void __iomem *ie = sfp->base + irq_reg->ie_reg_base754 + 4 * (gpio / 32);755 u32 mask = BIT(gpio % 32);756 unsigned long flags;757 u32 value;758 759 gpiochip_enable_irq(&sfp->gc, d->hwirq);760 761 raw_spin_lock_irqsave(&sfp->lock, flags);762 value = readl_relaxed(ie) | mask;763 writel_relaxed(value, ie);764 raw_spin_unlock_irqrestore(&sfp->lock, flags);765}766 767static int jh7110_irq_set_type(struct irq_data *d, unsigned int trigger)768{769 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);770 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;771 irq_hw_number_t gpio = irqd_to_hwirq(d);772 void __iomem *base = sfp->base + 4 * (gpio / 32);773 u32 mask = BIT(gpio % 32);774 u32 irq_type, edge_both, polarity;775 unsigned long flags;776 777 switch (trigger) {778 case IRQ_TYPE_EDGE_RISING:779 irq_type = mask; /* 1: edge triggered */780 edge_both = 0; /* 0: single edge */781 polarity = mask; /* 1: rising edge */782 break;783 case IRQ_TYPE_EDGE_FALLING:784 irq_type = mask; /* 1: edge triggered */785 edge_both = 0; /* 0: single edge */786 polarity = 0; /* 0: falling edge */787 break;788 case IRQ_TYPE_EDGE_BOTH:789 irq_type = mask; /* 1: edge triggered */790 edge_both = mask; /* 1: both edges */791 polarity = 0; /* 0: ignored */792 break;793 case IRQ_TYPE_LEVEL_HIGH:794 irq_type = 0; /* 0: level triggered */795 edge_both = 0; /* 0: ignored */796 polarity = 0; /* 0: high level */797 break;798 case IRQ_TYPE_LEVEL_LOW:799 irq_type = 0; /* 0: level triggered */800 edge_both = 0; /* 0: ignored */801 polarity = mask; /* 1: low level */802 break;803 default:804 return -EINVAL;805 }806 807 if (trigger & IRQ_TYPE_EDGE_BOTH)808 irq_set_handler_locked(d, handle_edge_irq);809 else810 irq_set_handler_locked(d, handle_level_irq);811 812 raw_spin_lock_irqsave(&sfp->lock, flags);813 irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask;814 writel_relaxed(irq_type, base + irq_reg->is_reg_base);815 816 edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask;817 writel_relaxed(edge_both, base + irq_reg->ibe_reg_base);818 819 polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask;820 writel_relaxed(polarity, base + irq_reg->iev_reg_base);821 raw_spin_unlock_irqrestore(&sfp->lock, flags);822 return 0;823}824 825static struct irq_chip jh7110_irq_chip = {826 .irq_ack = jh7110_irq_ack,827 .irq_mask = jh7110_irq_mask,828 .irq_mask_ack = jh7110_irq_mask_ack,829 .irq_unmask = jh7110_irq_unmask,830 .irq_set_type = jh7110_irq_set_type,831 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,832 GPIOCHIP_IRQ_RESOURCE_HELPERS,833};834 835static void jh7110_disable_clock(void *data)836{837 clk_disable_unprepare(data);838}839 840int jh7110_pinctrl_probe(struct platform_device *pdev)841{842 struct device *dev = &pdev->dev;843 const struct jh7110_pinctrl_soc_info *info;844 struct jh7110_pinctrl *sfp;845 struct pinctrl_desc *jh7110_pinctrl_desc;846 struct reset_control *rst;847 struct clk *clk;848 int ret;849 850 info = of_device_get_match_data(&pdev->dev);851 if (!info)852 return -ENODEV;853 854 if (!info->pins || !info->npins) {855 dev_err(dev, "wrong pinctrl info\n");856 return -EINVAL;857 }858 859 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);860 if (!sfp)861 return -ENOMEM;862 863#if IS_ENABLED(CONFIG_PM_SLEEP)864 sfp->saved_regs = devm_kcalloc(dev, info->nsaved_regs,865 sizeof(*sfp->saved_regs), GFP_KERNEL);866 if (!sfp->saved_regs)867 return -ENOMEM;868#endif869 870 sfp->base = devm_platform_ioremap_resource(pdev, 0);871 if (IS_ERR(sfp->base))872 return PTR_ERR(sfp->base);873 874 clk = devm_clk_get_optional(dev, NULL);875 if (IS_ERR(clk))876 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");877 878 rst = devm_reset_control_get_exclusive(dev, NULL);879 if (IS_ERR(rst))880 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");881 882 /*883 * we don't want to assert reset and risk undoing pin muxing for the884 * early boot serial console, but let's make sure the reset line is885 * deasserted in case someone runs a really minimal bootloader.886 */887 ret = reset_control_deassert(rst);888 if (ret)889 return dev_err_probe(dev, ret, "could not deassert reset\n");890 891 if (clk) {892 ret = clk_prepare_enable(clk);893 if (ret)894 return dev_err_probe(dev, ret, "could not enable clock\n");895 896 ret = devm_add_action_or_reset(dev, jh7110_disable_clock, clk);897 if (ret)898 return ret;899 }900 901 jh7110_pinctrl_desc = devm_kzalloc(&pdev->dev,902 sizeof(*jh7110_pinctrl_desc),903 GFP_KERNEL);904 if (!jh7110_pinctrl_desc)905 return -ENOMEM;906 907 jh7110_pinctrl_desc->name = dev_name(dev);908 jh7110_pinctrl_desc->pins = info->pins;909 jh7110_pinctrl_desc->npins = info->npins;910 jh7110_pinctrl_desc->pctlops = &jh7110_pinctrl_ops;911 jh7110_pinctrl_desc->pmxops = &jh7110_pinmux_ops;912 jh7110_pinctrl_desc->confops = &jh7110_pinconf_ops;913 jh7110_pinctrl_desc->owner = THIS_MODULE;914 915 sfp->info = info;916 sfp->dev = dev;917 platform_set_drvdata(pdev, sfp);918 sfp->gc.parent = dev;919 raw_spin_lock_init(&sfp->lock);920 mutex_init(&sfp->mutex);921 922 ret = devm_pinctrl_register_and_init(dev,923 jh7110_pinctrl_desc,924 sfp, &sfp->pctl);925 if (ret)926 return dev_err_probe(dev, ret,927 "could not register pinctrl driver\n");928 929 sfp->gc.label = dev_name(dev);930 sfp->gc.owner = THIS_MODULE;931 sfp->gc.request = pinctrl_gpio_request;932 sfp->gc.free = pinctrl_gpio_free;933 sfp->gc.get_direction = jh7110_gpio_get_direction;934 sfp->gc.direction_input = jh7110_gpio_direction_input;935 sfp->gc.direction_output = jh7110_gpio_direction_output;936 sfp->gc.get = jh7110_gpio_get;937 sfp->gc.set = jh7110_gpio_set;938 sfp->gc.set_config = jh7110_gpio_set_config;939 sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges;940 sfp->gc.base = info->gc_base;941 sfp->gc.ngpio = info->ngpios;942 943 jh7110_irq_chip.name = sfp->gc.label;944 gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip);945 sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler;946 sfp->gc.irq.num_parents = 1;947 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,948 sizeof(*sfp->gc.irq.parents),949 GFP_KERNEL);950 if (!sfp->gc.irq.parents)951 return -ENOMEM;952 sfp->gc.irq.default_type = IRQ_TYPE_NONE;953 sfp->gc.irq.handler = handle_bad_irq;954 sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw;955 956 ret = platform_get_irq(pdev, 0);957 if (ret < 0)958 return ret;959 sfp->gc.irq.parents[0] = ret;960 961 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);962 if (ret)963 return dev_err_probe(dev, ret, "could not register gpiochip\n");964 965 dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio);966 967 return pinctrl_enable(sfp->pctl);968}969EXPORT_SYMBOL_GPL(jh7110_pinctrl_probe);970 971static int jh7110_pinctrl_suspend(struct device *dev)972{973 struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);974 unsigned long flags;975 unsigned int i;976 977 raw_spin_lock_irqsave(&sfp->lock, flags);978 for (i = 0 ; i < sfp->info->nsaved_regs ; i++)979 sfp->saved_regs[i] = readl_relaxed(sfp->base + 4 * i);980 981 raw_spin_unlock_irqrestore(&sfp->lock, flags);982 return 0;983}984 985static int jh7110_pinctrl_resume(struct device *dev)986{987 struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);988 unsigned long flags;989 unsigned int i;990 991 raw_spin_lock_irqsave(&sfp->lock, flags);992 for (i = 0 ; i < sfp->info->nsaved_regs ; i++)993 writel_relaxed(sfp->saved_regs[i], sfp->base + 4 * i);994 995 raw_spin_unlock_irqrestore(&sfp->lock, flags);996 return 0;997}998 999const struct dev_pm_ops jh7110_pinctrl_pm_ops = {1000 LATE_SYSTEM_SLEEP_PM_OPS(jh7110_pinctrl_suspend, jh7110_pinctrl_resume)1001};1002EXPORT_SYMBOL_GPL(jh7110_pinctrl_pm_ops);1003 1004MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC");1005MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");1006MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");1007MODULE_LICENSE("GPL");1008