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1/*2 * Allwinner A23 SoCs special pins pinctrl driver.3 *4 * Copyright (C) 2014 Chen-Yu Tsai5 * Chen-Yu Tsai <wens@csie.org>6 *7 * Copyright (C) 2014 Boris Brezillon8 * Boris Brezillon <boris.brezillon@free-electrons.com>9 *10 * Copyright (C) 2014 Maxime Ripard11 * Maxime Ripard <maxime.ripard@free-electrons.com>12 *13 * This file is licensed under the terms of the GNU General Public14 * License version 2. This program is licensed "as is" without any15 * warranty of any kind, whether express or implied.16 */17 18#include <linux/init.h>19#include <linux/platform_device.h>20#include <linux/of.h>21#include <linux/pinctrl/pinctrl.h>22 23#include "pinctrl-sunxi.h"24 25static const struct sunxi_desc_pin sun8i_a23_r_pins[] = {26 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),27 SUNXI_FUNCTION(0x0, "gpio_in"),28 SUNXI_FUNCTION(0x1, "gpio_out"),29 SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */30 SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */31 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PL_EINT0 */32 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),33 SUNXI_FUNCTION(0x0, "gpio_in"),34 SUNXI_FUNCTION(0x1, "gpio_out"),35 SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */36 SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */37 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PL_EINT1 */38 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),39 SUNXI_FUNCTION(0x0, "gpio_in"),40 SUNXI_FUNCTION(0x1, "gpio_out"),41 SUNXI_FUNCTION(0x2, "s_uart"), /* TX */42 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PL_EINT2 */43 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),44 SUNXI_FUNCTION(0x0, "gpio_in"),45 SUNXI_FUNCTION(0x1, "gpio_out"),46 SUNXI_FUNCTION(0x2, "s_uart"), /* RX */47 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PL_EINT3 */48 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),49 SUNXI_FUNCTION(0x0, "gpio_in"),50 SUNXI_FUNCTION(0x1, "gpio_out"),51 SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */52 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PL_EINT4 */53 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),54 SUNXI_FUNCTION(0x0, "gpio_in"),55 SUNXI_FUNCTION(0x1, "gpio_out"),56 SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */57 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PL_EINT5 */58 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),59 SUNXI_FUNCTION(0x0, "gpio_in"),60 SUNXI_FUNCTION(0x1, "gpio_out"),61 SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */62 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PL_EINT6 */63 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),64 SUNXI_FUNCTION(0x0, "gpio_in"),65 SUNXI_FUNCTION(0x1, "gpio_out"),66 SUNXI_FUNCTION(0x3, "s_jtag"), /* DI */67 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PL_EINT7 */68 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),69 SUNXI_FUNCTION(0x0, "gpio_in"),70 SUNXI_FUNCTION(0x1, "gpio_out"),71 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */72 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 8)), /* PL_EINT8 */73 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),74 SUNXI_FUNCTION(0x0, "gpio_in"),75 SUNXI_FUNCTION(0x1, "gpio_out"),76 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */77 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 9)), /* PL_EINT9 */78 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),79 SUNXI_FUNCTION(0x0, "gpio_in"),80 SUNXI_FUNCTION(0x1, "gpio_out"),81 SUNXI_FUNCTION(0x2, "s_pwm"),82 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 10)), /* PL_EINT10 */83 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),84 SUNXI_FUNCTION(0x0, "gpio_in"),85 SUNXI_FUNCTION(0x1, "gpio_out"),86 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 11)), /* PL_EINT11 */87};88 89static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = {90 .pins = sun8i_a23_r_pins,91 .npins = ARRAY_SIZE(sun8i_a23_r_pins),92 .pin_base = PL_BASE,93 .irq_banks = 1,94 .disable_strict_mode = true,95};96 97static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)98{99 return sunxi_pinctrl_init(pdev, &sun8i_a23_r_pinctrl_data);100}101 102static const struct of_device_id sun8i_a23_r_pinctrl_match[] = {103 { .compatible = "allwinner,sun8i-a23-r-pinctrl", },104 {}105};106 107static struct platform_driver sun8i_a23_r_pinctrl_driver = {108 .probe = sun8i_a23_r_pinctrl_probe,109 .driver = {110 .name = "sun8i-a23-r-pinctrl",111 .of_match_table = sun8i_a23_r_pinctrl_match,112 },113};114builtin_platform_driver(sun8i_a23_r_pinctrl_driver);115