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1/*2 * Allwinner A1X SoCs pinctrl driver.3 *4 * Copyright (C) 2012 Maxime Ripard5 *6 * Maxime Ripard <maxime.ripard@free-electrons.com>7 *8 * This file is licensed under the terms of the GNU General Public9 * License version 2. This program is licensed "as is" without any10 * warranty of any kind, whether express or implied.11 */12 13#ifndef __PINCTRL_SUNXI_H14#define __PINCTRL_SUNXI_H15 16#include <linux/kernel.h>17#include <linux/spinlock.h>18 19#define PA_BASE 020#define PB_BASE 3221#define PC_BASE 6422#define PD_BASE 9623#define PE_BASE 12824#define PF_BASE 16025#define PG_BASE 19226#define PH_BASE 22427#define PI_BASE 25628#define PL_BASE 35229#define PM_BASE 38430#define PN_BASE 41631 32#define SUNXI_PINCTRL_PIN(bank, pin) \33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)34 35#define SUNXI_PIN_NAME_MAX_LEN 536 37#define BANK_MEM_SIZE 0x2438#define MUX_REGS_OFFSET 0x039#define MUX_FIELD_WIDTH 440#define DATA_REGS_OFFSET 0x1041#define DATA_FIELD_WIDTH 142#define DLEVEL_REGS_OFFSET 0x1443#define DLEVEL_FIELD_WIDTH 244#define PULL_REGS_OFFSET 0x1c45#define PULL_FIELD_WIDTH 246 47#define D1_BANK_MEM_SIZE 0x3048#define D1_DLEVEL_FIELD_WIDTH 449#define D1_PULL_REGS_OFFSET 0x2450 51#define PINS_PER_BANK 3252 53#define IRQ_PER_BANK 3254 55#define IRQ_CFG_REG 0x20056#define IRQ_CFG_IRQ_PER_REG 857#define IRQ_CFG_IRQ_BITS 458#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)59#define IRQ_CTRL_REG 0x21060#define IRQ_CTRL_IRQ_PER_REG 3261#define IRQ_CTRL_IRQ_BITS 162#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)63#define IRQ_STATUS_REG 0x21464#define IRQ_STATUS_IRQ_PER_REG 3265#define IRQ_STATUS_IRQ_BITS 166#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)67 68#define IRQ_DEBOUNCE_REG 0x21869 70#define IRQ_MEM_SIZE 0x2071 72#define IRQ_EDGE_RISING 0x0073#define IRQ_EDGE_FALLING 0x0174#define IRQ_LEVEL_HIGH 0x0275#define IRQ_LEVEL_LOW 0x0376#define IRQ_EDGE_BOTH 0x0477 78#define GRP_CFG_REG 0x30079 80#define IO_BIAS_MASK GENMASK(3, 0)81 82#define SUN4I_FUNC_INPUT 083#define SUN4I_FUNC_IRQ 684 85#define PINCTRL_SUN5I_A10S BIT(1)86#define PINCTRL_SUN5I_A13 BIT(2)87#define PINCTRL_SUN5I_GR8 BIT(3)88#define PINCTRL_SUN6I_A31 BIT(4)89#define PINCTRL_SUN6I_A31S BIT(5)90#define PINCTRL_SUN4I_A10 BIT(6)91#define PINCTRL_SUN7I_A20 BIT(7)92#define PINCTRL_SUN8I_R40 BIT(8)93#define PINCTRL_SUN8I_V3 BIT(9)94#define PINCTRL_SUN8I_V3S BIT(10)95/* Variants below here have an updated register layout. */96#define PINCTRL_SUN20I_D1 BIT(11)97 98#define PIO_POW_MOD_SEL_REG 0x34099#define PIO_POW_MOD_CTL_REG 0x344100 101enum sunxi_desc_bias_voltage {102 BIAS_VOLTAGE_NONE,103 /*104 * Bias voltage configuration is done through105 * Pn_GRP_CONFIG registers, as seen on A80 SoC.106 */107 BIAS_VOLTAGE_GRP_CONFIG,108 /*109 * Bias voltage is set through PIO_POW_MOD_SEL_REG110 * register, as seen on H6 SoC, for example.111 */112 BIAS_VOLTAGE_PIO_POW_MODE_SEL,113 /*114 * Bias voltage is set through PIO_POW_MOD_SEL_REG115 * and PIO_POW_MOD_CTL_REG register, as seen on116 * A100 and D1 SoC, for example.117 */118 BIAS_VOLTAGE_PIO_POW_MODE_CTL,119};120 121struct sunxi_desc_function {122 unsigned long variant;123 const char *name;124 u8 muxval;125 u8 irqbank;126 u8 irqnum;127};128 129struct sunxi_desc_pin {130 struct pinctrl_pin_desc pin;131 unsigned long variant;132 struct sunxi_desc_function *functions;133};134 135struct sunxi_pinctrl_desc {136 const struct sunxi_desc_pin *pins;137 int npins;138 unsigned pin_base;139 unsigned irq_banks;140 const unsigned int *irq_bank_map;141 bool irq_read_needs_mux;142 bool disable_strict_mode;143 enum sunxi_desc_bias_voltage io_bias_cfg_variant;144};145 146struct sunxi_pinctrl_function {147 const char *name;148 const char **groups;149 unsigned ngroups;150};151 152struct sunxi_pinctrl_group {153 const char *name;154 unsigned pin;155};156 157struct sunxi_pinctrl_regulator {158 struct regulator *regulator;159 refcount_t refcount;160};161 162struct sunxi_pinctrl {163 void __iomem *membase;164 struct gpio_chip *chip;165 const struct sunxi_pinctrl_desc *desc;166 struct device *dev;167 struct sunxi_pinctrl_regulator regulators[9];168 struct irq_domain *domain;169 struct sunxi_pinctrl_function *functions;170 unsigned nfunctions;171 struct sunxi_pinctrl_group *groups;172 unsigned ngroups;173 int *irq;174 unsigned *irq_array;175 raw_spinlock_t lock;176 struct pinctrl_dev *pctl_dev;177 unsigned long variant;178 u32 bank_mem_size;179 u32 pull_regs_offset;180 u32 dlevel_field_width;181};182 183#define SUNXI_PIN(_pin, ...) \184 { \185 .pin = _pin, \186 .functions = (struct sunxi_desc_function[]){ \187 __VA_ARGS__, { } }, \188 }189 190#define SUNXI_PIN_VARIANT(_pin, _variant, ...) \191 { \192 .pin = _pin, \193 .variant = _variant, \194 .functions = (struct sunxi_desc_function[]){ \195 __VA_ARGS__, { } }, \196 }197 198#define SUNXI_FUNCTION(_val, _name) \199 { \200 .name = _name, \201 .muxval = _val, \202 }203 204#define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \205 { \206 .name = _name, \207 .muxval = _val, \208 .variant = _variant, \209 }210 211#define SUNXI_FUNCTION_IRQ(_val, _irq) \212 { \213 .name = "irq", \214 .muxval = _val, \215 .irqnum = _irq, \216 }217 218#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \219 { \220 .name = "irq", \221 .muxval = _val, \222 .irqbank = _bank, \223 .irqnum = _irq, \224 }225 226static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)227{228 if (!desc->irq_bank_map)229 return bank;230 else231 return desc->irq_bank_map[bank];232}233 234static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,235 u16 irq)236{237 u8 bank = irq / IRQ_PER_BANK;238 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;239 240 return IRQ_CFG_REG +241 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;242}243 244static inline u32 sunxi_irq_cfg_offset(u16 irq)245{246 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;247 return irq_num * IRQ_CFG_IRQ_BITS;248}249 250static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)251{252 return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;253}254 255static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,256 u16 irq)257{258 u8 bank = irq / IRQ_PER_BANK;259 260 return sunxi_irq_ctrl_reg_from_bank(desc, bank);261}262 263static inline u32 sunxi_irq_ctrl_offset(u16 irq)264{265 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;266 return irq_num * IRQ_CTRL_IRQ_BITS;267}268 269static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)270{271 return IRQ_DEBOUNCE_REG +272 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;273}274 275static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)276{277 return IRQ_STATUS_REG +278 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;279}280 281static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,282 u16 irq)283{284 u8 bank = irq / IRQ_PER_BANK;285 286 return sunxi_irq_status_reg_from_bank(desc, bank);287}288 289static inline u32 sunxi_irq_status_offset(u16 irq)290{291 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;292 return irq_num * IRQ_STATUS_IRQ_BITS;293}294 295static inline u32 sunxi_grp_config_reg(u16 pin)296{297 u8 bank = pin / PINS_PER_BANK;298 299 return GRP_CFG_REG + bank * 0x4;300}301 302int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,303 const struct sunxi_pinctrl_desc *desc,304 unsigned long variant);305 306#define sunxi_pinctrl_init(_dev, _desc) \307 sunxi_pinctrl_init_with_variant(_dev, _desc, 0)308 309#endif /* __PINCTRL_SUNXI_H */310