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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Pinctrl data for the NVIDIA Tegra194 pinmux4 *5 * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.6 *7 * This program is free software; you can redistribute it and/or modify it8 * under the terms and conditions of the GNU General Public License,9 * version 2, as published by the Free Software Foundation.10 *11 * This program is distributed in the hope it will be useful, but WITHOUT12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for14 * more details.15 */16 17#include <linux/init.h>18#include <linux/of.h>19#include <linux/platform_device.h>20#include <linux/pinctrl/pinctrl.h>21#include <linux/pinctrl/pinmux.h>22 23#include "pinctrl-tegra.h"24 25/* Define unique ID for each pins */26enum {27	TEGRA_PIN_DAP6_SCLK_PA0,28	TEGRA_PIN_DAP6_DOUT_PA1,29	TEGRA_PIN_DAP6_DIN_PA2,30	TEGRA_PIN_DAP6_FS_PA3,31	TEGRA_PIN_DAP4_SCLK_PA4,32	TEGRA_PIN_DAP4_DOUT_PA5,33	TEGRA_PIN_DAP4_DIN_PA6,34	TEGRA_PIN_DAP4_FS_PA7,35	TEGRA_PIN_CPU_PWR_REQ_0_PB0,36	TEGRA_PIN_CPU_PWR_REQ_1_PB1,37	TEGRA_PIN_QSPI0_SCK_PC0,38	TEGRA_PIN_QSPI0_CS_N_PC1,39	TEGRA_PIN_QSPI0_IO0_PC2,40	TEGRA_PIN_QSPI0_IO1_PC3,41	TEGRA_PIN_QSPI0_IO2_PC4,42	TEGRA_PIN_QSPI0_IO3_PC5,43	TEGRA_PIN_QSPI1_SCK_PC6,44	TEGRA_PIN_QSPI1_CS_N_PC7,45	TEGRA_PIN_QSPI1_IO0_PD0,46	TEGRA_PIN_QSPI1_IO1_PD1,47	TEGRA_PIN_QSPI1_IO2_PD2,48	TEGRA_PIN_QSPI1_IO3_PD3,49	TEGRA_PIN_EQOS_TXC_PE0,50	TEGRA_PIN_EQOS_TD0_PE1,51	TEGRA_PIN_EQOS_TD1_PE2,52	TEGRA_PIN_EQOS_TD2_PE3,53	TEGRA_PIN_EQOS_TD3_PE4,54	TEGRA_PIN_EQOS_TX_CTL_PE5,55	TEGRA_PIN_EQOS_RD0_PE6,56	TEGRA_PIN_EQOS_RD1_PE7,57	TEGRA_PIN_EQOS_RD2_PF0,58	TEGRA_PIN_EQOS_RD3_PF1,59	TEGRA_PIN_EQOS_RX_CTL_PF2,60	TEGRA_PIN_EQOS_RXC_PF3,61	TEGRA_PIN_EQOS_SMA_MDIO_PF4,62	TEGRA_PIN_EQOS_SMA_MDC_PF5,63	TEGRA_PIN_SOC_GPIO00_PG0,64	TEGRA_PIN_SOC_GPIO01_PG1,65	TEGRA_PIN_SOC_GPIO02_PG2,66	TEGRA_PIN_SOC_GPIO03_PG3,67	TEGRA_PIN_SOC_GPIO08_PG4,68	TEGRA_PIN_SOC_GPIO09_PG5,69	TEGRA_PIN_SOC_GPIO10_PG6,70	TEGRA_PIN_SOC_GPIO11_PG7,71	TEGRA_PIN_SOC_GPIO12_PH0,72	TEGRA_PIN_SOC_GPIO13_PH1,73	TEGRA_PIN_SOC_GPIO14_PH2,74	TEGRA_PIN_UART4_TX_PH3,75	TEGRA_PIN_UART4_RX_PH4,76	TEGRA_PIN_UART4_RTS_PH5,77	TEGRA_PIN_UART4_CTS_PH6,78	TEGRA_PIN_DAP2_SCLK_PH7,79	TEGRA_PIN_DAP2_DOUT_PI0,80	TEGRA_PIN_DAP2_DIN_PI1,81	TEGRA_PIN_DAP2_FS_PI2,82	TEGRA_PIN_GEN1_I2C_SCL_PI3,83	TEGRA_PIN_GEN1_I2C_SDA_PI4,84	TEGRA_PIN_SDMMC1_CLK_PJ0,85	TEGRA_PIN_SDMMC1_CMD_PJ1,86	TEGRA_PIN_SDMMC1_DAT0_PJ2,87	TEGRA_PIN_SDMMC1_DAT1_PJ3,88	TEGRA_PIN_SDMMC1_DAT2_PJ4,89	TEGRA_PIN_SDMMC1_DAT3_PJ5,90	TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,91	TEGRA_PIN_PEX_L0_RST_N_PK1,92	TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,93	TEGRA_PIN_PEX_L1_RST_N_PK3,94	TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,95	TEGRA_PIN_PEX_L2_RST_N_PK5,96	TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,97	TEGRA_PIN_PEX_L3_RST_N_PK7,98	TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,99	TEGRA_PIN_PEX_L4_RST_N_PL1,100	TEGRA_PIN_PEX_WAKE_N_PL2,101	TEGRA_PIN_SATA_DEV_SLP_PL3,102	TEGRA_PIN_DP_AUX_CH0_HPD_PM0,103	TEGRA_PIN_DP_AUX_CH1_HPD_PM1,104	TEGRA_PIN_DP_AUX_CH2_HPD_PM2,105	TEGRA_PIN_DP_AUX_CH3_HPD_PM3,106	TEGRA_PIN_HDMI_CEC_PM4,107	TEGRA_PIN_SOC_GPIO50_PM5,108	TEGRA_PIN_SOC_GPIO51_PM6,109	TEGRA_PIN_SOC_GPIO52_PM7,110	TEGRA_PIN_SOC_GPIO53_PN0,111	TEGRA_PIN_SOC_GPIO54_PN1,112	TEGRA_PIN_SOC_GPIO55_PN2,113	TEGRA_PIN_SDMMC3_CLK_PO0,114	TEGRA_PIN_SDMMC3_CMD_PO1,115	TEGRA_PIN_SDMMC3_DAT0_PO2,116	TEGRA_PIN_SDMMC3_DAT1_PO3,117	TEGRA_PIN_SDMMC3_DAT2_PO4,118	TEGRA_PIN_SDMMC3_DAT3_PO5,119	TEGRA_PIN_EXTPERIPH1_CLK_PP0,120	TEGRA_PIN_EXTPERIPH2_CLK_PP1,121	TEGRA_PIN_CAM_I2C_SCL_PP2,122	TEGRA_PIN_CAM_I2C_SDA_PP3,123	TEGRA_PIN_SOC_GPIO04_PP4,124	TEGRA_PIN_SOC_GPIO05_PP5,125	TEGRA_PIN_SOC_GPIO06_PP6,126	TEGRA_PIN_SOC_GPIO07_PP7,127	TEGRA_PIN_SOC_GPIO20_PQ0,128	TEGRA_PIN_SOC_GPIO21_PQ1,129	TEGRA_PIN_SOC_GPIO22_PQ2,130	TEGRA_PIN_SOC_GPIO23_PQ3,131	TEGRA_PIN_SOC_GPIO40_PQ4,132	TEGRA_PIN_SOC_GPIO41_PQ5,133	TEGRA_PIN_SOC_GPIO42_PQ6,134	TEGRA_PIN_SOC_GPIO43_PQ7,135	TEGRA_PIN_SOC_GPIO44_PR0,136	TEGRA_PIN_SOC_GPIO45_PR1,137	TEGRA_PIN_UART1_TX_PR2,138	TEGRA_PIN_UART1_RX_PR3,139	TEGRA_PIN_UART1_RTS_PR4,140	TEGRA_PIN_UART1_CTS_PR5,141	TEGRA_PIN_DAP1_SCLK_PS0,142	TEGRA_PIN_DAP1_DOUT_PS1,143	TEGRA_PIN_DAP1_DIN_PS2,144	TEGRA_PIN_DAP1_FS_PS3,145	TEGRA_PIN_AUD_MCLK_PS4,146	TEGRA_PIN_SOC_GPIO30_PS5,147	TEGRA_PIN_SOC_GPIO31_PS6,148	TEGRA_PIN_SOC_GPIO32_PS7,149	TEGRA_PIN_SOC_GPIO33_PT0,150	TEGRA_PIN_DAP3_SCLK_PT1,151	TEGRA_PIN_DAP3_DOUT_PT2,152	TEGRA_PIN_DAP3_DIN_PT3,153	TEGRA_PIN_DAP3_FS_PT4,154	TEGRA_PIN_DAP5_SCLK_PT5,155	TEGRA_PIN_DAP5_DOUT_PT6,156	TEGRA_PIN_DAP5_DIN_PT7,157	TEGRA_PIN_DAP5_FS_PU0,158	TEGRA_PIN_DIRECTDC1_CLK_PV0,159	TEGRA_PIN_DIRECTDC1_IN_PV1,160	TEGRA_PIN_DIRECTDC1_OUT0_PV2,161	TEGRA_PIN_DIRECTDC1_OUT1_PV3,162	TEGRA_PIN_DIRECTDC1_OUT2_PV4,163	TEGRA_PIN_DIRECTDC1_OUT3_PV5,164	TEGRA_PIN_DIRECTDC1_OUT4_PV6,165	TEGRA_PIN_DIRECTDC1_OUT5_PV7,166	TEGRA_PIN_DIRECTDC1_OUT6_PW0,167	TEGRA_PIN_DIRECTDC1_OUT7_PW1,168	TEGRA_PIN_GPU_PWR_REQ_PX0,169	TEGRA_PIN_CV_PWR_REQ_PX1,170	TEGRA_PIN_GP_PWM2_PX2,171	TEGRA_PIN_GP_PWM3_PX3,172	TEGRA_PIN_UART2_TX_PX4,173	TEGRA_PIN_UART2_RX_PX5,174	TEGRA_PIN_UART2_RTS_PX6,175	TEGRA_PIN_UART2_CTS_PX7,176	TEGRA_PIN_SPI3_SCK_PY0,177	TEGRA_PIN_SPI3_MISO_PY1,178	TEGRA_PIN_SPI3_MOSI_PY2,179	TEGRA_PIN_SPI3_CS0_PY3,180	TEGRA_PIN_SPI3_CS1_PY4,181	TEGRA_PIN_UART5_TX_PY5,182	TEGRA_PIN_UART5_RX_PY6,183	TEGRA_PIN_UART5_RTS_PY7,184	TEGRA_PIN_UART5_CTS_PZ0,185	TEGRA_PIN_USB_VBUS_EN0_PZ1,186	TEGRA_PIN_USB_VBUS_EN1_PZ2,187	TEGRA_PIN_SPI1_SCK_PZ3,188	TEGRA_PIN_SPI1_MISO_PZ4,189	TEGRA_PIN_SPI1_MOSI_PZ5,190	TEGRA_PIN_SPI1_CS0_PZ6,191	TEGRA_PIN_SPI1_CS1_PZ7,192	TEGRA_PIN_UFS0_REF_CLK_PFF0,193	TEGRA_PIN_UFS0_RST_PFF1,194	TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,195	TEGRA_PIN_PEX_L5_RST_N_PGG1,196	TEGRA_PIN_DIRECTDC_COMP,197	TEGRA_PIN_SDMMC4_CLK,198	TEGRA_PIN_SDMMC4_CMD,199	TEGRA_PIN_SDMMC4_DQS,200	TEGRA_PIN_SDMMC4_DAT7,201	TEGRA_PIN_SDMMC4_DAT6,202	TEGRA_PIN_SDMMC4_DAT5,203	TEGRA_PIN_SDMMC4_DAT4,204	TEGRA_PIN_SDMMC4_DAT3,205	TEGRA_PIN_SDMMC4_DAT2,206	TEGRA_PIN_SDMMC4_DAT1,207	TEGRA_PIN_SDMMC4_DAT0,208	TEGRA_PIN_SDMMC1_COMP,209	TEGRA_PIN_SDMMC1_HV_TRIM,210	TEGRA_PIN_SDMMC3_COMP,211	TEGRA_PIN_SDMMC3_HV_TRIM,212	TEGRA_PIN_EQOS_COMP,213	TEGRA_PIN_QSPI_COMP,214};215 216enum {217	TEGRA_PIN_CAN1_DOUT_PAA0,218	TEGRA_PIN_CAN1_DIN_PAA1,219	TEGRA_PIN_CAN0_DOUT_PAA2,220	TEGRA_PIN_CAN0_DIN_PAA3,221	TEGRA_PIN_CAN0_STB_PAA4,222	TEGRA_PIN_CAN0_EN_PAA5,223	TEGRA_PIN_CAN0_WAKE_PAA6,224	TEGRA_PIN_CAN0_ERR_PAA7,225	TEGRA_PIN_CAN1_STB_PBB0,226	TEGRA_PIN_CAN1_EN_PBB1,227	TEGRA_PIN_CAN1_WAKE_PBB2,228	TEGRA_PIN_CAN1_ERR_PBB3,229	TEGRA_PIN_SPI2_SCK_PCC0,230	TEGRA_PIN_SPI2_MISO_PCC1,231	TEGRA_PIN_SPI2_MOSI_PCC2,232	TEGRA_PIN_SPI2_CS0_PCC3,233	TEGRA_PIN_TOUCH_CLK_PCC4,234	TEGRA_PIN_UART3_TX_PCC5,235	TEGRA_PIN_UART3_RX_PCC6,236	TEGRA_PIN_GEN2_I2C_SCL_PCC7,237	TEGRA_PIN_GEN2_I2C_SDA_PDD0,238	TEGRA_PIN_GEN8_I2C_SCL_PDD1,239	TEGRA_PIN_GEN8_I2C_SDA_PDD2,240	TEGRA_PIN_SAFE_STATE_PEE0,241	TEGRA_PIN_VCOMP_ALERT_PEE1,242	TEGRA_PIN_AO_RETENTION_N_PEE2,243	TEGRA_PIN_BATT_OC_PEE3,244	TEGRA_PIN_POWER_ON_PEE4,245	TEGRA_PIN_PWR_I2C_SCL_PEE5,246	TEGRA_PIN_PWR_I2C_SDA_PEE6,247	TEGRA_PIN_SYS_RESET_N,248	TEGRA_PIN_SHUTDOWN_N,249	TEGRA_PIN_PMU_INT_N,250	TEGRA_PIN_SOC_PWR_REQ,251	TEGRA_PIN_CLK_32K_IN,252};253 254/* Table for pin descriptor */255static const struct pinctrl_pin_desc tegra194_pins[] = {256	PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PA0, "DAP6_SCLK_PA0"),257	PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PA1, "DAP6_DOUT_PA1"),258	PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PA2, "DAP6_DIN_PA2"),259	PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PA3, "DAP6_FS_PA3"),260	PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PA4, "DAP4_SCLK_PA4"),261	PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PA5, "DAP4_DOUT_PA5"),262	PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PA6, "DAP4_DIN_PA6"),263	PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PA7, "DAP4_FS_PA7"),264	PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_0_PB0, "CPU_PWR_REQ_0_PB0"),265	PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_1_PB1, "CPU_PWR_REQ_1_PB1"),266	PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PC0, "QSPI0_SCK_PC0"),267	PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PC1, "QSPI0_CS_N_PC1"),268	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PC2, "QSPI0_IO0_PC2"),269	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PC3, "QSPI0_IO1_PC3"),270	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PC4, "QSPI0_IO2_PC4"),271	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PC5, "QSPI0_IO3_PC5"),272	PINCTRL_PIN(TEGRA_PIN_QSPI1_SCK_PC6, "QSPI1_SCK_PC6"),273	PINCTRL_PIN(TEGRA_PIN_QSPI1_CS_N_PC7, "QSPI1_CS_N_PC7"),274	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO0_PD0, "QSPI1_IO0_PD0"),275	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO1_PD1, "QSPI1_IO1_PD1"),276	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO2_PD2, "QSPI1_IO2_PD2"),277	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO3_PD3, "QSPI1_IO3_PD3"),278	PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"),279	PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"),280	PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"),281	PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"),282	PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"),283	PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"),284	PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"),285	PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"),286	PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"),287	PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"),288	PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"),289	PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"),290	PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDIO_PF4, "EQOS_SMA_MDIO_PF4"),291	PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDC_PF5, "EQOS_SMA_MDC_PF5"),292	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PG0, "SOC_GPIO00_PG0"),293	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO01_PG1, "SOC_GPIO01_PG1"),294	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO02_PG2, "SOC_GPIO02_PG2"),295	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO03_PG3, "SOC_GPIO03_PG3"),296	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PG4, "SOC_GPIO08_PG4"),297	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO09_PG5, "SOC_GPIO09_PG5"),298	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO10_PG6, "SOC_GPIO10_PG6"),299	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO11_PG7, "SOC_GPIO11_PG7"),300	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO12_PH0, "SOC_GPIO12_PH0"),301	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PH1, "SOC_GPIO13_PH1"),302	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PH2, "SOC_GPIO14_PH2"),303	PINCTRL_PIN(TEGRA_PIN_UART4_TX_PH3, "UART4_TX_PH3"),304	PINCTRL_PIN(TEGRA_PIN_UART4_RX_PH4, "UART4_RX_PH4"),305	PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PH5, "UART4_RTS_PH5"),306	PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PH6, "UART4_CTS_PH6"),307	PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PH7, "DAP2_SCLK_PH7"),308	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PI0, "DAP2_DOUT_PI0"),309	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PI1, "DAP2_DIN_PI1"),310	PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PI2, "DAP2_FS_PI2"),311	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PI3, "GEN1_I2C_SCL_PI3"),312	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PI4, "GEN1_I2C_SDA_PI4"),313	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PJ0, "SDMMC1_CLK_PJ0"),314	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PJ1, "SDMMC1_CMD_PJ1"),315	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PJ2, "SDMMC1_DAT0_PJ2"),316	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PJ3, "SDMMC1_DAT1_PJ3"),317	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PJ4, "SDMMC1_DAT2_PJ4"),318	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PJ5, "SDMMC1_DAT3_PJ5"),319	PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PK0, "PEX_L0_CLKREQ_N_PK0"),320	PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PK1, "PEX_L0_RST_N_PK1"),321	PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PK2, "PEX_L1_CLKREQ_N_PK2"),322	PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PK3, "PEX_L1_RST_N_PK3"),323	PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PK4, "PEX_L2_CLKREQ_N_PK4"),324	PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PK5, "PEX_L2_RST_N_PK5"),325	PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PK6, "PEX_L3_CLKREQ_N_PK6"),326	PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PK7, "PEX_L3_RST_N_PK7"),327	PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PL0, "PEX_L4_CLKREQ_N_PL0"),328	PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PL1, "PEX_L4_RST_N_PL1"),329	PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PL2, "PEX_WAKE_N_PL2"),330	PINCTRL_PIN(TEGRA_PIN_SATA_DEV_SLP_PL3, "SATA_DEV_SLP_PL3"),331	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PM0, "DP_AUX_CH0_HPD_PM0"),332	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PM1, "DP_AUX_CH1_HPD_PM1"),333	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PM2, "DP_AUX_CH2_HPD_PM2"),334	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PM3, "DP_AUX_CH3_HPD_PM3"),335	PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PM4, "HDMI_CEC_PM4"),336	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PM5, "SOC_GPIO50_PM5"),337	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO51_PM6, "SOC_GPIO51_PM6"),338	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO52_PM7, "SOC_GPIO52_PM7"),339	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PN0, "SOC_GPIO53_PN0"),340	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO54_PN1, "SOC_GPIO54_PN1"),341	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PN2, "SOC_GPIO55_PN2"),342	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PO0, "SDMMC3_CLK_PO0"),343	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PO1, "SDMMC3_CMD_PO1"),344	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PO2, "SDMMC3_DAT0_PO2"),345	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PO3, "SDMMC3_DAT1_PO3"),346	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PO4, "SDMMC3_DAT2_PO4"),347	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PO5, "SDMMC3_DAT3_PO5"),348	PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PP0, "EXTPERIPH1_CLK_PP0"),349	PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PP1, "EXTPERIPH2_CLK_PP1"),350	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PP2, "CAM_I2C_SCL_PP2"),351	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PP3, "CAM_I2C_SDA_PP3"),352	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO04_PP4, "SOC_GPIO04_PP4"),353	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO05_PP5, "SOC_GPIO05_PP5"),354	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PP6, "SOC_GPIO06_PP6"),355	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PP7, "SOC_GPIO07_PP7"),356	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PQ0, "SOC_GPIO20_PQ0"),357	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PQ1, "SOC_GPIO21_PQ1"),358	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PQ2, "SOC_GPIO22_PQ2"),359	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PQ3, "SOC_GPIO23_PQ3"),360	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PQ4, "SOC_GPIO40_PQ4"),361	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PQ5, "SOC_GPIO41_PQ5"),362	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PQ6, "SOC_GPIO42_PQ6"),363	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PQ7, "SOC_GPIO43_PQ7"),364	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PR0, "SOC_GPIO44_PR0"),365	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PR1, "SOC_GPIO45_PR1"),366	PINCTRL_PIN(TEGRA_PIN_UART1_TX_PR2, "UART1_TX_PR2"),367	PINCTRL_PIN(TEGRA_PIN_UART1_RX_PR3, "UART1_RX_PR3"),368	PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PR4, "UART1_RTS_PR4"),369	PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PR5, "UART1_CTS_PR5"),370	PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PS0, "DAP1_SCLK_PS0"),371	PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PS1, "DAP1_DOUT_PS1"),372	PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PS2, "DAP1_DIN_PS2"),373	PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PS3, "DAP1_FS_PS3"),374	PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PS4, "AUD_MCLK_PS4"),375	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO30_PS5, "SOC_GPIO30_PS5"),376	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO31_PS6, "SOC_GPIO31_PS6"),377	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PS7, "SOC_GPIO32_PS7"),378	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PT0, "SOC_GPIO33_PT0"),379	PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PT1, "DAP3_SCLK_PT1"),380	PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PT2, "DAP3_DOUT_PT2"),381	PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PT3, "DAP3_DIN_PT3"),382	PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PT4, "DAP3_FS_PT4"),383	PINCTRL_PIN(TEGRA_PIN_DAP5_SCLK_PT5, "DAP5_SCLK_PT5"),384	PINCTRL_PIN(TEGRA_PIN_DAP5_DOUT_PT6, "DAP5_DOUT_PT6"),385	PINCTRL_PIN(TEGRA_PIN_DAP5_DIN_PT7, "DAP5_DIN_PT7"),386	PINCTRL_PIN(TEGRA_PIN_DAP5_FS_PU0, "DAP5_FS_PU0"),387	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_CLK_PV0, "DIRECTDC1_CLK_PV0"),388	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_IN_PV1, "DIRECTDC1_IN_PV1"),389	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT0_PV2, "DIRECTDC1_OUT0_PV2"),390	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT1_PV3, "DIRECTDC1_OUT1_PV3"),391	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT2_PV4, "DIRECTDC1_OUT2_PV4"),392	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT3_PV5, "DIRECTDC1_OUT3_PV5"),393	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT4_PV6, "DIRECTDC1_OUT4_PV6"),394	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT5_PV7, "DIRECTDC1_OUT5_PV7"),395	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT6_PW0, "DIRECTDC1_OUT6_PW0"),396	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT7_PW1, "DIRECTDC1_OUT7_PW1"),397	PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PX0, "GPU_PWR_REQ_PX0"),398	PINCTRL_PIN(TEGRA_PIN_CV_PWR_REQ_PX1, "CV_PWR_REQ_PX1"),399	PINCTRL_PIN(TEGRA_PIN_GP_PWM2_PX2, "GP_PWM2_PX2"),400	PINCTRL_PIN(TEGRA_PIN_GP_PWM3_PX3, "GP_PWM3_PX3"),401	PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX4, "UART2_TX_PX4"),402	PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX5, "UART2_RX_PX5"),403	PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX6, "UART2_RTS_PX6"),404	PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX7, "UART2_CTS_PX7"),405	PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PY0, "SPI3_SCK_PY0"),406	PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PY1, "SPI3_MISO_PY1"),407	PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PY2, "SPI3_MOSI_PY2"),408	PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PY3, "SPI3_CS0_PY3"),409	PINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PY4, "SPI3_CS1_PY4"),410	PINCTRL_PIN(TEGRA_PIN_UART5_TX_PY5, "UART5_TX_PY5"),411	PINCTRL_PIN(TEGRA_PIN_UART5_RX_PY6, "UART5_RX_PY6"),412	PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PY7, "UART5_RTS_PY7"),413	PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PZ0, "UART5_CTS_PZ0"),414	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PZ1, "USB_VBUS_EN0_PZ1"),415	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PZ2, "USB_VBUS_EN1_PZ2"),416	PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PZ3, "SPI1_SCK_PZ3"),417	PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PZ4, "SPI1_MISO_PZ4"),418	PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"),419	PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"),420	PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"),421	PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PFF0, "UFS0_REF_CLK_PFF0"),422	PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PFF1, "UFS0_RST_PFF1"),423	PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),424	PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),425	PINCTRL_PIN(TEGRA_PIN_DIRECTDC_COMP, "DIRECTDC_COMP"),426	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK, "SDMMC4_CLK"),427	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD, "SDMMC4_CMD"),428	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DQS, "SDMMC4_DQS"),429	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7, "SDMMC4_DAT7"),430	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6, "SDMMC4_DAT6"),431	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5, "SDMMC4_DAT5"),432	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4, "SDMMC4_DAT4"),433	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3, "SDMMC4_DAT3"),434	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2, "SDMMC4_DAT2"),435	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1, "SDMMC4_DAT1"),436	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0, "SDMMC4_DAT0"),437	PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),438	PINCTRL_PIN(TEGRA_PIN_SDMMC1_HV_TRIM, "SDMMC1_HV_TRIM"),439	PINCTRL_PIN(TEGRA_PIN_SDMMC3_COMP, "SDMMC3_COMP"),440	PINCTRL_PIN(TEGRA_PIN_SDMMC3_HV_TRIM, "SDMMC3_HV_TRIM"),441	PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),442	PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),443};444 445static const unsigned int dap6_sclk_pa0_pins[] = {446	TEGRA_PIN_DAP6_SCLK_PA0,447};448static const unsigned int dap6_dout_pa1_pins[] = {449	TEGRA_PIN_DAP6_DOUT_PA1,450};451static const unsigned int dap6_din_pa2_pins[] = {452	TEGRA_PIN_DAP6_DIN_PA2,453};454static const unsigned int dap6_fs_pa3_pins[] = {455	TEGRA_PIN_DAP6_FS_PA3,456};457static const unsigned int dap4_sclk_pa4_pins[] = {458	TEGRA_PIN_DAP4_SCLK_PA4,459};460static const unsigned int dap4_dout_pa5_pins[] = {461	TEGRA_PIN_DAP4_DOUT_PA5,462};463static const unsigned int dap4_din_pa6_pins[] = {464	TEGRA_PIN_DAP4_DIN_PA6,465};466static const unsigned int dap4_fs_pa7_pins[] = {467	TEGRA_PIN_DAP4_FS_PA7,468};469static const unsigned int cpu_pwr_req_0_pb0_pins[] = {470	TEGRA_PIN_CPU_PWR_REQ_0_PB0,471};472static const unsigned int cpu_pwr_req_1_pb1_pins[] = {473	TEGRA_PIN_CPU_PWR_REQ_1_PB1,474};475static const unsigned int qspi0_sck_pc0_pins[] = {476	TEGRA_PIN_QSPI0_SCK_PC0,477};478static const unsigned int qspi0_cs_n_pc1_pins[] = {479	TEGRA_PIN_QSPI0_CS_N_PC1,480};481static const unsigned int qspi0_io0_pc2_pins[] = {482	TEGRA_PIN_QSPI0_IO0_PC2,483};484static const unsigned int qspi0_io1_pc3_pins[] = {485	TEGRA_PIN_QSPI0_IO1_PC3,486};487static const unsigned int qspi0_io2_pc4_pins[] = {488	TEGRA_PIN_QSPI0_IO2_PC4,489};490static const unsigned int qspi0_io3_pc5_pins[] = {491	TEGRA_PIN_QSPI0_IO3_PC5,492};493static const unsigned int qspi1_sck_pc6_pins[] = {494	TEGRA_PIN_QSPI1_SCK_PC6,495};496static const unsigned int qspi1_cs_n_pc7_pins[] = {497	TEGRA_PIN_QSPI1_CS_N_PC7,498};499static const unsigned int qspi1_io0_pd0_pins[] = {500	TEGRA_PIN_QSPI1_IO0_PD0,501};502static const unsigned int qspi1_io1_pd1_pins[] = {503	TEGRA_PIN_QSPI1_IO1_PD1,504};505static const unsigned int qspi1_io2_pd2_pins[] = {506	TEGRA_PIN_QSPI1_IO2_PD2,507};508static const unsigned int qspi1_io3_pd3_pins[] = {509	TEGRA_PIN_QSPI1_IO3_PD3,510};511static const unsigned int eqos_txc_pe0_pins[] = {512	TEGRA_PIN_EQOS_TXC_PE0,513};514static const unsigned int eqos_td0_pe1_pins[] = {515	TEGRA_PIN_EQOS_TD0_PE1,516};517static const unsigned int eqos_td1_pe2_pins[] = {518	TEGRA_PIN_EQOS_TD1_PE2,519};520static const unsigned int eqos_td2_pe3_pins[] = {521	TEGRA_PIN_EQOS_TD2_PE3,522};523static const unsigned int eqos_td3_pe4_pins[] = {524	TEGRA_PIN_EQOS_TD3_PE4,525};526static const unsigned int eqos_tx_ctl_pe5_pins[] = {527	TEGRA_PIN_EQOS_TX_CTL_PE5,528};529static const unsigned int eqos_rd0_pe6_pins[] = {530	TEGRA_PIN_EQOS_RD0_PE6,531};532static const unsigned int eqos_rd1_pe7_pins[] = {533	TEGRA_PIN_EQOS_RD1_PE7,534};535static const unsigned int eqos_rd2_pf0_pins[] = {536	TEGRA_PIN_EQOS_RD2_PF0,537};538static const unsigned int eqos_rd3_pf1_pins[] = {539	TEGRA_PIN_EQOS_RD3_PF1,540};541static const unsigned int eqos_rx_ctl_pf2_pins[] = {542	TEGRA_PIN_EQOS_RX_CTL_PF2,543};544static const unsigned int eqos_rxc_pf3_pins[] = {545	TEGRA_PIN_EQOS_RXC_PF3,546};547static const unsigned int eqos_sma_mdio_pf4_pins[] = {548	TEGRA_PIN_EQOS_SMA_MDIO_PF4,549};550static const unsigned int eqos_sma_mdc_pf5_pins[] = {551	TEGRA_PIN_EQOS_SMA_MDC_PF5,552};553static const unsigned int soc_gpio00_pg0_pins[] = {554	TEGRA_PIN_SOC_GPIO00_PG0,555};556static const unsigned int soc_gpio01_pg1_pins[] = {557	TEGRA_PIN_SOC_GPIO01_PG1,558};559static const unsigned int soc_gpio02_pg2_pins[] = {560	TEGRA_PIN_SOC_GPIO02_PG2,561};562static const unsigned int soc_gpio03_pg3_pins[] = {563	TEGRA_PIN_SOC_GPIO03_PG3,564};565static const unsigned int soc_gpio08_pg4_pins[] = {566	TEGRA_PIN_SOC_GPIO08_PG4,567};568static const unsigned int soc_gpio09_pg5_pins[] = {569	TEGRA_PIN_SOC_GPIO09_PG5,570};571static const unsigned int soc_gpio10_pg6_pins[] = {572	TEGRA_PIN_SOC_GPIO10_PG6,573};574static const unsigned int soc_gpio11_pg7_pins[] = {575	TEGRA_PIN_SOC_GPIO11_PG7,576};577static const unsigned int soc_gpio12_ph0_pins[] = {578	TEGRA_PIN_SOC_GPIO12_PH0,579};580static const unsigned int soc_gpio13_ph1_pins[] = {581	TEGRA_PIN_SOC_GPIO13_PH1,582};583static const unsigned int soc_gpio14_ph2_pins[] = {584	TEGRA_PIN_SOC_GPIO14_PH2,585};586static const unsigned int uart4_tx_ph3_pins[] = {587	TEGRA_PIN_UART4_TX_PH3,588};589static const unsigned int uart4_rx_ph4_pins[] = {590	TEGRA_PIN_UART4_RX_PH4,591};592static const unsigned int uart4_rts_ph5_pins[] = {593	TEGRA_PIN_UART4_RTS_PH5,594};595static const unsigned int uart4_cts_ph6_pins[] = {596	TEGRA_PIN_UART4_CTS_PH6,597};598static const unsigned int dap2_sclk_ph7_pins[] = {599	TEGRA_PIN_DAP2_SCLK_PH7,600};601static const unsigned int dap2_dout_pi0_pins[] = {602	TEGRA_PIN_DAP2_DOUT_PI0,603};604static const unsigned int dap2_din_pi1_pins[] = {605	TEGRA_PIN_DAP2_DIN_PI1,606};607static const unsigned int dap2_fs_pi2_pins[] = {608	TEGRA_PIN_DAP2_FS_PI2,609};610static const unsigned int gen1_i2c_scl_pi3_pins[] = {611	TEGRA_PIN_GEN1_I2C_SCL_PI3,612};613static const unsigned int gen1_i2c_sda_pi4_pins[] = {614	TEGRA_PIN_GEN1_I2C_SDA_PI4,615};616static const unsigned int sdmmc1_clk_pj0_pins[] = {617	TEGRA_PIN_SDMMC1_CLK_PJ0,618};619static const unsigned int sdmmc1_cmd_pj1_pins[] = {620	TEGRA_PIN_SDMMC1_CMD_PJ1,621};622static const unsigned int sdmmc1_dat0_pj2_pins[] = {623	TEGRA_PIN_SDMMC1_DAT0_PJ2,624};625static const unsigned int sdmmc1_dat1_pj3_pins[] = {626	TEGRA_PIN_SDMMC1_DAT1_PJ3,627};628static const unsigned int sdmmc1_dat2_pj4_pins[] = {629	TEGRA_PIN_SDMMC1_DAT2_PJ4,630};631static const unsigned int sdmmc1_dat3_pj5_pins[] = {632	TEGRA_PIN_SDMMC1_DAT3_PJ5,633};634static const unsigned int pex_l0_clkreq_n_pk0_pins[] = {635	TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,636};637static const unsigned int pex_l0_rst_n_pk1_pins[] = {638	TEGRA_PIN_PEX_L0_RST_N_PK1,639};640static const unsigned int pex_l1_clkreq_n_pk2_pins[] = {641	TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,642};643static const unsigned int pex_l1_rst_n_pk3_pins[] = {644	TEGRA_PIN_PEX_L1_RST_N_PK3,645};646static const unsigned int pex_l2_clkreq_n_pk4_pins[] = {647	TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,648};649static const unsigned int pex_l2_rst_n_pk5_pins[] = {650	TEGRA_PIN_PEX_L2_RST_N_PK5,651};652static const unsigned int pex_l3_clkreq_n_pk6_pins[] = {653	TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,654};655static const unsigned int pex_l3_rst_n_pk7_pins[] = {656	TEGRA_PIN_PEX_L3_RST_N_PK7,657};658static const unsigned int pex_l4_clkreq_n_pl0_pins[] = {659	TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,660};661static const unsigned int pex_l4_rst_n_pl1_pins[] = {662	TEGRA_PIN_PEX_L4_RST_N_PL1,663};664static const unsigned int pex_wake_n_pl2_pins[] = {665	TEGRA_PIN_PEX_WAKE_N_PL2,666};667static const unsigned int sata_dev_slp_pl3_pins[] = {668	TEGRA_PIN_SATA_DEV_SLP_PL3,669};670static const unsigned int dp_aux_ch0_hpd_pm0_pins[] = {671	TEGRA_PIN_DP_AUX_CH0_HPD_PM0,672};673static const unsigned int dp_aux_ch1_hpd_pm1_pins[] = {674	TEGRA_PIN_DP_AUX_CH1_HPD_PM1,675};676static const unsigned int dp_aux_ch2_hpd_pm2_pins[] = {677	TEGRA_PIN_DP_AUX_CH2_HPD_PM2,678};679static const unsigned int dp_aux_ch3_hpd_pm3_pins[] = {680	TEGRA_PIN_DP_AUX_CH3_HPD_PM3,681};682static const unsigned int hdmi_cec_pm4_pins[] = {683	TEGRA_PIN_HDMI_CEC_PM4,684};685static const unsigned int soc_gpio50_pm5_pins[] = {686	TEGRA_PIN_SOC_GPIO50_PM5,687};688static const unsigned int soc_gpio51_pm6_pins[] = {689	TEGRA_PIN_SOC_GPIO51_PM6,690};691static const unsigned int soc_gpio52_pm7_pins[] = {692	TEGRA_PIN_SOC_GPIO52_PM7,693};694static const unsigned int soc_gpio53_pn0_pins[] = {695	TEGRA_PIN_SOC_GPIO53_PN0,696};697static const unsigned int soc_gpio54_pn1_pins[] = {698	TEGRA_PIN_SOC_GPIO54_PN1,699};700static const unsigned int soc_gpio55_pn2_pins[] = {701	TEGRA_PIN_SOC_GPIO55_PN2,702};703static const unsigned int sdmmc3_clk_po0_pins[] = {704	TEGRA_PIN_SDMMC3_CLK_PO0,705};706static const unsigned int sdmmc3_cmd_po1_pins[] = {707	TEGRA_PIN_SDMMC3_CMD_PO1,708};709static const unsigned int sdmmc3_dat0_po2_pins[] = {710	TEGRA_PIN_SDMMC3_DAT0_PO2,711};712static const unsigned int sdmmc3_dat1_po3_pins[] = {713	TEGRA_PIN_SDMMC3_DAT1_PO3,714};715static const unsigned int sdmmc3_dat2_po4_pins[] = {716	TEGRA_PIN_SDMMC3_DAT2_PO4,717};718static const unsigned int sdmmc3_dat3_po5_pins[] = {719	TEGRA_PIN_SDMMC3_DAT3_PO5,720};721static const unsigned int extperiph1_clk_pp0_pins[] = {722	TEGRA_PIN_EXTPERIPH1_CLK_PP0,723};724static const unsigned int extperiph2_clk_pp1_pins[] = {725	TEGRA_PIN_EXTPERIPH2_CLK_PP1,726};727static const unsigned int cam_i2c_scl_pp2_pins[] = {728	TEGRA_PIN_CAM_I2C_SCL_PP2,729};730static const unsigned int cam_i2c_sda_pp3_pins[] = {731	TEGRA_PIN_CAM_I2C_SDA_PP3,732};733static const unsigned int soc_gpio04_pp4_pins[] = {734	TEGRA_PIN_SOC_GPIO04_PP4,735};736static const unsigned int soc_gpio05_pp5_pins[] = {737	TEGRA_PIN_SOC_GPIO05_PP5,738};739static const unsigned int soc_gpio06_pp6_pins[] = {740	TEGRA_PIN_SOC_GPIO06_PP6,741};742static const unsigned int soc_gpio07_pp7_pins[] = {743	TEGRA_PIN_SOC_GPIO07_PP7,744};745static const unsigned int soc_gpio20_pq0_pins[] = {746	TEGRA_PIN_SOC_GPIO20_PQ0,747};748static const unsigned int soc_gpio21_pq1_pins[] = {749	TEGRA_PIN_SOC_GPIO21_PQ1,750};751static const unsigned int soc_gpio22_pq2_pins[] = {752	TEGRA_PIN_SOC_GPIO22_PQ2,753};754static const unsigned int soc_gpio23_pq3_pins[] = {755	TEGRA_PIN_SOC_GPIO23_PQ3,756};757static const unsigned int soc_gpio40_pq4_pins[] = {758	TEGRA_PIN_SOC_GPIO40_PQ4,759};760static const unsigned int soc_gpio41_pq5_pins[] = {761	TEGRA_PIN_SOC_GPIO41_PQ5,762};763static const unsigned int soc_gpio42_pq6_pins[] = {764	TEGRA_PIN_SOC_GPIO42_PQ6,765};766static const unsigned int soc_gpio43_pq7_pins[] = {767	TEGRA_PIN_SOC_GPIO43_PQ7,768};769static const unsigned int soc_gpio44_pr0_pins[] = {770	TEGRA_PIN_SOC_GPIO44_PR0,771};772static const unsigned int soc_gpio45_pr1_pins[] = {773	TEGRA_PIN_SOC_GPIO45_PR1,774};775static const unsigned int uart1_tx_pr2_pins[] = {776	TEGRA_PIN_UART1_TX_PR2,777};778static const unsigned int uart1_rx_pr3_pins[] = {779	TEGRA_PIN_UART1_RX_PR3,780};781static const unsigned int uart1_rts_pr4_pins[] = {782	TEGRA_PIN_UART1_RTS_PR4,783};784static const unsigned int uart1_cts_pr5_pins[] = {785	TEGRA_PIN_UART1_CTS_PR5,786};787static const unsigned int dap1_sclk_ps0_pins[] = {788	TEGRA_PIN_DAP1_SCLK_PS0,789};790static const unsigned int dap1_dout_ps1_pins[] = {791	TEGRA_PIN_DAP1_DOUT_PS1,792};793static const unsigned int dap1_din_ps2_pins[] = {794	TEGRA_PIN_DAP1_DIN_PS2,795};796static const unsigned int dap1_fs_ps3_pins[] = {797	TEGRA_PIN_DAP1_FS_PS3,798};799static const unsigned int aud_mclk_ps4_pins[] = {800	TEGRA_PIN_AUD_MCLK_PS4,801};802static const unsigned int soc_gpio30_ps5_pins[] = {803	TEGRA_PIN_SOC_GPIO30_PS5,804};805static const unsigned int soc_gpio31_ps6_pins[] = {806	TEGRA_PIN_SOC_GPIO31_PS6,807};808static const unsigned int soc_gpio32_ps7_pins[] = {809	TEGRA_PIN_SOC_GPIO32_PS7,810};811static const unsigned int soc_gpio33_pt0_pins[] = {812	TEGRA_PIN_SOC_GPIO33_PT0,813};814static const unsigned int dap3_sclk_pt1_pins[] = {815	TEGRA_PIN_DAP3_SCLK_PT1,816};817static const unsigned int dap3_dout_pt2_pins[] = {818	TEGRA_PIN_DAP3_DOUT_PT2,819};820static const unsigned int dap3_din_pt3_pins[] = {821	TEGRA_PIN_DAP3_DIN_PT3,822};823static const unsigned int dap3_fs_pt4_pins[] = {824	TEGRA_PIN_DAP3_FS_PT4,825};826static const unsigned int dap5_sclk_pt5_pins[] = {827	TEGRA_PIN_DAP5_SCLK_PT5,828};829static const unsigned int dap5_dout_pt6_pins[] = {830	TEGRA_PIN_DAP5_DOUT_PT6,831};832static const unsigned int dap5_din_pt7_pins[] = {833	TEGRA_PIN_DAP5_DIN_PT7,834};835static const unsigned int dap5_fs_pu0_pins[] = {836	TEGRA_PIN_DAP5_FS_PU0,837};838static const unsigned int directdc1_clk_pv0_pins[] = {839	TEGRA_PIN_DIRECTDC1_CLK_PV0,840};841static const unsigned int directdc1_in_pv1_pins[] = {842	TEGRA_PIN_DIRECTDC1_IN_PV1,843};844static const unsigned int directdc1_out0_pv2_pins[] = {845	TEGRA_PIN_DIRECTDC1_OUT0_PV2,846};847static const unsigned int directdc1_out1_pv3_pins[] = {848	TEGRA_PIN_DIRECTDC1_OUT1_PV3,849};850static const unsigned int directdc1_out2_pv4_pins[] = {851	TEGRA_PIN_DIRECTDC1_OUT2_PV4,852};853static const unsigned int directdc1_out3_pv5_pins[] = {854	TEGRA_PIN_DIRECTDC1_OUT3_PV5,855};856static const unsigned int directdc1_out4_pv6_pins[] = {857	TEGRA_PIN_DIRECTDC1_OUT4_PV6,858};859static const unsigned int directdc1_out5_pv7_pins[] = {860	TEGRA_PIN_DIRECTDC1_OUT5_PV7,861};862static const unsigned int directdc1_out6_pw0_pins[] = {863	TEGRA_PIN_DIRECTDC1_OUT6_PW0,864};865static const unsigned int directdc1_out7_pw1_pins[] = {866	TEGRA_PIN_DIRECTDC1_OUT7_PW1,867};868static const unsigned int gpu_pwr_req_px0_pins[] = {869	TEGRA_PIN_GPU_PWR_REQ_PX0,870};871static const unsigned int cv_pwr_req_px1_pins[] = {872	TEGRA_PIN_CV_PWR_REQ_PX1,873};874static const unsigned int gp_pwm2_px2_pins[] = {875	TEGRA_PIN_GP_PWM2_PX2,876};877static const unsigned int gp_pwm3_px3_pins[] = {878	TEGRA_PIN_GP_PWM3_PX3,879};880static const unsigned int uart2_tx_px4_pins[] = {881	TEGRA_PIN_UART2_TX_PX4,882};883static const unsigned int uart2_rx_px5_pins[] = {884	TEGRA_PIN_UART2_RX_PX5,885};886static const unsigned int uart2_rts_px6_pins[] = {887	TEGRA_PIN_UART2_RTS_PX6,888};889static const unsigned int uart2_cts_px7_pins[] = {890	TEGRA_PIN_UART2_CTS_PX7,891};892static const unsigned int spi3_sck_py0_pins[] = {893	TEGRA_PIN_SPI3_SCK_PY0,894};895static const unsigned int spi3_miso_py1_pins[] = {896	TEGRA_PIN_SPI3_MISO_PY1,897};898static const unsigned int spi3_mosi_py2_pins[] = {899	TEGRA_PIN_SPI3_MOSI_PY2,900};901static const unsigned int spi3_cs0_py3_pins[] = {902	TEGRA_PIN_SPI3_CS0_PY3,903};904static const unsigned int spi3_cs1_py4_pins[] = {905	TEGRA_PIN_SPI3_CS1_PY4,906};907static const unsigned int uart5_tx_py5_pins[] = {908	TEGRA_PIN_UART5_TX_PY5,909};910static const unsigned int uart5_rx_py6_pins[] = {911	TEGRA_PIN_UART5_RX_PY6,912};913static const unsigned int uart5_rts_py7_pins[] = {914	TEGRA_PIN_UART5_RTS_PY7,915};916static const unsigned int uart5_cts_pz0_pins[] = {917	TEGRA_PIN_UART5_CTS_PZ0,918};919static const unsigned int usb_vbus_en0_pz1_pins[] = {920	TEGRA_PIN_USB_VBUS_EN0_PZ1,921};922static const unsigned int usb_vbus_en1_pz2_pins[] = {923	TEGRA_PIN_USB_VBUS_EN1_PZ2,924};925static const unsigned int spi1_sck_pz3_pins[] = {926	TEGRA_PIN_SPI1_SCK_PZ3,927};928static const unsigned int spi1_miso_pz4_pins[] = {929	TEGRA_PIN_SPI1_MISO_PZ4,930};931static const unsigned int spi1_mosi_pz5_pins[] = {932	TEGRA_PIN_SPI1_MOSI_PZ5,933};934static const unsigned int spi1_cs0_pz6_pins[] = {935	TEGRA_PIN_SPI1_CS0_PZ6,936};937static const unsigned int spi1_cs1_pz7_pins[] = {938	TEGRA_PIN_SPI1_CS1_PZ7,939};940static const unsigned int can1_dout_paa0_pins[] = {941	TEGRA_PIN_CAN1_DOUT_PAA0,942};943static const unsigned int can1_din_paa1_pins[] = {944	TEGRA_PIN_CAN1_DIN_PAA1,945};946static const unsigned int can0_dout_paa2_pins[] = {947	TEGRA_PIN_CAN0_DOUT_PAA2,948};949static const unsigned int can0_din_paa3_pins[] = {950	TEGRA_PIN_CAN0_DIN_PAA3,951};952static const unsigned int can0_stb_paa4_pins[] = {953	TEGRA_PIN_CAN0_STB_PAA4,954};955static const unsigned int can0_en_paa5_pins[] = {956	TEGRA_PIN_CAN0_EN_PAA5,957};958static const unsigned int can0_wake_paa6_pins[] = {959	TEGRA_PIN_CAN0_WAKE_PAA6,960};961static const unsigned int can0_err_paa7_pins[] = {962	TEGRA_PIN_CAN0_ERR_PAA7,963};964static const unsigned int can1_stb_pbb0_pins[] = {965	TEGRA_PIN_CAN1_STB_PBB0,966};967static const unsigned int can1_en_pbb1_pins[] = {968	TEGRA_PIN_CAN1_EN_PBB1,969};970static const unsigned int can1_wake_pbb2_pins[] = {971	TEGRA_PIN_CAN1_WAKE_PBB2,972};973static const unsigned int can1_err_pbb3_pins[] = {974	TEGRA_PIN_CAN1_ERR_PBB3,975};976static const unsigned int spi2_sck_pcc0_pins[] = {977	TEGRA_PIN_SPI2_SCK_PCC0,978};979static const unsigned int spi2_miso_pcc1_pins[] = {980	TEGRA_PIN_SPI2_MISO_PCC1,981};982static const unsigned int spi2_mosi_pcc2_pins[] = {983	TEGRA_PIN_SPI2_MOSI_PCC2,984};985static const unsigned int spi2_cs0_pcc3_pins[] = {986	TEGRA_PIN_SPI2_CS0_PCC3,987};988static const unsigned int touch_clk_pcc4_pins[] = {989	TEGRA_PIN_TOUCH_CLK_PCC4,990};991static const unsigned int uart3_tx_pcc5_pins[] = {992	TEGRA_PIN_UART3_TX_PCC5,993};994static const unsigned int uart3_rx_pcc6_pins[] = {995	TEGRA_PIN_UART3_RX_PCC6,996};997static const unsigned int gen2_i2c_scl_pcc7_pins[] = {998	TEGRA_PIN_GEN2_I2C_SCL_PCC7,999};1000static const unsigned int gen2_i2c_sda_pdd0_pins[] = {1001	TEGRA_PIN_GEN2_I2C_SDA_PDD0,1002};1003static const unsigned int gen8_i2c_scl_pdd1_pins[] = {1004	TEGRA_PIN_GEN8_I2C_SCL_PDD1,1005};1006static const unsigned int gen8_i2c_sda_pdd2_pins[] = {1007	TEGRA_PIN_GEN8_I2C_SDA_PDD2,1008};1009static const unsigned int safe_state_pee0_pins[] = {1010	TEGRA_PIN_SAFE_STATE_PEE0,1011};1012static const unsigned int vcomp_alert_pee1_pins[] = {1013	TEGRA_PIN_VCOMP_ALERT_PEE1,1014};1015static const unsigned int ao_retention_n_pee2_pins[] = {1016	TEGRA_PIN_AO_RETENTION_N_PEE2,1017};1018static const unsigned int batt_oc_pee3_pins[] = {1019	TEGRA_PIN_BATT_OC_PEE3,1020};1021static const unsigned int power_on_pee4_pins[] = {1022	TEGRA_PIN_POWER_ON_PEE4,1023};1024static const unsigned int pwr_i2c_scl_pee5_pins[] = {1025	TEGRA_PIN_PWR_I2C_SCL_PEE5,1026};1027static const unsigned int pwr_i2c_sda_pee6_pins[] = {1028	TEGRA_PIN_PWR_I2C_SDA_PEE6,1029};1030static const unsigned int ufs0_ref_clk_pff0_pins[] = {1031	TEGRA_PIN_UFS0_REF_CLK_PFF0,1032};1033static const unsigned int ufs0_rst_pff1_pins[] = {1034	TEGRA_PIN_UFS0_RST_PFF1,1035};1036static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {1037	TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,1038};1039static const unsigned int pex_l5_rst_n_pgg1_pins[] = {1040	TEGRA_PIN_PEX_L5_RST_N_PGG1,1041};1042static const unsigned int directdc_comp_pins[] = {1043	TEGRA_PIN_DIRECTDC_COMP,1044};1045static const unsigned int sdmmc4_clk_pins[] = {1046	TEGRA_PIN_SDMMC4_CLK,1047};1048static const unsigned int sdmmc4_cmd_pins[] = {1049	TEGRA_PIN_SDMMC4_CMD,1050};1051static const unsigned int sdmmc4_dqs_pins[] = {1052	TEGRA_PIN_SDMMC4_DQS,1053};1054static const unsigned int sdmmc4_dat7_pins[] = {1055	TEGRA_PIN_SDMMC4_DAT7,1056};1057static const unsigned int sdmmc4_dat6_pins[] = {1058	TEGRA_PIN_SDMMC4_DAT6,1059};1060static const unsigned int sdmmc4_dat5_pins[] = {1061	TEGRA_PIN_SDMMC4_DAT5,1062};1063static const unsigned int sdmmc4_dat4_pins[] = {1064	TEGRA_PIN_SDMMC4_DAT4,1065};1066static const unsigned int sdmmc4_dat3_pins[] = {1067	TEGRA_PIN_SDMMC4_DAT3,1068};1069static const unsigned int sdmmc4_dat2_pins[] = {1070	TEGRA_PIN_SDMMC4_DAT2,1071};1072static const unsigned int sdmmc4_dat1_pins[] = {1073	TEGRA_PIN_SDMMC4_DAT1,1074};1075static const unsigned int sdmmc4_dat0_pins[] = {1076	TEGRA_PIN_SDMMC4_DAT0,1077};1078static const unsigned int sdmmc1_comp_pins[] = {1079	TEGRA_PIN_SDMMC1_COMP,1080};1081static const unsigned int sdmmc3_comp_pins[] = {1082	TEGRA_PIN_SDMMC3_COMP,1083};1084static const unsigned int eqos_comp_pins[] = {1085	TEGRA_PIN_EQOS_COMP,1086};1087static const unsigned int qspi_comp_pins[] = {1088	TEGRA_PIN_QSPI_COMP,1089};1090static const unsigned int shutdown_n_pins[] = {1091	TEGRA_PIN_SHUTDOWN_N,1092};1093static const unsigned int pmu_int_n_pins[] = {1094	TEGRA_PIN_PMU_INT_N,1095};1096static const unsigned int soc_pwr_req_pins[] = {1097	TEGRA_PIN_SOC_PWR_REQ,1098};1099static const unsigned int clk_32k_in_pins[] = {1100	TEGRA_PIN_CLK_32K_IN,1101};1102 1103/* Define unique ID for each function */1104enum tegra_mux_dt {1105	TEGRA_MUX_RSVD0,1106	TEGRA_MUX_RSVD1,1107	TEGRA_MUX_RSVD2,1108	TEGRA_MUX_RSVD3,1109	TEGRA_MUX_TOUCH,1110	TEGRA_MUX_UARTC,1111	TEGRA_MUX_I2C8,1112	TEGRA_MUX_UARTG,1113	TEGRA_MUX_SPI2,1114	TEGRA_MUX_GP,1115	TEGRA_MUX_DCA,1116	TEGRA_MUX_WDT,1117	TEGRA_MUX_I2C2,1118	TEGRA_MUX_CAN1,1119	TEGRA_MUX_CAN0,1120	TEGRA_MUX_DMIC3,1121	TEGRA_MUX_DMIC5,1122	TEGRA_MUX_GPIO,1123	TEGRA_MUX_DSPK1,1124	TEGRA_MUX_DSPK0,1125	TEGRA_MUX_SPDIF,1126	TEGRA_MUX_AUD,1127	TEGRA_MUX_I2S1,1128	TEGRA_MUX_DMIC1,1129	TEGRA_MUX_DMIC2,1130	TEGRA_MUX_I2S3,1131	TEGRA_MUX_DMIC4,1132	TEGRA_MUX_I2S4,1133	TEGRA_MUX_EXTPERIPH2,1134	TEGRA_MUX_EXTPERIPH1,1135	TEGRA_MUX_I2C3,1136	TEGRA_MUX_VGP1,1137	TEGRA_MUX_VGP2,1138	TEGRA_MUX_VGP3,1139	TEGRA_MUX_VGP4,1140	TEGRA_MUX_VGP5,1141	TEGRA_MUX_VGP6,1142	TEGRA_MUX_SLVS,1143	TEGRA_MUX_EXTPERIPH3,1144	TEGRA_MUX_EXTPERIPH4,1145	TEGRA_MUX_I2S2,1146	TEGRA_MUX_UARTD,1147	TEGRA_MUX_I2C1,1148	TEGRA_MUX_UARTA,1149	TEGRA_MUX_DIRECTDC1,1150	TEGRA_MUX_DIRECTDC,1151	TEGRA_MUX_IQC1,1152	TEGRA_MUX_IQC2,1153	TEGRA_MUX_I2S6,1154	TEGRA_MUX_SDMMC3,1155	TEGRA_MUX_SDMMC1,1156	TEGRA_MUX_DP,1157	TEGRA_MUX_HDMI,1158	TEGRA_MUX_PE2,1159	TEGRA_MUX_IGPU,1160	TEGRA_MUX_SATA,1161	TEGRA_MUX_PE1,1162	TEGRA_MUX_PE0,1163	TEGRA_MUX_PE3,1164	TEGRA_MUX_PE4,1165	TEGRA_MUX_PE5,1166	TEGRA_MUX_SOC,1167	TEGRA_MUX_EQOS,1168	TEGRA_MUX_QSPI,1169	TEGRA_MUX_QSPI0,1170	TEGRA_MUX_QSPI1,1171	TEGRA_MUX_MIPI,1172	TEGRA_MUX_SCE,1173	TEGRA_MUX_I2C5,1174	TEGRA_MUX_DISPLAYA,1175	TEGRA_MUX_DISPLAYB,1176	TEGRA_MUX_DCB,1177	TEGRA_MUX_SPI1,1178	TEGRA_MUX_UARTB,1179	TEGRA_MUX_UARTE,1180	TEGRA_MUX_SPI3,1181	TEGRA_MUX_NV,1182	TEGRA_MUX_CCLA,1183	TEGRA_MUX_I2S5,1184	TEGRA_MUX_USB,1185	TEGRA_MUX_UFS0,1186	TEGRA_MUX_DGPU,1187	TEGRA_MUX_SDMMC4,1188};1189 1190/* Make list of each function name */1191#define TEGRA_PIN_FUNCTION(lid) #lid1192 1193static const char * const tegra194_functions[] = {1194	TEGRA_PIN_FUNCTION(rsvd0),1195	TEGRA_PIN_FUNCTION(rsvd1),1196	TEGRA_PIN_FUNCTION(rsvd2),1197	TEGRA_PIN_FUNCTION(rsvd3),1198	TEGRA_PIN_FUNCTION(touch),1199	TEGRA_PIN_FUNCTION(uartc),1200	TEGRA_PIN_FUNCTION(i2c8),1201	TEGRA_PIN_FUNCTION(uartg),1202	TEGRA_PIN_FUNCTION(spi2),1203	TEGRA_PIN_FUNCTION(gp),1204	TEGRA_PIN_FUNCTION(dca),1205	TEGRA_PIN_FUNCTION(wdt),1206	TEGRA_PIN_FUNCTION(i2c2),1207	TEGRA_PIN_FUNCTION(can1),1208	TEGRA_PIN_FUNCTION(can0),1209	TEGRA_PIN_FUNCTION(dmic3),1210	TEGRA_PIN_FUNCTION(dmic5),1211	TEGRA_PIN_FUNCTION(gpio),1212	TEGRA_PIN_FUNCTION(dspk1),1213	TEGRA_PIN_FUNCTION(dspk0),1214	TEGRA_PIN_FUNCTION(spdif),1215	TEGRA_PIN_FUNCTION(aud),1216	TEGRA_PIN_FUNCTION(i2s1),1217	TEGRA_PIN_FUNCTION(dmic1),1218	TEGRA_PIN_FUNCTION(dmic2),1219	TEGRA_PIN_FUNCTION(i2s3),1220	TEGRA_PIN_FUNCTION(dmic4),1221	TEGRA_PIN_FUNCTION(i2s4),1222	TEGRA_PIN_FUNCTION(extperiph2),1223	TEGRA_PIN_FUNCTION(extperiph1),1224	TEGRA_PIN_FUNCTION(i2c3),1225	TEGRA_PIN_FUNCTION(vgp1),1226	TEGRA_PIN_FUNCTION(vgp2),1227	TEGRA_PIN_FUNCTION(vgp3),1228	TEGRA_PIN_FUNCTION(vgp4),1229	TEGRA_PIN_FUNCTION(vgp5),1230	TEGRA_PIN_FUNCTION(vgp6),1231	TEGRA_PIN_FUNCTION(slvs),1232	TEGRA_PIN_FUNCTION(extperiph3),1233	TEGRA_PIN_FUNCTION(extperiph4),1234	TEGRA_PIN_FUNCTION(i2s2),1235	TEGRA_PIN_FUNCTION(uartd),1236	TEGRA_PIN_FUNCTION(i2c1),1237	TEGRA_PIN_FUNCTION(uarta),1238	TEGRA_PIN_FUNCTION(directdc1),1239	TEGRA_PIN_FUNCTION(directdc),1240	TEGRA_PIN_FUNCTION(iqc1),1241	TEGRA_PIN_FUNCTION(iqc2),1242	TEGRA_PIN_FUNCTION(i2s6),1243	TEGRA_PIN_FUNCTION(sdmmc3),1244	TEGRA_PIN_FUNCTION(sdmmc1),1245	TEGRA_PIN_FUNCTION(dp),1246	TEGRA_PIN_FUNCTION(hdmi),1247	TEGRA_PIN_FUNCTION(pe2),1248	TEGRA_PIN_FUNCTION(igpu),1249	TEGRA_PIN_FUNCTION(sata),1250	TEGRA_PIN_FUNCTION(pe1),1251	TEGRA_PIN_FUNCTION(pe0),1252	TEGRA_PIN_FUNCTION(pe3),1253	TEGRA_PIN_FUNCTION(pe4),1254	TEGRA_PIN_FUNCTION(pe5),1255	TEGRA_PIN_FUNCTION(soc),1256	TEGRA_PIN_FUNCTION(eqos),1257	TEGRA_PIN_FUNCTION(qspi),1258	TEGRA_PIN_FUNCTION(qspi0),1259	TEGRA_PIN_FUNCTION(qspi1),1260	TEGRA_PIN_FUNCTION(mipi),1261	TEGRA_PIN_FUNCTION(sce),1262	TEGRA_PIN_FUNCTION(i2c5),1263	TEGRA_PIN_FUNCTION(displaya),1264	TEGRA_PIN_FUNCTION(displayb),1265	TEGRA_PIN_FUNCTION(dcb),1266	TEGRA_PIN_FUNCTION(spi1),1267	TEGRA_PIN_FUNCTION(uartb),1268	TEGRA_PIN_FUNCTION(uarte),1269	TEGRA_PIN_FUNCTION(spi3),1270	TEGRA_PIN_FUNCTION(nv),1271	TEGRA_PIN_FUNCTION(ccla),1272	TEGRA_PIN_FUNCTION(i2s5),1273	TEGRA_PIN_FUNCTION(usb),1274	TEGRA_PIN_FUNCTION(ufs0),1275	TEGRA_PIN_FUNCTION(dgpu),1276	TEGRA_PIN_FUNCTION(sdmmc4),1277 1278};1279 1280#define PINGROUP_REG_Y(r) ((r))1281#define PINGROUP_REG_N(r) -11282 1283#define DRV_PINGROUP_Y(r) ((r))1284#define DRV_PINGROUP_N(r) -11285 1286#define DRV_PINGROUP_ENTRY_N(pg_name)				\1287		.drv_reg = -1,					\1288		.drv_bank = -1,					\1289		.drvdn_bit = -1,				\1290		.drvup_bit = -1,				\1291		.slwr_bit = -1,					\1292		.slwf_bit = -11293 1294#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b,	\1295			     drvup_w, slwr_b, slwr_w, slwf_b,	\1296			     slwf_w, bank)			\1297		.drv_reg = ((r)),				\1298		.drv_bank = bank,				\1299		.drvdn_bit = drvdn_b,				\1300		.drvdn_width = drvdn_w,				\1301		.drvup_bit = drvup_b,				\1302		.drvup_width = drvup_w,				\1303		.slwr_bit = slwr_b,				\1304		.slwr_width = slwr_w,				\1305		.slwf_bit = slwf_b,				\1306		.slwf_width = slwf_w1307 1308#define PIN_PINGROUP_ENTRY_N(pg_name)				\1309		.mux_reg = -1,					\1310		.pupd_reg = -1,					\1311		.tri_reg = -1,					\1312		.einput_bit = -1,				\1313		.e_io_hv_bit = -1,				\1314		.odrain_bit = -1,				\1315		.lock_bit = -1,					\1316		.parked_bit = -1,				\1317		.lpmd_bit = -1,					\1318		.drvtype_bit = -1,				\1319		.lpdr_bit = -1,					\1320		.pbias_buf_bit = -1,				\1321		.preemp_bit = -1,				\1322		.rfu_in_bit = -11323 1324#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input,	\1325			     e_lpdr, e_pbias_buf, gpio_sfio_sel, \1326			     e_od, schmitt_b, drvtype, epreemp,	\1327			     io_reset, rfu_in, io_rail)		\1328		.mux_reg = PINGROUP_REG_Y(r),			\1329		.lpmd_bit = -1,					\1330		.lock_bit = -1,					\1331		.hsm_bit = -1,					\1332		.mux_bank = bank,				\1333		.mux_bit = 0,					\1334		.pupd_reg = PINGROUP_REG_##pupd(r),		\1335		.pupd_bank = bank,				\1336		.pupd_bit = 2,					\1337		.tri_reg = PINGROUP_REG_Y(r),			\1338		.tri_bank = bank,				\1339		.tri_bit = 4,					\1340		.einput_bit = e_input,				\1341		.sfsel_bit = gpio_sfio_sel,			\1342		.odrain_bit = e_od,				\1343		.schmitt_bit = schmitt_b,			\1344		.drvtype_bit = 13,				\1345		.lpdr_bit = e_lpdr,				\1346 1347/* main drive pin groups */1348#define drive_soc_gpio33_pt0            DRV_PINGROUP_ENTRY_Y(0x1004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1349#define drive_soc_gpio32_ps7            DRV_PINGROUP_ENTRY_Y(0x100c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1350#define drive_soc_gpio31_ps6            DRV_PINGROUP_ENTRY_Y(0x1014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1351#define drive_soc_gpio30_ps5            DRV_PINGROUP_ENTRY_Y(0x101c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1352#define drive_aud_mclk_ps4              DRV_PINGROUP_ENTRY_Y(0x1024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1353#define drive_dap1_fs_ps3               DRV_PINGROUP_ENTRY_Y(0x102c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1354#define drive_dap1_din_ps2              DRV_PINGROUP_ENTRY_Y(0x1034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1355#define drive_dap1_dout_ps1             DRV_PINGROUP_ENTRY_Y(0x103c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1356#define drive_dap1_sclk_ps0             DRV_PINGROUP_ENTRY_Y(0x1044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1357#define drive_dap3_fs_pt4               DRV_PINGROUP_ENTRY_Y(0x104c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1358#define drive_dap3_din_pt3              DRV_PINGROUP_ENTRY_Y(0x1054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1359#define drive_dap3_dout_pt2             DRV_PINGROUP_ENTRY_Y(0x105c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1360#define drive_dap3_sclk_pt1             DRV_PINGROUP_ENTRY_Y(0x1064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1361#define drive_dap5_fs_pu0               DRV_PINGROUP_ENTRY_Y(0x106c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1362#define drive_dap5_din_pt7              DRV_PINGROUP_ENTRY_Y(0x1074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1363#define drive_dap5_dout_pt6             DRV_PINGROUP_ENTRY_Y(0x107c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1364#define drive_dap5_sclk_pt5             DRV_PINGROUP_ENTRY_Y(0x1084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1365#define drive_dap6_fs_pa3               DRV_PINGROUP_ENTRY_Y(0x2004,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1366#define drive_dap6_din_pa2              DRV_PINGROUP_ENTRY_Y(0x200c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1367#define drive_dap6_dout_pa1             DRV_PINGROUP_ENTRY_Y(0x2014,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1368#define drive_dap6_sclk_pa0             DRV_PINGROUP_ENTRY_Y(0x201c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1369#define drive_dap4_fs_pa7               DRV_PINGROUP_ENTRY_Y(0x2024,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1370#define drive_dap4_din_pa6              DRV_PINGROUP_ENTRY_Y(0x202c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1371#define drive_dap4_dout_pa5             DRV_PINGROUP_ENTRY_Y(0x2034,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1372#define drive_dap4_sclk_pa4             DRV_PINGROUP_ENTRY_Y(0x203c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1373#define drive_extperiph2_clk_pp1        DRV_PINGROUP_ENTRY_Y(0x0004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1374#define drive_extperiph1_clk_pp0        DRV_PINGROUP_ENTRY_Y(0x000c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1375#define drive_cam_i2c_sda_pp3           DRV_PINGROUP_ENTRY_Y(0x0014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1376#define drive_cam_i2c_scl_pp2           DRV_PINGROUP_ENTRY_Y(0x001c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1377#define drive_soc_gpio40_pq4            DRV_PINGROUP_ENTRY_Y(0x0024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1378#define drive_soc_gpio41_pq5            DRV_PINGROUP_ENTRY_Y(0x002c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1379#define drive_soc_gpio42_pq6            DRV_PINGROUP_ENTRY_Y(0x0034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1380#define drive_soc_gpio43_pq7            DRV_PINGROUP_ENTRY_Y(0x003c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1381#define drive_soc_gpio44_pr0            DRV_PINGROUP_ENTRY_Y(0x0044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1382#define drive_soc_gpio45_pr1            DRV_PINGROUP_ENTRY_Y(0x004c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1383#define drive_soc_gpio20_pq0            DRV_PINGROUP_ENTRY_Y(0x0054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1384#define drive_soc_gpio21_pq1            DRV_PINGROUP_ENTRY_Y(0x005c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1385#define drive_soc_gpio22_pq2            DRV_PINGROUP_ENTRY_Y(0x0064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1386#define drive_soc_gpio23_pq3            DRV_PINGROUP_ENTRY_Y(0x006c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1387#define drive_soc_gpio04_pp4            DRV_PINGROUP_ENTRY_Y(0x0074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1388#define drive_soc_gpio05_pp5            DRV_PINGROUP_ENTRY_Y(0x007c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1389#define drive_soc_gpio06_pp6            DRV_PINGROUP_ENTRY_Y(0x0084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1390#define drive_soc_gpio07_pp7            DRV_PINGROUP_ENTRY_Y(0x008c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1391#define drive_uart1_cts_pr5             DRV_PINGROUP_ENTRY_Y(0x0094,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1392#define drive_uart1_rts_pr4             DRV_PINGROUP_ENTRY_Y(0x009c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1393#define drive_uart1_rx_pr3              DRV_PINGROUP_ENTRY_Y(0x00a4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1394#define drive_uart1_tx_pr2              DRV_PINGROUP_ENTRY_Y(0x00ac,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1395#define drive_dap2_din_pi1              DRV_PINGROUP_ENTRY_Y(0x4004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1396#define drive_dap2_dout_pi0             DRV_PINGROUP_ENTRY_Y(0x400c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1397#define drive_dap2_fs_pi2               DRV_PINGROUP_ENTRY_Y(0x4014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1398#define drive_dap2_sclk_ph7             DRV_PINGROUP_ENTRY_Y(0x401c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1399#define drive_uart4_cts_ph6             DRV_PINGROUP_ENTRY_Y(0x4024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1400#define drive_uart4_rts_ph5             DRV_PINGROUP_ENTRY_Y(0x402c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1401#define drive_uart4_rx_ph4              DRV_PINGROUP_ENTRY_Y(0x4034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1402#define drive_uart4_tx_ph3              DRV_PINGROUP_ENTRY_Y(0x403c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1403#define drive_soc_gpio03_pg3            DRV_PINGROUP_ENTRY_Y(0x4044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1404#define drive_soc_gpio02_pg2            DRV_PINGROUP_ENTRY_Y(0x404c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1405#define drive_soc_gpio01_pg1            DRV_PINGROUP_ENTRY_Y(0x4054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1406#define drive_soc_gpio00_pg0            DRV_PINGROUP_ENTRY_Y(0x405c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1407#define drive_gen1_i2c_scl_pi3          DRV_PINGROUP_ENTRY_Y(0x4064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1408#define drive_gen1_i2c_sda_pi4          DRV_PINGROUP_ENTRY_Y(0x406c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1409#define drive_soc_gpio08_pg4            DRV_PINGROUP_ENTRY_Y(0x4074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1410#define drive_soc_gpio09_pg5            DRV_PINGROUP_ENTRY_Y(0x407c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1411#define drive_soc_gpio10_pg6            DRV_PINGROUP_ENTRY_Y(0x4084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1412#define drive_soc_gpio11_pg7            DRV_PINGROUP_ENTRY_Y(0x408c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1413#define drive_soc_gpio12_ph0            DRV_PINGROUP_ENTRY_Y(0x4094,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1414#define drive_soc_gpio13_ph1            DRV_PINGROUP_ENTRY_Y(0x409c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1415#define drive_soc_gpio14_ph2            DRV_PINGROUP_ENTRY_Y(0x40a4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1416#define drive_soc_gpio50_pm5            DRV_PINGROUP_ENTRY_Y(0x10004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1417#define drive_soc_gpio51_pm6            DRV_PINGROUP_ENTRY_Y(0x1000c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1418#define drive_soc_gpio52_pm7            DRV_PINGROUP_ENTRY_Y(0x10014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1419#define drive_soc_gpio53_pn0            DRV_PINGROUP_ENTRY_Y(0x1001c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1420#define drive_soc_gpio54_pn1            DRV_PINGROUP_ENTRY_Y(0x10024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1421#define drive_soc_gpio55_pn2            DRV_PINGROUP_ENTRY_Y(0x1002c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1422#define drive_dp_aux_ch0_hpd_pm0        DRV_PINGROUP_ENTRY_Y(0x10034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1423#define drive_dp_aux_ch1_hpd_pm1        DRV_PINGROUP_ENTRY_Y(0x1003c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1424#define drive_dp_aux_ch2_hpd_pm2        DRV_PINGROUP_ENTRY_Y(0x10044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1425#define drive_dp_aux_ch3_hpd_pm3        DRV_PINGROUP_ENTRY_Y(0x1004c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1426#define drive_hdmi_cec_pm4              DRV_PINGROUP_ENTRY_Y(0x10054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1427#define drive_pex_l2_clkreq_n_pk4       DRV_PINGROUP_ENTRY_Y(0x7004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1428#define drive_pex_wake_n_pl2            DRV_PINGROUP_ENTRY_Y(0x700c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1429#define drive_pex_l1_clkreq_n_pk2       DRV_PINGROUP_ENTRY_Y(0x7014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1430#define drive_pex_l1_rst_n_pk3          DRV_PINGROUP_ENTRY_Y(0x701c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1431#define drive_pex_l0_clkreq_n_pk0       DRV_PINGROUP_ENTRY_Y(0x7024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1432#define drive_pex_l0_rst_n_pk1          DRV_PINGROUP_ENTRY_Y(0x702c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1433#define drive_pex_l2_rst_n_pk5          DRV_PINGROUP_ENTRY_Y(0x7034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1434#define drive_pex_l3_clkreq_n_pk6       DRV_PINGROUP_ENTRY_Y(0x703c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1435#define drive_pex_l3_rst_n_pk7          DRV_PINGROUP_ENTRY_Y(0x7044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1436#define drive_pex_l4_clkreq_n_pl0       DRV_PINGROUP_ENTRY_Y(0x704c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1437#define drive_pex_l4_rst_n_pl1          DRV_PINGROUP_ENTRY_Y(0x7054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1438#define drive_sata_dev_slp_pl3          DRV_PINGROUP_ENTRY_Y(0x705c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1439#define drive_pex_l5_clkreq_n_pgg0      DRV_PINGROUP_ENTRY_Y(0x14004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1440#define drive_pex_l5_rst_n_pgg1         DRV_PINGROUP_ENTRY_Y(0x1400c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1441#define drive_cpu_pwr_req_1_pb1         DRV_PINGROUP_ENTRY_Y(0x16004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1442#define drive_cpu_pwr_req_0_pb0         DRV_PINGROUP_ENTRY_Y(0x1600c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1443#define drive_sdmmc1_clk_pj0            DRV_PINGROUP_ENTRY_Y(0x8004,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1444#define drive_sdmmc1_cmd_pj1            DRV_PINGROUP_ENTRY_Y(0x800c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1445#define drive_sdmmc1_dat3_pj5           DRV_PINGROUP_ENTRY_Y(0x801c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1446#define drive_sdmmc1_dat2_pj4           DRV_PINGROUP_ENTRY_Y(0x8024,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1447#define drive_sdmmc1_dat1_pj3           DRV_PINGROUP_ENTRY_Y(0x802c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1448#define drive_sdmmc1_dat0_pj2           DRV_PINGROUP_ENTRY_Y(0x8034,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1449#define drive_sdmmc3_dat3_po5           DRV_PINGROUP_ENTRY_Y(0xa004,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1450#define drive_sdmmc3_dat2_po4           DRV_PINGROUP_ENTRY_Y(0xa00c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1451#define drive_sdmmc3_dat1_po3           DRV_PINGROUP_ENTRY_Y(0xa014,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1452#define drive_sdmmc3_dat0_po2           DRV_PINGROUP_ENTRY_Y(0xa01c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1453#define drive_sdmmc3_cmd_po1            DRV_PINGROUP_ENTRY_Y(0xa02c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1454#define drive_sdmmc3_clk_po0            DRV_PINGROUP_ENTRY_Y(0xa034,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)1455#define drive_gpu_pwr_req_px0           DRV_PINGROUP_ENTRY_Y(0xD004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1456#define drive_spi3_miso_py1             DRV_PINGROUP_ENTRY_Y(0xD00c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1457#define drive_spi1_cs0_pz6              DRV_PINGROUP_ENTRY_Y(0xD014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1458#define drive_spi3_cs0_py3              DRV_PINGROUP_ENTRY_Y(0xD01c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1459#define drive_spi1_miso_pz4             DRV_PINGROUP_ENTRY_Y(0xD024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1460#define drive_spi3_cs1_py4              DRV_PINGROUP_ENTRY_Y(0xD02c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1461#define drive_gp_pwm3_px3               DRV_PINGROUP_ENTRY_Y(0xD034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1462#define drive_gp_pwm2_px2               DRV_PINGROUP_ENTRY_Y(0xD03c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1463#define drive_spi1_sck_pz3              DRV_PINGROUP_ENTRY_Y(0xD044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1464#define drive_spi3_sck_py0              DRV_PINGROUP_ENTRY_Y(0xD04c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1465#define drive_spi1_cs1_pz7              DRV_PINGROUP_ENTRY_Y(0xD054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1466#define drive_spi1_mosi_pz5             DRV_PINGROUP_ENTRY_Y(0xD05c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1467#define drive_spi3_mosi_py2             DRV_PINGROUP_ENTRY_Y(0xD064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1468#define drive_cv_pwr_req_px1            DRV_PINGROUP_ENTRY_Y(0xD06c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1469#define drive_uart2_tx_px4              DRV_PINGROUP_ENTRY_Y(0xD074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1470#define drive_uart2_rx_px5              DRV_PINGROUP_ENTRY_Y(0xD07c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1471#define drive_uart2_rts_px6             DRV_PINGROUP_ENTRY_Y(0xD084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1472#define drive_uart2_cts_px7             DRV_PINGROUP_ENTRY_Y(0xD08c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1473#define drive_uart5_rx_py6              DRV_PINGROUP_ENTRY_Y(0xD094,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1474#define drive_uart5_tx_py5              DRV_PINGROUP_ENTRY_Y(0xD09c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1475#define drive_uart5_rts_py7             DRV_PINGROUP_ENTRY_Y(0xD0a4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1476#define drive_uart5_cts_pz0             DRV_PINGROUP_ENTRY_Y(0xD0ac,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1477#define drive_usb_vbus_en0_pz1          DRV_PINGROUP_ENTRY_Y(0xD0b4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1478#define drive_usb_vbus_en1_pz2          DRV_PINGROUP_ENTRY_Y(0xD0bc,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1479#define drive_ufs0_rst_pff1             DRV_PINGROUP_ENTRY_Y(0x11004,	12,	9,	24,	8,	-1,	-1,	-1,	-1,	0)1480#define drive_ufs0_ref_clk_pff0         DRV_PINGROUP_ENTRY_Y(0x1100c,	12,	9,	24,	8,	-1,	-1,	-1,	-1,	0)1481 1482#define drive_directdc_comp             DRV_PINGROUP_ENTRY_N(no_entry)1483#define drive_sdmmc1_comp               DRV_PINGROUP_ENTRY_N(no_entry)1484#define drive_eqos_comp                 DRV_PINGROUP_ENTRY_N(no_entry)1485#define drive_sdmmc3_comp               DRV_PINGROUP_ENTRY_N(no_entry)1486#define drive_sdmmc4_clk                DRV_PINGROUP_ENTRY_N(no_entry)1487#define drive_sdmmc4_cmd                DRV_PINGROUP_ENTRY_N(no_entry)1488#define drive_sdmmc4_dqs                DRV_PINGROUP_ENTRY_N(no_entry)1489#define drive_sdmmc4_dat7               DRV_PINGROUP_ENTRY_N(no_entry)1490#define drive_sdmmc4_dat6               DRV_PINGROUP_ENTRY_N(no_entry)1491#define drive_sdmmc4_dat5               DRV_PINGROUP_ENTRY_N(no_entry)1492#define drive_sdmmc4_dat4               DRV_PINGROUP_ENTRY_N(no_entry)1493#define drive_sdmmc4_dat3               DRV_PINGROUP_ENTRY_N(no_entry)1494#define drive_sdmmc4_dat2               DRV_PINGROUP_ENTRY_N(no_entry)1495#define drive_sdmmc4_dat1               DRV_PINGROUP_ENTRY_N(no_entry)1496#define drive_sdmmc4_dat0               DRV_PINGROUP_ENTRY_N(no_entry)1497#define drive_qspi_comp                 DRV_PINGROUP_ENTRY_N(no_entry)1498#define drive_qspi1_cs_n_pc7            DRV_PINGROUP_ENTRY_N(no_entry)1499#define drive_qspi1_sck_pc6             DRV_PINGROUP_ENTRY_N(no_entry)1500#define drive_qspi1_io0_pd0             DRV_PINGROUP_ENTRY_N(no_entry)1501#define drive_qspi1_io1_pd1             DRV_PINGROUP_ENTRY_N(no_entry)1502#define drive_qspi1_io2_pd2             DRV_PINGROUP_ENTRY_N(no_entry)1503#define drive_qspi1_io3_pd3             DRV_PINGROUP_ENTRY_N(no_entry)1504#define drive_qspi0_io0_pc2             DRV_PINGROUP_ENTRY_N(no_entry)1505#define drive_qspi0_io1_pc3             DRV_PINGROUP_ENTRY_N(no_entry)1506#define drive_qspi0_io2_pc4             DRV_PINGROUP_ENTRY_N(no_entry)1507#define drive_qspi0_io3_pc5             DRV_PINGROUP_ENTRY_N(no_entry)1508#define drive_qspi0_cs_n_pc1            DRV_PINGROUP_ENTRY_N(no_entry)1509#define drive_qspi0_sck_pc0             DRV_PINGROUP_ENTRY_N(no_entry)1510#define drive_eqos_rx_ctl_pf2           DRV_PINGROUP_ENTRY_N(no_entry)1511#define drive_eqos_tx_ctl_pe5           DRV_PINGROUP_ENTRY_N(no_entry)1512#define drive_eqos_rxc_pf3              DRV_PINGROUP_ENTRY_N(no_entry)1513#define drive_eqos_txc_pe0              DRV_PINGROUP_ENTRY_N(no_entry)1514#define drive_eqos_sma_mdc_pf5          DRV_PINGROUP_ENTRY_N(no_entry)1515#define drive_eqos_sma_mdio_pf4         DRV_PINGROUP_ENTRY_N(no_entry)1516#define drive_eqos_rd0_pe6              DRV_PINGROUP_ENTRY_N(no_entry)1517#define drive_eqos_rd1_pe7              DRV_PINGROUP_ENTRY_N(no_entry)1518#define drive_eqos_rd2_pf0              DRV_PINGROUP_ENTRY_N(no_entry)1519#define drive_eqos_rd3_pf1              DRV_PINGROUP_ENTRY_N(no_entry)1520#define drive_eqos_td0_pe1              DRV_PINGROUP_ENTRY_N(no_entry)1521#define drive_eqos_td1_pe2              DRV_PINGROUP_ENTRY_N(no_entry)1522#define drive_eqos_td2_pe3              DRV_PINGROUP_ENTRY_N(no_entry)1523#define drive_eqos_td3_pe4              DRV_PINGROUP_ENTRY_N(no_entry)1524#define drive_directdc1_out7_pw1        DRV_PINGROUP_ENTRY_N(no_entry)1525#define drive_directdc1_out6_pw0        DRV_PINGROUP_ENTRY_N(no_entry)1526#define drive_directdc1_out5_pv7        DRV_PINGROUP_ENTRY_N(no_entry)1527#define drive_directdc1_out4_pv6        DRV_PINGROUP_ENTRY_N(no_entry)1528#define drive_directdc1_out3_pv5        DRV_PINGROUP_ENTRY_N(no_entry)1529#define drive_directdc1_out2_pv4        DRV_PINGROUP_ENTRY_N(no_entry)1530#define drive_directdc1_out1_pv3        DRV_PINGROUP_ENTRY_N(no_entry)1531#define drive_directdc1_out0_pv2        DRV_PINGROUP_ENTRY_N(no_entry)1532#define drive_directdc1_in_pv1          DRV_PINGROUP_ENTRY_N(no_entry)1533#define drive_directdc1_clk_pv0         DRV_PINGROUP_ENTRY_N(no_entry)1534 1535/* AON drive pin groups */1536#define drive_shutdown_n                DRV_PINGROUP_ENTRY_Y(0x1004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1537#define drive_pmu_int_n                 DRV_PINGROUP_ENTRY_Y(0x100c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1538#define drive_safe_state_pee0           DRV_PINGROUP_ENTRY_Y(0x1014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1539#define drive_vcomp_alert_pee1          DRV_PINGROUP_ENTRY_Y(0x101c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1540#define drive_soc_pwr_req               DRV_PINGROUP_ENTRY_Y(0x1024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1541#define drive_batt_oc_pee3              DRV_PINGROUP_ENTRY_Y(0x102c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1542#define drive_clk_32k_in                DRV_PINGROUP_ENTRY_Y(0x1034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1543#define drive_power_on_pee4             DRV_PINGROUP_ENTRY_Y(0x103c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1544#define drive_pwr_i2c_scl_pee5          DRV_PINGROUP_ENTRY_Y(0x1044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1545#define drive_pwr_i2c_sda_pee6          DRV_PINGROUP_ENTRY_Y(0x104c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1546#define drive_ao_retention_n_pee2       DRV_PINGROUP_ENTRY_Y(0x1064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1547#define drive_touch_clk_pcc4            DRV_PINGROUP_ENTRY_Y(0x2004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1548#define drive_uart3_rx_pcc6             DRV_PINGROUP_ENTRY_Y(0x200c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1549#define drive_uart3_tx_pcc5             DRV_PINGROUP_ENTRY_Y(0x2014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1550#define drive_gen8_i2c_sda_pdd2         DRV_PINGROUP_ENTRY_Y(0x201c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1551#define drive_gen8_i2c_scl_pdd1         DRV_PINGROUP_ENTRY_Y(0x2024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1552#define drive_spi2_mosi_pcc2            DRV_PINGROUP_ENTRY_Y(0x202c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1553#define drive_gen2_i2c_scl_pcc7         DRV_PINGROUP_ENTRY_Y(0x2034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1554#define drive_spi2_cs0_pcc3             DRV_PINGROUP_ENTRY_Y(0x203c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1555#define drive_gen2_i2c_sda_pdd0         DRV_PINGROUP_ENTRY_Y(0x2044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1556#define drive_spi2_sck_pcc0             DRV_PINGROUP_ENTRY_Y(0x204c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1557#define drive_spi2_miso_pcc1            DRV_PINGROUP_ENTRY_Y(0x2054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1558#define drive_can1_dout_paa0            DRV_PINGROUP_ENTRY_Y(0x3004,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1559#define drive_can1_din_paa1             DRV_PINGROUP_ENTRY_Y(0x300c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1560#define drive_can0_dout_paa2            DRV_PINGROUP_ENTRY_Y(0x3014,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1561#define drive_can0_din_paa3             DRV_PINGROUP_ENTRY_Y(0x301c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1562#define drive_can0_stb_paa4             DRV_PINGROUP_ENTRY_Y(0x3024,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1563#define drive_can0_en_paa5              DRV_PINGROUP_ENTRY_Y(0x302c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1564#define drive_can0_wake_paa6            DRV_PINGROUP_ENTRY_Y(0x3034,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1565#define drive_can0_err_paa7             DRV_PINGROUP_ENTRY_Y(0x303c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1566#define drive_can1_stb_pbb0             DRV_PINGROUP_ENTRY_Y(0x3044,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1567#define drive_can1_en_pbb1              DRV_PINGROUP_ENTRY_Y(0x304c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1568#define drive_can1_wake_pbb2            DRV_PINGROUP_ENTRY_Y(0x3054,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1569#define drive_can1_err_pbb3             DRV_PINGROUP_ENTRY_Y(0x305c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1570 1571#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \1572			gpio_sfio_sel, e_od, schmitt_b, drvtype, epreemp, io_reset, rfu_in, io_rail)	\1573	{							\1574		.name = #pg_name,				\1575		.pins = pg_name##_pins,				\1576		.npins = ARRAY_SIZE(pg_name##_pins),		\1577			.funcs = {				\1578				TEGRA_MUX_##f0,			\1579				TEGRA_MUX_##f1,			\1580				TEGRA_MUX_##f2,			\1581				TEGRA_MUX_##f3,			\1582			},					\1583		PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk,	\1584				     e_input, e_lpdr, e_pbias_buf, \1585				     gpio_sfio_sel, e_od,	\1586				     schmitt_b, drvtype,	\1587				     epreemp, io_reset,		\1588				     rfu_in, io_rail)		\1589		drive_##pg_name,				\1590	}1591 1592static const struct tegra_pingroup tegra194_groups[] = {1593	PINGROUP(soc_gpio33_pt0,	RSVD0,		SPDIF,		RSVD2,		RSVD3,		0x1000,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1594	PINGROUP(soc_gpio32_ps7,	RSVD0,		SPDIF,		RSVD2,		RSVD3,		0x1008,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1595	PINGROUP(soc_gpio31_ps6,	RSVD0,		SDMMC1,		RSVD2,		RSVD3,		0x1010,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1596	PINGROUP(soc_gpio30_ps5,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1018,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1597	PINGROUP(aud_mclk_ps4,		AUD,		RSVD1,		RSVD2,		RSVD3,		0x1020,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1598	PINGROUP(dap1_fs_ps3,		I2S1,		RSVD1,		RSVD2,		RSVD3,		0x1028,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1599	PINGROUP(dap1_din_ps2,		I2S1,		RSVD1,		RSVD2,		RSVD3,		0x1030,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1600	PINGROUP(dap1_dout_ps1,		I2S1,		RSVD1,		RSVD2,		RSVD3,		0x1038,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1601	PINGROUP(dap1_sclk_ps0,		I2S1,		RSVD1,		RSVD2,		RSVD3,		0x1040,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1602	PINGROUP(dap3_fs_pt4,		I2S3,		DMIC2,		RSVD2,		RSVD3,		0x1048,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1603	PINGROUP(dap3_din_pt3,		I2S3,		DMIC2,		RSVD2,		RSVD3,		0x1050,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1604	PINGROUP(dap3_dout_pt2,		I2S3,		DMIC1,		RSVD2,		RSVD3,		0x1058,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1605	PINGROUP(dap3_sclk_pt1,		I2S3,		DMIC1,		RSVD2,		RSVD3,		0x1060,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1606	PINGROUP(dap5_fs_pu0,		I2S5,		DMIC4,		DSPK1,		RSVD3,		0x1068,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1607	PINGROUP(dap5_din_pt7,		I2S5,		DMIC4,		DSPK1,		RSVD3,		0x1070,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1608	PINGROUP(dap5_dout_pt6,		I2S5,		DSPK0,		RSVD2,		RSVD3,		0x1078,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1609	PINGROUP(dap5_sclk_pt5,		I2S5,		DSPK0,		RSVD2,		RSVD3,		0x1080,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),1610	PINGROUP(dap6_fs_pa3,		I2S6,		IQC1,		RSVD2,		RSVD3,		0x2000,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),1611	PINGROUP(dap6_din_pa2,		I2S6,		IQC1,		RSVD2,		RSVD3,		0x2008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),1612	PINGROUP(dap6_dout_pa1,		I2S6,		IQC1,		RSVD2,		RSVD3,		0x2010,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),1613	PINGROUP(dap6_sclk_pa0,		I2S6,		IQC1,		RSVD2,		RSVD3,		0x2018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),1614	PINGROUP(dap4_fs_pa7,		I2S4,		IQC2,		RSVD2,		RSVD3,		0x2020,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),1615	PINGROUP(dap4_din_pa6,		I2S4,		IQC2,		RSVD2,		RSVD3,		0x2028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),1616	PINGROUP(dap4_dout_pa5,		I2S4,		IQC2,		RSVD2,		RSVD3,		0x2030,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),1617	PINGROUP(dap4_sclk_pa4,		I2S4,		IQC2,		RSVD2,		RSVD3,		0x2038,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),1618	PINGROUP(extperiph2_clk_pp1,	EXTPERIPH2,	RSVD1,		RSVD2,		RSVD3,		0x0000,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1619	PINGROUP(extperiph1_clk_pp0,	EXTPERIPH1,	RSVD1,		RSVD2,		RSVD3,		0x0008,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1620	PINGROUP(cam_i2c_sda_pp3,	I2C3,		RSVD1,		RSVD2,		RSVD3,		0x0010,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1621	PINGROUP(cam_i2c_scl_pp2,	I2C3,		RSVD1,		RSVD2,		RSVD3,		0x0018,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1622	PINGROUP(soc_gpio40_pq4,	VGP1,		SLVS,		RSVD2,		RSVD3,		0x0020,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1623	PINGROUP(soc_gpio41_pq5,	VGP2,		EXTPERIPH3,	RSVD2,		RSVD3,		0x0028,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1624	PINGROUP(soc_gpio42_pq6,	VGP3,		EXTPERIPH4,	RSVD2,		RSVD3,		0x0030,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1625	PINGROUP(soc_gpio43_pq7,	VGP4,		SLVS,		RSVD2,		RSVD3,		0x0038,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1626	PINGROUP(soc_gpio44_pr0,	VGP5,		GP,		RSVD2,		RSVD3,		0x0040,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1627	PINGROUP(soc_gpio45_pr1,	VGP6,		RSVD1,		RSVD2,		RSVD3,		0x0048,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1628	PINGROUP(soc_gpio20_pq0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x0050,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1629	PINGROUP(soc_gpio21_pq1,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x0058,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1630	PINGROUP(soc_gpio22_pq2,	RSVD0,		NV,		RSVD2,		RSVD3,		0x0060,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1631	PINGROUP(soc_gpio23_pq3,	RSVD0,		WDT,		RSVD2,		RSVD3,		0x0068,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1632	PINGROUP(soc_gpio04_pp4,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x0070,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1633	PINGROUP(soc_gpio05_pp5,	RSVD0,		IGPU,		RSVD2,		RSVD3,		0x0078,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1634	PINGROUP(soc_gpio06_pp6,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x0080,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1635	PINGROUP(soc_gpio07_pp7,	RSVD0,		SATA,		SOC,		RSVD3,		0x0088,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1636	PINGROUP(uart1_cts_pr5,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x0090,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1637	PINGROUP(uart1_rts_pr4,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x0098,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1638	PINGROUP(uart1_rx_pr3,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x00a0,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1639	PINGROUP(uart1_tx_pr2,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x00a8,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),1640	PINGROUP(dap2_din_pi1,		I2S2,		RSVD1,		RSVD2,		RSVD3,		0x4000,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1641	PINGROUP(dap2_dout_pi0,		I2S2,		RSVD1,		RSVD2,		RSVD3,		0x4008,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1642	PINGROUP(dap2_fs_pi2,		I2S2,		RSVD1,		RSVD2,		RSVD3,		0x4010,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1643	PINGROUP(dap2_sclk_ph7,		I2S2,		RSVD1,		RSVD2,		RSVD3,		0x4018,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1644	PINGROUP(uart4_cts_ph6,		UARTD,		RSVD1,		RSVD2,		RSVD3,		0x4020,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1645	PINGROUP(uart4_rts_ph5,		UARTD,		RSVD1,		RSVD2,		RSVD3,		0x4028,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1646	PINGROUP(uart4_rx_ph4,		UARTD,		RSVD1,		RSVD2,		RSVD3,		0x4030,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1647	PINGROUP(uart4_tx_ph3,		UARTD,		RSVD1,		RSVD2,		RSVD3,		0x4038,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1648	PINGROUP(soc_gpio03_pg3,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4040,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1649	PINGROUP(soc_gpio02_pg2,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4048,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1650	PINGROUP(soc_gpio01_pg1,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4050,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1651	PINGROUP(soc_gpio00_pg0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4058,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1652	PINGROUP(gen1_i2c_scl_pi3,	I2C1,		RSVD1,		RSVD2,		RSVD3,		0x4060,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1653	PINGROUP(gen1_i2c_sda_pi4,	I2C1,		RSVD1,		RSVD2,		RSVD3,		0x4068,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1654	PINGROUP(soc_gpio08_pg4,	RSVD0,		CCLA,		RSVD2,		RSVD3,		0x4070,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1655	PINGROUP(soc_gpio09_pg5,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4078,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1656	PINGROUP(soc_gpio10_pg6,	GP,		RSVD1,		RSVD2,		RSVD3,		0x4080,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1657	PINGROUP(soc_gpio11_pg7,	RSVD0,		SDMMC1,		RSVD2,		RSVD3,		0x4088,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1658	PINGROUP(soc_gpio12_ph0,	RSVD0,		GP,		RSVD2,		RSVD3,		0x4090,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1659	PINGROUP(soc_gpio13_ph1,	RSVD0,		GP,		RSVD2,		RSVD3,		0x4098,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1660	PINGROUP(soc_gpio14_ph2,	RSVD0,		SDMMC1,		RSVD2,		RSVD3,		0x40a0,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),1661	PINGROUP(directdc1_out7_pw1,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),1662	PINGROUP(directdc1_out6_pw0,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5010,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),1663	PINGROUP(directdc1_out5_pv7,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),1664	PINGROUP(directdc1_out4_pv6,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5020,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),1665	PINGROUP(directdc1_out3_pv5,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),1666	PINGROUP(directdc1_out2_pv4,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5030,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),1667	PINGROUP(directdc1_out1_pv3,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5038,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),1668	PINGROUP(directdc1_out0_pv2,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5040,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),1669	PINGROUP(directdc1_in_pv1,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5048,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),1670	PINGROUP(directdc1_clk_pv0,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5050,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),1671	PINGROUP(directdc_comp,		DIRECTDC,	RSVD1,		RSVD2,		RSVD3,		0x5058,		0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	Y,	"vddio_debug"),1672	PINGROUP(soc_gpio50_pm5,	RSVD0,		DCA,		RSVD2,		RSVD3,		0x10000,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1673	PINGROUP(soc_gpio51_pm6,	RSVD0,		DCA,		RSVD2,		RSVD3,		0x10008,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1674	PINGROUP(soc_gpio52_pm7,	RSVD0,		DCB,		DGPU,		RSVD3,		0x10010,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1675	PINGROUP(soc_gpio53_pn0,	RSVD0,		DCB,		RSVD2,		RSVD3,		0x10018,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1676	PINGROUP(soc_gpio54_pn1,	RSVD0,		SDMMC3,		GP,		RSVD3,		0x10020,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1677	PINGROUP(soc_gpio55_pn2,	RSVD0,		SDMMC3,		RSVD2,		RSVD3,		0x10028,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1678	PINGROUP(dp_aux_ch0_hpd_pm0,	DP,		RSVD1,		RSVD2,		RSVD3,		0x10030,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1679	PINGROUP(dp_aux_ch1_hpd_pm1,	DP,		RSVD1,		RSVD2,		RSVD3,		0x10038,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1680	PINGROUP(dp_aux_ch2_hpd_pm2,	DP,		DISPLAYA,	RSVD2,		RSVD3,		0x10040,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1681	PINGROUP(dp_aux_ch3_hpd_pm3,	DP,		DISPLAYB,	RSVD2,		RSVD3,		0x10048,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1682	PINGROUP(hdmi_cec_pm4,		HDMI,		RSVD1,		RSVD2,		RSVD3,		0x10050,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),1683	PINGROUP(eqos_td3_pe4,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15000,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1684	PINGROUP(eqos_td2_pe3,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15008,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1685	PINGROUP(eqos_td1_pe2,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15010,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1686	PINGROUP(eqos_td0_pe1,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15018,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1687	PINGROUP(eqos_rd3_pf1,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15020,	0,	Y,	-1,	5,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1688	PINGROUP(eqos_rd2_pf0,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15028,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1689	PINGROUP(eqos_rd1_pe7,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15030,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1690	PINGROUP(eqos_sma_mdio_pf4,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15038,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1691	PINGROUP(eqos_rd0_pe6,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15040,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1692	PINGROUP(eqos_sma_mdc_pf5,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15048,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1693	PINGROUP(eqos_comp,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15050,	0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	Y,	"vddio_eqos"),1694	PINGROUP(eqos_txc_pe0,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15058,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1695	PINGROUP(eqos_rxc_pf3,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15060,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1696	PINGROUP(eqos_tx_ctl_pe5,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15068,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1697	PINGROUP(eqos_rx_ctl_pf2,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15070,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),1698	PINGROUP(pex_l2_clkreq_n_pk4,	PE2,		RSVD1,		RSVD2,		RSVD3,		0x7000,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1699	PINGROUP(pex_wake_n_pl2,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x7008,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1700	PINGROUP(pex_l1_clkreq_n_pk2,	PE1,		RSVD1,		RSVD2,		RSVD3,		0x7010,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1701	PINGROUP(pex_l1_rst_n_pk3,	PE1,		RSVD1,		RSVD2,		RSVD3,		0x7018,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1702	PINGROUP(pex_l0_clkreq_n_pk0,	PE0,		RSVD1,		RSVD2,		RSVD3,		0x7020,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1703	PINGROUP(pex_l0_rst_n_pk1,	PE0,		RSVD1,		RSVD2,		RSVD3,		0x7028,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1704	PINGROUP(pex_l2_rst_n_pk5,	PE2,		RSVD1,		RSVD2,		RSVD3,		0x7030,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1705	PINGROUP(pex_l3_clkreq_n_pk6,	PE3,		RSVD1,		RSVD2,		RSVD3,		0x7038,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1706	PINGROUP(pex_l3_rst_n_pk7,	PE3,		RSVD1,		RSVD2,		RSVD3,		0x7040,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1707	PINGROUP(pex_l4_clkreq_n_pl0,	PE4,		RSVD1,		RSVD2,		RSVD3,		0x7048,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1708	PINGROUP(pex_l4_rst_n_pl1,	PE4,		RSVD1,		RSVD2,		RSVD3,		0x7050,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1709	PINGROUP(sata_dev_slp_pl3,	SATA,		RSVD1,		RSVD2,		RSVD3,		0x7058,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),1710	PINGROUP(pex_l5_clkreq_n_pgg0,	PE5,		RSVD1,		RSVD2,		RSVD3,		0x14000,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl_2"),1711	PINGROUP(pex_l5_rst_n_pgg1,	PE5,		RSVD1,		RSVD2,		RSVD3,		0x14008,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl_2"),1712	PINGROUP(cpu_pwr_req_1_pb1,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x16000,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pwr_ctl"),1713	PINGROUP(cpu_pwr_req_0_pb0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x16008,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pwr_ctl"),1714	PINGROUP(qspi0_io3_pc5,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB000,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1715	PINGROUP(qspi0_io2_pc4,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1716	PINGROUP(qspi0_io1_pc3,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB010,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1717	PINGROUP(qspi0_io0_pc2,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1718	PINGROUP(qspi0_sck_pc0,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB020,		0,	Y,	-1,	5,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1719	PINGROUP(qspi0_cs_n_pc1,	QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1720	PINGROUP(qspi1_io3_pd3,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB030,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1721	PINGROUP(qspi1_io2_pd2,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB038,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1722	PINGROUP(qspi1_io1_pd1,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB040,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1723	PINGROUP(qspi1_io0_pd0,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB048,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1724	PINGROUP(qspi1_sck_pc6,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB050,		0,	Y,	-1,	5,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1725	PINGROUP(qspi1_cs_n_pc7,	QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB058,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),1726	PINGROUP(qspi_comp,		QSPI,		RSVD1,		RSVD2,		RSVD3,		0xB060,		0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	Y,	"vddio_qspi"),1727	PINGROUP(sdmmc1_clk_pj0,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8000,		0,	Y,	-1,	5,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),1728	PINGROUP(sdmmc1_cmd_pj1,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),1729	PINGROUP(sdmmc1_comp,		SDMMC1,		RSVD1,		RSVD2,		RSVD3,		0x8010,		0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	N,	-1,	-1,	N,	"vddio_sdmmc1_hv"),1730	PINGROUP(sdmmc1_dat3_pj5,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),1731	PINGROUP(sdmmc1_dat2_pj4,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8020,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),1732	PINGROUP(sdmmc1_dat1_pj3,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),1733	PINGROUP(sdmmc1_dat0_pj2,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8030,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),1734	PINGROUP(sdmmc3_dat3_po5,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA000,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),1735	PINGROUP(sdmmc3_dat2_po4,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),1736	PINGROUP(sdmmc3_dat1_po3,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA010,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),1737	PINGROUP(sdmmc3_dat0_po2,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),1738	PINGROUP(sdmmc3_comp,		SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA020,		0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	N,	-1,	-1,	N,	"vddio_sdmmc3_hv"),1739	PINGROUP(sdmmc3_cmd_po1,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),1740	PINGROUP(sdmmc3_clk_po0,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA030,		0,	Y,	-1,	5,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),1741	PINGROUP(sdmmc4_clk,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6008,		0,	Y,	-1,	5,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),1742	PINGROUP(sdmmc4_cmd,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6010,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),1743	PINGROUP(sdmmc4_dqs,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6018,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	N,	-1,	-1,	N,	"vddio_sdmmc4"),1744	PINGROUP(sdmmc4_dat7,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6020,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),1745	PINGROUP(sdmmc4_dat6,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6028,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),1746	PINGROUP(sdmmc4_dat5,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6030,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),1747	PINGROUP(sdmmc4_dat4,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6038,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),1748	PINGROUP(sdmmc4_dat3,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6040,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),1749	PINGROUP(sdmmc4_dat2,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6048,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),1750	PINGROUP(sdmmc4_dat1,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6050,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),1751	PINGROUP(sdmmc4_dat0,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6058,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),1752	PINGROUP(gpu_pwr_req_px0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0xD000,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1753	PINGROUP(spi3_miso_py1,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD008,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1754	PINGROUP(spi1_cs0_pz6,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD010,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1755	PINGROUP(spi3_cs0_py3,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD018,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1756	PINGROUP(spi1_miso_pz4,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD020,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1757	PINGROUP(spi3_cs1_py4,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD028,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1758	PINGROUP(gp_pwm3_px3,		GP,		RSVD1,		RSVD2,		RSVD3,		0xD030,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1759	PINGROUP(gp_pwm2_px2,		GP,		RSVD1,		RSVD2,		RSVD3,		0xD038,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1760	PINGROUP(spi1_sck_pz3,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD040,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1761	PINGROUP(spi3_sck_py0,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD048,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1762	PINGROUP(spi1_cs1_pz7,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD050,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1763	PINGROUP(spi1_mosi_pz5,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD058,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1764	PINGROUP(spi3_mosi_py2,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD060,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1765	PINGROUP(cv_pwr_req_px1,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0xD068,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1766	PINGROUP(uart2_tx_px4,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD070,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1767	PINGROUP(uart2_rx_px5,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD078,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1768	PINGROUP(uart2_rts_px6,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD080,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1769	PINGROUP(uart2_cts_px7,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD088,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1770	PINGROUP(uart5_rx_py6,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD090,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1771	PINGROUP(uart5_tx_py5,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD098,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1772	PINGROUP(uart5_rts_py7,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD0a0,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1773	PINGROUP(uart5_cts_pz0,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD0a8,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1774	PINGROUP(usb_vbus_en0_pz1,	USB,		RSVD1,		RSVD2,		RSVD3,		0xD0b0,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1775	PINGROUP(usb_vbus_en1_pz2,	USB,		RSVD1,		RSVD2,		RSVD3,		0xD0b8,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),1776	PINGROUP(ufs0_rst_pff1,		UFS0,		RSVD1,		RSVD2,		RSVD3,		0x11000,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_ufs"),1777	PINGROUP(ufs0_ref_clk_pff0,	UFS0,		RSVD1,		RSVD2,		RSVD3,		0x11008,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_ufs"),1778};1779 1780static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {1781	.pins = tegra194_pins,1782	.npins = ARRAY_SIZE(tegra194_pins),1783	.functions = tegra194_functions,1784	.nfunctions = ARRAY_SIZE(tegra194_functions),1785	.groups = tegra194_groups,1786	.ngroups = ARRAY_SIZE(tegra194_groups),1787	.hsm_in_mux = true,1788	.schmitt_in_mux = true,1789	.drvtype_in_mux = true,1790	.sfsel_in_mux = true,1791};1792 1793static const struct pinctrl_pin_desc tegra194_aon_pins[] = {1794	PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"),1795	PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"),1796	PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"),1797	PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"),1798	PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"),1799	PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"),1800	PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"),1801	PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"),1802	PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"),1803	PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"),1804	PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"),1805	PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"),1806	PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),1807	PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),1808	PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),1809	PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),1810	PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"),1811	PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),1812	PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),1813	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),1814	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),1815	PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),1816	PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),1817	PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"),1818	PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"),1819	PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"),1820	PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"),1821	PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"),1822	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"),1823	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"),1824	PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),1825	PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"),1826	PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"),1827	PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),1828	PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),1829};1830 1831static const struct tegra_pingroup tegra194_aon_groups[] = {1832	PINGROUP(shutdown_n,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1000,		0,	Y,	5,	-1,	6,	8,	-1,	-1,	-1,	12,	N,	-1,	-1,	N,	"vddio_sys"),1833	PINGROUP(pmu_int_n,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1008,		0,	Y,	-1,	-1,	6,	8,	-1,	-1,	-1,	12,	N,	-1,	-1,	N,	"vddio_sys"),1834	PINGROUP(safe_state_pee0,	SCE,		RSVD1,		RSVD2,		RSVD3,		0x1010,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),1835	PINGROUP(vcomp_alert_pee1,	SOC,		RSVD1,		RSVD2,		RSVD3,		0x1018,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),1836	PINGROUP(soc_pwr_req,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1020,		0,	Y,	-1,	-1,	6,	8,	-1,	-1,	-1,	12,	N,	-1,	-1,	N,	"vddio_sys"),1837	PINGROUP(batt_oc_pee3,		SOC,		RSVD1,		RSVD2,		RSVD3,		0x1028,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),1838	PINGROUP(clk_32k_in,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1030,		0,	Y,	-1,	-1,	-1,	8,	-1,	-1,	-1,	12,	N,	-1,	-1,	N,	"vddio_sys"),1839	PINGROUP(power_on_pee4,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1038,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),1840	PINGROUP(pwr_i2c_scl_pee5,	I2C5,		RSVD1,		RSVD2,		RSVD3,		0x1040,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),1841	PINGROUP(pwr_i2c_sda_pee6,	I2C5,		RSVD1,		RSVD2,		RSVD3,		0x1048,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),1842	PINGROUP(ao_retention_n_pee2,	GPIO,		RSVD1,		RSVD2,		RSVD3,		0x1060,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),1843	PINGROUP(touch_clk_pcc4,	GP,		TOUCH,		RSVD2,		RSVD3,		0x2000,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1844	PINGROUP(uart3_rx_pcc6,		UARTC,		RSVD1,		RSVD2,		RSVD3,		0x2008,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1845	PINGROUP(uart3_tx_pcc5,		UARTC,		RSVD1,		RSVD2,		RSVD3,		0x2010,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1846	PINGROUP(gen8_i2c_sda_pdd2,	I2C8,		RSVD1,		RSVD2,		RSVD3,		0x2018,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1847	PINGROUP(gen8_i2c_scl_pdd1,	I2C8,		RSVD1,		RSVD2,		RSVD3,		0x2020,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1848	PINGROUP(spi2_mosi_pcc2,	SPI2,		UARTG,		RSVD2,		RSVD3,		0x2028,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1849	PINGROUP(gen2_i2c_scl_pcc7,	I2C2,		RSVD1,		RSVD2,		RSVD3,		0x2030,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1850	PINGROUP(spi2_cs0_pcc3,		SPI2,		UARTG,		RSVD2,		RSVD3,		0x2038,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1851	PINGROUP(gen2_i2c_sda_pdd0,	I2C2,		RSVD1,		RSVD2,		RSVD3,		0x2040,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1852	PINGROUP(spi2_sck_pcc0,		SPI2,		UARTG,		RSVD2,		RSVD3,		0x2048,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1853	PINGROUP(spi2_miso_pcc1,	SPI2,		UARTG,		RSVD2,		RSVD3,		0x2050,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),1854	PINGROUP(can1_dout_paa0,	CAN1,		RSVD1,		RSVD2,		RSVD3,		0x3000,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1855	PINGROUP(can1_din_paa1,		CAN1,		RSVD1,		RSVD2,		RSVD3,		0x3008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1856	PINGROUP(can0_dout_paa2,	CAN0,		RSVD1,		RSVD2,		RSVD3,		0x3010,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1857	PINGROUP(can0_din_paa3,		CAN0,		RSVD1,		RSVD2,		RSVD3,		0x3018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1858	PINGROUP(can0_stb_paa4,		RSVD0,		WDT,		RSVD2,		RSVD3,		0x3020,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1859	PINGROUP(can0_en_paa5,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1860	PINGROUP(can0_wake_paa6,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3030,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1861	PINGROUP(can0_err_paa7,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3038,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1862	PINGROUP(can1_stb_pbb0,		RSVD0,		DMIC3,		DMIC5,		RSVD3,		0x3040,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1863	PINGROUP(can1_en_pbb1,		RSVD0,		DMIC3,		DMIC5,		RSVD3,		0x3048,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1864	PINGROUP(can1_wake_pbb2,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3050,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1865	PINGROUP(can1_err_pbb3,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3058,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),1866};1867 1868static const struct tegra_pinctrl_soc_data tegra194_pinctrl_aon = {1869	.pins = tegra194_aon_pins,1870	.npins = ARRAY_SIZE(tegra194_aon_pins),1871	.functions = tegra194_functions,1872	.nfunctions = ARRAY_SIZE(tegra194_functions),1873	.groups = tegra194_aon_groups,1874	.ngroups = ARRAY_SIZE(tegra194_aon_groups),1875	.hsm_in_mux = true,1876	.schmitt_in_mux = true,1877	.drvtype_in_mux = true,1878	.sfsel_in_mux = true,1879};1880 1881static int tegra194_pinctrl_probe(struct platform_device *pdev)1882{1883	const struct tegra_pinctrl_soc_data *soc = of_device_get_match_data(&pdev->dev);1884 1885	return tegra_pinctrl_probe(pdev, soc);1886}1887 1888static const struct of_device_id tegra194_pinctrl_of_match[] = {1889	{ .compatible = "nvidia,tegra194-pinmux", .data = &tegra194_pinctrl },1890	{ .compatible = "nvidia,tegra194-pinmux-aon", .data = &tegra194_pinctrl_aon },1891	{ },1892};1893 1894static struct platform_driver tegra194_pinctrl_driver = {1895	.driver = {1896		.name = "tegra194-pinctrl",1897		.of_match_table = tegra194_pinctrl_of_match,1898	},1899	.probe = tegra194_pinctrl_probe,1900};1901 1902static int __init tegra194_pinctrl_init(void)1903{1904	return platform_driver_register(&tegra194_pinctrl_driver);1905}1906arch_initcall(tegra194_pinctrl_init);1907