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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Pinctrl data for the NVIDIA Tegra234 pinmux4 *5 * Copyright (c) 2021-2023, NVIDIA CORPORATION.  All rights reserved.6 */7 8#include <linux/mod_devicetable.h>9#include <linux/module.h>10#include <linux/platform_device.h>11#include <linux/property.h>12 13#include <linux/pinctrl/pinctrl.h>14#include <linux/pinctrl/pinmux.h>15 16#include "pinctrl-tegra.h"17 18/* Define unique ID for each pins */19enum {20	TEGRA_PIN_DAP6_SCLK_PA0,21	TEGRA_PIN_DAP6_DOUT_PA1,22	TEGRA_PIN_DAP6_DIN_PA2,23	TEGRA_PIN_DAP6_FS_PA3,24	TEGRA_PIN_DAP4_SCLK_PA4,25	TEGRA_PIN_DAP4_DOUT_PA5,26	TEGRA_PIN_DAP4_DIN_PA6,27	TEGRA_PIN_DAP4_FS_PA7,28	TEGRA_PIN_SOC_GPIO08_PB0,29	TEGRA_PIN_QSPI0_SCK_PC0,30	TEGRA_PIN_QSPI0_CS_N_PC1,31	TEGRA_PIN_QSPI0_IO0_PC2,32	TEGRA_PIN_QSPI0_IO1_PC3,33	TEGRA_PIN_QSPI0_IO2_PC4,34	TEGRA_PIN_QSPI0_IO3_PC5,35	TEGRA_PIN_QSPI1_SCK_PC6,36	TEGRA_PIN_QSPI1_CS_N_PC7,37	TEGRA_PIN_QSPI1_IO0_PD0,38	TEGRA_PIN_QSPI1_IO1_PD1,39	TEGRA_PIN_QSPI1_IO2_PD2,40	TEGRA_PIN_QSPI1_IO3_PD3,41	TEGRA_PIN_EQOS_TXC_PE0,42	TEGRA_PIN_EQOS_TD0_PE1,43	TEGRA_PIN_EQOS_TD1_PE2,44	TEGRA_PIN_EQOS_TD2_PE3,45	TEGRA_PIN_EQOS_TD3_PE4,46	TEGRA_PIN_EQOS_TX_CTL_PE5,47	TEGRA_PIN_EQOS_RD0_PE6,48	TEGRA_PIN_EQOS_RD1_PE7,49	TEGRA_PIN_EQOS_RD2_PF0,50	TEGRA_PIN_EQOS_RD3_PF1,51	TEGRA_PIN_EQOS_RX_CTL_PF2,52	TEGRA_PIN_EQOS_RXC_PF3,53	TEGRA_PIN_EQOS_SMA_MDIO_PF4,54	TEGRA_PIN_EQOS_SMA_MDC_PF5,55	TEGRA_PIN_SOC_GPIO13_PG0,56	TEGRA_PIN_SOC_GPIO14_PG1,57	TEGRA_PIN_SOC_GPIO15_PG2,58	TEGRA_PIN_SOC_GPIO16_PG3,59	TEGRA_PIN_SOC_GPIO17_PG4,60	TEGRA_PIN_SOC_GPIO18_PG5,61	TEGRA_PIN_SOC_GPIO19_PG6,62	TEGRA_PIN_SOC_GPIO20_PG7,63	TEGRA_PIN_SOC_GPIO21_PH0,64	TEGRA_PIN_SOC_GPIO22_PH1,65	TEGRA_PIN_SOC_GPIO06_PH2,66	TEGRA_PIN_UART4_TX_PH3,67	TEGRA_PIN_UART4_RX_PH4,68	TEGRA_PIN_UART4_RTS_PH5,69	TEGRA_PIN_UART4_CTS_PH6,70	TEGRA_PIN_SOC_GPIO41_PH7,71	TEGRA_PIN_SOC_GPIO42_PI0,72	TEGRA_PIN_SOC_GPIO43_PI1,73	TEGRA_PIN_SOC_GPIO44_PI2,74	TEGRA_PIN_GEN1_I2C_SCL_PI3,75	TEGRA_PIN_GEN1_I2C_SDA_PI4,76	TEGRA_PIN_CPU_PWR_REQ_PI5,77	TEGRA_PIN_SOC_GPIO07_PI6,78	TEGRA_PIN_SDMMC1_CLK_PJ0,79	TEGRA_PIN_SDMMC1_CMD_PJ1,80	TEGRA_PIN_SDMMC1_DAT0_PJ2,81	TEGRA_PIN_SDMMC1_DAT1_PJ3,82	TEGRA_PIN_SDMMC1_DAT2_PJ4,83	TEGRA_PIN_SDMMC1_DAT3_PJ5,84	TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,85	TEGRA_PIN_PEX_L0_RST_N_PK1,86	TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,87	TEGRA_PIN_PEX_L1_RST_N_PK3,88	TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,89	TEGRA_PIN_PEX_L2_RST_N_PK5,90	TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,91	TEGRA_PIN_PEX_L3_RST_N_PK7,92	TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,93	TEGRA_PIN_PEX_L4_RST_N_PL1,94	TEGRA_PIN_PEX_WAKE_N_PL2,95	TEGRA_PIN_SOC_GPIO34_PL3,96	TEGRA_PIN_DP_AUX_CH0_HPD_PM0,97	TEGRA_PIN_DP_AUX_CH1_HPD_PM1,98	TEGRA_PIN_DP_AUX_CH2_HPD_PM2,99	TEGRA_PIN_DP_AUX_CH3_HPD_PM3,100	TEGRA_PIN_SOC_GPIO55_PM4,101	TEGRA_PIN_SOC_GPIO36_PM5,102	TEGRA_PIN_SOC_GPIO53_PM6,103	TEGRA_PIN_SOC_GPIO38_PM7,104	TEGRA_PIN_DP_AUX_CH3_N_PN0,105	TEGRA_PIN_SOC_GPIO39_PN1,106	TEGRA_PIN_SOC_GPIO40_PN2,107	TEGRA_PIN_DP_AUX_CH1_P_PN3,108	TEGRA_PIN_DP_AUX_CH1_N_PN4,109	TEGRA_PIN_DP_AUX_CH2_P_PN5,110	TEGRA_PIN_DP_AUX_CH2_N_PN6,111	TEGRA_PIN_DP_AUX_CH3_P_PN7,112	TEGRA_PIN_EXTPERIPH1_CLK_PP0,113	TEGRA_PIN_EXTPERIPH2_CLK_PP1,114	TEGRA_PIN_CAM_I2C_SCL_PP2,115	TEGRA_PIN_CAM_I2C_SDA_PP3,116	TEGRA_PIN_SOC_GPIO23_PP4,117	TEGRA_PIN_SOC_GPIO24_PP5,118	TEGRA_PIN_SOC_GPIO25_PP6,119	TEGRA_PIN_PWR_I2C_SCL_PP7,120	TEGRA_PIN_PWR_I2C_SDA_PQ0,121	TEGRA_PIN_SOC_GPIO28_PQ1,122	TEGRA_PIN_SOC_GPIO29_PQ2,123	TEGRA_PIN_SOC_GPIO30_PQ3,124	TEGRA_PIN_SOC_GPIO31_PQ4,125	TEGRA_PIN_SOC_GPIO32_PQ5,126	TEGRA_PIN_SOC_GPIO33_PQ6,127	TEGRA_PIN_SOC_GPIO35_PQ7,128	TEGRA_PIN_SOC_GPIO37_PR0,129	TEGRA_PIN_SOC_GPIO56_PR1,130	TEGRA_PIN_UART1_TX_PR2,131	TEGRA_PIN_UART1_RX_PR3,132	TEGRA_PIN_UART1_RTS_PR4,133	TEGRA_PIN_UART1_CTS_PR5,134	TEGRA_PIN_GPU_PWR_REQ_PX0,135	TEGRA_PIN_CV_PWR_REQ_PX1,136	TEGRA_PIN_GP_PWM2_PX2,137	TEGRA_PIN_GP_PWM3_PX3,138	TEGRA_PIN_UART2_TX_PX4,139	TEGRA_PIN_UART2_RX_PX5,140	TEGRA_PIN_UART2_RTS_PX6,141	TEGRA_PIN_UART2_CTS_PX7,142	TEGRA_PIN_SPI3_SCK_PY0,143	TEGRA_PIN_SPI3_MISO_PY1,144	TEGRA_PIN_SPI3_MOSI_PY2,145	TEGRA_PIN_SPI3_CS0_PY3,146	TEGRA_PIN_SPI3_CS1_PY4,147	TEGRA_PIN_UART5_TX_PY5,148	TEGRA_PIN_UART5_RX_PY6,149	TEGRA_PIN_UART5_RTS_PY7,150	TEGRA_PIN_UART5_CTS_PZ0,151	TEGRA_PIN_USB_VBUS_EN0_PZ1,152	TEGRA_PIN_USB_VBUS_EN1_PZ2,153	TEGRA_PIN_SPI1_SCK_PZ3,154	TEGRA_PIN_SPI1_MISO_PZ4,155	TEGRA_PIN_SPI1_MOSI_PZ5,156	TEGRA_PIN_SPI1_CS0_PZ6,157	TEGRA_PIN_SPI1_CS1_PZ7,158	TEGRA_PIN_SPI5_SCK_PAC0,159	TEGRA_PIN_SPI5_MISO_PAC1,160	TEGRA_PIN_SPI5_MOSI_PAC2,161	TEGRA_PIN_SPI5_CS0_PAC3,162	TEGRA_PIN_SOC_GPIO57_PAC4,163	TEGRA_PIN_SOC_GPIO58_PAC5,164	TEGRA_PIN_SOC_GPIO59_PAC6,165	TEGRA_PIN_SOC_GPIO60_PAC7,166	TEGRA_PIN_SOC_GPIO45_PAD0,167	TEGRA_PIN_SOC_GPIO46_PAD1,168	TEGRA_PIN_SOC_GPIO47_PAD2,169	TEGRA_PIN_SOC_GPIO48_PAD3,170	TEGRA_PIN_UFS0_REF_CLK_PAE0,171	TEGRA_PIN_UFS0_RST_N_PAE1,172	TEGRA_PIN_PEX_L5_CLKREQ_N_PAF0,173	TEGRA_PIN_PEX_L5_RST_N_PAF1,174	TEGRA_PIN_PEX_L6_CLKREQ_N_PAF2,175	TEGRA_PIN_PEX_L6_RST_N_PAF3,176	TEGRA_PIN_PEX_L7_CLKREQ_N_PAG0,177	TEGRA_PIN_PEX_L7_RST_N_PAG1,178	TEGRA_PIN_PEX_L8_CLKREQ_N_PAG2,179	TEGRA_PIN_PEX_L8_RST_N_PAG3,180	TEGRA_PIN_PEX_L9_CLKREQ_N_PAG4,181	TEGRA_PIN_PEX_L9_RST_N_PAG5,182	TEGRA_PIN_PEX_L10_CLKREQ_N_PAG6,183	TEGRA_PIN_PEX_L10_RST_N_PAG7,184	TEGRA_PIN_EQOS_COMP,185	TEGRA_PIN_QSPI_COMP,186	TEGRA_PIN_SDMMC1_COMP,187};188 189enum {190	TEGRA_PIN_CAN0_DOUT_PAA0,191	TEGRA_PIN_CAN0_DIN_PAA1,192	TEGRA_PIN_CAN1_DOUT_PAA2,193	TEGRA_PIN_CAN1_DIN_PAA3,194	TEGRA_PIN_CAN0_STB_PAA4,195	TEGRA_PIN_CAN0_EN_PAA5,196	TEGRA_PIN_SOC_GPIO49_PAA6,197	TEGRA_PIN_CAN0_ERR_PAA7,198	TEGRA_PIN_CAN1_STB_PBB0,199	TEGRA_PIN_CAN1_EN_PBB1,200	TEGRA_PIN_SOC_GPIO50_PBB2,201	TEGRA_PIN_CAN1_ERR_PBB3,202	TEGRA_PIN_SPI2_SCK_PCC0,203	TEGRA_PIN_SPI2_MISO_PCC1,204	TEGRA_PIN_SPI2_MOSI_PCC2,205	TEGRA_PIN_SPI2_CS0_PCC3,206	TEGRA_PIN_TOUCH_CLK_PCC4,207	TEGRA_PIN_UART3_TX_PCC5,208	TEGRA_PIN_UART3_RX_PCC6,209	TEGRA_PIN_GEN2_I2C_SCL_PCC7,210	TEGRA_PIN_GEN2_I2C_SDA_PDD0,211	TEGRA_PIN_GEN8_I2C_SCL_PDD1,212	TEGRA_PIN_GEN8_I2C_SDA_PDD2,213	TEGRA_PIN_SCE_ERROR_PEE0,214	TEGRA_PIN_VCOMP_ALERT_PEE1,215	TEGRA_PIN_AO_RETENTION_N_PEE2,216	TEGRA_PIN_BATT_OC_PEE3,217	TEGRA_PIN_POWER_ON_PEE4,218	TEGRA_PIN_SOC_GPIO26_PEE5,219	TEGRA_PIN_SOC_GPIO27_PEE6,220	TEGRA_PIN_BOOTV_CTL_N_PEE7,221	TEGRA_PIN_HDMI_CEC_PGG0,222};223 224/* Table for pin descriptor */225static const struct pinctrl_pin_desc tegra234_pins[] = {226	PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PA0, "DAP6_SCLK_PA0"),227	PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PA1, "DAP6_DOUT_PA1"),228	PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PA2, "DAP6_DIN_PA2"),229	PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PA3, "DAP6_FS_PA3"),230	PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PA4, "DAP4_SCLK_PA4"),231	PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PA5, "DAP4_DOUT_PA5"),232	PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PA6, "DAP4_DIN_PA6"),233	PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PA7, "DAP4_FS_PA7"),234	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PB0, "SOC_GPIO08_PB0"),235	PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PC0, "QSPI0_SCK_PC0"),236	PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PC1, "QSPI0_CS_N_PC1"),237	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PC2, "QSPI0_IO0_PC2"),238	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PC3, "QSPI0_IO1_PC3"),239	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PC4, "QSPI0_IO2_PC4"),240	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PC5, "QSPI0_IO3_PC5"),241	PINCTRL_PIN(TEGRA_PIN_QSPI1_SCK_PC6, "QSPI1_SCK_PC6"),242	PINCTRL_PIN(TEGRA_PIN_QSPI1_CS_N_PC7, "QSPI1_CS_N_PC7"),243	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO0_PD0, "QSPI1_IO0_PD0"),244	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO1_PD1, "QSPI1_IO1_PD1"),245	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO2_PD2, "QSPI1_IO2_PD2"),246	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO3_PD3, "QSPI1_IO3_PD3"),247	PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"),248	PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"),249	PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"),250	PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"),251	PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"),252	PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"),253	PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"),254	PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"),255	PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"),256	PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"),257	PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"),258	PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"),259	PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDIO_PF4, "EQOS_SMA_MDIO_PF4"),260	PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDC_PF5, "EQOS_SMA_MDC_PF5"),261	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PG0, "SOC_GPIO13_PG0"),262	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PG1, "SOC_GPIO14_PG1"),263	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO15_PG2, "SOC_GPIO15_PG2"),264	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO16_PG3, "SOC_GPIO16_PG3"),265	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO17_PG4, "SOC_GPIO17_PG4"),266	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO18_PG5, "SOC_GPIO18_PG5"),267	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO19_PG6, "SOC_GPIO19_PG6"),268	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PG7, "SOC_GPIO20_PG7"),269	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PH0, "SOC_GPIO21_PH0"),270	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PH1, "SOC_GPIO22_PH1"),271	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PH2, "SOC_GPIO06_PH2"),272	PINCTRL_PIN(TEGRA_PIN_UART4_TX_PH3, "UART4_TX_PH3"),273	PINCTRL_PIN(TEGRA_PIN_UART4_RX_PH4, "UART4_RX_PH4"),274	PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PH5, "UART4_RTS_PH5"),275	PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PH6, "UART4_CTS_PH6"),276	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PH7, "SOC_GPIO41_PH7"),277	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PI0, "SOC_GPIO42_PI0"),278	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PI1, "SOC_GPIO43_PI1"),279	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PI2, "SOC_GPIO44_PI2"),280	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PI3, "GEN1_I2C_SCL_PI3"),281	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PI4, "GEN1_I2C_SDA_PI4"),282	PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PI5, "CPU_PWR_REQ_PI5"),283	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PI6, "SOC_GPIO07_PI6"),284	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PJ0, "SDMMC1_CLK_PJ0"),285	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PJ1, "SDMMC1_CMD_PJ1"),286	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PJ2, "SDMMC1_DAT0_PJ2"),287	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PJ3, "SDMMC1_DAT1_PJ3"),288	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PJ4, "SDMMC1_DAT2_PJ4"),289	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PJ5, "SDMMC1_DAT3_PJ5"),290	PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PK0, "PEX_L0_CLKREQ_N_PK0"),291	PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PK1, "PEX_L0_RST_N_PK1"),292	PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PK2, "PEX_L1_CLKREQ_N_PK2"),293	PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PK3, "PEX_L1_RST_N_PK3"),294	PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PK4, "PEX_L2_CLKREQ_N_PK4"),295	PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PK5, "PEX_L2_RST_N_PK5"),296	PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PK6, "PEX_L3_CLKREQ_N_PK6"),297	PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PK7, "PEX_L3_RST_N_PK7"),298	PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PL0, "PEX_L4_CLKREQ_N_PL0"),299	PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PL1, "PEX_L4_RST_N_PL1"),300	PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PL2, "PEX_WAKE_N_PL2"),301	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO34_PL3, "SOC_GPIO34_PL3"),302	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PM0, "DP_AUX_CH0_HPD_PM0"),303	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PM1, "DP_AUX_CH1_HPD_PM1"),304	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PM2, "DP_AUX_CH2_HPD_PM2"),305	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PM3, "DP_AUX_CH3_HPD_PM3"),306	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PM4, "SOC_GPIO55_PM4"),307	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO36_PM5, "SOC_GPIO36_PM5"),308	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PM6, "SOC_GPIO53_PM6"),309	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO38_PM7, "SOC_GPIO38_PM7"),310	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_N_PN0, "DP_AUX_CH3_N_PN0"),311	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO39_PN1, "SOC_GPIO39_PN1"),312	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PN2, "SOC_GPIO40_PN2"),313	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_P_PN3, "DP_AUX_CH1_P_PN3"),314	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_N_PN4, "DP_AUX_CH1_N_PN4"),315	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_P_PN5, "DP_AUX_CH2_P_PN5"),316	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_N_PN6, "DP_AUX_CH2_N_PN6"),317	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_P_PN7, "DP_AUX_CH3_P_PN7"),318	PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PP0, "EXTPERIPH1_CLK_PP0"),319	PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PP1, "EXTPERIPH2_CLK_PP1"),320	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PP2, "CAM_I2C_SCL_PP2"),321	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PP3, "CAM_I2C_SDA_PP3"),322	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PP4, "SOC_GPIO23_PP4"),323	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PP5, "SOC_GPIO24_PP5"),324	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PP6, "SOC_GPIO25_PP6"),325	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PP7, "PWR_I2C_SCL_PP7"),326	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PQ0, "PWR_I2C_SDA_PQ0"),327	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO28_PQ1, "SOC_GPIO28_PQ1"),328	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PQ2, "SOC_GPIO29_PQ2"),329	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO30_PQ3, "SOC_GPIO30_PQ3"),330	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO31_PQ4, "SOC_GPIO31_PQ4"),331	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PQ5, "SOC_GPIO32_PQ5"),332	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PQ6, "SOC_GPIO33_PQ6"),333	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO35_PQ7, "SOC_GPIO35_PQ7"),334	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO37_PR0, "SOC_GPIO37_PR0"),335	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO56_PR1, "SOC_GPIO56_PR1"),336	PINCTRL_PIN(TEGRA_PIN_UART1_TX_PR2, "UART1_TX_PR2"),337	PINCTRL_PIN(TEGRA_PIN_UART1_RX_PR3, "UART1_RX_PR3"),338	PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PR4, "UART1_RTS_PR4"),339	PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PR5, "UART1_CTS_PR5"),340	PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PX0, "GPU_PWR_REQ_PX0"),341	PINCTRL_PIN(TEGRA_PIN_CV_PWR_REQ_PX1, "CV_PWR_REQ_PX1"),342	PINCTRL_PIN(TEGRA_PIN_GP_PWM2_PX2, "GP_PWM2_PX2"),343	PINCTRL_PIN(TEGRA_PIN_GP_PWM3_PX3, "GP_PWM3_PX3"),344	PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX4, "UART2_TX_PX4"),345	PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX5, "UART2_RX_PX5"),346	PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX6, "UART2_RTS_PX6"),347	PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX7, "UART2_CTS_PX7"),348	PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PY0, "SPI3_SCK_PY0"),349	PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PY1, "SPI3_MISO_PY1"),350	PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PY2, "SPI3_MOSI_PY2"),351	PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PY3, "SPI3_CS0_PY3"),352	PINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PY4, "SPI3_CS1_PY4"),353	PINCTRL_PIN(TEGRA_PIN_UART5_TX_PY5, "UART5_TX_PY5"),354	PINCTRL_PIN(TEGRA_PIN_UART5_RX_PY6, "UART5_RX_PY6"),355	PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PY7, "UART5_RTS_PY7"),356	PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PZ0, "UART5_CTS_PZ0"),357	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PZ1, "USB_VBUS_EN0_PZ1"),358	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PZ2, "USB_VBUS_EN1_PZ2"),359	PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PZ3, "SPI1_SCK_PZ3"),360	PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PZ4, "SPI1_MISO_PZ4"),361	PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"),362	PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"),363	PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"),364	PINCTRL_PIN(TEGRA_PIN_SPI5_SCK_PAC0, "SPI5_SCK_PAC0"),365	PINCTRL_PIN(TEGRA_PIN_SPI5_MISO_PAC1, "SPI5_MISO_PAC1"),366	PINCTRL_PIN(TEGRA_PIN_SPI5_MOSI_PAC2, "SPI5_MOSI_PAC2"),367	PINCTRL_PIN(TEGRA_PIN_SPI5_CS0_PAC3, "SPI5_CS0_PAC3"),368	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO57_PAC4, "SOC_GPIO57_PAC4"),369	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO58_PAC5, "SOC_GPIO58_PAC5"),370	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO59_PAC6, "SOC_GPIO59_PAC6"),371	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO60_PAC7, "SOC_GPIO60_PAC7"),372	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PAD0, "SOC_GPIO45_PAD0"),373	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO46_PAD1, "SOC_GPIO46_PAD1"),374	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO47_PAD2, "SOC_GPIO47_PAD2"),375	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO48_PAD3, "SOC_GPIO48_PAD3"),376	PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PAE0, "UFS0_REF_CLK_PAE0"),377	PINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PAE1, "UFS0_RST_N_PAE1"),378	PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PAF0, "PEX_L5_CLKREQ_N_PAF0"),379	PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PAF1, "PEX_L5_RST_N_PAF1"),380	PINCTRL_PIN(TEGRA_PIN_PEX_L6_CLKREQ_N_PAF2, "PEX_L6_CLKREQ_N_PAF2"),381	PINCTRL_PIN(TEGRA_PIN_PEX_L6_RST_N_PAF3, "PEX_L6_RST_N_PAF3"),382	PINCTRL_PIN(TEGRA_PIN_PEX_L7_CLKREQ_N_PAG0, "PEX_L7_CLKREQ_N_PAG0"),383	PINCTRL_PIN(TEGRA_PIN_PEX_L7_RST_N_PAG1, "PEX_L7_RST_N_PAG1"),384	PINCTRL_PIN(TEGRA_PIN_PEX_L8_CLKREQ_N_PAG2, "PEX_L8_CLKREQ_N_PAG2"),385	PINCTRL_PIN(TEGRA_PIN_PEX_L8_RST_N_PAG3, "PEX_L8_RST_N_PAG3"),386	PINCTRL_PIN(TEGRA_PIN_PEX_L9_CLKREQ_N_PAG4, "PEX_L9_CLKREQ_N_PAG4"),387	PINCTRL_PIN(TEGRA_PIN_PEX_L9_RST_N_PAG5, "PEX_L9_RST_N_PAG5"),388	PINCTRL_PIN(TEGRA_PIN_PEX_L10_CLKREQ_N_PAG6, "PEX_L10_CLKREQ_N_PAG6"),389	PINCTRL_PIN(TEGRA_PIN_PEX_L10_RST_N_PAG7, "PEX_L10_RST_N_PAG7"),390	PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),391	PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),392	PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),393};394 395static const unsigned int dap6_sclk_pa0_pins[] = {396	TEGRA_PIN_DAP6_SCLK_PA0,397};398 399static const unsigned int dap6_dout_pa1_pins[] = {400	TEGRA_PIN_DAP6_DOUT_PA1,401};402 403static const unsigned int dap6_din_pa2_pins[] = {404	TEGRA_PIN_DAP6_DIN_PA2,405};406 407static const unsigned int dap6_fs_pa3_pins[] = {408	TEGRA_PIN_DAP6_FS_PA3,409};410 411static const unsigned int dap4_sclk_pa4_pins[] = {412	TEGRA_PIN_DAP4_SCLK_PA4,413};414 415static const unsigned int dap4_dout_pa5_pins[] = {416	TEGRA_PIN_DAP4_DOUT_PA5,417};418 419static const unsigned int dap4_din_pa6_pins[] = {420	TEGRA_PIN_DAP4_DIN_PA6,421};422 423static const unsigned int dap4_fs_pa7_pins[] = {424	TEGRA_PIN_DAP4_FS_PA7,425};426 427static const unsigned int soc_gpio08_pb0_pins[] = {428	TEGRA_PIN_SOC_GPIO08_PB0,429};430 431static const unsigned int qspi0_sck_pc0_pins[] = {432	TEGRA_PIN_QSPI0_SCK_PC0,433};434 435static const unsigned int qspi0_cs_n_pc1_pins[] = {436	TEGRA_PIN_QSPI0_CS_N_PC1,437};438 439static const unsigned int qspi0_io0_pc2_pins[] = {440	TEGRA_PIN_QSPI0_IO0_PC2,441};442 443static const unsigned int qspi0_io1_pc3_pins[] = {444	TEGRA_PIN_QSPI0_IO1_PC3,445};446 447static const unsigned int qspi0_io2_pc4_pins[] = {448	TEGRA_PIN_QSPI0_IO2_PC4,449};450 451static const unsigned int qspi0_io3_pc5_pins[] = {452	TEGRA_PIN_QSPI0_IO3_PC5,453};454 455static const unsigned int qspi1_sck_pc6_pins[] = {456	TEGRA_PIN_QSPI1_SCK_PC6,457};458 459static const unsigned int qspi1_cs_n_pc7_pins[] = {460	TEGRA_PIN_QSPI1_CS_N_PC7,461};462 463static const unsigned int qspi1_io0_pd0_pins[] = {464	TEGRA_PIN_QSPI1_IO0_PD0,465};466 467static const unsigned int qspi1_io1_pd1_pins[] = {468	TEGRA_PIN_QSPI1_IO1_PD1,469};470 471static const unsigned int qspi1_io2_pd2_pins[] = {472	TEGRA_PIN_QSPI1_IO2_PD2,473};474 475static const unsigned int qspi1_io3_pd3_pins[] = {476	TEGRA_PIN_QSPI1_IO3_PD3,477};478 479static const unsigned int eqos_txc_pe0_pins[] = {480	TEGRA_PIN_EQOS_TXC_PE0,481};482 483static const unsigned int eqos_td0_pe1_pins[] = {484	TEGRA_PIN_EQOS_TD0_PE1,485};486 487static const unsigned int eqos_td1_pe2_pins[] = {488	TEGRA_PIN_EQOS_TD1_PE2,489};490 491static const unsigned int eqos_td2_pe3_pins[] = {492	TEGRA_PIN_EQOS_TD2_PE3,493};494 495static const unsigned int eqos_td3_pe4_pins[] = {496	TEGRA_PIN_EQOS_TD3_PE4,497};498 499static const unsigned int eqos_tx_ctl_pe5_pins[] = {500	TEGRA_PIN_EQOS_TX_CTL_PE5,501};502 503static const unsigned int eqos_rd0_pe6_pins[] = {504	TEGRA_PIN_EQOS_RD0_PE6,505};506 507static const unsigned int eqos_rd1_pe7_pins[] = {508	TEGRA_PIN_EQOS_RD1_PE7,509};510 511static const unsigned int eqos_rd2_pf0_pins[] = {512	TEGRA_PIN_EQOS_RD2_PF0,513};514 515static const unsigned int eqos_rd3_pf1_pins[] = {516	TEGRA_PIN_EQOS_RD3_PF1,517};518 519static const unsigned int eqos_rx_ctl_pf2_pins[] = {520	TEGRA_PIN_EQOS_RX_CTL_PF2,521};522 523static const unsigned int eqos_rxc_pf3_pins[] = {524	TEGRA_PIN_EQOS_RXC_PF3,525};526 527static const unsigned int eqos_sma_mdio_pf4_pins[] = {528	TEGRA_PIN_EQOS_SMA_MDIO_PF4,529};530 531static const unsigned int eqos_sma_mdc_pf5_pins[] = {532	TEGRA_PIN_EQOS_SMA_MDC_PF5,533};534 535static const unsigned int soc_gpio13_pg0_pins[] = {536	TEGRA_PIN_SOC_GPIO13_PG0,537};538 539static const unsigned int soc_gpio14_pg1_pins[] = {540	TEGRA_PIN_SOC_GPIO14_PG1,541};542 543static const unsigned int soc_gpio15_pg2_pins[] = {544	TEGRA_PIN_SOC_GPIO15_PG2,545};546 547static const unsigned int soc_gpio16_pg3_pins[] = {548	TEGRA_PIN_SOC_GPIO16_PG3,549};550 551static const unsigned int soc_gpio17_pg4_pins[] = {552	TEGRA_PIN_SOC_GPIO17_PG4,553};554 555static const unsigned int soc_gpio18_pg5_pins[] = {556	TEGRA_PIN_SOC_GPIO18_PG5,557};558 559static const unsigned int soc_gpio19_pg6_pins[] = {560	TEGRA_PIN_SOC_GPIO19_PG6,561};562 563static const unsigned int soc_gpio20_pg7_pins[] = {564	TEGRA_PIN_SOC_GPIO20_PG7,565};566 567static const unsigned int soc_gpio21_ph0_pins[] = {568	TEGRA_PIN_SOC_GPIO21_PH0,569};570 571static const unsigned int soc_gpio22_ph1_pins[] = {572	TEGRA_PIN_SOC_GPIO22_PH1,573};574 575static const unsigned int soc_gpio06_ph2_pins[] = {576	TEGRA_PIN_SOC_GPIO06_PH2,577};578 579static const unsigned int uart4_tx_ph3_pins[] = {580	TEGRA_PIN_UART4_TX_PH3,581};582 583static const unsigned int uart4_rx_ph4_pins[] = {584	TEGRA_PIN_UART4_RX_PH4,585};586 587static const unsigned int uart4_rts_ph5_pins[] = {588	TEGRA_PIN_UART4_RTS_PH5,589};590 591static const unsigned int uart4_cts_ph6_pins[] = {592	TEGRA_PIN_UART4_CTS_PH6,593};594 595static const unsigned int soc_gpio41_ph7_pins[] = {596	TEGRA_PIN_SOC_GPIO41_PH7,597};598 599static const unsigned int soc_gpio42_pi0_pins[] = {600	TEGRA_PIN_SOC_GPIO42_PI0,601};602 603static const unsigned int soc_gpio43_pi1_pins[] = {604	TEGRA_PIN_SOC_GPIO43_PI1,605};606 607static const unsigned int soc_gpio44_pi2_pins[] = {608	TEGRA_PIN_SOC_GPIO44_PI2,609};610 611static const unsigned int gen1_i2c_scl_pi3_pins[] = {612	TEGRA_PIN_GEN1_I2C_SCL_PI3,613};614 615static const unsigned int gen1_i2c_sda_pi4_pins[] = {616	TEGRA_PIN_GEN1_I2C_SDA_PI4,617};618 619static const unsigned int cpu_pwr_req_pi5_pins[] = {620	TEGRA_PIN_CPU_PWR_REQ_PI5,621};622 623static const unsigned int soc_gpio07_pi6_pins[] = {624	TEGRA_PIN_SOC_GPIO07_PI6,625};626 627static const unsigned int sdmmc1_clk_pj0_pins[] = {628	TEGRA_PIN_SDMMC1_CLK_PJ0,629};630 631static const unsigned int sdmmc1_cmd_pj1_pins[] = {632	TEGRA_PIN_SDMMC1_CMD_PJ1,633};634 635static const unsigned int sdmmc1_dat0_pj2_pins[] = {636	TEGRA_PIN_SDMMC1_DAT0_PJ2,637};638 639static const unsigned int sdmmc1_dat1_pj3_pins[] = {640	TEGRA_PIN_SDMMC1_DAT1_PJ3,641};642 643static const unsigned int sdmmc1_dat2_pj4_pins[] = {644	TEGRA_PIN_SDMMC1_DAT2_PJ4,645};646 647static const unsigned int sdmmc1_dat3_pj5_pins[] = {648	TEGRA_PIN_SDMMC1_DAT3_PJ5,649};650 651static const unsigned int pex_l0_clkreq_n_pk0_pins[] = {652	TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,653};654 655static const unsigned int pex_l0_rst_n_pk1_pins[] = {656	TEGRA_PIN_PEX_L0_RST_N_PK1,657};658 659static const unsigned int pex_l1_clkreq_n_pk2_pins[] = {660	TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,661};662 663static const unsigned int pex_l1_rst_n_pk3_pins[] = {664	TEGRA_PIN_PEX_L1_RST_N_PK3,665};666 667static const unsigned int pex_l2_clkreq_n_pk4_pins[] = {668	TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,669};670 671static const unsigned int pex_l2_rst_n_pk5_pins[] = {672	TEGRA_PIN_PEX_L2_RST_N_PK5,673};674 675static const unsigned int pex_l3_clkreq_n_pk6_pins[] = {676	TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,677};678 679static const unsigned int pex_l3_rst_n_pk7_pins[] = {680	TEGRA_PIN_PEX_L3_RST_N_PK7,681};682 683static const unsigned int pex_l4_clkreq_n_pl0_pins[] = {684	TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,685};686 687static const unsigned int pex_l4_rst_n_pl1_pins[] = {688	TEGRA_PIN_PEX_L4_RST_N_PL1,689};690 691static const unsigned int pex_wake_n_pl2_pins[] = {692	TEGRA_PIN_PEX_WAKE_N_PL2,693};694 695static const unsigned int soc_gpio34_pl3_pins[] = {696	TEGRA_PIN_SOC_GPIO34_PL3,697};698 699static const unsigned int dp_aux_ch0_hpd_pm0_pins[] = {700	TEGRA_PIN_DP_AUX_CH0_HPD_PM0,701};702 703static const unsigned int dp_aux_ch1_hpd_pm1_pins[] = {704	TEGRA_PIN_DP_AUX_CH1_HPD_PM1,705};706 707static const unsigned int dp_aux_ch2_hpd_pm2_pins[] = {708	TEGRA_PIN_DP_AUX_CH2_HPD_PM2,709};710 711static const unsigned int dp_aux_ch3_hpd_pm3_pins[] = {712	TEGRA_PIN_DP_AUX_CH3_HPD_PM3,713};714 715static const unsigned int soc_gpio55_pm4_pins[] = {716	TEGRA_PIN_SOC_GPIO55_PM4,717};718 719static const unsigned int soc_gpio36_pm5_pins[] = {720	TEGRA_PIN_SOC_GPIO36_PM5,721};722 723static const unsigned int soc_gpio53_pm6_pins[] = {724	TEGRA_PIN_SOC_GPIO53_PM6,725};726 727static const unsigned int soc_gpio38_pm7_pins[] = {728	TEGRA_PIN_SOC_GPIO38_PM7,729};730 731static const unsigned int dp_aux_ch3_n_pn0_pins[] = {732	TEGRA_PIN_DP_AUX_CH3_N_PN0,733};734 735static const unsigned int soc_gpio39_pn1_pins[] = {736	TEGRA_PIN_SOC_GPIO39_PN1,737};738 739static const unsigned int soc_gpio40_pn2_pins[] = {740	TEGRA_PIN_SOC_GPIO40_PN2,741};742 743static const unsigned int dp_aux_ch1_p_pn3_pins[] = {744	TEGRA_PIN_DP_AUX_CH1_P_PN3,745};746 747static const unsigned int dp_aux_ch1_n_pn4_pins[] = {748	TEGRA_PIN_DP_AUX_CH1_N_PN4,749};750 751static const unsigned int dp_aux_ch2_p_pn5_pins[] = {752	TEGRA_PIN_DP_AUX_CH2_P_PN5,753};754 755static const unsigned int dp_aux_ch2_n_pn6_pins[] = {756	TEGRA_PIN_DP_AUX_CH2_N_PN6,757};758 759static const unsigned int dp_aux_ch3_p_pn7_pins[] = {760	TEGRA_PIN_DP_AUX_CH3_P_PN7,761};762 763static const unsigned int extperiph1_clk_pp0_pins[] = {764	TEGRA_PIN_EXTPERIPH1_CLK_PP0,765};766 767static const unsigned int extperiph2_clk_pp1_pins[] = {768	TEGRA_PIN_EXTPERIPH2_CLK_PP1,769};770 771static const unsigned int cam_i2c_scl_pp2_pins[] = {772	TEGRA_PIN_CAM_I2C_SCL_PP2,773};774 775static const unsigned int cam_i2c_sda_pp3_pins[] = {776	TEGRA_PIN_CAM_I2C_SDA_PP3,777};778 779static const unsigned int soc_gpio23_pp4_pins[] = {780	TEGRA_PIN_SOC_GPIO23_PP4,781};782 783static const unsigned int soc_gpio24_pp5_pins[] = {784	TEGRA_PIN_SOC_GPIO24_PP5,785};786 787static const unsigned int soc_gpio25_pp6_pins[] = {788	TEGRA_PIN_SOC_GPIO25_PP6,789};790 791static const unsigned int pwr_i2c_scl_pp7_pins[] = {792	TEGRA_PIN_PWR_I2C_SCL_PP7,793};794 795static const unsigned int pwr_i2c_sda_pq0_pins[] = {796	TEGRA_PIN_PWR_I2C_SDA_PQ0,797};798 799static const unsigned int soc_gpio28_pq1_pins[] = {800	TEGRA_PIN_SOC_GPIO28_PQ1,801};802 803static const unsigned int soc_gpio29_pq2_pins[] = {804	TEGRA_PIN_SOC_GPIO29_PQ2,805};806 807static const unsigned int soc_gpio30_pq3_pins[] = {808	TEGRA_PIN_SOC_GPIO30_PQ3,809};810 811static const unsigned int soc_gpio31_pq4_pins[] = {812	TEGRA_PIN_SOC_GPIO31_PQ4,813};814 815static const unsigned int soc_gpio32_pq5_pins[] = {816	TEGRA_PIN_SOC_GPIO32_PQ5,817};818 819static const unsigned int soc_gpio33_pq6_pins[] = {820	TEGRA_PIN_SOC_GPIO33_PQ6,821};822 823static const unsigned int soc_gpio35_pq7_pins[] = {824	TEGRA_PIN_SOC_GPIO35_PQ7,825};826 827static const unsigned int soc_gpio37_pr0_pins[] = {828	TEGRA_PIN_SOC_GPIO37_PR0,829};830 831static const unsigned int soc_gpio56_pr1_pins[] = {832	TEGRA_PIN_SOC_GPIO56_PR1,833};834 835static const unsigned int uart1_tx_pr2_pins[] = {836	TEGRA_PIN_UART1_TX_PR2,837};838 839static const unsigned int uart1_rx_pr3_pins[] = {840	TEGRA_PIN_UART1_RX_PR3,841};842 843static const unsigned int uart1_rts_pr4_pins[] = {844	TEGRA_PIN_UART1_RTS_PR4,845};846 847static const unsigned int uart1_cts_pr5_pins[] = {848	TEGRA_PIN_UART1_CTS_PR5,849};850 851static const unsigned int gpu_pwr_req_px0_pins[] = {852	TEGRA_PIN_GPU_PWR_REQ_PX0,853};854 855static const unsigned int cv_pwr_req_px1_pins[] = {856	TEGRA_PIN_CV_PWR_REQ_PX1,857};858 859static const unsigned int gp_pwm2_px2_pins[] = {860	TEGRA_PIN_GP_PWM2_PX2,861};862 863static const unsigned int gp_pwm3_px3_pins[] = {864	TEGRA_PIN_GP_PWM3_PX3,865};866 867static const unsigned int uart2_tx_px4_pins[] = {868	TEGRA_PIN_UART2_TX_PX4,869};870 871static const unsigned int uart2_rx_px5_pins[] = {872	TEGRA_PIN_UART2_RX_PX5,873};874 875static const unsigned int uart2_rts_px6_pins[] = {876	TEGRA_PIN_UART2_RTS_PX6,877};878 879static const unsigned int uart2_cts_px7_pins[] = {880	TEGRA_PIN_UART2_CTS_PX7,881};882 883static const unsigned int spi3_sck_py0_pins[] = {884	TEGRA_PIN_SPI3_SCK_PY0,885};886 887static const unsigned int spi3_miso_py1_pins[] = {888	TEGRA_PIN_SPI3_MISO_PY1,889};890 891static const unsigned int spi3_mosi_py2_pins[] = {892	TEGRA_PIN_SPI3_MOSI_PY2,893};894 895static const unsigned int spi3_cs0_py3_pins[] = {896	TEGRA_PIN_SPI3_CS0_PY3,897};898 899static const unsigned int spi3_cs1_py4_pins[] = {900	TEGRA_PIN_SPI3_CS1_PY4,901};902 903static const unsigned int uart5_tx_py5_pins[] = {904	TEGRA_PIN_UART5_TX_PY5,905};906 907static const unsigned int uart5_rx_py6_pins[] = {908	TEGRA_PIN_UART5_RX_PY6,909};910 911static const unsigned int uart5_rts_py7_pins[] = {912	TEGRA_PIN_UART5_RTS_PY7,913};914 915static const unsigned int uart5_cts_pz0_pins[] = {916	TEGRA_PIN_UART5_CTS_PZ0,917};918 919static const unsigned int usb_vbus_en0_pz1_pins[] = {920	TEGRA_PIN_USB_VBUS_EN0_PZ1,921};922 923static const unsigned int usb_vbus_en1_pz2_pins[] = {924	TEGRA_PIN_USB_VBUS_EN1_PZ2,925};926 927static const unsigned int spi1_sck_pz3_pins[] = {928	TEGRA_PIN_SPI1_SCK_PZ3,929};930 931static const unsigned int spi1_miso_pz4_pins[] = {932	TEGRA_PIN_SPI1_MISO_PZ4,933};934 935static const unsigned int spi1_mosi_pz5_pins[] = {936	TEGRA_PIN_SPI1_MOSI_PZ5,937};938 939static const unsigned int spi1_cs0_pz6_pins[] = {940	TEGRA_PIN_SPI1_CS0_PZ6,941};942 943static const unsigned int spi1_cs1_pz7_pins[] = {944	TEGRA_PIN_SPI1_CS1_PZ7,945};946 947static const unsigned int can0_dout_paa0_pins[] = {948	TEGRA_PIN_CAN0_DOUT_PAA0,949};950 951static const unsigned int can0_din_paa1_pins[] = {952	TEGRA_PIN_CAN0_DIN_PAA1,953};954 955static const unsigned int can1_dout_paa2_pins[] = {956	TEGRA_PIN_CAN1_DOUT_PAA2,957};958 959static const unsigned int can1_din_paa3_pins[] = {960	TEGRA_PIN_CAN1_DIN_PAA3,961};962 963static const unsigned int can0_stb_paa4_pins[] = {964	TEGRA_PIN_CAN0_STB_PAA4,965};966 967static const unsigned int can0_en_paa5_pins[] = {968	TEGRA_PIN_CAN0_EN_PAA5,969};970 971static const unsigned int soc_gpio49_paa6_pins[] = {972	TEGRA_PIN_SOC_GPIO49_PAA6,973};974 975static const unsigned int can0_err_paa7_pins[] = {976	TEGRA_PIN_CAN0_ERR_PAA7,977};978 979static const unsigned int spi5_sck_pac0_pins[] = {980	TEGRA_PIN_SPI5_SCK_PAC0,981};982 983static const unsigned int spi5_miso_pac1_pins[] = {984	TEGRA_PIN_SPI5_MISO_PAC1,985};986 987static const unsigned int spi5_mosi_pac2_pins[] = {988	TEGRA_PIN_SPI5_MOSI_PAC2,989};990 991static const unsigned int spi5_cs0_pac3_pins[] = {992	TEGRA_PIN_SPI5_CS0_PAC3,993};994 995static const unsigned int soc_gpio57_pac4_pins[] = {996	TEGRA_PIN_SOC_GPIO57_PAC4,997};998 999static const unsigned int soc_gpio58_pac5_pins[] = {1000	TEGRA_PIN_SOC_GPIO58_PAC5,1001};1002 1003static const unsigned int soc_gpio59_pac6_pins[] = {1004	TEGRA_PIN_SOC_GPIO59_PAC6,1005};1006 1007static const unsigned int soc_gpio60_pac7_pins[] = {1008	TEGRA_PIN_SOC_GPIO60_PAC7,1009};1010 1011static const unsigned int soc_gpio45_pad0_pins[] = {1012	TEGRA_PIN_SOC_GPIO45_PAD0,1013};1014 1015static const unsigned int soc_gpio46_pad1_pins[] = {1016	TEGRA_PIN_SOC_GPIO46_PAD1,1017};1018 1019static const unsigned int soc_gpio47_pad2_pins[] = {1020	TEGRA_PIN_SOC_GPIO47_PAD2,1021};1022 1023static const unsigned int soc_gpio48_pad3_pins[] = {1024	TEGRA_PIN_SOC_GPIO48_PAD3,1025};1026 1027static const unsigned int ufs0_ref_clk_pae0_pins[] = {1028	TEGRA_PIN_UFS0_REF_CLK_PAE0,1029};1030 1031static const unsigned int ufs0_rst_n_pae1_pins[] = {1032	TEGRA_PIN_UFS0_RST_N_PAE1,1033};1034 1035static const unsigned int pex_l5_clkreq_n_paf0_pins[] = {1036	TEGRA_PIN_PEX_L5_CLKREQ_N_PAF0,1037};1038 1039static const unsigned int pex_l5_rst_n_paf1_pins[] = {1040	TEGRA_PIN_PEX_L5_RST_N_PAF1,1041};1042 1043static const unsigned int pex_l6_clkreq_n_paf2_pins[] = {1044	TEGRA_PIN_PEX_L6_CLKREQ_N_PAF2,1045};1046 1047static const unsigned int pex_l6_rst_n_paf3_pins[] = {1048	TEGRA_PIN_PEX_L6_RST_N_PAF3,1049};1050 1051static const unsigned int pex_l7_clkreq_n_pag0_pins[] = {1052	TEGRA_PIN_PEX_L7_CLKREQ_N_PAG0,1053};1054 1055static const unsigned int pex_l7_rst_n_pag1_pins[] = {1056	TEGRA_PIN_PEX_L7_RST_N_PAG1,1057};1058 1059static const unsigned int pex_l8_clkreq_n_pag2_pins[] = {1060	TEGRA_PIN_PEX_L8_CLKREQ_N_PAG2,1061};1062 1063static const unsigned int pex_l8_rst_n_pag3_pins[] = {1064	TEGRA_PIN_PEX_L8_RST_N_PAG3,1065};1066 1067static const unsigned int pex_l9_clkreq_n_pag4_pins[] = {1068	TEGRA_PIN_PEX_L9_CLKREQ_N_PAG4,1069};1070 1071static const unsigned int pex_l9_rst_n_pag5_pins[] = {1072	TEGRA_PIN_PEX_L9_RST_N_PAG5,1073};1074 1075static const unsigned int pex_l10_clkreq_n_pag6_pins[] = {1076	TEGRA_PIN_PEX_L10_CLKREQ_N_PAG6,1077};1078 1079static const unsigned int pex_l10_rst_n_pag7_pins[] = {1080	TEGRA_PIN_PEX_L10_RST_N_PAG7,1081};1082 1083static const unsigned int can1_stb_pbb0_pins[] = {1084	TEGRA_PIN_CAN1_STB_PBB0,1085};1086 1087static const unsigned int can1_en_pbb1_pins[] = {1088	TEGRA_PIN_CAN1_EN_PBB1,1089};1090 1091static const unsigned int soc_gpio50_pbb2_pins[] = {1092	TEGRA_PIN_SOC_GPIO50_PBB2,1093};1094 1095static const unsigned int can1_err_pbb3_pins[] = {1096	TEGRA_PIN_CAN1_ERR_PBB3,1097};1098 1099static const unsigned int spi2_sck_pcc0_pins[] = {1100	TEGRA_PIN_SPI2_SCK_PCC0,1101};1102 1103static const unsigned int spi2_miso_pcc1_pins[] = {1104	TEGRA_PIN_SPI2_MISO_PCC1,1105};1106 1107static const unsigned int spi2_mosi_pcc2_pins[] = {1108	TEGRA_PIN_SPI2_MOSI_PCC2,1109};1110 1111static const unsigned int spi2_cs0_pcc3_pins[] = {1112	TEGRA_PIN_SPI2_CS0_PCC3,1113};1114 1115static const unsigned int touch_clk_pcc4_pins[] = {1116	TEGRA_PIN_TOUCH_CLK_PCC4,1117};1118 1119static const unsigned int uart3_tx_pcc5_pins[] = {1120	TEGRA_PIN_UART3_TX_PCC5,1121};1122 1123static const unsigned int uart3_rx_pcc6_pins[] = {1124	TEGRA_PIN_UART3_RX_PCC6,1125};1126 1127static const unsigned int gen2_i2c_scl_pcc7_pins[] = {1128	TEGRA_PIN_GEN2_I2C_SCL_PCC7,1129};1130 1131static const unsigned int gen2_i2c_sda_pdd0_pins[] = {1132	TEGRA_PIN_GEN2_I2C_SDA_PDD0,1133};1134 1135static const unsigned int gen8_i2c_scl_pdd1_pins[] = {1136	TEGRA_PIN_GEN8_I2C_SCL_PDD1,1137};1138 1139static const unsigned int gen8_i2c_sda_pdd2_pins[] = {1140	TEGRA_PIN_GEN8_I2C_SDA_PDD2,1141};1142 1143static const unsigned int sce_error_pee0_pins[] = {1144	TEGRA_PIN_SCE_ERROR_PEE0,1145};1146 1147static const unsigned int vcomp_alert_pee1_pins[] = {1148	TEGRA_PIN_VCOMP_ALERT_PEE1,1149};1150 1151static const unsigned int ao_retention_n_pee2_pins[] = {1152	TEGRA_PIN_AO_RETENTION_N_PEE2,1153};1154 1155static const unsigned int batt_oc_pee3_pins[] = {1156	TEGRA_PIN_BATT_OC_PEE3,1157};1158 1159static const unsigned int power_on_pee4_pins[] = {1160	TEGRA_PIN_POWER_ON_PEE4,1161};1162 1163static const unsigned int soc_gpio26_pee5_pins[] = {1164	TEGRA_PIN_SOC_GPIO26_PEE5,1165};1166 1167static const unsigned int soc_gpio27_pee6_pins[] = {1168	TEGRA_PIN_SOC_GPIO27_PEE6,1169};1170 1171static const unsigned int bootv_ctl_n_pee7_pins[] = {1172	TEGRA_PIN_BOOTV_CTL_N_PEE7,1173};1174 1175static const unsigned int hdmi_cec_pgg0_pins[] = {1176	TEGRA_PIN_HDMI_CEC_PGG0,1177};1178 1179static const unsigned int eqos_comp_pins[] = {1180	TEGRA_PIN_EQOS_COMP,1181};1182 1183static const unsigned int qspi_comp_pins[] = {1184	TEGRA_PIN_QSPI_COMP,1185};1186 1187static const unsigned int sdmmc1_comp_pins[] = {1188	TEGRA_PIN_SDMMC1_COMP,1189};1190 1191/* Define unique ID for each function */1192enum tegra_mux_dt {1193	TEGRA_MUX_GP,1194	TEGRA_MUX_UARTC,1195	TEGRA_MUX_I2C8,1196	TEGRA_MUX_SPI2,1197	TEGRA_MUX_I2C2,1198	TEGRA_MUX_CAN1,1199	TEGRA_MUX_CAN0,1200	TEGRA_MUX_RSVD0,1201	TEGRA_MUX_ETH0,1202	TEGRA_MUX_ETH2,1203	TEGRA_MUX_ETH1,1204	TEGRA_MUX_DP,1205	TEGRA_MUX_ETH3,1206	TEGRA_MUX_I2C4,1207	TEGRA_MUX_I2C7,1208	TEGRA_MUX_I2C9,1209	TEGRA_MUX_EQOS,1210	TEGRA_MUX_PE2,1211	TEGRA_MUX_PE1,1212	TEGRA_MUX_PE0,1213	TEGRA_MUX_PE3,1214	TEGRA_MUX_PE4,1215	TEGRA_MUX_PE5,1216	TEGRA_MUX_PE6,1217	TEGRA_MUX_PE10,1218	TEGRA_MUX_PE7,1219	TEGRA_MUX_PE8,1220	TEGRA_MUX_PE9,1221	TEGRA_MUX_QSPI0,1222	TEGRA_MUX_QSPI1,1223	TEGRA_MUX_QSPI,1224	TEGRA_MUX_SDMMC1,1225	TEGRA_MUX_SCE,1226	TEGRA_MUX_SOC,1227	TEGRA_MUX_GPIO,1228	TEGRA_MUX_HDMI,1229	TEGRA_MUX_UFS0,1230	TEGRA_MUX_SPI3,1231	TEGRA_MUX_SPI1,1232	TEGRA_MUX_UARTB,1233	TEGRA_MUX_UARTE,1234	TEGRA_MUX_USB,1235	TEGRA_MUX_EXTPERIPH2,1236	TEGRA_MUX_EXTPERIPH1,1237	TEGRA_MUX_I2C3,1238	TEGRA_MUX_VI0,1239	TEGRA_MUX_I2C5,1240	TEGRA_MUX_UARTA,1241	TEGRA_MUX_UARTD,1242	TEGRA_MUX_I2C1,1243	TEGRA_MUX_I2S4,1244	TEGRA_MUX_I2S6,1245	TEGRA_MUX_AUD,1246	TEGRA_MUX_SPI5,1247	TEGRA_MUX_TOUCH,1248	TEGRA_MUX_UARTJ,1249	TEGRA_MUX_RSVD1,1250	TEGRA_MUX_WDT,1251	TEGRA_MUX_TSC,1252	TEGRA_MUX_DMIC3,1253	TEGRA_MUX_LED,1254	TEGRA_MUX_VI0_ALT,1255	TEGRA_MUX_I2S5,1256	TEGRA_MUX_NV,1257	TEGRA_MUX_EXTPERIPH3,1258	TEGRA_MUX_EXTPERIPH4,1259	TEGRA_MUX_SPI4,1260	TEGRA_MUX_CCLA,1261	TEGRA_MUX_I2S2,1262	TEGRA_MUX_I2S1,1263	TEGRA_MUX_I2S8,1264	TEGRA_MUX_I2S3,1265	TEGRA_MUX_RSVD2,1266	TEGRA_MUX_DMIC5,1267	TEGRA_MUX_DCA,1268	TEGRA_MUX_DISPLAYB,1269	TEGRA_MUX_DISPLAYA,1270	TEGRA_MUX_VI1,1271	TEGRA_MUX_DCB,1272	TEGRA_MUX_DMIC1,1273	TEGRA_MUX_DMIC4,1274	TEGRA_MUX_I2S7,1275	TEGRA_MUX_DMIC2,1276	TEGRA_MUX_DSPK0,1277	TEGRA_MUX_RSVD3,1278	TEGRA_MUX_TSC_ALT,1279	TEGRA_MUX_ISTCTRL,1280	TEGRA_MUX_VI1_ALT,1281	TEGRA_MUX_DSPK1,1282	TEGRA_MUX_IGPU,1283};1284 1285/* Make list of each function name */1286#define TEGRA_PIN_FUNCTION(lid) #lid1287 1288static const char * const tegra234_functions[] = {1289	TEGRA_PIN_FUNCTION(gp),1290	TEGRA_PIN_FUNCTION(uartc),1291	TEGRA_PIN_FUNCTION(i2c8),1292	TEGRA_PIN_FUNCTION(spi2),1293	TEGRA_PIN_FUNCTION(i2c2),1294	TEGRA_PIN_FUNCTION(can1),1295	TEGRA_PIN_FUNCTION(can0),1296	TEGRA_PIN_FUNCTION(rsvd0),1297	TEGRA_PIN_FUNCTION(eth0),1298	TEGRA_PIN_FUNCTION(eth2),1299	TEGRA_PIN_FUNCTION(eth1),1300	TEGRA_PIN_FUNCTION(dp),1301	TEGRA_PIN_FUNCTION(eth3),1302	TEGRA_PIN_FUNCTION(i2c4),1303	TEGRA_PIN_FUNCTION(i2c7),1304	TEGRA_PIN_FUNCTION(i2c9),1305	TEGRA_PIN_FUNCTION(eqos),1306	TEGRA_PIN_FUNCTION(pe2),1307	TEGRA_PIN_FUNCTION(pe1),1308	TEGRA_PIN_FUNCTION(pe0),1309	TEGRA_PIN_FUNCTION(pe3),1310	TEGRA_PIN_FUNCTION(pe4),1311	TEGRA_PIN_FUNCTION(pe5),1312	TEGRA_PIN_FUNCTION(pe6),1313	TEGRA_PIN_FUNCTION(pe10),1314	TEGRA_PIN_FUNCTION(pe7),1315	TEGRA_PIN_FUNCTION(pe8),1316	TEGRA_PIN_FUNCTION(pe9),1317	TEGRA_PIN_FUNCTION(qspi0),1318	TEGRA_PIN_FUNCTION(qspi1),1319	TEGRA_PIN_FUNCTION(qspi),1320	TEGRA_PIN_FUNCTION(sdmmc1),1321	TEGRA_PIN_FUNCTION(sce),1322	TEGRA_PIN_FUNCTION(soc),1323	TEGRA_PIN_FUNCTION(gpio),1324	TEGRA_PIN_FUNCTION(hdmi),1325	TEGRA_PIN_FUNCTION(ufs0),1326	TEGRA_PIN_FUNCTION(spi3),1327	TEGRA_PIN_FUNCTION(spi1),1328	TEGRA_PIN_FUNCTION(uartb),1329	TEGRA_PIN_FUNCTION(uarte),1330	TEGRA_PIN_FUNCTION(usb),1331	TEGRA_PIN_FUNCTION(extperiph2),1332	TEGRA_PIN_FUNCTION(extperiph1),1333	TEGRA_PIN_FUNCTION(i2c3),1334	TEGRA_PIN_FUNCTION(vi0),1335	TEGRA_PIN_FUNCTION(i2c5),1336	TEGRA_PIN_FUNCTION(uarta),1337	TEGRA_PIN_FUNCTION(uartd),1338	TEGRA_PIN_FUNCTION(i2c1),1339	TEGRA_PIN_FUNCTION(i2s4),1340	TEGRA_PIN_FUNCTION(i2s6),1341	TEGRA_PIN_FUNCTION(aud),1342	TEGRA_PIN_FUNCTION(spi5),1343	TEGRA_PIN_FUNCTION(touch),1344	TEGRA_PIN_FUNCTION(uartj),1345	TEGRA_PIN_FUNCTION(rsvd1),1346	TEGRA_PIN_FUNCTION(wdt),1347	TEGRA_PIN_FUNCTION(tsc),1348	TEGRA_PIN_FUNCTION(dmic3),1349	TEGRA_PIN_FUNCTION(led),1350	TEGRA_PIN_FUNCTION(vi0_alt),1351	TEGRA_PIN_FUNCTION(i2s5),1352	TEGRA_PIN_FUNCTION(nv),1353	TEGRA_PIN_FUNCTION(extperiph3),1354	TEGRA_PIN_FUNCTION(extperiph4),1355	TEGRA_PIN_FUNCTION(spi4),1356	TEGRA_PIN_FUNCTION(ccla),1357	TEGRA_PIN_FUNCTION(i2s2),1358	TEGRA_PIN_FUNCTION(i2s1),1359	TEGRA_PIN_FUNCTION(i2s8),1360	TEGRA_PIN_FUNCTION(i2s3),1361	TEGRA_PIN_FUNCTION(rsvd2),1362	TEGRA_PIN_FUNCTION(dmic5),1363	TEGRA_PIN_FUNCTION(dca),1364	TEGRA_PIN_FUNCTION(displayb),1365	TEGRA_PIN_FUNCTION(displaya),1366	TEGRA_PIN_FUNCTION(vi1),1367	TEGRA_PIN_FUNCTION(dcb),1368	TEGRA_PIN_FUNCTION(dmic1),1369	TEGRA_PIN_FUNCTION(dmic4),1370	TEGRA_PIN_FUNCTION(i2s7),1371	TEGRA_PIN_FUNCTION(dmic2),1372	TEGRA_PIN_FUNCTION(dspk0),1373	TEGRA_PIN_FUNCTION(rsvd3),1374	TEGRA_PIN_FUNCTION(tsc_alt),1375	TEGRA_PIN_FUNCTION(istctrl),1376	TEGRA_PIN_FUNCTION(vi1_alt),1377	TEGRA_PIN_FUNCTION(dspk1),1378	TEGRA_PIN_FUNCTION(igpu),1379};1380 1381#define PINGROUP_REG_Y(r) ((r))1382#define PINGROUP_REG_N(r) -11383 1384#define DRV_PINGROUP_Y(r) ((r))1385#define DRV_PINGROUP_N(r) -11386 1387#define DRV_PINGROUP_ENTRY_N(pg_name)				\1388		.drv_reg = -1,					\1389		.drv_bank = -1,					\1390		.drvdn_bit = -1,				\1391		.drvup_bit = -1,				\1392		.slwr_bit = -1,					\1393		.slwf_bit = -11394 1395#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b,	\1396			     drvup_w, slwr_b, slwr_w, slwf_b,	\1397			     slwf_w, bank)			\1398		.drv_reg = DRV_PINGROUP_Y(r),			\1399		.drv_bank = bank,				\1400		.drvdn_bit = drvdn_b,				\1401		.drvdn_width = drvdn_w,				\1402		.drvup_bit = drvup_b,				\1403		.drvup_width = drvup_w,				\1404		.slwr_bit = slwr_b,				\1405		.slwr_width = slwr_w,				\1406		.slwf_bit = slwf_b,				\1407		.slwf_width = slwf_w1408 1409#define PIN_PINGROUP_ENTRY_N(pg_name)				\1410		.mux_reg = -1,					\1411		.pupd_reg = -1,					\1412		.tri_reg = -1,					\1413		.einput_bit = -1,				\1414		.e_io_hv_bit = -1,				\1415		.odrain_bit = -1,				\1416		.lock_bit = -1,					\1417		.parked_bit = -1,				\1418		.lpmd_bit = -1,					\1419		.drvtype_bit = -1,				\1420		.lpdr_bit = -1,					\1421		.pbias_buf_bit = -1,				\1422		.preemp_bit = -1,				\1423		.rfu_in_bit = -11424 1425#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input,	\1426				e_lpdr, e_pbias_buf, gpio_sfio_sel,	\1427				schmitt_b)				\1428		.mux_reg = PINGROUP_REG_Y(r),			\1429		.lpmd_bit = -1,					\1430		.lock_bit = -1,					\1431		.hsm_bit = -1,					\1432		.mux_bank = bank,				\1433		.mux_bit = 0,					\1434		.pupd_reg = PINGROUP_REG_##pupd(r),		\1435		.pupd_bank = bank,				\1436		.pupd_bit = 2,					\1437		.tri_reg = PINGROUP_REG_Y(r),			\1438		.tri_bank = bank,				\1439		.tri_bit = 4,					\1440		.einput_bit = e_input,				\1441		.sfsel_bit = gpio_sfio_sel,			\1442		.schmitt_bit = schmitt_b,			\1443		.drvtype_bit = 13,				\1444		.lpdr_bit = e_lpdr,				\1445 1446/* main drive pin groups */1447#define	drive_soc_gpio08_pb0			DRV_PINGROUP_ENTRY_Y(0x500c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1448#define	drive_soc_gpio36_pm5			DRV_PINGROUP_ENTRY_Y(0x10004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1449#define	drive_soc_gpio53_pm6			DRV_PINGROUP_ENTRY_Y(0x1000c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1450#define	drive_soc_gpio55_pm4			DRV_PINGROUP_ENTRY_Y(0x10014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1451#define	drive_soc_gpio38_pm7			DRV_PINGROUP_ENTRY_Y(0x1001c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1452#define	drive_soc_gpio39_pn1			DRV_PINGROUP_ENTRY_Y(0x10024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1453#define	drive_soc_gpio40_pn2			DRV_PINGROUP_ENTRY_Y(0x1002c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1454#define	drive_dp_aux_ch0_hpd_pm0		DRV_PINGROUP_ENTRY_Y(0x10034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1455#define	drive_dp_aux_ch1_hpd_pm1		DRV_PINGROUP_ENTRY_Y(0x1003c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1456#define	drive_dp_aux_ch2_hpd_pm2		DRV_PINGROUP_ENTRY_Y(0x10044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1457#define	drive_dp_aux_ch3_hpd_pm3		DRV_PINGROUP_ENTRY_Y(0x1004c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1458#define	drive_dp_aux_ch1_p_pn3			DRV_PINGROUP_ENTRY_Y(0x10054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1459#define	drive_dp_aux_ch1_n_pn4			DRV_PINGROUP_ENTRY_Y(0x1005c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1460#define	drive_dp_aux_ch2_p_pn5			DRV_PINGROUP_ENTRY_Y(0x10064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1461#define	drive_dp_aux_ch2_n_pn6			DRV_PINGROUP_ENTRY_Y(0x1006c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1462#define	drive_dp_aux_ch3_p_pn7			DRV_PINGROUP_ENTRY_Y(0x10074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1463#define	drive_dp_aux_ch3_n_pn0			DRV_PINGROUP_ENTRY_Y(0x1007c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1464#define	drive_pex_l2_clkreq_n_pk4		DRV_PINGROUP_ENTRY_Y(0x7004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1465#define	drive_pex_wake_n_pl2			DRV_PINGROUP_ENTRY_Y(0x700c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1466#define	drive_pex_l1_clkreq_n_pk2		DRV_PINGROUP_ENTRY_Y(0x7014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1467#define	drive_pex_l1_rst_n_pk3			DRV_PINGROUP_ENTRY_Y(0x701c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1468#define	drive_pex_l0_clkreq_n_pk0		DRV_PINGROUP_ENTRY_Y(0x7024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1469#define	drive_pex_l0_rst_n_pk1			DRV_PINGROUP_ENTRY_Y(0x702c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1470#define	drive_pex_l2_rst_n_pk5			DRV_PINGROUP_ENTRY_Y(0x7034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1471#define	drive_pex_l3_clkreq_n_pk6		DRV_PINGROUP_ENTRY_Y(0x703c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1472#define	drive_pex_l3_rst_n_pk7			DRV_PINGROUP_ENTRY_Y(0x7044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1473#define	drive_pex_l4_clkreq_n_pl0		DRV_PINGROUP_ENTRY_Y(0x704c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1474#define	drive_pex_l4_rst_n_pl1			DRV_PINGROUP_ENTRY_Y(0x7054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1475#define	drive_soc_gpio34_pl3			DRV_PINGROUP_ENTRY_Y(0x705c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1476#define	drive_pex_l5_clkreq_n_paf0		DRV_PINGROUP_ENTRY_Y(0x14004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1477#define	drive_pex_l5_rst_n_paf1			DRV_PINGROUP_ENTRY_Y(0x1400c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1478#define	drive_pex_l6_clkreq_n_paf2		DRV_PINGROUP_ENTRY_Y(0x14014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1479#define	drive_pex_l6_rst_n_paf3			DRV_PINGROUP_ENTRY_Y(0x1401c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1480#define	drive_pex_l10_clkreq_n_pag6		DRV_PINGROUP_ENTRY_Y(0x19004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1481#define	drive_pex_l10_rst_n_pag7		DRV_PINGROUP_ENTRY_Y(0x1900c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1482#define	drive_pex_l7_clkreq_n_pag0		DRV_PINGROUP_ENTRY_Y(0x19014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1483#define	drive_pex_l7_rst_n_pag1			DRV_PINGROUP_ENTRY_Y(0x1901c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1484#define	drive_pex_l8_clkreq_n_pag2		DRV_PINGROUP_ENTRY_Y(0x19024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1485#define	drive_pex_l8_rst_n_pag3			DRV_PINGROUP_ENTRY_Y(0x1902c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1486#define	drive_pex_l9_clkreq_n_pag4		DRV_PINGROUP_ENTRY_Y(0x19034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1487#define	drive_pex_l9_rst_n_pag5			DRV_PINGROUP_ENTRY_Y(0x1903c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1488#define	drive_sdmmc1_clk_pj0			DRV_PINGROUP_ENTRY_Y(0x8004,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1489#define	drive_sdmmc1_cmd_pj1			DRV_PINGROUP_ENTRY_Y(0x800c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1490#define	drive_sdmmc1_dat3_pj5			DRV_PINGROUP_ENTRY_Y(0x801c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1491#define	drive_sdmmc1_dat2_pj4			DRV_PINGROUP_ENTRY_Y(0x8024,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1492#define	drive_sdmmc1_dat1_pj3			DRV_PINGROUP_ENTRY_Y(0x802c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1493#define	drive_sdmmc1_dat0_pj2			DRV_PINGROUP_ENTRY_Y(0x8034,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1494#define	drive_ufs0_rst_n_pae1			DRV_PINGROUP_ENTRY_Y(0x11004,	12,	5,	24,	5,	-1,	-1,	-1,	-1,	0)1495#define	drive_ufs0_ref_clk_pae0			DRV_PINGROUP_ENTRY_Y(0x1100c,	12,	5,	24,	5,	-1,	-1,	-1,	-1,	0)1496#define	drive_spi3_miso_py1			DRV_PINGROUP_ENTRY_Y(0xd004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1497#define	drive_spi1_cs0_pz6			DRV_PINGROUP_ENTRY_Y(0xd00c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1498#define	drive_spi3_cs0_py3			DRV_PINGROUP_ENTRY_Y(0xd014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1499#define	drive_spi1_miso_pz4			DRV_PINGROUP_ENTRY_Y(0xd01c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1500#define	drive_spi3_cs1_py4			DRV_PINGROUP_ENTRY_Y(0xd024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1501#define	drive_spi1_sck_pz3			DRV_PINGROUP_ENTRY_Y(0xd02c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1502#define	drive_spi3_sck_py0			DRV_PINGROUP_ENTRY_Y(0xd034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1503#define	drive_spi1_cs1_pz7			DRV_PINGROUP_ENTRY_Y(0xd03c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1504#define	drive_spi1_mosi_pz5			DRV_PINGROUP_ENTRY_Y(0xd044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1505#define	drive_spi3_mosi_py2			DRV_PINGROUP_ENTRY_Y(0xd04c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1506#define	drive_uart2_tx_px4			DRV_PINGROUP_ENTRY_Y(0xd054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1507#define	drive_uart2_rx_px5			DRV_PINGROUP_ENTRY_Y(0xd05c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1508#define	drive_uart2_rts_px6			DRV_PINGROUP_ENTRY_Y(0xd064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1509#define	drive_uart2_cts_px7			DRV_PINGROUP_ENTRY_Y(0xd06c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1510#define	drive_uart5_tx_py5			DRV_PINGROUP_ENTRY_Y(0xd074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1511#define	drive_uart5_rx_py6			DRV_PINGROUP_ENTRY_Y(0xd07c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1512#define	drive_uart5_rts_py7			DRV_PINGROUP_ENTRY_Y(0xd084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1513#define	drive_uart5_cts_pz0			DRV_PINGROUP_ENTRY_Y(0xd08c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1514#define	drive_gpu_pwr_req_px0			DRV_PINGROUP_ENTRY_Y(0xd094,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1515#define	drive_gp_pwm3_px3			DRV_PINGROUP_ENTRY_Y(0xd09c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1516#define	drive_gp_pwm2_px2			DRV_PINGROUP_ENTRY_Y(0xd0a4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1517#define	drive_cv_pwr_req_px1			DRV_PINGROUP_ENTRY_Y(0xd0ac,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1518#define	drive_usb_vbus_en0_pz1			DRV_PINGROUP_ENTRY_Y(0xd0b4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1519#define	drive_usb_vbus_en1_pz2			DRV_PINGROUP_ENTRY_Y(0xd0bc,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1520#define	drive_extperiph2_clk_pp1		DRV_PINGROUP_ENTRY_Y(0x0004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1521#define	drive_extperiph1_clk_pp0		DRV_PINGROUP_ENTRY_Y(0x000c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1522#define	drive_cam_i2c_sda_pp3			DRV_PINGROUP_ENTRY_Y(0x0014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1523#define	drive_cam_i2c_scl_pp2			DRV_PINGROUP_ENTRY_Y(0x001c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1524#define	drive_soc_gpio23_pp4			DRV_PINGROUP_ENTRY_Y(0x0024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1525#define	drive_soc_gpio24_pp5			DRV_PINGROUP_ENTRY_Y(0x002c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1526#define	drive_soc_gpio25_pp6			DRV_PINGROUP_ENTRY_Y(0x0034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1527#define	drive_pwr_i2c_scl_pp7			DRV_PINGROUP_ENTRY_Y(0x003c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1528#define	drive_pwr_i2c_sda_pq0			DRV_PINGROUP_ENTRY_Y(0x0044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1529#define	drive_soc_gpio28_pq1			DRV_PINGROUP_ENTRY_Y(0x004c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1530#define	drive_soc_gpio29_pq2			DRV_PINGROUP_ENTRY_Y(0x0054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1531#define	drive_soc_gpio30_pq3			DRV_PINGROUP_ENTRY_Y(0x005c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1532#define	drive_soc_gpio31_pq4			DRV_PINGROUP_ENTRY_Y(0x0064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1533#define	drive_soc_gpio32_pq5			DRV_PINGROUP_ENTRY_Y(0x006c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1534#define	drive_soc_gpio33_pq6			DRV_PINGROUP_ENTRY_Y(0x0074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1535#define	drive_soc_gpio35_pq7			DRV_PINGROUP_ENTRY_Y(0x007c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1536#define	drive_soc_gpio37_pr0			DRV_PINGROUP_ENTRY_Y(0x0084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1537#define	drive_soc_gpio56_pr1			DRV_PINGROUP_ENTRY_Y(0x008c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1538#define	drive_uart1_cts_pr5			DRV_PINGROUP_ENTRY_Y(0x0094,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1539#define	drive_uart1_rts_pr4			DRV_PINGROUP_ENTRY_Y(0x009c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1540#define	drive_uart1_rx_pr3			DRV_PINGROUP_ENTRY_Y(0x00a4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1541#define	drive_uart1_tx_pr2			DRV_PINGROUP_ENTRY_Y(0x00ac,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1542#define	drive_cpu_pwr_req_pi5			DRV_PINGROUP_ENTRY_Y(0x4004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1543#define	drive_uart4_cts_ph6			DRV_PINGROUP_ENTRY_Y(0x400c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1544#define	drive_uart4_rts_ph5			DRV_PINGROUP_ENTRY_Y(0x4014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1545#define	drive_uart4_rx_ph4			DRV_PINGROUP_ENTRY_Y(0x401c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1546#define	drive_uart4_tx_ph3			DRV_PINGROUP_ENTRY_Y(0x4024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1547#define	drive_gen1_i2c_scl_pi3			DRV_PINGROUP_ENTRY_Y(0x402c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1548#define	drive_gen1_i2c_sda_pi4			DRV_PINGROUP_ENTRY_Y(0x4034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1549#define	drive_soc_gpio20_pg7			DRV_PINGROUP_ENTRY_Y(0x403c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1550#define	drive_soc_gpio21_ph0			DRV_PINGROUP_ENTRY_Y(0x4044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1551#define	drive_soc_gpio22_ph1			DRV_PINGROUP_ENTRY_Y(0x404c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1552#define	drive_soc_gpio13_pg0			DRV_PINGROUP_ENTRY_Y(0x4054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1553#define	drive_soc_gpio14_pg1			DRV_PINGROUP_ENTRY_Y(0x405c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1554#define	drive_soc_gpio15_pg2			DRV_PINGROUP_ENTRY_Y(0x4064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1555#define	drive_soc_gpio16_pg3			DRV_PINGROUP_ENTRY_Y(0x406c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1556#define	drive_soc_gpio17_pg4			DRV_PINGROUP_ENTRY_Y(0x4074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1557#define	drive_soc_gpio18_pg5			DRV_PINGROUP_ENTRY_Y(0x407c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1558#define	drive_soc_gpio19_pg6			DRV_PINGROUP_ENTRY_Y(0x4084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1559#define	drive_soc_gpio41_ph7			DRV_PINGROUP_ENTRY_Y(0x408c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1560#define	drive_soc_gpio42_pi0			DRV_PINGROUP_ENTRY_Y(0x4094,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1561#define	drive_soc_gpio43_pi1			DRV_PINGROUP_ENTRY_Y(0x409c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1562#define	drive_soc_gpio44_pi2			DRV_PINGROUP_ENTRY_Y(0x40a4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1563#define	drive_soc_gpio06_ph2			DRV_PINGROUP_ENTRY_Y(0x40ac,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1564#define	drive_soc_gpio07_pi6			DRV_PINGROUP_ENTRY_Y(0x40b4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1565#define	drive_dap4_sclk_pa4			DRV_PINGROUP_ENTRY_Y(0x2004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1566#define	drive_dap4_dout_pa5			DRV_PINGROUP_ENTRY_Y(0x200c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1567#define	drive_dap4_din_pa6			DRV_PINGROUP_ENTRY_Y(0x2014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1568#define	drive_dap4_fs_pa7			DRV_PINGROUP_ENTRY_Y(0x201c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1569#define	drive_dap6_sclk_pa0			DRV_PINGROUP_ENTRY_Y(0x2024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1570#define	drive_dap6_dout_pa1			DRV_PINGROUP_ENTRY_Y(0x202c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1571#define	drive_dap6_din_pa2			DRV_PINGROUP_ENTRY_Y(0x2034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1572#define	drive_dap6_fs_pa3			DRV_PINGROUP_ENTRY_Y(0x203c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1573#define	drive_soc_gpio45_pad0			DRV_PINGROUP_ENTRY_Y(0x18004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1574#define	drive_soc_gpio46_pad1			DRV_PINGROUP_ENTRY_Y(0x1800c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1575#define	drive_soc_gpio47_pad2			DRV_PINGROUP_ENTRY_Y(0x18014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1576#define	drive_soc_gpio48_pad3			DRV_PINGROUP_ENTRY_Y(0x1801c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1577#define	drive_soc_gpio57_pac4			DRV_PINGROUP_ENTRY_Y(0x18024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1578#define	drive_soc_gpio58_pac5			DRV_PINGROUP_ENTRY_Y(0x1802c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1579#define	drive_soc_gpio59_pac6			DRV_PINGROUP_ENTRY_Y(0x18034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1580#define	drive_soc_gpio60_pac7			DRV_PINGROUP_ENTRY_Y(0x1803c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1581#define	drive_spi5_cs0_pac3			DRV_PINGROUP_ENTRY_Y(0x18044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1582#define	drive_spi5_miso_pac1			DRV_PINGROUP_ENTRY_Y(0x1804c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1583#define	drive_spi5_mosi_pac2			DRV_PINGROUP_ENTRY_Y(0x18054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1584#define	drive_spi5_sck_pac0			DRV_PINGROUP_ENTRY_Y(0x1805c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1585#define	drive_eqos_td3_pe4			DRV_PINGROUP_ENTRY_N(no_entry)1586#define	drive_eqos_td2_pe3			DRV_PINGROUP_ENTRY_N(no_entry)1587#define	drive_eqos_td1_pe2			DRV_PINGROUP_ENTRY_N(no_entry)1588#define	drive_eqos_td0_pe1			DRV_PINGROUP_ENTRY_N(no_entry)1589#define	drive_eqos_rd3_pf1			DRV_PINGROUP_ENTRY_N(no_entry)1590#define	drive_eqos_rd2_pf0			DRV_PINGROUP_ENTRY_N(no_entry)1591#define	drive_eqos_rd1_pe7			DRV_PINGROUP_ENTRY_N(no_entry)1592#define	drive_eqos_sma_mdio_pf4			DRV_PINGROUP_ENTRY_N(no_entry)1593#define	drive_eqos_rd0_pe6			DRV_PINGROUP_ENTRY_N(no_entry)1594#define	drive_eqos_sma_mdc_pf5			DRV_PINGROUP_ENTRY_N(no_entry)1595#define	drive_eqos_comp				DRV_PINGROUP_ENTRY_N(no_entry)1596#define	drive_eqos_txc_pe0			DRV_PINGROUP_ENTRY_N(no_entry)1597#define	drive_eqos_rxc_pf3			DRV_PINGROUP_ENTRY_N(no_entry)1598#define	drive_eqos_tx_ctl_pe5			DRV_PINGROUP_ENTRY_N(no_entry)1599#define	drive_eqos_rx_ctl_pf2			DRV_PINGROUP_ENTRY_N(no_entry)1600#define	drive_qspi0_io3_pc5			DRV_PINGROUP_ENTRY_N(no_entry)1601#define	drive_qspi0_io2_pc4			DRV_PINGROUP_ENTRY_N(no_entry)1602#define	drive_qspi0_io1_pc3			DRV_PINGROUP_ENTRY_N(no_entry)1603#define	drive_qspi0_io0_pc2			DRV_PINGROUP_ENTRY_N(no_entry)1604#define	drive_qspi0_sck_pc0			DRV_PINGROUP_ENTRY_N(no_entry)1605#define	drive_qspi0_cs_n_pc1			DRV_PINGROUP_ENTRY_N(no_entry)1606#define	drive_qspi1_io3_pd3			DRV_PINGROUP_ENTRY_N(no_entry)1607#define	drive_qspi1_io2_pd2			DRV_PINGROUP_ENTRY_N(no_entry)1608#define	drive_qspi1_io1_pd1			DRV_PINGROUP_ENTRY_N(no_entry)1609#define	drive_qspi1_io0_pd0			DRV_PINGROUP_ENTRY_N(no_entry)1610#define	drive_qspi1_sck_pc6			DRV_PINGROUP_ENTRY_N(no_entry)1611#define	drive_qspi1_cs_n_pc7			DRV_PINGROUP_ENTRY_N(no_entry)1612#define	drive_qspi_comp				DRV_PINGROUP_ENTRY_N(no_entry)1613#define	drive_sdmmc1_comp			DRV_PINGROUP_ENTRY_N(no_entry)1614 1615#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf,	\1616			gpio_sfio_sel, schmitt_b)							\1617	{								\1618		.name = #pg_name,					\1619		.pins = pg_name##_pins,					\1620		.npins = ARRAY_SIZE(pg_name##_pins),			\1621			.funcs = {					\1622				TEGRA_MUX_##f0,				\1623				TEGRA_MUX_##f1,				\1624				TEGRA_MUX_##f2,				\1625				TEGRA_MUX_##f3,				\1626			},						\1627		PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk,	\1628					e_input, e_lpdr, e_pbias_buf,	\1629					gpio_sfio_sel, schmitt_b)	\1630		drive_##pg_name,					\1631	}1632 1633static const struct tegra_pingroup tegra234_groups[] = {1634	PINGROUP(soc_gpio08_pb0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x5008,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1635	PINGROUP(soc_gpio36_pm5,	ETH0,		RSVD1,		DCA,		RSVD3,		0x10000,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1636	PINGROUP(soc_gpio53_pm6,	ETH0,		RSVD1,		DCA,		RSVD3,		0x10008,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1637	PINGROUP(soc_gpio55_pm4,	ETH2,		RSVD1,		RSVD2,		RSVD3,		0x10010,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1638	PINGROUP(soc_gpio38_pm7,	ETH1,		RSVD1,		RSVD2,		RSVD3,		0x10018,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1639	PINGROUP(soc_gpio39_pn1,	GP,		RSVD1,		RSVD2,		RSVD3,		0x10020,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1640	PINGROUP(soc_gpio40_pn2,	ETH1,		RSVD1,		RSVD2,		RSVD3,		0x10028,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1641	PINGROUP(dp_aux_ch0_hpd_pm0,	DP,		RSVD1,		RSVD2,		RSVD3,		0x10030,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1642	PINGROUP(dp_aux_ch1_hpd_pm1,	ETH3,		RSVD1,		RSVD2,		RSVD3,		0x10038,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1643	PINGROUP(dp_aux_ch2_hpd_pm2,	ETH3,		RSVD1,		DISPLAYB,	RSVD3,		0x10040,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1644	PINGROUP(dp_aux_ch3_hpd_pm3,	ETH2,		RSVD1,		DISPLAYA,	RSVD3,		0x10048,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1645	PINGROUP(dp_aux_ch1_p_pn3,	I2C4,		RSVD1,		RSVD2,		RSVD3,		0x10050,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1646	PINGROUP(dp_aux_ch1_n_pn4,	I2C4,		RSVD1,		RSVD2,		RSVD3,		0x10058,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1647	PINGROUP(dp_aux_ch2_p_pn5,	I2C7,		RSVD1,		RSVD2,		RSVD3,		0x10060,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1648	PINGROUP(dp_aux_ch2_n_pn6,	I2C7,		RSVD1,		RSVD2,		RSVD3,		0x10068,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1649	PINGROUP(dp_aux_ch3_p_pn7,	I2C9,		RSVD1,		RSVD2,		RSVD3,		0x10070,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1650	PINGROUP(dp_aux_ch3_n_pn0,	I2C9,		RSVD1,		RSVD2,		RSVD3,		0x10078,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1651	PINGROUP(eqos_td3_pe4,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15000,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1652	PINGROUP(eqos_td2_pe3,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15008,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1653	PINGROUP(eqos_td1_pe2,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15010,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1654	PINGROUP(eqos_td0_pe1,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15018,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1655	PINGROUP(eqos_rd3_pf1,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15020,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1656	PINGROUP(eqos_rd2_pf0,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15028,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1657	PINGROUP(eqos_rd1_pe7,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15030,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1658	PINGROUP(eqos_sma_mdio_pf4,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15038,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1659	PINGROUP(eqos_rd0_pe6,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15040,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1660	PINGROUP(eqos_sma_mdc_pf5,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15048,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1661	PINGROUP(eqos_comp,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15050,	0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1),1662	PINGROUP(eqos_txc_pe0,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15058,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1663	PINGROUP(eqos_rxc_pf3,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15060,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1664	PINGROUP(eqos_tx_ctl_pe5,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15068,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1665	PINGROUP(eqos_rx_ctl_pf2,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15070,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1666	PINGROUP(pex_l2_clkreq_n_pk4,	PE2,		RSVD1,		RSVD2,		RSVD3,		0x7000,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1667	PINGROUP(pex_wake_n_pl2,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x7008,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1668	PINGROUP(pex_l1_clkreq_n_pk2,	PE1,		RSVD1,		RSVD2,		RSVD3,		0x7010,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1669	PINGROUP(pex_l1_rst_n_pk3,	PE1,		RSVD1,		RSVD2,		RSVD3,		0x7018,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1670	PINGROUP(pex_l0_clkreq_n_pk0,	PE0,		RSVD1,		RSVD2,		RSVD3,		0x7020,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1671	PINGROUP(pex_l0_rst_n_pk1,	PE0,		RSVD1,		RSVD2,		RSVD3,		0x7028,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1672	PINGROUP(pex_l2_rst_n_pk5,	PE2,		RSVD1,		RSVD2,		RSVD3,		0x7030,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1673	PINGROUP(pex_l3_clkreq_n_pk6,	PE3,		RSVD1,		RSVD2,		RSVD3,		0x7038,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1674	PINGROUP(pex_l3_rst_n_pk7,	PE3,		RSVD1,		RSVD2,		RSVD3,		0x7040,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1675	PINGROUP(pex_l4_clkreq_n_pl0,	PE4,		RSVD1,		RSVD2,		RSVD3,		0x7048,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1676	PINGROUP(pex_l4_rst_n_pl1,	PE4,		RSVD1,		RSVD2,		RSVD3,		0x7050,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1677	PINGROUP(soc_gpio34_pl3,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x7058,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1678	PINGROUP(pex_l5_clkreq_n_paf0,	PE5,		RSVD1,		RSVD2,		RSVD3,		0x14000,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1679	PINGROUP(pex_l5_rst_n_paf1,	PE5,		RSVD1,		RSVD2,		RSVD3,		0x14008,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1680	PINGROUP(pex_l6_clkreq_n_paf2,  PE6,		RSVD1,		RSVD2,		RSVD3,		0x14010,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1681	PINGROUP(pex_l6_rst_n_paf3,	PE6,		RSVD1,		RSVD2,		RSVD3,		0x14018,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1682	PINGROUP(pex_l10_clkreq_n_pag6,	PE10,		RSVD1,		RSVD2,		RSVD3,		0x19000,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1683	PINGROUP(pex_l10_rst_n_pag7,	PE10,		RSVD1,		RSVD2,		RSVD3,		0x19008,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1684	PINGROUP(pex_l7_clkreq_n_pag0,	PE7,		RSVD1,		RSVD2,		RSVD3,		0x19010,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1685	PINGROUP(pex_l7_rst_n_pag1,	PE7,		RSVD1,		RSVD2,		RSVD3,		0x19018,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1686	PINGROUP(pex_l8_clkreq_n_pag2,	PE8,		RSVD1,		RSVD2,		RSVD3,		0x19020,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1687	PINGROUP(pex_l8_rst_n_pag3,	PE8,		RSVD1,		RSVD2,		RSVD3,		0x19028,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1688	PINGROUP(pex_l9_clkreq_n_pag4,	PE9,		RSVD1,		RSVD2,		RSVD3,		0x19030,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1689	PINGROUP(pex_l9_rst_n_pag5,	PE9,		RSVD1,		RSVD2,		RSVD3,		0x19038,	0,	Y,	5,	7,	6,	8,	-1,	10,	12),1690	PINGROUP(qspi0_io3_pc5,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB000,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1691	PINGROUP(qspi0_io2_pc4,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB008,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1692	PINGROUP(qspi0_io1_pc3,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB010,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1693	PINGROUP(qspi0_io0_pc2,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB018,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1694	PINGROUP(qspi0_sck_pc0,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB020,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1695	PINGROUP(qspi0_cs_n_pc1,	QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB028,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1696	PINGROUP(qspi1_io3_pd3,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB030,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1697	PINGROUP(qspi1_io2_pd2,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB038,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1698	PINGROUP(qspi1_io1_pd1,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB040,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1699	PINGROUP(qspi1_io0_pd0,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB048,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1700	PINGROUP(qspi1_sck_pc6,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB050,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1701	PINGROUP(qspi1_cs_n_pc7,	QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB058,		0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1702	PINGROUP(qspi_comp,		QSPI,		RSVD1,		RSVD2,		RSVD3,		0xB060,		0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1),1703	PINGROUP(sdmmc1_clk_pj0,	SDMMC1,		RSVD1,		RSVD2,		RSVD3,		0x8000,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1704	PINGROUP(sdmmc1_cmd_pj1,	SDMMC1,		RSVD1,		RSVD2,		RSVD3,		0x8008,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1705	PINGROUP(sdmmc1_comp,		SDMMC1,		RSVD1,		RSVD2,		RSVD3,		0x8010,		0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1),1706	PINGROUP(sdmmc1_dat3_pj5,	SDMMC1,		RSVD1,		RSVD2,		RSVD3,		0x8018,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1707	PINGROUP(sdmmc1_dat2_pj4,	SDMMC1,		RSVD1,		RSVD2,		RSVD3,		0x8020,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1708	PINGROUP(sdmmc1_dat1_pj3,	SDMMC1,		RSVD1,		RSVD2,		RSVD3,		0x8028,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1709	PINGROUP(sdmmc1_dat0_pj2,	SDMMC1,		RSVD1,		RSVD2,		RSVD3,		0x8030,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1710	PINGROUP(ufs0_rst_n_pae1,	UFS0,		RSVD1,		RSVD2,		RSVD3,		0x11000,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1711	PINGROUP(ufs0_ref_clk_pae0,	UFS0,		RSVD1,		RSVD2,		RSVD3,		0x11008,	0,	Y,	-1,	5,	6,	-1,	-1,	10,	12),1712	PINGROUP(spi3_miso_py1,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD000,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1713	PINGROUP(spi1_cs0_pz6,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD008,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1714	PINGROUP(spi3_cs0_py3,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD010,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1715	PINGROUP(spi1_miso_pz4,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD018,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1716	PINGROUP(spi3_cs1_py4,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD020,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1717	PINGROUP(spi1_sck_pz3,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD028,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1718	PINGROUP(spi3_sck_py0,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD030,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1719	PINGROUP(spi1_cs1_pz7,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD038,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1720	PINGROUP(spi1_mosi_pz5,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD040,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1721	PINGROUP(spi3_mosi_py2,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD048,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1722	PINGROUP(uart2_tx_px4,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD050,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1723	PINGROUP(uart2_rx_px5,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD058,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1724	PINGROUP(uart2_rts_px6,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD060,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1725	PINGROUP(uart2_cts_px7,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD068,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1726	PINGROUP(uart5_tx_py5,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD070,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1727	PINGROUP(uart5_rx_py6,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD078,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1728	PINGROUP(uart5_rts_py7,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD080,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1729	PINGROUP(uart5_cts_pz0,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD088,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1730	PINGROUP(gpu_pwr_req_px0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0xD090,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1731	PINGROUP(gp_pwm3_px3,		GP,		RSVD1,		RSVD2,		RSVD3,		0xD098,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1732	PINGROUP(gp_pwm2_px2,		GP,		RSVD1,		RSVD2,		RSVD3,		0xD0A0,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1733	PINGROUP(cv_pwr_req_px1,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0xD0A8,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1734	PINGROUP(usb_vbus_en0_pz1,	USB,		RSVD1,		RSVD2,		RSVD3,		0xD0B0,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1735	PINGROUP(usb_vbus_en1_pz2,	USB,		RSVD1,		RSVD2,		RSVD3,		0xD0B8,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1736	PINGROUP(extperiph2_clk_pp1,	EXTPERIPH2,	RSVD1,		RSVD2,		RSVD3,		0x0000,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1737	PINGROUP(extperiph1_clk_pp0,	EXTPERIPH1,	RSVD1,		RSVD2,		RSVD3,		0x0008,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1738	PINGROUP(cam_i2c_sda_pp3,	I2C3,		VI0,		RSVD2,		VI1,		0x0010,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1739	PINGROUP(cam_i2c_scl_pp2,	I2C3,		VI0,		VI0_ALT,	VI1,		0x0018,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1740	PINGROUP(soc_gpio23_pp4,	VI0,		VI0_ALT,	VI1,		VI1_ALT,	0x0020,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1741	PINGROUP(soc_gpio24_pp5,	VI0,		SOC,		VI1,		VI1_ALT,	0x0028,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1742	PINGROUP(soc_gpio25_pp6,	VI0,		I2S5,		VI1,		DMIC1,		0x0030,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1743	PINGROUP(pwr_i2c_scl_pp7,	I2C5,		RSVD1,		RSVD2,		RSVD3,		0x0038,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1744	PINGROUP(pwr_i2c_sda_pq0,	I2C5,		RSVD1,		RSVD2,		RSVD3,		0x0040,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1745	PINGROUP(soc_gpio28_pq1,	VI0,		RSVD1,		VI1,		RSVD3,		0x0048,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1746	PINGROUP(soc_gpio29_pq2,	RSVD0,		NV,		RSVD2,		RSVD3,		0x0050,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1747	PINGROUP(soc_gpio30_pq3,	RSVD0,		WDT,		RSVD2,		RSVD3,		0x0058,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1748	PINGROUP(soc_gpio31_pq4,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x0060,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1749	PINGROUP(soc_gpio32_pq5,	RSVD0,		EXTPERIPH3,	DCB,		RSVD3,		0x0068,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1750	PINGROUP(soc_gpio33_pq6,	RSVD0,		EXTPERIPH4,	DCB,		RSVD3,		0x0070,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1751	PINGROUP(soc_gpio35_pq7,	RSVD0,		I2S5,		DMIC1,		RSVD3,		0x0078,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1752	PINGROUP(soc_gpio37_pr0,	GP,		I2S5,		DMIC4,		DSPK1,		0x0080,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1753	PINGROUP(soc_gpio56_pr1,	RSVD0,		I2S5,		DMIC4,		DSPK1,		0x0088,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1754	PINGROUP(uart1_cts_pr5,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x0090,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1755	PINGROUP(uart1_rts_pr4,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x0098,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1756	PINGROUP(uart1_rx_pr3,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x00A0,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1757	PINGROUP(uart1_tx_pr2,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x00A8,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1758	PINGROUP(cpu_pwr_req_pi5,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4000,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1759	PINGROUP(uart4_cts_ph6,		UARTD,		RSVD1,		I2S7,		RSVD3,		0x4008,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1760	PINGROUP(uart4_rts_ph5,		UARTD,		SPI4,		RSVD2,		RSVD3,		0x4010,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1761	PINGROUP(uart4_rx_ph4,		UARTD,		RSVD1,		I2S7,		RSVD3,		0x4018,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1762	PINGROUP(uart4_tx_ph3,		UARTD,		SPI4,		RSVD2,		RSVD3,		0x4020,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1763	PINGROUP(gen1_i2c_scl_pi3,	I2C1,		RSVD1,		RSVD2,		RSVD3,		0x4028,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1764	PINGROUP(gen1_i2c_sda_pi4,	I2C1,		RSVD1,		RSVD2,		RSVD3,		0x4030,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1765	PINGROUP(soc_gpio20_pg7,	RSVD0,		SDMMC1,		RSVD2,		RSVD3,		0x4038,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1766	PINGROUP(soc_gpio21_ph0,	RSVD0,		GP,		I2S7,		RSVD3,		0x4040,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1767	PINGROUP(soc_gpio22_ph1,	RSVD0,		RSVD1,		I2S7,		RSVD3,		0x4048,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1768	PINGROUP(soc_gpio13_pg0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4050,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1769	PINGROUP(soc_gpio14_pg1,	RSVD0,		SPI4,		RSVD2,		RSVD3,		0x4058,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1770	PINGROUP(soc_gpio15_pg2,	RSVD0,		SPI4,		RSVD2,		RSVD3,		0x4060,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1771	PINGROUP(soc_gpio16_pg3,	RSVD0,		SPI4,		RSVD2,		RSVD3,		0x4068,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1772	PINGROUP(soc_gpio17_pg4,	RSVD0,		CCLA,		RSVD2,		RSVD3,		0x4070,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1773	PINGROUP(soc_gpio18_pg5,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4078,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1774	PINGROUP(soc_gpio19_pg6,	GP,		RSVD1,		RSVD2,		RSVD3,		0x4080,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1775	PINGROUP(soc_gpio41_ph7,	RSVD0,		I2S2,		RSVD2,		RSVD3,		0x4088,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1776	PINGROUP(soc_gpio42_pi0,	RSVD0,		I2S2,		RSVD2,		RSVD3,		0x4090,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1777	PINGROUP(soc_gpio43_pi1,	RSVD0,		I2S2,		RSVD2,		RSVD3,		0x4098,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1778	PINGROUP(soc_gpio44_pi2,	RSVD0,		I2S2,		RSVD2,		RSVD3,		0x40A0,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1779	PINGROUP(soc_gpio06_ph2,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x40A8,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1780	PINGROUP(soc_gpio07_pi6,	GP,		RSVD1,		RSVD2,		RSVD3,		0x40B0,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1781	PINGROUP(dap4_sclk_pa4,		I2S4,		RSVD1,		RSVD2,		RSVD3,		0x2000,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1782	PINGROUP(dap4_dout_pa5,		I2S4,		RSVD1,		RSVD2,		RSVD3,		0x2008,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1783	PINGROUP(dap4_din_pa6,		I2S4,		RSVD1,		RSVD2,		RSVD3,		0x2010,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1784	PINGROUP(dap4_fs_pa7,		I2S4,		RSVD1,		RSVD2,		RSVD3,		0x2018,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1785	PINGROUP(dap6_sclk_pa0,		I2S6,		RSVD1,		RSVD2,		RSVD3,		0x2020,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1786	PINGROUP(dap6_dout_pa1,		I2S6,		RSVD1,		RSVD2,		RSVD3,		0x2028,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1787	PINGROUP(dap6_din_pa2,		I2S6,		RSVD1,		RSVD2,		RSVD3,		0x2030,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1788	PINGROUP(dap6_fs_pa3,		I2S6,		RSVD1,		RSVD2,		RSVD3,		0x2038,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1789	PINGROUP(soc_gpio45_pad0,	RSVD0,		I2S1,		RSVD2,		RSVD3,		0x18000,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1790	PINGROUP(soc_gpio46_pad1,	RSVD0,		I2S1,		RSVD2,		RSVD3,		0x18008,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1791	PINGROUP(soc_gpio47_pad2,	RSVD0,		I2S1,		RSVD2,		RSVD3,		0x18010,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1792	PINGROUP(soc_gpio48_pad3,	RSVD0,		I2S1,		RSVD2,		RSVD3,		0x18018,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1793	PINGROUP(soc_gpio57_pac4,	RSVD0,		I2S8,		RSVD2,		SDMMC1,		0x18020,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1794	PINGROUP(soc_gpio58_pac5,	RSVD0,		I2S8,		RSVD2,		SDMMC1,		0x18028,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1795	PINGROUP(soc_gpio59_pac6,	AUD,		I2S8,		RSVD2,		RSVD3,		0x18030,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1796	PINGROUP(soc_gpio60_pac7,	RSVD0,		I2S8,		NV,		IGPU,		0x18038,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1797	PINGROUP(spi5_cs0_pac3,		SPI5,		I2S3,		DMIC2,		RSVD3,		0x18040,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1798	PINGROUP(spi5_miso_pac1,	SPI5,		I2S3,		DSPK0,		RSVD3,		0x18048,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1799	PINGROUP(spi5_mosi_pac2,	SPI5,		I2S3,		DMIC2,		RSVD3,		0x18050,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1800	PINGROUP(spi5_sck_pac0,		SPI5,		I2S3,		DSPK0,		RSVD3,		0x18058,	0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1801 1802};1803 1804static const struct tegra_pinctrl_soc_data tegra234_pinctrl = {1805	.pins = tegra234_pins,1806	.npins = ARRAY_SIZE(tegra234_pins),1807	.functions = tegra234_functions,1808	.nfunctions = ARRAY_SIZE(tegra234_functions),1809	.groups = tegra234_groups,1810	.ngroups = ARRAY_SIZE(tegra234_groups),1811	.hsm_in_mux = false,1812	.schmitt_in_mux = true,1813	.drvtype_in_mux = true,1814	.sfsel_in_mux = true,1815};1816 1817static const struct pinctrl_pin_desc tegra234_aon_pins[] = {1818	PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA0, "CAN0_DOUT_PAA0"),1819	PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA1, "CAN0_DIN_PAA1"),1820	PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA2, "CAN1_DOUT_PAA2"),1821	PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA3, "CAN1_DIN_PAA3"),1822	PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"),1823	PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"),1824	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO49_PAA6, "SOC_GPIO49_PAA6"),1825	PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"),1826	PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"),1827	PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"),1828	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PBB2, "SOC_GPIO50_PBB2"),1829	PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"),1830	PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),1831	PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),1832	PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),1833	PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),1834	PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"),1835	PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),1836	PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),1837	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),1838	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),1839	PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),1840	PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),1841	PINCTRL_PIN(TEGRA_PIN_SCE_ERROR_PEE0, "SCE_ERROR_PEE0"),1842	PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"),1843	PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"),1844	PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"),1845	PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"),1846	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PEE5, "SOC_GPIO26_PEE5"),1847	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PEE6, "SOC_GPIO27_PEE6"),1848	PINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PEE7, "BOOTV_CTL_N_PEE7"),1849	PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PGG0, "HDMI_CEC_PGG0"),1850};1851 1852/* AON drive pin groups */1853#define	drive_touch_clk_pcc4			DRV_PINGROUP_ENTRY_Y(0x2004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1854#define	drive_uart3_rx_pcc6			DRV_PINGROUP_ENTRY_Y(0x200c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1855#define	drive_uart3_tx_pcc5			DRV_PINGROUP_ENTRY_Y(0x2014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1856#define	drive_gen8_i2c_sda_pdd2			DRV_PINGROUP_ENTRY_Y(0x201c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1857#define	drive_gen8_i2c_scl_pdd1			DRV_PINGROUP_ENTRY_Y(0x2024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1858#define	drive_spi2_mosi_pcc2			DRV_PINGROUP_ENTRY_Y(0x202c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1859#define	drive_gen2_i2c_scl_pcc7			DRV_PINGROUP_ENTRY_Y(0x2034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1860#define	drive_spi2_cs0_pcc3			DRV_PINGROUP_ENTRY_Y(0x203c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1861#define	drive_gen2_i2c_sda_pdd0			DRV_PINGROUP_ENTRY_Y(0x2044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1862#define	drive_spi2_sck_pcc0			DRV_PINGROUP_ENTRY_Y(0x204c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1863#define	drive_spi2_miso_pcc1			DRV_PINGROUP_ENTRY_Y(0x2054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1864#define	drive_can1_dout_paa2			DRV_PINGROUP_ENTRY_Y(0x3004,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1865#define	drive_can1_din_paa3			DRV_PINGROUP_ENTRY_Y(0x300c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1866#define	drive_can0_dout_paa0			DRV_PINGROUP_ENTRY_Y(0x3014,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1867#define	drive_can0_din_paa1			DRV_PINGROUP_ENTRY_Y(0x301c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1868#define	drive_can0_stb_paa4			DRV_PINGROUP_ENTRY_Y(0x3024,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1869#define	drive_can0_en_paa5			DRV_PINGROUP_ENTRY_Y(0x302c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1870#define	drive_soc_gpio49_paa6			DRV_PINGROUP_ENTRY_Y(0x3034,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1871#define	drive_can0_err_paa7			DRV_PINGROUP_ENTRY_Y(0x303c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1872#define	drive_can1_stb_pbb0			DRV_PINGROUP_ENTRY_Y(0x3044,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1873#define	drive_can1_en_pbb1			DRV_PINGROUP_ENTRY_Y(0x304c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1874#define	drive_soc_gpio50_pbb2			DRV_PINGROUP_ENTRY_Y(0x3054,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1875#define	drive_can1_err_pbb3			DRV_PINGROUP_ENTRY_Y(0x305c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)1876#define	drive_sce_error_pee0			DRV_PINGROUP_ENTRY_Y(0x1014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1877#define	drive_batt_oc_pee3			DRV_PINGROUP_ENTRY_Y(0x1024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1878#define	drive_bootv_ctl_n_pee7			DRV_PINGROUP_ENTRY_Y(0x102c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1879#define	drive_power_on_pee4			DRV_PINGROUP_ENTRY_Y(0x103c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1880#define	drive_soc_gpio26_pee5			DRV_PINGROUP_ENTRY_Y(0x1044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1881#define	drive_soc_gpio27_pee6			DRV_PINGROUP_ENTRY_Y(0x104c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1882#define	drive_ao_retention_n_pee2		DRV_PINGROUP_ENTRY_Y(0x1054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1883#define	drive_vcomp_alert_pee1			DRV_PINGROUP_ENTRY_Y(0x105c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1884#define	drive_hdmi_cec_pgg0			DRV_PINGROUP_ENTRY_Y(0x1064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)1885 1886static const struct tegra_pingroup tegra234_aon_groups[] = {1887	PINGROUP(touch_clk_pcc4,	GP,		TOUCH,		RSVD2,		RSVD3,		0x2000,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1888	PINGROUP(uart3_rx_pcc6,		UARTC,		UARTJ,		RSVD2,		RSVD3,		0x2008,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1889	PINGROUP(uart3_tx_pcc5,		UARTC,		UARTJ,		RSVD2,		RSVD3,		0x2010,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1890	PINGROUP(gen8_i2c_sda_pdd2,	I2C8,		RSVD1,		RSVD2,		RSVD3,		0x2018,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1891	PINGROUP(gen8_i2c_scl_pdd1,	I2C8,		RSVD1,		RSVD2,		RSVD3,		0x2020,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1892	PINGROUP(spi2_mosi_pcc2,	SPI2,		RSVD1,		RSVD2,		RSVD3,		0x2028,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1893	PINGROUP(gen2_i2c_scl_pcc7,	I2C2,		RSVD1,		RSVD2,		RSVD3,		0x2030,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1894	PINGROUP(spi2_cs0_pcc3,		SPI2,		RSVD1,		RSVD2,		RSVD3,		0x2038,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1895	PINGROUP(gen2_i2c_sda_pdd0,	I2C2,		RSVD1,		RSVD2,		RSVD3,		0x2040,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1896	PINGROUP(spi2_sck_pcc0,		SPI2,		RSVD1,		RSVD2,		RSVD3,		0x2048,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1897	PINGROUP(spi2_miso_pcc1,	SPI2,		RSVD1,		RSVD2,		RSVD3,		0x2050,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1898	PINGROUP(can1_dout_paa2,	CAN1,		RSVD1,		RSVD2,		RSVD3,		0x3000,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1899	PINGROUP(can1_din_paa3,		CAN1,		RSVD1,		RSVD2,		RSVD3,		0x3008,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1900	PINGROUP(can0_dout_paa0,	CAN0,		RSVD1,		RSVD2,		RSVD3,		0x3010,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1901	PINGROUP(can0_din_paa1,		CAN0,		RSVD1,		RSVD2,		RSVD3,		0x3018,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1902	PINGROUP(can0_stb_paa4,		RSVD0,		WDT,		TSC,		TSC_ALT,	0x3020,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1903	PINGROUP(can0_en_paa5,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3028,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1904	PINGROUP(soc_gpio49_paa6,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3030,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1905	PINGROUP(can0_err_paa7,		RSVD0,		TSC,		RSVD2,		TSC_ALT,	0x3038,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1906	PINGROUP(can1_stb_pbb0,		RSVD0,		DMIC3,		DMIC5,		RSVD3,		0x3040,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1907	PINGROUP(can1_en_pbb1,		RSVD0,		DMIC3,		DMIC5,		RSVD3,		0x3048,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1908	PINGROUP(soc_gpio50_pbb2,	RSVD0,		TSC,		RSVD2,		TSC_ALT,	0x3050,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1909	PINGROUP(can1_err_pbb3,		RSVD0,		TSC,		RSVD2,		TSC_ALT,	0x3058,		0,	Y,	-1,	5,	6,	-1,	9,	10,	12),1910	PINGROUP(sce_error_pee0,	SCE,		RSVD1,		RSVD2,		RSVD3,		0x1010,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1911	PINGROUP(batt_oc_pee3,		SOC,		RSVD1,		RSVD2,		RSVD3,		0x1020,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1912	PINGROUP(bootv_ctl_n_pee7,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1028,		0,	Y,	-1,	7,	6,	8,	-1,	10,	12),1913	PINGROUP(power_on_pee4,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1038,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1914	PINGROUP(soc_gpio26_pee5,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1040,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1915	PINGROUP(soc_gpio27_pee6,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1048,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1916	PINGROUP(ao_retention_n_pee2,	GPIO,		LED,		RSVD2,		ISTCTRL,	0x1050,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1917	PINGROUP(vcomp_alert_pee1,	SOC,		RSVD1,		RSVD2,		RSVD3,		0x1058,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1918	PINGROUP(hdmi_cec_pgg0,		HDMI,		RSVD1,		RSVD2,		RSVD3,		0x1060,		0,	Y,	5,	7,	6,	8,	-1,	10,	12),1919};1920 1921static const struct tegra_pinctrl_soc_data tegra234_pinctrl_aon = {1922	.pins = tegra234_aon_pins,1923	.npins = ARRAY_SIZE(tegra234_aon_pins),1924	.functions = tegra234_functions,1925	.nfunctions = ARRAY_SIZE(tegra234_functions),1926	.groups = tegra234_aon_groups,1927	.ngroups = ARRAY_SIZE(tegra234_aon_groups),1928	.hsm_in_mux = false,1929	.schmitt_in_mux = true,1930	.drvtype_in_mux = true,1931	.sfsel_in_mux = true,1932};1933 1934static int tegra234_pinctrl_probe(struct platform_device *pdev)1935{1936	const struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev);1937 1938	return tegra_pinctrl_probe(pdev, soc);1939}1940 1941static const struct of_device_id tegra234_pinctrl_of_match[] = {1942	{ .compatible = "nvidia,tegra234-pinmux", .data = &tegra234_pinctrl},1943	{ .compatible = "nvidia,tegra234-pinmux-aon", .data = &tegra234_pinctrl_aon },1944	{ }1945};1946MODULE_DEVICE_TABLE(of, tegra234_pinctrl_of_match);1947 1948static struct platform_driver tegra234_pinctrl_driver = {1949	.driver = {1950		.name = "tegra234-pinctrl",1951		.of_match_table = tegra234_pinctrl_of_match,1952	},1953	.probe = tegra234_pinctrl_probe,1954};1955 1956static int __init tegra234_pinctrl_init(void)1957{1958	return platform_driver_register(&tegra234_pinctrl_driver);1959}1960arch_initcall(tegra234_pinctrl_init);1961