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1/*2 * Support for configuration of IO Delay module found on Texas Instruments SoCs3 * such as DRA74 *5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/6 *7 * This file is licensed under the terms of the GNU General Public8 * License version 2. This program is licensed "as is" without any9 * warranty of any kind, whether express or implied.10 */11 12#include <linux/err.h>13#include <linux/init.h>14#include <linux/io.h>15#include <linux/module.h>16#include <linux/of.h>17#include <linux/platform_device.h>18#include <linux/property.h>19#include <linux/regmap.h>20#include <linux/seq_file.h>21#include <linux/slab.h>22 23#include <linux/pinctrl/pinconf-generic.h>24#include <linux/pinctrl/pinconf.h>25#include <linux/pinctrl/pinctrl.h>26 27#include "../core.h"28#include "../devicetree.h"29 30#define DRIVER_NAME "ti-iodelay"31 32/**33 * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance34 * @signature_mask: CONFIG_REG mask for the signature bits (see TRM)35 * @signature_value: CONFIG_REG signature value to be written (see TRM)36 * @lock_mask: CONFIG_REG mask for the lock bits (see TRM)37 * @lock_val: CONFIG_REG lock value for the lock bits (see TRM)38 * @unlock_val:CONFIG_REG unlock value for the lock bits (see TRM)39 * @binary_data_coarse_mask: CONFIG_REG coarse mask (see TRM)40 * @binary_data_fine_mask: CONFIG_REG fine mask (see TRM)41 * @reg_refclk_offset: Refclk register offset42 * @refclk_period_mask: Refclk mask43 * @reg_coarse_offset: Coarse register configuration offset44 * @coarse_delay_count_mask: Coarse delay count mask45 * @coarse_ref_count_mask: Coarse ref count mask46 * @reg_fine_offset: Fine register configuration offset47 * @fine_delay_count_mask: Fine delay count mask48 * @fine_ref_count_mask: Fine ref count mask49 * @reg_global_lock_offset: Global iodelay module lock register offset50 * @global_lock_mask: Lock mask51 * @global_unlock_val: Unlock value52 * @global_lock_val: Lock value53 * @reg_start_offset: Offset to iodelay registers after the CONFIG_REG_0 to 854 * @reg_nr_per_pin: Number of iodelay registers for each pin55 * @regmap_config: Regmap configuration for the IODelay region56 */57struct ti_iodelay_reg_data {58 u32 signature_mask;59 u32 signature_value;60 u32 lock_mask;61 u32 lock_val;62 u32 unlock_val;63 u32 binary_data_coarse_mask;64 u32 binary_data_fine_mask;65 66 u32 reg_refclk_offset;67 u32 refclk_period_mask;68 69 u32 reg_coarse_offset;70 u32 coarse_delay_count_mask;71 u32 coarse_ref_count_mask;72 73 u32 reg_fine_offset;74 u32 fine_delay_count_mask;75 u32 fine_ref_count_mask;76 77 u32 reg_global_lock_offset;78 u32 global_lock_mask;79 u32 global_unlock_val;80 u32 global_lock_val;81 82 u32 reg_start_offset;83 u32 reg_nr_per_pin;84 85 const struct regmap_config *regmap_config;86};87 88/**89 * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM)90 * @coarse_ref_count: Coarse reference count91 * @coarse_delay_count: Coarse delay count92 * @fine_ref_count: Fine reference count93 * @fine_delay_count: Fine Delay count94 * @ref_clk_period: Reference Clock period95 * @cdpe: Coarse delay parameter96 * @fdpe: Fine delay parameter97 */98struct ti_iodelay_reg_values {99 u16 coarse_ref_count;100 u16 coarse_delay_count;101 102 u16 fine_ref_count;103 u16 fine_delay_count;104 105 u16 ref_clk_period;106 107 u32 cdpe;108 u32 fdpe;109};110 111/**112 * struct ti_iodelay_cfg - Description of each configuration parameters113 * @offset: Configuration register offset114 * @a_delay: Agnostic Delay (in ps)115 * @g_delay: Gnostic Delay (in ps)116 */117struct ti_iodelay_cfg {118 u16 offset;119 u16 a_delay;120 u16 g_delay;121};122 123/**124 * struct ti_iodelay_pingroup - Structure that describes one group125 * @cfg: configuration array for the pin (from dt)126 * @ncfg: number of configuration values allocated127 * @config: pinconf "Config" - currently a dummy value128 */129struct ti_iodelay_pingroup {130 struct ti_iodelay_cfg *cfg;131 int ncfg;132 unsigned long config;133};134 135/**136 * struct ti_iodelay_device - Represents information for a iodelay instance137 * @dev: Device pointer138 * @phys_base: Physical address base of the iodelay device139 * @reg_base: Virtual address base of the iodelay device140 * @regmap: Regmap for this iodelay instance141 * @pctl: Pinctrl device142 * @desc: pinctrl descriptor for pctl143 * @pa: pinctrl pin wise description144 * @reg_data: Register definition data for the IODelay instance145 * @reg_init_conf_values: Initial configuration values.146 */147struct ti_iodelay_device {148 struct device *dev;149 unsigned long phys_base;150 void __iomem *reg_base;151 struct regmap *regmap;152 153 struct pinctrl_dev *pctl;154 struct pinctrl_desc desc;155 struct pinctrl_pin_desc *pa;156 157 const struct ti_iodelay_reg_data *reg_data;158 struct ti_iodelay_reg_values reg_init_conf_values;159};160 161/**162 * ti_iodelay_extract() - extract bits for a field163 * @val: Register value164 * @mask: Mask165 *166 * Return: extracted value which is appropriately shifted167 */168static inline u32 ti_iodelay_extract(u32 val, u32 mask)169{170 return (val & mask) >> __ffs(mask);171}172 173/**174 * ti_iodelay_compute_dpe() - Compute equation for delay parameter175 * @period: Period to use176 * @ref: Reference Count177 * @delay: Delay count178 * @delay_m: Delay multiplier179 *180 * Return: Computed delay parameter181 */182static inline u32 ti_iodelay_compute_dpe(u16 period, u16 ref, u16 delay,183 u16 delay_m)184{185 u64 m, d;186 187 /* Handle overflow conditions */188 m = 10 * (u64)period * (u64)ref;189 d = 2 * (u64)delay * (u64)delay_m;190 191 /* Truncate result back to 32 bits */192 return div64_u64(m, d);193}194 195/**196 * ti_iodelay_pinconf_set() - Configure the pin configuration197 * @iod: iodelay device198 * @cfg: Configuration199 *200 * Update the configuration register as per TRM and lockup once done.201 * *IMPORTANT NOTE* SoC TRM does recommend doing iodelay programmation only202 * while in Isolation. But, then, isolation also implies that every pin203 * on the SoC (including DDR) will be isolated out. The only benefit being204 * a glitchless configuration, However, the intent of this driver is purely205 * to support a "glitchy" configuration where applicable.206 *207 * Return: 0 in case of success, else appropriate error value208 */209static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod,210 struct ti_iodelay_cfg *cfg)211{212 const struct ti_iodelay_reg_data *reg = iod->reg_data;213 struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values;214 struct device *dev = iod->dev;215 u32 g_delay_coarse, g_delay_fine;216 u32 a_delay_coarse, a_delay_fine;217 u32 c_elements, f_elements;218 u32 total_delay;219 u32 reg_mask, reg_val, tmp_val;220 int r;221 222 /* NOTE: Truncation is expected in all division below */223 g_delay_coarse = cfg->g_delay / 920;224 g_delay_fine = ((cfg->g_delay % 920) * 10) / 60;225 226 a_delay_coarse = cfg->a_delay / ival->cdpe;227 a_delay_fine = ((cfg->a_delay % ival->cdpe) * 10) / ival->fdpe;228 229 c_elements = g_delay_coarse + a_delay_coarse;230 f_elements = (g_delay_fine + a_delay_fine) / 10;231 232 if (f_elements > 22) {233 total_delay = c_elements * ival->cdpe + f_elements * ival->fdpe;234 c_elements = total_delay / ival->cdpe;235 f_elements = (total_delay % ival->cdpe) / ival->fdpe;236 }237 238 reg_mask = reg->signature_mask;239 reg_val = reg->signature_value << __ffs(reg->signature_mask);240 241 reg_mask |= reg->binary_data_coarse_mask;242 tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask);243 if (tmp_val & ~reg->binary_data_coarse_mask) {244 dev_err(dev, "Masking overflow of coarse elements %08x\n",245 tmp_val);246 tmp_val &= reg->binary_data_coarse_mask;247 }248 reg_val |= tmp_val;249 250 reg_mask |= reg->binary_data_fine_mask;251 tmp_val = f_elements << __ffs(reg->binary_data_fine_mask);252 if (tmp_val & ~reg->binary_data_fine_mask) {253 dev_err(dev, "Masking overflow of fine elements %08x\n",254 tmp_val);255 tmp_val &= reg->binary_data_fine_mask;256 }257 reg_val |= tmp_val;258 259 /*260 * NOTE: we leave the iodelay values unlocked - this is to work around261 * situations such as those found with mmc mode change.262 * However, this leaves open any unwarranted changes to padconf register263 * impacting iodelay configuration. Use with care!264 */265 reg_mask |= reg->lock_mask;266 reg_val |= reg->unlock_val << __ffs(reg->lock_mask);267 r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val);268 269 dev_dbg(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n",270 cfg->offset, cfg->a_delay, cfg->g_delay, c_elements,271 f_elements, reg_val);272 273 return r;274}275 276/**277 * ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device278 * @data: IODelay device279 *280 * Deinitialize the IODelay device (basically just lock the region back up.281 */282static void ti_iodelay_pinconf_deinit_dev(void *data)283{284 struct ti_iodelay_device *iod = data;285 const struct ti_iodelay_reg_data *reg = iod->reg_data;286 287 /* lock the iodelay region back again */288 regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,289 reg->global_lock_mask, reg->global_lock_val);290}291 292/**293 * ti_iodelay_pinconf_init_dev() - Initialize IODelay device294 * @iod: iodelay device295 *296 * Unlocks the iodelay region, computes the common parameters297 *298 * Return: 0 in case of success, else appropriate error value299 */300static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod)301{302 const struct ti_iodelay_reg_data *reg = iod->reg_data;303 struct device *dev = iod->dev;304 struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values;305 u32 val;306 int r;307 308 /* unlock the iodelay region */309 r = regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,310 reg->global_lock_mask, reg->global_unlock_val);311 if (r)312 return r;313 314 r = devm_add_action_or_reset(iod->dev, ti_iodelay_pinconf_deinit_dev,315 iod);316 if (r)317 return r;318 319 /* Read up Recalibration sequence done by bootloader */320 r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val);321 if (r)322 return r;323 ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask);324 dev_dbg(dev, "refclk_period=0x%04x\n", ival->ref_clk_period);325 326 r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val);327 if (r)328 return r;329 ival->coarse_ref_count =330 ti_iodelay_extract(val, reg->coarse_ref_count_mask);331 ival->coarse_delay_count =332 ti_iodelay_extract(val, reg->coarse_delay_count_mask);333 if (!ival->coarse_delay_count) {334 dev_err(dev, "Invalid Coarse delay count (0) (reg=0x%08x)\n",335 val);336 return -EINVAL;337 }338 ival->cdpe = ti_iodelay_compute_dpe(ival->ref_clk_period,339 ival->coarse_ref_count,340 ival->coarse_delay_count, 88);341 if (!ival->cdpe) {342 dev_err(dev, "Invalid cdpe computed params = %d %d %d\n",343 ival->ref_clk_period, ival->coarse_ref_count,344 ival->coarse_delay_count);345 return -EINVAL;346 }347 dev_dbg(iod->dev, "coarse: ref=0x%04x delay=0x%04x cdpe=0x%08x\n",348 ival->coarse_ref_count, ival->coarse_delay_count, ival->cdpe);349 350 r = regmap_read(iod->regmap, reg->reg_fine_offset, &val);351 if (r)352 return r;353 ival->fine_ref_count =354 ti_iodelay_extract(val, reg->fine_ref_count_mask);355 ival->fine_delay_count =356 ti_iodelay_extract(val, reg->fine_delay_count_mask);357 if (!ival->fine_delay_count) {358 dev_err(dev, "Invalid Fine delay count (0) (reg=0x%08x)\n",359 val);360 return -EINVAL;361 }362 ival->fdpe = ti_iodelay_compute_dpe(ival->ref_clk_period,363 ival->fine_ref_count,364 ival->fine_delay_count, 264);365 if (!ival->fdpe) {366 dev_err(dev, "Invalid fdpe(0) computed params = %d %d %d\n",367 ival->ref_clk_period, ival->fine_ref_count,368 ival->fine_delay_count);369 return -EINVAL;370 }371 dev_dbg(iod->dev, "fine: ref=0x%04x delay=0x%04x fdpe=0x%08x\n",372 ival->fine_ref_count, ival->fine_delay_count, ival->fdpe);373 374 return 0;375}376 377/**378 * ti_iodelay_get_pingroup() - Find the group mapped by a group selector379 * @iod: iodelay device380 * @selector: Group Selector381 *382 * Return: Corresponding group representing group selector383 */384static struct ti_iodelay_pingroup *385ti_iodelay_get_pingroup(struct ti_iodelay_device *iod, unsigned int selector)386{387 struct group_desc *g;388 389 g = pinctrl_generic_get_group(iod->pctl, selector);390 if (!g) {391 dev_err(iod->dev, "%s could not find pingroup %i\n", __func__,392 selector);393 394 return NULL;395 }396 397 return g->data;398}399 400/**401 * ti_iodelay_offset_to_pin() - get a pin index based on the register offset402 * @iod: iodelay driver instance403 * @offset: register offset from the base404 */405static int ti_iodelay_offset_to_pin(struct ti_iodelay_device *iod,406 unsigned int offset)407{408 const struct ti_iodelay_reg_data *r = iod->reg_data;409 unsigned int index;410 411 if (offset > r->regmap_config->max_register) {412 dev_err(iod->dev, "mux offset out of range: 0x%x (0x%x)\n",413 offset, r->regmap_config->max_register);414 return -EINVAL;415 }416 417 index = (offset - r->reg_start_offset) / r->regmap_config->reg_stride;418 index /= r->reg_nr_per_pin;419 420 return index;421}422 423/**424 * ti_iodelay_node_iterator() - Iterate iodelay node425 * @pctldev: Pin controller driver426 * @np: Device node427 * @pinctrl_spec: Parsed arguments from device tree428 * @pins: Array of pins in the pin group429 * @pin_index: Pin index in the pin array430 * @data: Pin controller driver specific data431 *432 */433static int ti_iodelay_node_iterator(struct pinctrl_dev *pctldev,434 struct device_node *np,435 const struct of_phandle_args *pinctrl_spec,436 int *pins, int pin_index, void *data)437{438 struct ti_iodelay_device *iod;439 struct ti_iodelay_cfg *cfg = data;440 const struct ti_iodelay_reg_data *r;441 struct pinctrl_pin_desc *pd;442 int pin;443 444 iod = pinctrl_dev_get_drvdata(pctldev);445 if (!iod)446 return -EINVAL;447 448 r = iod->reg_data;449 450 if (pinctrl_spec->args_count < r->reg_nr_per_pin) {451 dev_err(iod->dev, "invalid args_count for spec: %i\n",452 pinctrl_spec->args_count);453 454 return -EINVAL;455 }456 457 /* Index plus two value cells */458 cfg[pin_index].offset = pinctrl_spec->args[0];459 cfg[pin_index].a_delay = pinctrl_spec->args[1] & 0xffff;460 cfg[pin_index].g_delay = pinctrl_spec->args[2] & 0xffff;461 462 pin = ti_iodelay_offset_to_pin(iod, cfg[pin_index].offset);463 if (pin < 0) {464 dev_err(iod->dev, "could not add functions for %pOFn %ux\n",465 np, cfg[pin_index].offset);466 return -ENODEV;467 }468 pins[pin_index] = pin;469 470 pd = &iod->pa[pin];471 pd->drv_data = &cfg[pin_index];472 473 dev_dbg(iod->dev, "%pOFn offset=%x a_delay = %d g_delay = %d\n",474 np, cfg[pin_index].offset, cfg[pin_index].a_delay,475 cfg[pin_index].g_delay);476 477 return 0;478}479 480/**481 * ti_iodelay_dt_node_to_map() - Map a device tree node to appropriate group482 * @pctldev: pinctrl device representing IODelay device483 * @np: Node Pointer (device tree)484 * @map: Pinctrl Map returned back to pinctrl framework485 * @num_maps: Number of maps (1)486 *487 * Maps the device tree description into a group of configuration parameters488 * for iodelay block entry.489 *490 * Return: 0 in case of success, else appropriate error value491 */492static int ti_iodelay_dt_node_to_map(struct pinctrl_dev *pctldev,493 struct device_node *np,494 struct pinctrl_map **map,495 unsigned int *num_maps)496{497 struct ti_iodelay_device *iod;498 struct ti_iodelay_cfg *cfg;499 struct ti_iodelay_pingroup *g;500 const char *name = "pinctrl-pin-array";501 int rows, *pins, error = -EINVAL, i;502 503 iod = pinctrl_dev_get_drvdata(pctldev);504 if (!iod)505 return -EINVAL;506 507 rows = pinctrl_count_index_with_args(np, name);508 if (rows < 0)509 return rows;510 511 *map = devm_kzalloc(iod->dev, sizeof(**map), GFP_KERNEL);512 if (!*map)513 return -ENOMEM;514 *num_maps = 0;515 516 g = devm_kzalloc(iod->dev, sizeof(*g), GFP_KERNEL);517 if (!g) {518 error = -ENOMEM;519 goto free_map;520 }521 522 pins = devm_kcalloc(iod->dev, rows, sizeof(*pins), GFP_KERNEL);523 if (!pins) {524 error = -ENOMEM;525 goto free_group;526 }527 528 cfg = devm_kcalloc(iod->dev, rows, sizeof(*cfg), GFP_KERNEL);529 if (!cfg) {530 error = -ENOMEM;531 goto free_pins;532 }533 534 for (i = 0; i < rows; i++) {535 struct of_phandle_args pinctrl_spec;536 537 error = pinctrl_parse_index_with_args(np, name, i,538 &pinctrl_spec);539 if (error)540 goto free_data;541 542 error = ti_iodelay_node_iterator(pctldev, np, &pinctrl_spec,543 pins, i, cfg);544 if (error)545 goto free_data;546 }547 548 g->cfg = cfg;549 g->ncfg = i;550 g->config = PIN_CONFIG_END;551 552 error = pinctrl_generic_add_group(iod->pctl, np->name, pins, i, g);553 if (error < 0)554 goto free_data;555 556 (*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP;557 (*map)->data.configs.group_or_pin = np->name;558 (*map)->data.configs.configs = &g->config;559 (*map)->data.configs.num_configs = 1;560 *num_maps = 1;561 562 return 0;563 564free_data:565 devm_kfree(iod->dev, cfg);566free_pins:567 devm_kfree(iod->dev, pins);568free_group:569 devm_kfree(iod->dev, g);570free_map:571 devm_kfree(iod->dev, *map);572 573 return error;574}575 576/**577 * ti_iodelay_pinconf_group_get() - Get the group configuration578 * @pctldev: pinctrl device representing IODelay device579 * @selector: Group selector580 * @config: Configuration returned581 *582 * Return: The configuration if the group is valid, else returns -EINVAL583 */584static int ti_iodelay_pinconf_group_get(struct pinctrl_dev *pctldev,585 unsigned int selector,586 unsigned long *config)587{588 struct ti_iodelay_device *iod;589 struct ti_iodelay_pingroup *group;590 591 iod = pinctrl_dev_get_drvdata(pctldev);592 group = ti_iodelay_get_pingroup(iod, selector);593 594 if (!group)595 return -EINVAL;596 597 *config = group->config;598 return 0;599}600 601/**602 * ti_iodelay_pinconf_group_set() - Configure the groups of pins603 * @pctldev: pinctrl device representing IODelay device604 * @selector: Group selector605 * @configs: Configurations606 * @num_configs: Number of configurations607 *608 * Return: 0 if all went fine, else appropriate error value.609 */610static int ti_iodelay_pinconf_group_set(struct pinctrl_dev *pctldev,611 unsigned int selector,612 unsigned long *configs,613 unsigned int num_configs)614{615 struct ti_iodelay_device *iod;616 struct device *dev;617 struct ti_iodelay_pingroup *group;618 int i;619 620 iod = pinctrl_dev_get_drvdata(pctldev);621 dev = iod->dev;622 group = ti_iodelay_get_pingroup(iod, selector);623 624 if (num_configs != 1) {625 dev_err(dev, "Unsupported number of configurations %d\n",626 num_configs);627 return -EINVAL;628 }629 630 if (*configs != PIN_CONFIG_END) {631 dev_err(dev, "Unsupported configuration\n");632 return -EINVAL;633 }634 635 for (i = 0; i < group->ncfg; i++) {636 if (ti_iodelay_pinconf_set(iod, &group->cfg[i]))637 return -ENOTSUPP;638 }639 640 return 0;641}642 643#ifdef CONFIG_DEBUG_FS644/**645 * ti_iodelay_pin_to_offset() - get pin register offset based on the pin index646 * @iod: iodelay driver instance647 * @selector: Pin index648 */649static unsigned int ti_iodelay_pin_to_offset(struct ti_iodelay_device *iod,650 unsigned int selector)651{652 const struct ti_iodelay_reg_data *r = iod->reg_data;653 unsigned int offset;654 655 offset = selector * r->regmap_config->reg_stride;656 offset *= r->reg_nr_per_pin;657 offset += r->reg_start_offset;658 659 return offset;660}661 662static void ti_iodelay_pin_dbg_show(struct pinctrl_dev *pctldev,663 struct seq_file *s,664 unsigned int pin)665{666 struct ti_iodelay_device *iod;667 struct pinctrl_pin_desc *pd;668 struct ti_iodelay_cfg *cfg;669 const struct ti_iodelay_reg_data *r;670 unsigned long offset;671 u32 in, oen, out;672 673 iod = pinctrl_dev_get_drvdata(pctldev);674 r = iod->reg_data;675 676 offset = ti_iodelay_pin_to_offset(iod, pin);677 pd = &iod->pa[pin];678 cfg = pd->drv_data;679 680 regmap_read(iod->regmap, offset, &in);681 regmap_read(iod->regmap, offset + r->regmap_config->reg_stride, &oen);682 regmap_read(iod->regmap, offset + r->regmap_config->reg_stride * 2,683 &out);684 685 seq_printf(s, "%lx a: %i g: %i (%08x %08x %08x) %s ",686 iod->phys_base + offset,687 cfg ? cfg->a_delay : -1,688 cfg ? cfg->g_delay : -1,689 in, oen, out, DRIVER_NAME);690}691 692/**693 * ti_iodelay_pinconf_group_dbg_show() - show the group information694 * @pctldev: Show the group information695 * @s: Sequence file696 * @selector: Group selector697 *698 * Provide the configuration information of the selected group699 */700static void ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,701 struct seq_file *s,702 unsigned int selector)703{704 struct ti_iodelay_device *iod;705 struct ti_iodelay_pingroup *group;706 int i;707 708 iod = pinctrl_dev_get_drvdata(pctldev);709 group = ti_iodelay_get_pingroup(iod, selector);710 if (!group)711 return;712 713 for (i = 0; i < group->ncfg; i++) {714 struct ti_iodelay_cfg *cfg;715 u32 reg = 0;716 717 cfg = &group->cfg[i];718 regmap_read(iod->regmap, cfg->offset, ®);719 seq_printf(s, "\n\t0x%08x = 0x%08x (%3d, %3d)",720 cfg->offset, reg, cfg->a_delay, cfg->g_delay);721 }722}723#endif724 725static const struct pinctrl_ops ti_iodelay_pinctrl_ops = {726 .get_groups_count = pinctrl_generic_get_group_count,727 .get_group_name = pinctrl_generic_get_group_name,728 .get_group_pins = pinctrl_generic_get_group_pins,729#ifdef CONFIG_DEBUG_FS730 .pin_dbg_show = ti_iodelay_pin_dbg_show,731#endif732 .dt_node_to_map = ti_iodelay_dt_node_to_map,733};734 735static const struct pinconf_ops ti_iodelay_pinctrl_pinconf_ops = {736 .pin_config_group_get = ti_iodelay_pinconf_group_get,737 .pin_config_group_set = ti_iodelay_pinconf_group_set,738#ifdef CONFIG_DEBUG_FS739 .pin_config_group_dbg_show = ti_iodelay_pinconf_group_dbg_show,740#endif741};742 743/**744 * ti_iodelay_alloc_pins() - Allocate structures needed for pins for iodelay745 * @dev: Device pointer746 * @iod: iodelay device747 * @base_phy: Base Physical Address748 *749 * Return: 0 if all went fine, else appropriate error value.750 */751static int ti_iodelay_alloc_pins(struct device *dev,752 struct ti_iodelay_device *iod, u32 base_phy)753{754 const struct ti_iodelay_reg_data *r = iod->reg_data;755 struct pinctrl_pin_desc *pin;756 u32 phy_reg;757 int nr_pins, i;758 759 nr_pins = ti_iodelay_offset_to_pin(iod, r->regmap_config->max_register);760 dev_dbg(dev, "Allocating %i pins\n", nr_pins);761 762 iod->pa = devm_kcalloc(dev, nr_pins, sizeof(*iod->pa), GFP_KERNEL);763 if (!iod->pa)764 return -ENOMEM;765 766 iod->desc.pins = iod->pa;767 iod->desc.npins = nr_pins;768 769 phy_reg = r->reg_start_offset + base_phy;770 771 for (i = 0; i < nr_pins; i++, phy_reg += 4) {772 pin = &iod->pa[i];773 pin->number = i;774 }775 776 return 0;777}778 779static const struct regmap_config dra7_iodelay_regmap_config = {780 .reg_bits = 32,781 .reg_stride = 4,782 .val_bits = 32,783 .max_register = 0xd1c,784};785 786static const struct ti_iodelay_reg_data dra7_iodelay_data = {787 .signature_mask = 0x0003f000,788 .signature_value = 0x29,789 .lock_mask = 0x00000400,790 .lock_val = 1,791 .unlock_val = 0,792 .binary_data_coarse_mask = 0x000003e0,793 .binary_data_fine_mask = 0x0000001f,794 795 .reg_refclk_offset = 0x14,796 .refclk_period_mask = 0xffff,797 798 .reg_coarse_offset = 0x18,799 .coarse_delay_count_mask = 0xffff0000,800 .coarse_ref_count_mask = 0x0000ffff,801 802 .reg_fine_offset = 0x1C,803 .fine_delay_count_mask = 0xffff0000,804 .fine_ref_count_mask = 0x0000ffff,805 806 .reg_global_lock_offset = 0x2c,807 .global_lock_mask = 0x0000ffff,808 .global_unlock_val = 0x0000aaaa,809 .global_lock_val = 0x0000aaab,810 811 .reg_start_offset = 0x30,812 .reg_nr_per_pin = 3,813 .regmap_config = &dra7_iodelay_regmap_config,814};815 816static const struct of_device_id ti_iodelay_of_match[] = {817 {.compatible = "ti,dra7-iodelay", .data = &dra7_iodelay_data},818 { /* Hopefully no more.. */ },819};820MODULE_DEVICE_TABLE(of, ti_iodelay_of_match);821 822/**823 * ti_iodelay_probe() - Standard probe824 * @pdev: platform device825 *826 * Return: 0 if all went fine, else appropriate error value.827 */828static int ti_iodelay_probe(struct platform_device *pdev)829{830 struct device *dev = &pdev->dev;831 struct device_node *np __free(device_node) = of_node_get(dev->of_node);832 struct resource *res;833 struct ti_iodelay_device *iod;834 int ret;835 836 if (!np) {837 dev_err(dev, "No OF node\n");838 return -EINVAL;839 }840 841 iod = devm_kzalloc(dev, sizeof(*iod), GFP_KERNEL);842 if (!iod)843 return -ENOMEM;844 845 iod->dev = dev;846 iod->reg_data = device_get_match_data(dev);847 if (!iod->reg_data) {848 dev_err(dev, "No DATA match\n");849 return -EINVAL;850 }851 852 /* So far We can assume there is only 1 bank of registers */853 iod->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);854 if (IS_ERR(iod->reg_base))855 return PTR_ERR(iod->reg_base);856 857 iod->phys_base = res->start;858 859 iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base,860 iod->reg_data->regmap_config);861 if (IS_ERR(iod->regmap)) {862 dev_err(dev, "Regmap MMIO init failed.\n");863 return PTR_ERR(iod->regmap);864 }865 866 ret = ti_iodelay_pinconf_init_dev(iod);867 if (ret)868 return ret;869 870 ret = ti_iodelay_alloc_pins(dev, iod, res->start);871 if (ret)872 return ret;873 874 iod->desc.pctlops = &ti_iodelay_pinctrl_ops;875 /* no pinmux ops - we are pinconf */876 iod->desc.confops = &ti_iodelay_pinctrl_pinconf_ops;877 iod->desc.name = dev_name(dev);878 iod->desc.owner = THIS_MODULE;879 880 ret = devm_pinctrl_register_and_init(dev, &iod->desc, iod, &iod->pctl);881 if (ret) {882 dev_err(dev, "Failed to register pinctrl\n");883 return ret;884 }885 886 return pinctrl_enable(iod->pctl);887}888 889static struct platform_driver ti_iodelay_driver = {890 .probe = ti_iodelay_probe,891 .driver = {892 .name = DRIVER_NAME,893 .of_match_table = ti_iodelay_of_match,894 },895};896module_platform_driver(ti_iodelay_driver);897 898MODULE_AUTHOR("Texas Instruments, Inc.");899MODULE_DESCRIPTION("Pinconf driver for TI's IO Delay module");900MODULE_LICENSE("GPL v2");901