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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2019, Mellanox Technologies. All rights reserved.4 */5 6#ifndef __MLXBF_TMFIFO_REGS_H__7#define __MLXBF_TMFIFO_REGS_H__8 9#include <linux/types.h>10#include <linux/bits.h>11 12#define MLXBF_TMFIFO_TX_DATA 0x0013#define MLXBF_TMFIFO_TX_STS 0x0814#define MLXBF_TMFIFO_TX_STS__LENGTH 0x000115#define MLXBF_TMFIFO_TX_STS__COUNT_SHIFT 016#define MLXBF_TMFIFO_TX_STS__COUNT_WIDTH 917#define MLXBF_TMFIFO_TX_STS__COUNT_RESET_VAL 018#define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)19#define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)20#define MLXBF_TMFIFO_TX_CTL 0x1021#define MLXBF_TMFIFO_TX_CTL__LENGTH 0x000122#define MLXBF_TMFIFO_TX_CTL__LWM_SHIFT 023#define MLXBF_TMFIFO_TX_CTL__LWM_WIDTH 824#define MLXBF_TMFIFO_TX_CTL__LWM_RESET_VAL 12825#define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)26#define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)27#define MLXBF_TMFIFO_TX_CTL__HWM_SHIFT 828#define MLXBF_TMFIFO_TX_CTL__HWM_WIDTH 829#define MLXBF_TMFIFO_TX_CTL__HWM_RESET_VAL 12830#define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)31#define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)32#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_SHIFT 3233#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_WIDTH 934#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RESET_VAL 25635#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)36#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)37#define MLXBF_TMFIFO_RX_DATA 0x0038#define MLXBF_TMFIFO_RX_STS 0x0839#define MLXBF_TMFIFO_RX_STS__LENGTH 0x000140#define MLXBF_TMFIFO_RX_STS__COUNT_SHIFT 041#define MLXBF_TMFIFO_RX_STS__COUNT_WIDTH 942#define MLXBF_TMFIFO_RX_STS__COUNT_RESET_VAL 043#define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)44#define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0)45#define MLXBF_TMFIFO_RX_CTL 0x1046#define MLXBF_TMFIFO_RX_CTL__LENGTH 0x000147#define MLXBF_TMFIFO_RX_CTL__LWM_SHIFT 048#define MLXBF_TMFIFO_RX_CTL__LWM_WIDTH 849#define MLXBF_TMFIFO_RX_CTL__LWM_RESET_VAL 12850#define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0)51#define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0)52#define MLXBF_TMFIFO_RX_CTL__HWM_SHIFT 853#define MLXBF_TMFIFO_RX_CTL__HWM_WIDTH 854#define MLXBF_TMFIFO_RX_CTL__HWM_RESET_VAL 12855#define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0)56#define MLXBF_TMFIFO_RX_CTL__HWM_MASK GENMASK_ULL(15, 8)57#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_SHIFT 3258#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_WIDTH 959#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RESET_VAL 25660#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)61#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)62 63/* BF3 register offsets within resource 0. */64#define MLXBF_TMFIFO_RX_DATA_BF3 0x000065#define MLXBF_TMFIFO_TX_DATA_BF3 0x100066 67/* BF3 register offsets within resource 1. */68#define MLXBF_TMFIFO_RX_STS_BF3 0x000069#define MLXBF_TMFIFO_RX_CTL_BF3 0x000870#define MLXBF_TMFIFO_TX_STS_BF3 0x010071#define MLXBF_TMFIFO_TX_CTL_BF3 0x010872 73#endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */74