802 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * AMD Platform Management Framework Driver4 *5 * Copyright (c) 2022, Advanced Micro Devices, Inc.6 * All Rights Reserved.7 *8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>9 */10 11#ifndef PMF_H12#define PMF_H13 14#include <linux/acpi.h>15#include <linux/input.h>16#include <linux/platform_profile.h>17 18#define POLICY_BUF_MAX_SZ 0x4b00019#define POLICY_SIGN_COOKIE 0x3153502420#define POLICY_COOKIE_OFFSET 0x1021 22/* List of supported CPU ids */23#define AMD_CPU_ID_RMB 0x14b524#define AMD_CPU_ID_PS 0x14e825#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x150726#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x112227 28struct cookie_header {29 u32 sign;30 u32 length;31} __packed;32 33/* APMF Functions */34#define APMF_FUNC_VERIFY_INTERFACE 035#define APMF_FUNC_GET_SYS_PARAMS 136#define APMF_FUNC_SBIOS_REQUESTS 237#define APMF_FUNC_SBIOS_HEARTBEAT 438#define APMF_FUNC_AUTO_MODE 539#define APMF_FUNC_SET_FAN_IDX 740#define APMF_FUNC_OS_POWER_SLIDER_UPDATE 841#define APMF_FUNC_STATIC_SLIDER_GRANULAR 942#define APMF_FUNC_DYN_SLIDER_AC 1143#define APMF_FUNC_DYN_SLIDER_DC 1244#define APMF_FUNC_NOTIFY_SMART_PC_UPDATES 1445#define APMF_FUNC_SBIOS_HEARTBEAT_V2 1646 47/* Message Definitions */48#define SET_SPL 0x03 /* SPL: Sustained Power Limit */49#define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */50#define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */51#define GET_SPL 0x0B52#define GET_SPPT 0x0D53#define GET_FPPT 0x0F54#define SET_DRAM_ADDR_HIGH 0x1455#define SET_DRAM_ADDR_LOW 0x1556#define SET_TRANSFER_TABLE 0x1657#define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */58#define SET_STT_LIMIT_APU 0x1959#define SET_STT_LIMIT_HS2 0x1A60#define SET_SPPT_APU_ONLY 0x1D61#define GET_SPPT_APU_ONLY 0x1E62#define GET_STT_MIN_LIMIT 0x1F63#define GET_STT_LIMIT_APU 0x2064#define GET_STT_LIMIT_HS2 0x2165#define SET_P3T 0x23 /* P3T: Peak Package Power Limit */66#define SET_PMF_PPT 0x2567#define SET_PMF_PPT_APU_ONLY 0x2668 69/* OS slider update notification */70#define DC_BEST_PERF 071#define DC_BETTER_PERF 172#define DC_BATTERY_SAVER 373#define AC_BEST_PERF 474#define AC_BETTER_PERF 575#define AC_BETTER_BATTERY 676 77/* Fan Index for Auto Mode */78#define FAN_INDEX_AUTO 0xFFFFFFFF79 80#define ARG_NONE 081#define AVG_SAMPLE_SIZE 382 83/* Policy Actions */84#define PMF_POLICY_SPL 285#define PMF_POLICY_SPPT 386#define PMF_POLICY_FPPT 487#define PMF_POLICY_SPPT_APU_ONLY 588#define PMF_POLICY_STT_MIN 689#define PMF_POLICY_STT_SKINTEMP_APU 790#define PMF_POLICY_STT_SKINTEMP_HS2 891#define PMF_POLICY_SYSTEM_STATE 992#define PMF_POLICY_BIOS_OUTPUT_1 1093#define PMF_POLICY_BIOS_OUTPUT_2 1194#define PMF_POLICY_P3T 3895#define PMF_POLICY_BIOS_OUTPUT_3 5796#define PMF_POLICY_BIOS_OUTPUT_4 5897#define PMF_POLICY_BIOS_OUTPUT_5 5998#define PMF_POLICY_BIOS_OUTPUT_6 6099#define PMF_POLICY_BIOS_OUTPUT_7 61100#define PMF_POLICY_BIOS_OUTPUT_8 62101#define PMF_POLICY_BIOS_OUTPUT_9 63102#define PMF_POLICY_BIOS_OUTPUT_10 64103 104/* TA macros */105#define PMF_TA_IF_VERSION_MAJOR 1106#define TA_PMF_ACTION_MAX 32107#define TA_PMF_UNDO_MAX 8108#define TA_OUTPUT_RESERVED_MEM 906109#define MAX_OPERATION_PARAMS 4110 111#define PMF_IF_V1 1112#define PMF_IF_V2 2113 114#define APTS_MAX_STATES 16115 116/* APTS PMF BIOS Interface */117struct amd_pmf_apts_output {118 u16 table_version;119 u32 fan_table_idx;120 u32 pmf_ppt;121 u32 ppt_pmf_apu_only;122 u32 stt_min_limit;123 u8 stt_skin_temp_limit_apu;124 u8 stt_skin_temp_limit_hs2;125} __packed;126 127struct amd_pmf_apts_granular_output {128 u16 size;129 struct amd_pmf_apts_output val;130} __packed;131 132struct amd_pmf_apts_granular {133 u16 size;134 struct amd_pmf_apts_output val[APTS_MAX_STATES];135};136 137struct sbios_hb_event_v2 {138 u16 size;139 u8 load;140 u8 unload;141 u8 suspend;142 u8 resume;143} __packed;144 145enum sbios_hb_v2 {146 ON_LOAD,147 ON_UNLOAD,148 ON_SUSPEND,149 ON_RESUME,150};151 152/* AMD PMF BIOS interfaces */153struct apmf_verify_interface {154 u16 size;155 u16 version;156 u32 notification_mask;157 u32 supported_functions;158} __packed;159 160struct apmf_system_params {161 u16 size;162 u32 valid_mask;163 u32 flags;164 u8 command_code;165 u32 heartbeat_int;166} __packed;167 168struct apmf_sbios_req {169 u16 size;170 u32 pending_req;171 u8 rsd;172 u8 cql_event;173 u8 amt_event;174 u32 fppt;175 u32 sppt;176 u32 fppt_apu_only;177 u32 spl;178 u32 stt_min_limit;179 u8 skin_temp_apu;180 u8 skin_temp_hs2;181} __packed;182 183struct apmf_sbios_req_v2 {184 u16 size;185 u32 pending_req;186 u8 rsd;187 u32 ppt_pmf;188 u32 ppt_pmf_apu_only;189 u32 stt_min_limit;190 u8 skin_temp_apu;191 u8 skin_temp_hs2;192 u32 custom_policy[10];193} __packed;194 195struct apmf_fan_idx {196 u16 size;197 u8 fan_ctl_mode;198 u32 fan_ctl_idx;199} __packed;200 201struct smu_pmf_metrics_v2 {202 u16 core_frequency[16]; /* MHz */203 u16 core_power[16]; /* mW */204 u16 core_temp[16]; /* centi-C */205 u16 gfx_temp; /* centi-C */206 u16 soc_temp; /* centi-C */207 u16 stapm_opn_limit; /* mW */208 u16 stapm_cur_limit; /* mW */209 u16 infra_cpu_maxfreq; /* MHz */210 u16 infra_gfx_maxfreq; /* MHz */211 u16 skin_temp; /* centi-C */212 u16 gfxclk_freq; /* MHz */213 u16 fclk_freq; /* MHz */214 u16 gfx_activity; /* GFX busy % [0-100] */215 u16 socclk_freq; /* MHz */216 u16 vclk_freq; /* MHz */217 u16 vcn_activity; /* VCN busy % [0-100] */218 u16 vpeclk_freq; /* MHz */219 u16 ipuclk_freq; /* MHz */220 u16 ipu_busy[8]; /* NPU busy % [0-100] */221 u16 dram_reads; /* MB/sec */222 u16 dram_writes; /* MB/sec */223 u16 core_c0residency[16]; /* C0 residency % [0-100] */224 u16 ipu_power; /* mW */225 u32 apu_power; /* mW */226 u32 gfx_power; /* mW */227 u32 dgpu_power; /* mW */228 u32 socket_power; /* mW */229 u32 all_core_power; /* mW */230 u32 filter_alpha_value; /* time constant [us] */231 u32 metrics_counter;232 u16 memclk_freq; /* MHz */233 u16 mpipuclk_freq; /* MHz */234 u16 ipu_reads; /* MB/sec */235 u16 ipu_writes; /* MB/sec */236 u32 throttle_residency_prochot;237 u32 throttle_residency_spl;238 u32 throttle_residency_fppt;239 u32 throttle_residency_sppt;240 u32 throttle_residency_thm_core;241 u32 throttle_residency_thm_gfx;242 u32 throttle_residency_thm_soc;243 u16 psys;244 u16 spare1;245 u32 spare[6];246} __packed;247 248struct smu_pmf_metrics {249 u16 gfxclk_freq; /* in MHz */250 u16 socclk_freq; /* in MHz */251 u16 vclk_freq; /* in MHz */252 u16 dclk_freq; /* in MHz */253 u16 memclk_freq; /* in MHz */254 u16 spare;255 u16 gfx_activity; /* in Centi */256 u16 uvd_activity; /* in Centi */257 u16 voltage[2]; /* in mV */258 u16 currents[2]; /* in mA */259 u16 power[2];/* in mW */260 u16 core_freq[8]; /* in MHz */261 u16 core_power[8]; /* in mW */262 u16 core_temp[8]; /* in centi-Celsius */263 u16 l3_freq; /* in MHz */264 u16 l3_temp; /* in centi-Celsius */265 u16 gfx_temp; /* in centi-Celsius */266 u16 soc_temp; /* in centi-Celsius */267 u16 throttler_status;268 u16 current_socketpower; /* in mW */269 u16 stapm_orig_limit; /* in W */270 u16 stapm_cur_limit; /* in W */271 u32 apu_power; /* in mW */272 u32 dgpu_power; /* in mW */273 u16 vdd_tdc_val; /* in mA */274 u16 soc_tdc_val; /* in mA */275 u16 vdd_edc_val; /* in mA */276 u16 soc_edcv_al; /* in mA */277 u16 infra_cpu_maxfreq; /* in MHz */278 u16 infra_gfx_maxfreq; /* in MHz */279 u16 skin_temp; /* in centi-Celsius */280 u16 device_state;281 u16 curtemp; /* in centi-Celsius */282 u16 filter_alpha_value;283 u16 avg_gfx_clkfrequency;284 u16 avg_fclk_frequency;285 u16 avg_gfx_activity;286 u16 avg_socclk_frequency;287 u16 avg_vclk_frequency;288 u16 avg_vcn_activity;289 u16 avg_dram_reads;290 u16 avg_dram_writes;291 u16 avg_socket_power;292 u16 avg_core_power[2];293 u16 avg_core_c0residency[16];294 u16 spare1;295 u32 metrics_counter;296} __packed;297 298enum amd_stt_skin_temp {299 STT_TEMP_APU,300 STT_TEMP_HS2,301 STT_TEMP_COUNT,302};303 304enum amd_slider_op {305 SLIDER_OP_GET,306 SLIDER_OP_SET,307};308 309enum power_source {310 POWER_SOURCE_AC,311 POWER_SOURCE_DC,312 POWER_SOURCE_MAX,313};314 315enum power_modes {316 POWER_MODE_PERFORMANCE,317 POWER_MODE_BALANCED_POWER,318 POWER_MODE_POWER_SAVER,319 POWER_MODE_MAX,320};321 322enum power_modes_v2 {323 POWER_MODE_BEST_PERFORMANCE,324 POWER_MODE_BALANCED,325 POWER_MODE_BEST_POWER_EFFICIENCY,326 POWER_MODE_ENERGY_SAVE,327 POWER_MODE_V2_MAX,328};329 330struct amd_pmf_dev {331 void __iomem *regbase;332 void __iomem *smu_virt_addr;333 void *buf;334 u32 base_addr;335 u32 cpu_id;336 struct device *dev;337 struct mutex lock; /* protects the PMF interface */338 u32 supported_func;339 enum platform_profile_option current_profile;340 struct platform_profile_handler pprof;341 struct dentry *dbgfs_dir;342 int hb_interval; /* SBIOS heartbeat interval */343 struct delayed_work heart_beat;344 struct smu_pmf_metrics m_table;345 struct smu_pmf_metrics_v2 m_table_v2;346 struct delayed_work work_buffer;347 ktime_t start_time;348 int socket_power_history[AVG_SAMPLE_SIZE];349 int socket_power_history_idx;350 bool amt_enabled;351 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */352 bool cnqf_enabled;353 bool cnqf_supported;354 struct notifier_block pwr_src_notifier;355 /* Smart PC solution builder */356 struct dentry *esbin;357 unsigned char *policy_buf;358 u32 policy_sz;359 struct tee_context *tee_ctx;360 struct tee_shm *fw_shm_pool;361 u32 session_id;362 void *shbuf;363 struct delayed_work pb_work;364 struct pmf_action_table *prev_data;365 u64 policy_addr;366 void __iomem *policy_base;367 bool smart_pc_enabled;368 u16 pmf_if_version;369 struct input_dev *pmf_idev;370 size_t mtable_size;371};372 373struct apmf_sps_prop_granular_v2 {374 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX];375} __packed;376 377struct apmf_sps_prop_granular {378 u32 fppt;379 u32 sppt;380 u32 sppt_apu_only;381 u32 spl;382 u32 stt_min;383 u8 stt_skin_temp[STT_TEMP_COUNT];384 u32 fan_id;385} __packed;386 387/* Static Slider */388struct apmf_static_slider_granular_output {389 u16 size;390 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX];391} __packed;392 393struct amd_pmf_static_slider_granular {394 u16 size;395 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX];396};397 398struct apmf_static_slider_granular_output_v2 {399 u16 size;400 struct apmf_sps_prop_granular_v2 sps_idx;401} __packed;402 403struct amd_pmf_static_slider_granular_v2 {404 u16 size;405 struct apmf_sps_prop_granular_v2 sps_idx;406};407 408struct os_power_slider {409 u16 size;410 u8 slider_event;411} __packed;412 413struct amd_pmf_notify_smart_pc_update {414 u16 size;415 u32 pending_req;416 u32 custom_bios[10];417} __packed;418 419struct fan_table_control {420 bool manual;421 unsigned long fan_id;422};423 424struct power_table_control {425 u32 spl;426 u32 sppt;427 u32 fppt;428 u32 sppt_apu_only;429 u32 stt_min;430 u32 stt_skin_temp[STT_TEMP_COUNT];431 u32 reserved[16];432};433 434/* Auto Mode Layer */435enum auto_mode_transition_priority {436 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */437 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */438 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */439 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */440 AUTO_TRANSITION_MAX,441};442 443enum auto_mode_mode {444 AUTO_QUIET,445 AUTO_BALANCE,446 AUTO_PERFORMANCE_ON_LAP,447 AUTO_PERFORMANCE,448 AUTO_MODE_MAX,449};450 451struct auto_mode_trans_params {452 u32 time_constant; /* minimum time required to switch to next mode */453 u32 power_delta; /* delta power to shift mode */454 u32 power_threshold;455 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */456 u32 applied;457 enum auto_mode_mode target_mode;458 u32 shifting_up;459};460 461struct auto_mode_mode_settings {462 struct power_table_control power_control;463 struct fan_table_control fan_control;464 u32 power_floor;465};466 467struct auto_mode_mode_config {468 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX];469 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX];470 enum auto_mode_mode current_mode;471};472 473struct apmf_auto_mode {474 u16 size;475 /* time constant */476 u32 balanced_to_perf;477 u32 perf_to_balanced;478 u32 quiet_to_balanced;479 u32 balanced_to_quiet;480 /* power floor */481 u32 pfloor_perf;482 u32 pfloor_balanced;483 u32 pfloor_quiet;484 /* Power delta for mode change */485 u32 pd_balanced_to_perf;486 u32 pd_perf_to_balanced;487 u32 pd_quiet_to_balanced;488 u32 pd_balanced_to_quiet;489 /* skin temperature limits */490 u8 stt_apu_perf_on_lap; /* CQL ON */491 u8 stt_hs2_perf_on_lap; /* CQL ON */492 u8 stt_apu_perf;493 u8 stt_hs2_perf;494 u8 stt_apu_balanced;495 u8 stt_hs2_balanced;496 u8 stt_apu_quiet;497 u8 stt_hs2_quiet;498 u32 stt_min_limit_perf_on_lap; /* CQL ON */499 u32 stt_min_limit_perf;500 u32 stt_min_limit_balanced;501 u32 stt_min_limit_quiet;502 /* SPL based */503 u32 fppt_perf_on_lap; /* CQL ON */504 u32 sppt_perf_on_lap; /* CQL ON */505 u32 spl_perf_on_lap; /* CQL ON */506 u32 sppt_apu_only_perf_on_lap; /* CQL ON */507 u32 fppt_perf;508 u32 sppt_perf;509 u32 spl_perf;510 u32 sppt_apu_only_perf;511 u32 fppt_balanced;512 u32 sppt_balanced;513 u32 spl_balanced;514 u32 sppt_apu_only_balanced;515 u32 fppt_quiet;516 u32 sppt_quiet;517 u32 spl_quiet;518 u32 sppt_apu_only_quiet;519 /* Fan ID */520 u32 fan_id_perf;521 u32 fan_id_balanced;522 u32 fan_id_quiet;523} __packed;524 525/* CnQF Layer */526enum cnqf_trans_priority {527 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */528 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */529 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */530 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */531 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */532 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */533 CNQF_TRANSITION_MAX,534};535 536enum cnqf_mode {537 CNQF_MODE_QUIET,538 CNQF_MODE_BALANCE,539 CNQF_MODE_PERFORMANCE,540 CNQF_MODE_TURBO,541 CNQF_MODE_MAX,542};543 544enum apmf_cnqf_pos {545 APMF_CNQF_TURBO,546 APMF_CNQF_PERFORMANCE,547 APMF_CNQF_BALANCE,548 APMF_CNQF_QUIET,549 APMF_CNQF_MAX,550};551 552struct cnqf_mode_settings {553 struct power_table_control power_control;554 struct fan_table_control fan_control;555 u32 power_floor;556};557 558struct cnqf_tran_params {559 u32 time_constant; /* minimum time required to switch to next mode */560 u32 power_threshold;561 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */562 u32 total_power;563 u32 count;564 bool priority;565 bool shifting_up;566 enum cnqf_mode target_mode;567};568 569struct cnqf_config {570 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX];571 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX];572 struct power_table_control defaults;573 enum cnqf_mode current_mode;574 u32 power_src;575 u32 avg_power;576};577 578struct apmf_cnqf_power_set {579 u32 pfloor;580 u32 fppt;581 u32 sppt;582 u32 sppt_apu_only;583 u32 spl;584 u32 stt_min_limit;585 u8 stt_skintemp[STT_TEMP_COUNT];586 u32 fan_id;587} __packed;588 589struct apmf_dyn_slider_output {590 u16 size;591 u16 flags;592 u32 t_perf_to_turbo;593 u32 t_balanced_to_perf;594 u32 t_quiet_to_balanced;595 u32 t_balanced_to_quiet;596 u32 t_perf_to_balanced;597 u32 t_turbo_to_perf;598 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];599} __packed;600 601/* Smart PC - TA internals */602enum system_state {603 SYSTEM_STATE_S0i3,604 SYSTEM_STATE_S4,605 SYSTEM_STATE_SCREEN_LOCK,606 SYSTEM_STATE_MAX,607};608 609enum ta_slider {610 TA_BEST_BATTERY,611 TA_BETTER_BATTERY,612 TA_BETTER_PERFORMANCE,613 TA_BEST_PERFORMANCE,614 TA_MAX,615};616 617/* Command ids for TA communication */618enum ta_pmf_command {619 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE,620 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES,621};622 623enum ta_pmf_error_type {624 TA_PMF_TYPE_SUCCESS,625 TA_PMF_ERROR_TYPE_GENERIC,626 TA_PMF_ERROR_TYPE_CRYPTO,627 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE,628 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM,629 TA_PMF_ERROR_TYPE_POLICY_BUILDER,630 TA_PMF_ERROR_TYPE_PB_CONVERT,631 TA_PMF_ERROR_TYPE_PB_SETUP,632 TA_PMF_ERROR_TYPE_PB_ENACT,633 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO,634 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO,635 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION,636 TA_PMF_ERROR_TYPE_MAX,637};638 639struct pmf_action_table {640 enum system_state system_state;641 u32 spl; /* in mW */642 u32 sppt; /* in mW */643 u32 sppt_apuonly; /* in mW */644 u32 fppt; /* in mW */645 u32 stt_minlimit; /* in mW */646 u32 stt_skintemp_apu; /* in C */647 u32 stt_skintemp_hs2; /* in C */648 u32 p3t_limit; /* in mW */649};650 651/* Input conditions */652struct ta_pmf_condition_info {653 u32 power_source;654 u32 bat_percentage;655 u32 power_slider;656 u32 lid_state;657 bool user_present;658 u32 rsvd1[2];659 u32 monitor_count;660 u32 rsvd2[2];661 u32 bat_design;662 u32 full_charge_capacity;663 int drain_rate;664 bool user_engaged;665 u32 device_state;666 u32 socket_power;667 u32 skin_temperature;668 u32 rsvd3[5];669 u32 ambient_light;670 u32 length;671 u32 avg_c0residency;672 u32 max_c0residency;673 u32 s0i3_entry;674 u32 gfx_busy;675 u32 rsvd4[7];676 bool camera_state;677 u32 workload_type;678 u32 display_type;679 u32 display_state;680 u32 rsvd5[150];681};682 683struct ta_pmf_load_policy_table {684 u32 table_size;685 u8 table[POLICY_BUF_MAX_SZ];686};687 688/* TA initialization params */689struct ta_pmf_init_table {690 u32 frequency; /* SMU sampling frequency */691 bool validate;692 bool sku_check;693 bool metadata_macrocheck;694 struct ta_pmf_load_policy_table policies_table;695};696 697/* Everything the TA needs to Enact Policies */698struct ta_pmf_enact_table {699 struct ta_pmf_condition_info ev_info;700 u32 name;701};702 703struct ta_pmf_action {704 u32 action_index;705 u32 value;706};707 708/* Output actions from TA */709struct ta_pmf_enact_result {710 u32 actions_count;711 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX];712 u32 undo_count;713 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX];714};715 716union ta_pmf_input {717 struct ta_pmf_enact_table enact_table;718 struct ta_pmf_init_table init_table;719};720 721union ta_pmf_output {722 struct ta_pmf_enact_result policy_apply_table;723 u32 rsvd[TA_OUTPUT_RESERVED_MEM];724};725 726struct ta_pmf_shared_memory {727 int command_id;728 int resp_id;729 u32 pmf_result;730 u32 if_version;731 union ta_pmf_output pmf_output;732 union ta_pmf_input pmf_input;733};734 735/* Core Layer */736int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);737void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);738int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);739int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);740int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);741int amd_pmf_get_power_source(void);742int apmf_install_handler(struct amd_pmf_dev *pmf_dev);743int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag);744int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer);745int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag);746 747/* SPS Layer */748int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf);749void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,750 struct amd_pmf_static_slider_granular *table);751int amd_pmf_init_sps(struct amd_pmf_dev *dev);752void amd_pmf_deinit_sps(struct amd_pmf_dev *dev);753int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev,754 struct apmf_static_slider_granular_output *output);755bool is_pprof_balanced(struct amd_pmf_dev *pmf);756int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev);757const char *amd_pmf_source_as_str(unsigned int state);758 759const char *amd_pmf_source_as_str(unsigned int state);760 761int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx);762int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf);763int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev,764 struct apmf_static_slider_granular_output_v2 *data);765int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev,766 struct amd_pmf_apts_granular_output *data, u32 apts_idx);767 768/* Auto Mode Layer */769int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data);770void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev);771void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev);772void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms);773int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req);774int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req);775 776void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event);777int amd_pmf_reset_amt(struct amd_pmf_dev *dev);778void amd_pmf_handle_amt(struct amd_pmf_dev *dev);779 780/* CnQF Layer */781int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);782int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);783int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);784void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);785int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);786extern const struct attribute_group cnqf_feature_attribute_group;787 788/* Smart PC builder Layer */789int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev);790void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev);791int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev);792int amd_pmf_smartpc_apply_bios_output(struct amd_pmf_dev *dev, u32 val, u32 preq, u32 idx);793 794/* Smart PC - TA interfaces */795void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);796void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);797 798/* Quirk infrastructure */799void amd_pmf_quirks_init(struct amd_pmf_dev *dev);800 801#endif /* PMF_H */802