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1// SPDX-License-Identifier: GPL-2.02/*3 * This file contains platform specific structure definitions4 * and init function used by Arrow Lake PCH.5 *6 * Copyright (c) 2022, Intel Corporation.7 * All Rights Reserved.8 *9 */10 11#include <linux/pci.h>12#include "core.h"13#include "../pmt/telemetry.h"14 15/* PMC SSRAM PMT Telemetry GUID */16#define IOEP_LPM_REQ_GUID 0x507761217#define SOCS_LPM_REQ_GUID 0x847865718#define PCHS_LPM_REQ_GUID 0x968457219 20static const u8 ARL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};21 22const struct pmc_bit_map arl_socs_ltr_show_map[] = {23 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},24 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},25 {"SATA", CNP_PMC_LTR_SATA},26 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},27 {"XHCI", CNP_PMC_LTR_XHCI},28 {"SOUTHPORT_F", ADL_PMC_LTR_SPF},29 {"ME", CNP_PMC_LTR_ME},30 /* EVA is Enterprise Value Add, doesn't really exist on PCH */31 {"SATA1", CNP_PMC_LTR_EVA},32 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},33 {"HD_AUDIO", CNP_PMC_LTR_AZ},34 {"CNV", CNP_PMC_LTR_CNV},35 {"LPSS", CNP_PMC_LTR_LPSS},36 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},37 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},38 {"SATA2", CNP_PMC_LTR_CAM},39 {"ESPI", CNP_PMC_LTR_ESPI},40 {"SCC", CNP_PMC_LTR_SCC},41 {"ISH", CNP_PMC_LTR_ISH},42 {"UFSX2", CNP_PMC_LTR_UFSX2},43 {"EMMC", CNP_PMC_LTR_EMMC},44 /*45 * Check intel_pmc_core_ids[] users of cnp_reg_map for46 * a list of core SoCs using this.47 */48 {"WIGIG", ICL_PMC_LTR_WIGIG},49 {"THC0", TGL_PMC_LTR_THC0},50 {"THC1", TGL_PMC_LTR_THC1},51 {"SOUTHPORT_G", MTL_PMC_LTR_SPG},52 {"Reserved", ARL_SOCS_PMC_LTR_RESERVED},53 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC},54 {"DMI3", ARL_PMC_LTR_DMI3},55 56 /* Below two cannot be used for LTR_IGNORE */57 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},58 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},59 {}60};61 62const struct pmc_bit_map arl_socs_clocksource_status_map[] = {63 {"AON2_OFF_STS", BIT(0)},64 {"AON3_OFF_STS", BIT(1)},65 {"AON4_OFF_STS", BIT(2)},66 {"AON5_OFF_STS", BIT(3)},67 {"AON1_OFF_STS", BIT(4)},68 {"XTAL_LVM_OFF_STS", BIT(5)},69 {"AON3_SPL_OFF_STS", BIT(9)},70 {"DMI3FPW_0_PLL_OFF_STS", BIT(10)},71 {"DMI3FPW_1_PLL_OFF_STS", BIT(11)},72 {"G5X16FPW_0_PLL_OFF_STS", BIT(14)},73 {"G5X16FPW_1_PLL_OFF_STS", BIT(15)},74 {"G5X16FPW_2_PLL_OFF_STS", BIT(16)},75 {"XTAL_AGGR_OFF_STS", BIT(17)},76 {"USB2_PLL_OFF_STS", BIT(18)},77 {"G5X16FPW_3_PLL_OFF_STS", BIT(19)},78 {"BCLK_EXT_INJ_CLK_OFF_STS", BIT(20)},79 {"PHY_OC_EXT_INJ_CLK_OFF_STS", BIT(21)},80 {"FILTER_PLL_OFF_STS", BIT(22)},81 {"FABRIC_PLL_OFF_STS", BIT(25)},82 {"SOC_PLL_OFF_STS", BIT(26)},83 {"PCIEFAB_PLL_OFF_STS", BIT(27)},84 {"REF_PLL_OFF_STS", BIT(28)},85 {"GENLOCK_FILTER_PLL_OFF_STS", BIT(30)},86 {"RTC_PLL_OFF_STS", BIT(31)},87 {}88};89 90const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {91 {"PMC_PGD0_PG_STS", BIT(0)},92 {"DMI_PGD0_PG_STS", BIT(1)},93 {"ESPISPI_PGD0_PG_STS", BIT(2)},94 {"XHCI_PGD0_PG_STS", BIT(3)},95 {"SPA_PGD0_PG_STS", BIT(4)},96 {"SPB_PGD0_PG_STS", BIT(5)},97 {"SPC_PGD0_PG_STS", BIT(6)},98 {"GBE_PGD0_PG_STS", BIT(7)},99 {"SATA_PGD0_PG_STS", BIT(8)},100 {"FIACPCB_P5x16_PGD0_PG_STS", BIT(9)},101 {"G5x16FPW_PGD0_PG_STS", BIT(10)},102 {"FIA_D_PGD0_PG_STS", BIT(11)},103 {"MPFPW2_PGD0_PG_STS", BIT(12)},104 {"SPD_PGD0_PG_STS", BIT(13)},105 {"LPSS_PGD0_PG_STS", BIT(14)},106 {"LPC_PGD0_PG_STS", BIT(15)},107 {"SMB_PGD0_PG_STS", BIT(16)},108 {"ISH_PGD0_PG_STS", BIT(17)},109 {"P2S_PGD0_PG_STS", BIT(18)},110 {"NPK_PGD0_PG_STS", BIT(19)},111 {"DMI3FPW_PGD0_PG_STS", BIT(20)},112 {"GBETSN1_PGD0_PG_STS", BIT(21)},113 {"FUSE_PGD0_PG_STS", BIT(22)},114 {"FIACPCB_D_PGD0_PG_STS", BIT(23)},115 {"FUSEGPSB_PGD0_PG_STS", BIT(24)},116 {"XDCI_PGD0_PG_STS", BIT(25)},117 {"EXI_PGD0_PG_STS", BIT(26)},118 {"CSE_PGD0_PG_STS", BIT(27)},119 {"KVMCC_PGD0_PG_STS", BIT(28)},120 {"PMT_PGD0_PG_STS", BIT(29)},121 {"CLINK_PGD0_PG_STS", BIT(30)},122 {"PTIO_PGD0_PG_STS", BIT(31)},123 {}124};125 126const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = {127 {"USBR0_PGD0_PG_STS", BIT(0)},128 {"SUSRAM_PGD0_PG_STS", BIT(1)},129 {"SMT1_PGD0_PG_STS", BIT(2)},130 {"FIACPCB_U_PGD0_PG_STS", BIT(3)},131 {"SMS2_PGD0_PG_STS", BIT(4)},132 {"SMS1_PGD0_PG_STS", BIT(5)},133 {"CSMERTC_PGD0_PG_STS", BIT(6)},134 {"CSMEPSF_PGD0_PG_STS", BIT(7)},135 {"SBR0_PGD0_PG_STS", BIT(8)},136 {"SBR1_PGD0_PG_STS", BIT(9)},137 {"SBR2_PGD0_PG_STS", BIT(10)},138 {"SBR3_PGD0_PG_STS", BIT(11)},139 {"MPFPW1_PGD0_PG_STS", BIT(12)},140 {"SBR5_PGD0_PG_STS", BIT(13)},141 {"FIA_X_PGD0_PG_STS", BIT(14)},142 {"FIACPCB_X_PGD0_PG_STS", BIT(15)},143 {"SBRG_PGD0_PG_STS", BIT(16)},144 {"SOC_D2D_PGD1_PG_STS", BIT(17)},145 {"PSF4_PGD0_PG_STS", BIT(18)},146 {"CNVI_PGD0_PG_STS", BIT(19)},147 {"UFSX2_PGD0_PG_STS", BIT(20)},148 {"ENDBG_PGD0_PG_STS", BIT(21)},149 {"DBG_PSF_PGD0_PG_STS", BIT(22)},150 {"SBR6_PGD0_PG_STS", BIT(23)},151 {"SOC_D2D_PGD2_PG_STS", BIT(24)},152 {"NPK_PGD1_PG_STS", BIT(25)},153 {"DMI3_PGD0_PG_STS", BIT(26)},154 {"DBG_SBR_PGD0_PG_STS", BIT(27)},155 {"SOC_D2D_PGD0_PG_STS", BIT(28)},156 {"PSF6_PGD0_PG_STS", BIT(29)},157 {"PSF7_PGD0_PG_STS", BIT(30)},158 {"MPFPW3_PGD0_PG_STS", BIT(31)},159 {}160};161 162const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = {163 {"PSF8_PGD0_PG_STS", BIT(0)},164 {"FIA_PGD0_PG_STS", BIT(1)},165 {"SOC_D2D_PGD3_PG_STS", BIT(2)},166 {"FIA_U_PGD0_PG_STS", BIT(3)},167 {"TAM_PGD0_PG_STS", BIT(4)},168 {"GBETSN_PGD0_PG_STS", BIT(5)},169 {"TBTLSX_PGD0_PG_STS", BIT(6)},170 {"THC0_PGD0_PG_STS", BIT(7)},171 {"THC1_PGD0_PG_STS", BIT(8)},172 {"PMC_PGD1_PG_STS", BIT(9)},173 {"FIA_P5x16_PGD0_PG_STS", BIT(10)},174 {"GNA_PGD0_PG_STS", BIT(11)},175 {"ACE_PGD0_PG_STS", BIT(12)},176 {"ACE_PGD1_PG_STS", BIT(13)},177 {"ACE_PGD2_PG_STS", BIT(14)},178 {"ACE_PGD3_PG_STS", BIT(15)},179 {"ACE_PGD4_PG_STS", BIT(16)},180 {"ACE_PGD5_PG_STS", BIT(17)},181 {"ACE_PGD6_PG_STS", BIT(18)},182 {"ACE_PGD7_PG_STS", BIT(19)},183 {"ACE_PGD8_PG_STS", BIT(20)},184 {"FIA_PGS_PGD0_PG_STS", BIT(21)},185 {"FIACPCB_PGS_PGD0_PG_STS", BIT(22)},186 {"FUSEPMSB_PGD0_PG_STS", BIT(23)},187 {}188};189 190const struct pmc_bit_map arl_socs_d3_status_2_map[] = {191 {"CSMERTC_D3_STS", BIT(1)},192 {"SUSRAM_D3_STS", BIT(2)},193 {"CSE_D3_STS", BIT(4)},194 {"KVMCC_D3_STS", BIT(5)},195 {"USBR0_D3_STS", BIT(6)},196 {"ISH_D3_STS", BIT(7)},197 {"SMT1_D3_STS", BIT(8)},198 {"SMT2_D3_STS", BIT(9)},199 {"SMT3_D3_STS", BIT(10)},200 {"GNA_D3_STS", BIT(12)},201 {"CLINK_D3_STS", BIT(14)},202 {"PTIO_D3_STS", BIT(16)},203 {"PMT_D3_STS", BIT(17)},204 {"SMS1_D3_STS", BIT(18)},205 {"SMS2_D3_STS", BIT(19)},206 {}207};208 209const struct pmc_bit_map arl_socs_d3_status_3_map[] = {210 {"GBETSN_D3_STS", BIT(13)},211 {"THC0_D3_STS", BIT(14)},212 {"THC1_D3_STS", BIT(15)},213 {"ACE_D3_STS", BIT(23)},214 {}215};216 217const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = {218 {"DTS0_VNN_REQ_STS", BIT(7)},219 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},220 {}221};222 223const struct pmc_bit_map *arl_socs_lpm_maps[] = {224 arl_socs_clocksource_status_map,225 arl_socs_power_gating_status_0_map,226 arl_socs_power_gating_status_1_map,227 arl_socs_power_gating_status_2_map,228 mtl_socm_d3_status_0_map,229 mtl_socm_d3_status_1_map,230 arl_socs_d3_status_2_map,231 arl_socs_d3_status_3_map,232 mtl_socm_vnn_req_status_0_map,233 mtl_socm_vnn_req_status_1_map,234 mtl_socm_vnn_req_status_2_map,235 arl_socs_vnn_req_status_3_map,236 mtl_socm_vnn_misc_status_map,237 mtl_socm_signal_status_map,238 NULL239};240 241const struct pmc_bit_map arl_socs_pfear_map[] = {242 {"RSVD64", BIT(0)},243 {"RSVD65", BIT(1)},244 {"RSVD66", BIT(2)},245 {"RSVD67", BIT(3)},246 {"RSVD68", BIT(4)},247 {"GBETSN", BIT(5)},248 {"TBTLSX", BIT(6)},249 {}250};251 252const struct pmc_bit_map *ext_arl_socs_pfear_map[] = {253 mtl_socm_pfear_map,254 arl_socs_pfear_map,255 NULL256};257 258const struct pmc_reg_map arl_socs_reg_map = {259 .pfear_sts = ext_arl_socs_pfear_map,260 .ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,261 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,262 .lpm_sts = arl_socs_lpm_maps,263 .ltr_ignore_max = ARL_SOCS_NUM_IP_IGN_ALLOWED,264 .ltr_show_sts = arl_socs_ltr_show_map,265 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,266 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,267 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,268 .msr_sts = msr_map,269 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,270 .regmap_length = MTL_SOC_PMC_MMIO_REG_LEN,271 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,272 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,273 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,274 .lpm_en_offset = MTL_LPM_EN_OFFSET,275 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,276 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,277 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,278 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,279 .lpm_num_maps = ADL_LPM_NUM_MAPS,280 .lpm_reg_index = ARL_LPM_REG_INDEX,281 .etr3_offset = ETR3_OFFSET,282 .pson_residency_offset = TGL_PSON_RESIDENCY_OFFSET,283 .pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP,284};285 286const struct pmc_bit_map arl_pchs_ltr_show_map[] = {287 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},288 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},289 {"SATA", CNP_PMC_LTR_SATA},290 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},291 {"XHCI", CNP_PMC_LTR_XHCI},292 {"SOUTHPORT_F", ADL_PMC_LTR_SPF},293 {"ME", CNP_PMC_LTR_ME},294 /* EVA is Enterprise Value Add, doesn't really exist on PCH */295 {"SATA1", CNP_PMC_LTR_EVA},296 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},297 {"HD_AUDIO", CNP_PMC_LTR_AZ},298 {"CNV", CNP_PMC_LTR_CNV},299 {"LPSS", CNP_PMC_LTR_LPSS},300 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},301 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},302 {"SATA2", CNP_PMC_LTR_CAM},303 {"ESPI", CNP_PMC_LTR_ESPI},304 {"SCC", CNP_PMC_LTR_SCC},305 {"ISH", CNP_PMC_LTR_ISH},306 {"UFSX2", CNP_PMC_LTR_UFSX2},307 {"EMMC", CNP_PMC_LTR_EMMC},308 /*309 * Check intel_pmc_core_ids[] users of cnp_reg_map for310 * a list of core SoCs using this.311 */312 {"WIGIG", ICL_PMC_LTR_WIGIG},313 {"THC0", TGL_PMC_LTR_THC0},314 {"THC1", TGL_PMC_LTR_THC1},315 {"SOUTHPORT_G", MTL_PMC_LTR_SPG},316 {"ESE", MTL_PMC_LTR_ESE},317 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC},318 {"DMI3", ARL_PMC_LTR_DMI3},319 320 /* Below two cannot be used for LTR_IGNORE */321 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},322 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},323 {}324};325 326const struct pmc_bit_map arl_pchs_clocksource_status_map[] = {327 {"AON2_OFF_STS", BIT(0)},328 {"AON3_OFF_STS", BIT(1)},329 {"AON4_OFF_STS", BIT(2)},330 {"AON2_SPL_OFF_STS", BIT(3)},331 {"AONL_OFF_STS", BIT(4)},332 {"XTAL_LVM_OFF_STS", BIT(5)},333 {"AON5_ACRO_OFF_STS", BIT(6)},334 {"AON6_ACRO_OFF_STS", BIT(7)},335 {"USB3_PLL_OFF_STS", BIT(8)},336 {"ACRO_OFF_STS", BIT(9)},337 {"AUDIO_PLL_OFF_STS", BIT(10)},338 {"MAIN_CRO_OFF_STS", BIT(11)},339 {"MAIN_DIVIDER_OFF_STS", BIT(12)},340 {"REF_PLL_NON_OC_OFF_STS", BIT(13)},341 {"DMI_PLL_OFF_STS", BIT(14)},342 {"PHY_EXT_INJ_OFF_STS", BIT(15)},343 {"AON6_MCRO_OFF_STS", BIT(16)},344 {"XTAL_AGGR_OFF_STS", BIT(17)},345 {"USB2_PLL_OFF_STS", BIT(18)},346 {"TSN0_PLL_OFF_STS", BIT(19)},347 {"TSN1_PLL_OFF_STS", BIT(20)},348 {"GBE_PLL_OFF_STS", BIT(21)},349 {"SATA_PLL_OFF_STS", BIT(22)},350 {"PCIE0_PLL_OFF_STS", BIT(23)},351 {"PCIE1_PLL_OFF_STS", BIT(24)},352 {"PCIE2_PLL_OFF_STS", BIT(26)},353 {"PCIE3_PLL_OFF_STS", BIT(27)},354 {"REF_PLL_OFF_STS", BIT(28)},355 {"PCIE4_PLL_OFF_STS", BIT(29)},356 {"PCIE5_PLL_OFF_STS", BIT(30)},357 {"REF38P4_PLL_OFF_STS", BIT(31)},358 {}359};360 361const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = {362 {"PMC_PGD0_PG_STS", BIT(0)},363 {"DMI_PGD0_PG_STS", BIT(1)},364 {"ESPISPI_PGD0_PG_STS", BIT(2)},365 {"XHCI_PGD0_PG_STS", BIT(3)},366 {"SPA_PGD0_PG_STS", BIT(4)},367 {"SPB_PGD0_PG_STS", BIT(5)},368 {"SPC_PGD0_PG_STS", BIT(6)},369 {"GBE_PGD0_PG_STS", BIT(7)},370 {"SATA_PGD0_PG_STS", BIT(8)},371 {"FIA_X_PGD0_PG_STS", BIT(9)},372 {"MPFPW4_PGD0_PG_STS", BIT(10)},373 {"EAH_PGD0_PG_STS", BIT(11)},374 {"MPFPW1_PGD0_PG_STS", BIT(12)},375 {"SPD_PGD0_PG_STS", BIT(13)},376 {"LPSS_PGD0_PG_STS", BIT(14)},377 {"LPC_PGD0_PG_STS", BIT(15)},378 {"SMB_PGD0_PG_STS", BIT(16)},379 {"ISH_PGD0_PG_STS", BIT(17)},380 {"P2S_PGD0_PG_STS", BIT(18)},381 {"NPK_PGD0_PG_STS", BIT(19)},382 {"U3FPW1_PGD0_PG_STS", BIT(20)},383 {"PECI_PGD0_PG_STS", BIT(21)},384 {"FUSE_PGD0_PG_STS", BIT(22)},385 {"SBR8_PGD0_PG_STS", BIT(23)},386 {"EXE_PGD0_PG_STS", BIT(24)},387 {"XDCI_PGD0_PG_STS", BIT(25)},388 {"EXI_PGD0_PG_STS", BIT(26)},389 {"CSE_PGD0_PG_STS", BIT(27)},390 {"KVMCC_PGD0_PG_STS", BIT(28)},391 {"PMT_PGD0_PG_STS", BIT(29)},392 {"CLINK_PGD0_PG_STS", BIT(30)},393 {"PTIO_PGD0_PG_STS", BIT(31)},394 {}395};396 397const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = {398 {"USBR0_PGD0_PG_STS", BIT(0)},399 {"SUSRAM_PGD0_PG_STS", BIT(1)},400 {"SMT1_PGD0_PG_STS", BIT(2)},401 {"SMT4_PGD0_PG_STS", BIT(3)},402 {"SMS2_PGD0_PG_STS", BIT(4)},403 {"SMS1_PGD0_PG_STS", BIT(5)},404 {"CSMERTC_PGD0_PG_STS", BIT(6)},405 {"CSMEPSF_PGD0_PG_STS", BIT(7)},406 {"SBR0_PGD0_PG_STS", BIT(8)},407 {"SBR1_PGD0_PG_STS", BIT(9)},408 {"SBR2_PGD0_PG_STS", BIT(10)},409 {"SBR3_PGD0_PG_STS", BIT(11)},410 {"SBR4_PGD0_PG_STS", BIT(12)},411 {"SBR5_PGD0_PG_STS", BIT(13)},412 {"MPFPW3_PGD0_PG_STS", BIT(14)},413 {"PSF1_PGD0_PG_STS", BIT(15)},414 {"PSF2_PGD0_PG_STS", BIT(16)},415 {"PSF3_PGD0_PG_STS", BIT(17)},416 {"PSF4_PGD0_PG_STS", BIT(18)},417 {"CNVI_PGD0_PG_STS", BIT(19)},418 {"DMI3_PGD0_PG_STS", BIT(20)},419 {"ENDBG_PGD0_PG_STS", BIT(21)},420 {"DBG_SBR_PGD0_PG_STS", BIT(22)},421 {"SBR6_PGD0_PG_STS", BIT(23)},422 {"SBR7_PGD0_PG_STS", BIT(24)},423 {"NPK_PGD1_PG_STS", BIT(25)},424 {"U3FPW3_PGD0_PG_STS", BIT(26)},425 {"MPFPW2_PGD0_PG_STS", BIT(27)},426 {"MPFPW7_PGD0_PG_STS", BIT(28)},427 {"GBETSN1_PGD0_PG_STS", BIT(29)},428 {"PSF7_PGD0_PG_STS", BIT(30)},429 {"FIA2_PGD0_PG_STS", BIT(31)},430 {}431};432 433const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = {434 {"U3FPW2_PGD0_PG_STS", BIT(0)},435 {"FIA_PGD0_PG_STS", BIT(1)},436 {"FIACPCB_X_PGD0_PG_STS", BIT(2)},437 {"FIA1_PGD0_PG_STS", BIT(3)},438 {"TAM_PGD0_PG_STS", BIT(4)},439 {"GBETSN_PGD0_PG_STS", BIT(5)},440 {"SBR9_PGD0_PG_STS", BIT(6)},441 {"THC0_PGD0_PG_STS", BIT(7)},442 {"THC1_PGD0_PG_STS", BIT(8)},443 {"PMC_PGD1_PG_STS", BIT(9)},444 {"DBC_PGD0_PG_STS", BIT(10)},445 {"DBG_PSF_PGD0_PG_STS", BIT(11)},446 {"SPF_PGD0_PG_STS", BIT(12)},447 {"ACE_PGD0_PG_STS", BIT(13)},448 {"ACE_PGD1_PG_STS", BIT(14)},449 {"ACE_PGD2_PG_STS", BIT(15)},450 {"ACE_PGD3_PG_STS", BIT(16)},451 {"ACE_PGD4_PG_STS", BIT(17)},452 {"ACE_PGD5_PG_STS", BIT(18)},453 {"ACE_PGD6_PG_STS", BIT(19)},454 {"ACE_PGD7_PG_STS", BIT(20)},455 {"SPE_PGD0_PG_STS", BIT(21)},456 {"MPFPW5_PG_STS", BIT(22)},457 {}458};459 460const struct pmc_bit_map arl_pchs_d3_status_0_map[] = {461 {"SPF_D3_STS", BIT(0)},462 {"LPSS_D3_STS", BIT(3)},463 {"XDCI_D3_STS", BIT(4)},464 {"XHCI_D3_STS", BIT(5)},465 {"SPA_D3_STS", BIT(12)},466 {"SPB_D3_STS", BIT(13)},467 {"SPC_D3_STS", BIT(14)},468 {"SPD_D3_STS", BIT(15)},469 {"SPE_D3_STS", BIT(16)},470 {"ESPISPI_D3_STS", BIT(18)},471 {"SATA_D3_STS", BIT(20)},472 {"PSTH_D3_STS", BIT(21)},473 {"DMI_D3_STS", BIT(22)},474 {}475};476 477const struct pmc_bit_map arl_pchs_d3_status_1_map[] = {478 {"GBETSN1_D3_STS", BIT(14)},479 {"GBE_D3_STS", BIT(19)},480 {"ITSS_D3_STS", BIT(23)},481 {"P2S_D3_STS", BIT(24)},482 {"CNVI_D3_STS", BIT(27)},483 {}484};485 486const struct pmc_bit_map arl_pchs_d3_status_2_map[] = {487 {"CSMERTC_D3_STS", BIT(1)},488 {"SUSRAM_D3_STS", BIT(2)},489 {"CSE_D3_STS", BIT(4)},490 {"KVMCC_D3_STS", BIT(5)},491 {"USBR0_D3_STS", BIT(6)},492 {"ISH_D3_STS", BIT(7)},493 {"SMT1_D3_STS", BIT(8)},494 {"SMT2_D3_STS", BIT(9)},495 {"SMT3_D3_STS", BIT(10)},496 {"SMT4_D3_STS", BIT(11)},497 {"SMT5_D3_STS", BIT(12)},498 {"SMT6_D3_STS", BIT(13)},499 {"CLINK_D3_STS", BIT(14)},500 {"PTIO_D3_STS", BIT(16)},501 {"PMT_D3_STS", BIT(17)},502 {"SMS1_D3_STS", BIT(18)},503 {"SMS2_D3_STS", BIT(19)},504 {}505};506 507const struct pmc_bit_map arl_pchs_d3_status_3_map[] = {508 {"ESE_D3_STS", BIT(3)},509 {"GBETSN_D3_STS", BIT(13)},510 {"THC0_D3_STS", BIT(14)},511 {"THC1_D3_STS", BIT(15)},512 {"ACE_D3_STS", BIT(23)},513 {}514};515 516const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = {517 {"FIA_VNN_REQ_STS", BIT(17)},518 {"ESPISPI_VNN_REQ_STS", BIT(18)},519 {}520};521 522const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = {523 {"NPK_VNN_REQ_STS", BIT(4)},524 {"DFXAGG_VNN_REQ_STS", BIT(8)},525 {"EXI_VNN_REQ_STS", BIT(9)},526 {"GBE_VNN_REQ_STS", BIT(19)},527 {"SMB_VNN_REQ_STS", BIT(25)},528 {"LPC_VNN_REQ_STS", BIT(26)},529 {"CNVI_VNN_REQ_STS", BIT(27)},530 {}531};532 533const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = {534 {"FIA2_VNN_REQ_STS", BIT(0)},535 {"CSMERTC_VNN_REQ_STS", BIT(1)},536 {"CSE_VNN_REQ_STS", BIT(4)},537 {"ISH_VNN_REQ_STS", BIT(7)},538 {"SMT1_VNN_REQ_STS", BIT(8)},539 {"SMT4_VNN_REQ_STS", BIT(11)},540 {"CLINK_VNN_REQ_STS", BIT(14)},541 {"SMS1_VNN_REQ_STS", BIT(18)},542 {"SMS2_VNN_REQ_STS", BIT(19)},543 {"GPIOCOM4_VNN_REQ_STS", BIT(20)},544 {"GPIOCOM3_VNN_REQ_STS", BIT(21)},545 {"GPIOCOM2_VNN_REQ_STS", BIT(22)},546 {"GPIOCOM1_VNN_REQ_STS", BIT(23)},547 {"GPIOCOM0_VNN_REQ_STS", BIT(24)},548 {}549};550 551const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = {552 {"ESE_VNN_REQ_STS", BIT(3)},553 {"DTS0_VNN_REQ_STS", BIT(7)},554 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},555 {"FIA1_VNN_REQ_STS", BIT(12)},556 {}557};558 559const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = {560 {"CPU_C10_REQ_STS", BIT(0)},561 {"TS_OFF_REQ_STS", BIT(1)},562 {"PNDE_MET_REQ_STS", BIT(2)},563 {"PCIE_DEEP_PM_REQ_STS", BIT(3)},564 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4)},565 {"ISH_VNNAON_REQ_STS", BIT(7)},566 {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)},567 {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)},568 {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)},569 {"PLT_GREATER_REQ_STS", BIT(11)},570 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},571 {"PM_SYNC_STATES_REQ_STS", BIT(14)},572 {"EA_REQ_STS", BIT(15)},573 {"DMI_CLKREQ_B_REQ_STS", BIT(16)},574 {"BRK_EV_EN_REQ_STS", BIT(17)},575 {"AUTO_DEMO_EN_REQ_STS", BIT(18)},576 {"ITSS_CLK_SRC_REQ_STS", BIT(19)},577 {"ARC_IDLE_REQ_STS", BIT(21)},578 {"DMI_IN_REQ_STS", BIT(22)},579 {"FIA_DEEP_PM_REQ_STS", BIT(23)},580 {"XDCI_ATTACHED_REQ_STS", BIT(24)},581 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},582 {"PRE_WAKE0_REQ_STS", BIT(27)},583 {"PRE_WAKE1_REQ_STS", BIT(28)},584 {"PRE_WAKE2_EN_REQ_STS", BIT(29)},585 {"CNVI_V1P05_REQ_STS", BIT(31)},586 {}587};588 589const struct pmc_bit_map arl_pchs_signal_status_map[] = {590 {"LSX_Wake0_STS", BIT(0)},591 {"LSX_Wake1_STS", BIT(1)},592 {"LSX_Wake2_STS", BIT(2)},593 {"LSX_Wake3_STS", BIT(3)},594 {"LSX_Wake4_STS", BIT(4)},595 {"LSX_Wake5_STS", BIT(5)},596 {"LSX_Wake6_STS", BIT(6)},597 {"LSX_Wake7_STS", BIT(7)},598 {"Int_Timer_SS_Wake0_STS", BIT(8)},599 {"Int_Timer_SS_Wake1_STS", BIT(9)},600 {"Int_Timer_SS_Wake0_STS", BIT(10)},601 {"Int_Timer_SS_Wake1_STS", BIT(11)},602 {"Int_Timer_SS_Wake2_STS", BIT(12)},603 {"Int_Timer_SS_Wake3_STS", BIT(13)},604 {"Int_Timer_SS_Wake4_STS", BIT(14)},605 {"Int_Timer_SS_Wake5_STS", BIT(15)},606 {}607};608 609const struct pmc_bit_map *arl_pchs_lpm_maps[] = {610 arl_pchs_clocksource_status_map,611 arl_pchs_power_gating_status_0_map,612 arl_pchs_power_gating_status_1_map,613 arl_pchs_power_gating_status_2_map,614 arl_pchs_d3_status_0_map,615 arl_pchs_d3_status_1_map,616 arl_pchs_d3_status_2_map,617 arl_pchs_d3_status_3_map,618 arl_pchs_vnn_req_status_0_map,619 arl_pchs_vnn_req_status_1_map,620 arl_pchs_vnn_req_status_2_map,621 arl_pchs_vnn_req_status_3_map,622 arl_pchs_vnn_misc_status_map,623 arl_pchs_signal_status_map,624 NULL625};626 627const struct pmc_reg_map arl_pchs_reg_map = {628 .pfear_sts = ext_arl_socs_pfear_map,629 .ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,630 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,631 .ltr_ignore_max = ARL_SOCS_NUM_IP_IGN_ALLOWED,632 .lpm_sts = arl_pchs_lpm_maps,633 .ltr_show_sts = arl_pchs_ltr_show_map,634 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,635 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,636 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,637 .msr_sts = msr_map,638 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,639 .regmap_length = ARL_PCH_PMC_MMIO_REG_LEN,640 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,641 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,642 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,643 .lpm_en_offset = MTL_LPM_EN_OFFSET,644 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,645 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,646 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,647 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,648 .lpm_num_maps = ADL_LPM_NUM_MAPS,649 .lpm_reg_index = ARL_LPM_REG_INDEX,650 .etr3_offset = ETR3_OFFSET,651};652 653#define PMC_DEVID_SOCS 0xae7f654#define PMC_DEVID_IOEP 0x7ecf655#define PMC_DEVID_PCHS 0x7f27656static struct pmc_info arl_pmc_info_list[] = {657 {658 .guid = IOEP_LPM_REQ_GUID,659 .devid = PMC_DEVID_IOEP,660 .map = &mtl_ioep_reg_map,661 },662 {663 .guid = SOCS_LPM_REQ_GUID,664 .devid = PMC_DEVID_SOCS,665 .map = &arl_socs_reg_map,666 },667 {668 .guid = PCHS_LPM_REQ_GUID,669 .devid = PMC_DEVID_PCHS,670 .map = &arl_pchs_reg_map,671 },672 {}673};674 675#define ARL_NPU_PCI_DEV 0xad1d676#define ARL_GNA_PCI_DEV 0xae4c677/*678 * Set power state of select devices that do not have drivers to D3679 * so that they do not block Package C entry.680 */681static void arl_d3_fixup(void)682{683 pmc_core_set_device_d3(ARL_NPU_PCI_DEV);684 pmc_core_set_device_d3(ARL_GNA_PCI_DEV);685}686 687static int arl_resume(struct pmc_dev *pmcdev)688{689 arl_d3_fixup();690 pmc_core_send_ltr_ignore(pmcdev, 3, 0);691 692 return pmc_core_resume_common(pmcdev);693}694 695int arl_core_init(struct pmc_dev *pmcdev)696{697 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC];698 int ret;699 int func = 0;700 bool ssram_init = true;701 702 arl_d3_fixup();703 pmcdev->suspend = cnl_suspend;704 pmcdev->resume = arl_resume;705 pmcdev->regmap_list = arl_pmc_info_list;706 707 /*708 * If ssram init fails use legacy method to at least get the709 * primary PMC710 */711 ret = pmc_core_ssram_init(pmcdev, func);712 if (ret) {713 ssram_init = false;714 pmc->map = &arl_socs_reg_map;715 716 ret = get_primary_reg_base(pmc);717 if (ret)718 return ret;719 }720 721 pmc_core_get_low_power_modes(pmcdev);722 pmc_core_punit_pmt_init(pmcdev, ARL_PMT_DMU_GUID);723 724 if (ssram_init) {725 ret = pmc_core_ssram_get_lpm_reqs(pmcdev);726 if (ret)727 return ret;728 }729 730 return 0;731}732