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1// SPDX-License-Identifier: GPL-2.02/*3 * This file contains platform specific structure definitions4 * and init function used by Meteor Lake PCH.5 *6 * Copyright (c) 2022, Intel Corporation.7 * All Rights Reserved.8 *9 */10 11#include <linux/pci.h>12#include "core.h"13#include "../pmt/telemetry.h"14 15/* PMC SSRAM PMT Telemetry GUIDS */16#define SOCP_LPM_REQ_GUID 0x262503017#define IOEM_LPM_REQ_GUID 0x435746418#define IOEP_LPM_REQ_GUID 0x507761219 20static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};21 22/*23 * Die Mapping to Product.24 * Product SOCDie IOEDie PCHDie25 * MTL-M SOC-M IOE-M None26 * MTL-P SOC-M IOE-P None27 * MTL-S SOC-S IOE-P PCH-S28 */29 30const struct pmc_bit_map mtl_socm_pfear_map[] = {31 {"PMC", BIT(0)},32 {"OPI", BIT(1)},33 {"SPI", BIT(2)},34 {"XHCI", BIT(3)},35 {"SPA", BIT(4)},36 {"SPB", BIT(5)},37 {"SPC", BIT(6)},38 {"GBE", BIT(7)},39 40 {"SATA", BIT(0)},41 {"DSP0", BIT(1)},42 {"DSP1", BIT(2)},43 {"DSP2", BIT(3)},44 {"DSP3", BIT(4)},45 {"SPD", BIT(5)},46 {"LPSS", BIT(6)},47 {"LPC", BIT(7)},48 49 {"SMB", BIT(0)},50 {"ISH", BIT(1)},51 {"P2SB", BIT(2)},52 {"NPK_VNN", BIT(3)},53 {"SDX", BIT(4)},54 {"SPE", BIT(5)},55 {"FUSE", BIT(6)},56 {"SBR8", BIT(7)},57 58 {"RSVD24", BIT(0)},59 {"OTG", BIT(1)},60 {"EXI", BIT(2)},61 {"CSE", BIT(3)},62 {"CSME_KVM", BIT(4)},63 {"CSME_PMT", BIT(5)},64 {"CSME_CLINK", BIT(6)},65 {"CSME_PTIO", BIT(7)},66 67 {"CSME_USBR", BIT(0)},68 {"CSME_SUSRAM", BIT(1)},69 {"CSME_SMT1", BIT(2)},70 {"RSVD35", BIT(3)},71 {"CSME_SMS2", BIT(4)},72 {"CSME_SMS", BIT(5)},73 {"CSME_RTC", BIT(6)},74 {"CSME_PSF", BIT(7)},75 76 {"SBR0", BIT(0)},77 {"SBR1", BIT(1)},78 {"SBR2", BIT(2)},79 {"SBR3", BIT(3)},80 {"SBR4", BIT(4)},81 {"SBR5", BIT(5)},82 {"RSVD46", BIT(6)},83 {"PSF1", BIT(7)},84 85 {"PSF2", BIT(0)},86 {"PSF3", BIT(1)},87 {"PSF4", BIT(2)},88 {"CNVI", BIT(3)},89 {"UFSX2", BIT(4)},90 {"EMMC", BIT(5)},91 {"SPF", BIT(6)},92 {"SBR6", BIT(7)},93 94 {"SBR7", BIT(0)},95 {"NPK_AON", BIT(1)},96 {"HDA4", BIT(2)},97 {"HDA5", BIT(3)},98 {"HDA6", BIT(4)},99 {"PSF6", BIT(5)},100 {"RSVD62", BIT(6)},101 {"RSVD63", BIT(7)},102 {}103};104 105const struct pmc_bit_map *ext_mtl_socm_pfear_map[] = {106 mtl_socm_pfear_map,107 NULL108};109 110const struct pmc_bit_map mtl_socm_ltr_show_map[] = {111 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},112 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},113 {"SATA", CNP_PMC_LTR_SATA},114 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},115 {"XHCI", CNP_PMC_LTR_XHCI},116 {"SOUTHPORT_F", ADL_PMC_LTR_SPF},117 {"ME", CNP_PMC_LTR_ME},118 {"SATA1", CNP_PMC_LTR_EVA},119 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},120 {"HD_AUDIO", CNP_PMC_LTR_AZ},121 {"CNV", CNP_PMC_LTR_CNV},122 {"LPSS", CNP_PMC_LTR_LPSS},123 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},124 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},125 {"SATA2", CNP_PMC_LTR_CAM},126 {"ESPI", CNP_PMC_LTR_ESPI},127 {"SCC", CNP_PMC_LTR_SCC},128 {"ISH", CNP_PMC_LTR_ISH},129 {"UFSX2", CNP_PMC_LTR_UFSX2},130 {"EMMC", CNP_PMC_LTR_EMMC},131 {"WIGIG", ICL_PMC_LTR_WIGIG},132 {"THC0", TGL_PMC_LTR_THC0},133 {"THC1", TGL_PMC_LTR_THC1},134 {"SOUTHPORT_G", MTL_PMC_LTR_SPG},135 {"ESE", MTL_PMC_LTR_ESE},136 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC},137 138 /* Below two cannot be used for LTR_IGNORE */139 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},140 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},141 {}142};143 144const struct pmc_bit_map mtl_socm_clocksource_status_map[] = {145 {"AON2_OFF_STS", BIT(0)},146 {"AON3_OFF_STS", BIT(1)},147 {"AON4_OFF_STS", BIT(2)},148 {"AON5_OFF_STS", BIT(3)},149 {"AON1_OFF_STS", BIT(4)},150 {"XTAL_LVM_OFF_STS", BIT(5)},151 {"MPFPW1_0_PLL_OFF_STS", BIT(6)},152 {"MPFPW1_1_PLL_OFF_STS", BIT(7)},153 {"USB3_PLL_OFF_STS", BIT(8)},154 {"AON3_SPL_OFF_STS", BIT(9)},155 {"MPFPW2_0_PLL_OFF_STS", BIT(12)},156 {"MPFPW3_0_PLL_OFF_STS", BIT(13)},157 {"XTAL_AGGR_OFF_STS", BIT(17)},158 {"USB2_PLL_OFF_STS", BIT(18)},159 {"FILTER_PLL_OFF_STS", BIT(22)},160 {"ACE_PLL_OFF_STS", BIT(24)},161 {"FABRIC_PLL_OFF_STS", BIT(25)},162 {"SOC_PLL_OFF_STS", BIT(26)},163 {"PCIFAB_PLL_OFF_STS", BIT(27)},164 {"REF_PLL_OFF_STS", BIT(28)},165 {"IMG_PLL_OFF_STS", BIT(29)},166 {"RTC_PLL_OFF_STS", BIT(31)},167 {}168};169 170const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] = {171 {"PMC_PGD0_PG_STS", BIT(0)},172 {"DMI_PGD0_PG_STS", BIT(1)},173 {"ESPISPI_PGD0_PG_STS", BIT(2)},174 {"XHCI_PGD0_PG_STS", BIT(3)},175 {"SPA_PGD0_PG_STS", BIT(4)},176 {"SPB_PGD0_PG_STS", BIT(5)},177 {"SPC_PGD0_PG_STS", BIT(6)},178 {"GBE_PGD0_PG_STS", BIT(7)},179 {"SATA_PGD0_PG_STS", BIT(8)},180 {"PSF13_PGD0_PG_STS", BIT(9)},181 {"SOC_D2D_PGD3_PG_STS", BIT(10)},182 {"MPFPW3_PGD0_PG_STS", BIT(11)},183 {"ESE_PGD0_PG_STS", BIT(12)},184 {"SPD_PGD0_PG_STS", BIT(13)},185 {"LPSS_PGD0_PG_STS", BIT(14)},186 {"LPC_PGD0_PG_STS", BIT(15)},187 {"SMB_PGD0_PG_STS", BIT(16)},188 {"ISH_PGD0_PG_STS", BIT(17)},189 {"P2S_PGD0_PG_STS", BIT(18)},190 {"NPK_PGD0_PG_STS", BIT(19)},191 {"DBG_SBR_PGD0_PG_STS", BIT(20)},192 {"SBRG_PGD0_PG_STS", BIT(21)},193 {"FUSE_PGD0_PG_STS", BIT(22)},194 {"SBR8_PGD0_PG_STS", BIT(23)},195 {"SOC_D2D_PGD2_PG_STS", BIT(24)},196 {"XDCI_PGD0_PG_STS", BIT(25)},197 {"EXI_PGD0_PG_STS", BIT(26)},198 {"CSE_PGD0_PG_STS", BIT(27)},199 {"KVMCC_PGD0_PG_STS", BIT(28)},200 {"PMT_PGD0_PG_STS", BIT(29)},201 {"CLINK_PGD0_PG_STS", BIT(30)},202 {"PTIO_PGD0_PG_STS", BIT(31)},203 {}204};205 206const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] = {207 {"USBR0_PGD0_PG_STS", BIT(0)},208 {"SUSRAM_PGD0_PG_STS", BIT(1)},209 {"SMT1_PGD0_PG_STS", BIT(2)},210 {"FIACPCB_U_PGD0_PG_STS", BIT(3)},211 {"SMS2_PGD0_PG_STS", BIT(4)},212 {"SMS1_PGD0_PG_STS", BIT(5)},213 {"CSMERTC_PGD0_PG_STS", BIT(6)},214 {"CSMEPSF_PGD0_PG_STS", BIT(7)},215 {"SBR0_PGD0_PG_STS", BIT(8)},216 {"SBR1_PGD0_PG_STS", BIT(9)},217 {"SBR2_PGD0_PG_STS", BIT(10)},218 {"SBR3_PGD0_PG_STS", BIT(11)},219 {"U3FPW1_PGD0_PG_STS", BIT(12)},220 {"SBR5_PGD0_PG_STS", BIT(13)},221 {"MPFPW1_PGD0_PG_STS", BIT(14)},222 {"UFSPW1_PGD0_PG_STS", BIT(15)},223 {"FIA_X_PGD0_PG_STS", BIT(16)},224 {"SOC_D2D_PGD0_PG_STS", BIT(17)},225 {"MPFPW2_PGD0_PG_STS", BIT(18)},226 {"CNVI_PGD0_PG_STS", BIT(19)},227 {"UFSX2_PGD0_PG_STS", BIT(20)},228 {"ENDBG_PGD0_PG_STS", BIT(21)},229 {"DBG_PSF_PGD0_PG_STS", BIT(22)},230 {"SBR6_PGD0_PG_STS", BIT(23)},231 {"SBR7_PGD0_PG_STS", BIT(24)},232 {"NPK_PGD1_PG_STS", BIT(25)},233 {"FIACPCB_X_PGD0_PG_STS", BIT(26)},234 {"DBC_PGD0_PG_STS", BIT(27)},235 {"FUSEGPSB_PGD0_PG_STS", BIT(28)},236 {"PSF6_PGD0_PG_STS", BIT(29)},237 {"PSF7_PGD0_PG_STS", BIT(30)},238 {"GBETSN1_PGD0_PG_STS", BIT(31)},239 {}240};241 242const struct pmc_bit_map mtl_socm_power_gating_status_2_map[] = {243 {"PSF8_PGD0_PG_STS", BIT(0)},244 {"FIA_PGD0_PG_STS", BIT(1)},245 {"SOC_D2D_PGD1_PG_STS", BIT(2)},246 {"FIA_U_PGD0_PG_STS", BIT(3)},247 {"TAM_PGD0_PG_STS", BIT(4)},248 {"GBETSN_PGD0_PG_STS", BIT(5)},249 {"TBTLSX_PGD0_PG_STS", BIT(6)},250 {"THC0_PGD0_PG_STS", BIT(7)},251 {"THC1_PGD0_PG_STS", BIT(8)},252 {"PMC_PGD1_PG_STS", BIT(9)},253 {"GNA_PGD0_PG_STS", BIT(10)},254 {"ACE_PGD0_PG_STS", BIT(11)},255 {"ACE_PGD1_PG_STS", BIT(12)},256 {"ACE_PGD2_PG_STS", BIT(13)},257 {"ACE_PGD3_PG_STS", BIT(14)},258 {"ACE_PGD4_PG_STS", BIT(15)},259 {"ACE_PGD5_PG_STS", BIT(16)},260 {"ACE_PGD6_PG_STS", BIT(17)},261 {"ACE_PGD7_PG_STS", BIT(18)},262 {"ACE_PGD8_PG_STS", BIT(19)},263 {"FIA_PGS_PGD0_PG_STS", BIT(20)},264 {"FIACPCB_PGS_PGD0_PG_STS", BIT(21)},265 {"FUSEPMSB_PGD0_PG_STS", BIT(22)},266 {}267};268 269const struct pmc_bit_map mtl_socm_d3_status_0_map[] = {270 {"LPSS_D3_STS", BIT(3)},271 {"XDCI_D3_STS", BIT(4)},272 {"XHCI_D3_STS", BIT(5)},273 {"SPA_D3_STS", BIT(12)},274 {"SPB_D3_STS", BIT(13)},275 {"SPC_D3_STS", BIT(14)},276 {"SPD_D3_STS", BIT(15)},277 {"ESPISPI_D3_STS", BIT(18)},278 {"SATA_D3_STS", BIT(20)},279 {"PSTH_D3_STS", BIT(21)},280 {"DMI_D3_STS", BIT(22)},281 {}282};283 284const struct pmc_bit_map mtl_socm_d3_status_1_map[] = {285 {"GBETSN1_D3_STS", BIT(14)},286 {"GBE_D3_STS", BIT(19)},287 {"ITSS_D3_STS", BIT(23)},288 {"P2S_D3_STS", BIT(24)},289 {"CNVI_D3_STS", BIT(27)},290 {"UFSX2_D3_STS", BIT(28)},291 {}292};293 294const struct pmc_bit_map mtl_socm_d3_status_2_map[] = {295 {"GNA_D3_STS", BIT(0)},296 {"CSMERTC_D3_STS", BIT(1)},297 {"SUSRAM_D3_STS", BIT(2)},298 {"CSE_D3_STS", BIT(4)},299 {"KVMCC_D3_STS", BIT(5)},300 {"USBR0_D3_STS", BIT(6)},301 {"ISH_D3_STS", BIT(7)},302 {"SMT1_D3_STS", BIT(8)},303 {"SMT2_D3_STS", BIT(9)},304 {"SMT3_D3_STS", BIT(10)},305 {"CLINK_D3_STS", BIT(14)},306 {"PTIO_D3_STS", BIT(16)},307 {"PMT_D3_STS", BIT(17)},308 {"SMS1_D3_STS", BIT(18)},309 {"SMS2_D3_STS", BIT(19)},310 {}311};312 313const struct pmc_bit_map mtl_socm_d3_status_3_map[] = {314 {"ESE_D3_STS", BIT(2)},315 {"GBETSN_D3_STS", BIT(13)},316 {"THC0_D3_STS", BIT(14)},317 {"THC1_D3_STS", BIT(15)},318 {"ACE_D3_STS", BIT(23)},319 {}320};321 322const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[] = {323 {"LPSS_VNN_REQ_STS", BIT(3)},324 {"FIA_VNN_REQ_STS", BIT(17)},325 {"ESPISPI_VNN_REQ_STS", BIT(18)},326 {}327};328 329const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[] = {330 {"NPK_VNN_REQ_STS", BIT(4)},331 {"DFXAGG_VNN_REQ_STS", BIT(8)},332 {"EXI_VNN_REQ_STS", BIT(9)},333 {"P2D_VNN_REQ_STS", BIT(18)},334 {"GBE_VNN_REQ_STS", BIT(19)},335 {"SMB_VNN_REQ_STS", BIT(25)},336 {"LPC_VNN_REQ_STS", BIT(26)},337 {}338};339 340const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[] = {341 {"CSMERTC_VNN_REQ_STS", BIT(1)},342 {"CSE_VNN_REQ_STS", BIT(4)},343 {"ISH_VNN_REQ_STS", BIT(7)},344 {"SMT1_VNN_REQ_STS", BIT(8)},345 {"CLINK_VNN_REQ_STS", BIT(14)},346 {"SMS1_VNN_REQ_STS", BIT(18)},347 {"SMS2_VNN_REQ_STS", BIT(19)},348 {"GPIOCOM4_VNN_REQ_STS", BIT(20)},349 {"GPIOCOM3_VNN_REQ_STS", BIT(21)},350 {"GPIOCOM2_VNN_REQ_STS", BIT(22)},351 {"GPIOCOM1_VNN_REQ_STS", BIT(23)},352 {"GPIOCOM0_VNN_REQ_STS", BIT(24)},353 {}354};355 356const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[] = {357 {"ESE_VNN_REQ_STS", BIT(2)},358 {"DTS0_VNN_REQ_STS", BIT(7)},359 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},360 {}361};362 363const struct pmc_bit_map mtl_socm_vnn_misc_status_map[] = {364 {"CPU_C10_REQ_STS", BIT(0)},365 {"TS_OFF_REQ_STS", BIT(1)},366 {"PNDE_MET_REQ_STS", BIT(2)},367 {"PCIE_DEEP_PM_REQ_STS", BIT(3)},368 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)},369 {"NPK_VNNAON_REQ_STS", BIT(5)},370 {"VNN_SOC_REQ_STS", BIT(6)},371 {"ISH_VNNAON_REQ_STS", BIT(7)},372 {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)},373 {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)},374 {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)},375 {"PLT_GREATER_REQ_STS", BIT(11)},376 {"PCIE_CLKREQ_REQ_STS", BIT(12)},377 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},378 {"PM_SYNC_STATES_REQ_STS", BIT(14)},379 {"EA_REQ_STS", BIT(15)},380 {"MPHY_CORE_OFF_REQ_STS", BIT(16)},381 {"BRK_EV_EN_REQ_STS", BIT(17)},382 {"AUTO_DEMO_EN_REQ_STS", BIT(18)},383 {"ITSS_CLK_SRC_REQ_STS", BIT(19)},384 {"LPC_CLK_SRC_REQ_STS", BIT(20)},385 {"ARC_IDLE_REQ_STS", BIT(21)},386 {"MPHY_SUS_REQ_STS", BIT(22)},387 {"FIA_DEEP_PM_REQ_STS", BIT(23)},388 {"UXD_CONNECTED_REQ_STS", BIT(24)},389 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},390 {"USB2_VNNAON_ACT_REQ_STS", BIT(26)},391 {"PRE_WAKE0_REQ_STS", BIT(27)},392 {"PRE_WAKE1_REQ_STS", BIT(28)},393 {"PRE_WAKE2_EN_REQ_STS", BIT(29)},394 {"WOV_REQ_STS", BIT(30)},395 {"CNVI_V1P05_REQ_STS", BIT(31)},396 {}397};398 399const struct pmc_bit_map mtl_socm_signal_status_map[] = {400 {"LSX_Wake0_En_STS", BIT(0)},401 {"LSX_Wake0_Pol_STS", BIT(1)},402 {"LSX_Wake1_En_STS", BIT(2)},403 {"LSX_Wake1_Pol_STS", BIT(3)},404 {"LSX_Wake2_En_STS", BIT(4)},405 {"LSX_Wake2_Pol_STS", BIT(5)},406 {"LSX_Wake3_En_STS", BIT(6)},407 {"LSX_Wake3_Pol_STS", BIT(7)},408 {"LSX_Wake4_En_STS", BIT(8)},409 {"LSX_Wake4_Pol_STS", BIT(9)},410 {"LSX_Wake5_En_STS", BIT(10)},411 {"LSX_Wake5_Pol_STS", BIT(11)},412 {"LSX_Wake6_En_STS", BIT(12)},413 {"LSX_Wake6_Pol_STS", BIT(13)},414 {"LSX_Wake7_En_STS", BIT(14)},415 {"LSX_Wake7_Pol_STS", BIT(15)},416 {"LPSS_Wake0_En_STS", BIT(16)},417 {"LPSS_Wake0_Pol_STS", BIT(17)},418 {"LPSS_Wake1_En_STS", BIT(18)},419 {"LPSS_Wake1_Pol_STS", BIT(19)},420 {"Int_Timer_SS_Wake0_En_STS", BIT(20)},421 {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)},422 {"Int_Timer_SS_Wake1_En_STS", BIT(22)},423 {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)},424 {"Int_Timer_SS_Wake2_En_STS", BIT(24)},425 {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)},426 {"Int_Timer_SS_Wake3_En_STS", BIT(26)},427 {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)},428 {"Int_Timer_SS_Wake4_En_STS", BIT(28)},429 {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)},430 {"Int_Timer_SS_Wake5_En_STS", BIT(30)},431 {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)},432 {}433};434 435const struct pmc_bit_map *mtl_socm_lpm_maps[] = {436 mtl_socm_clocksource_status_map,437 mtl_socm_power_gating_status_0_map,438 mtl_socm_power_gating_status_1_map,439 mtl_socm_power_gating_status_2_map,440 mtl_socm_d3_status_0_map,441 mtl_socm_d3_status_1_map,442 mtl_socm_d3_status_2_map,443 mtl_socm_d3_status_3_map,444 mtl_socm_vnn_req_status_0_map,445 mtl_socm_vnn_req_status_1_map,446 mtl_socm_vnn_req_status_2_map,447 mtl_socm_vnn_req_status_3_map,448 mtl_socm_vnn_misc_status_map,449 mtl_socm_signal_status_map,450 NULL451};452 453const struct pmc_reg_map mtl_socm_reg_map = {454 .pfear_sts = ext_mtl_socm_pfear_map,455 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,456 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,457 .ltr_show_sts = mtl_socm_ltr_show_map,458 .msr_sts = msr_map,459 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,460 .regmap_length = MTL_SOC_PMC_MMIO_REG_LEN,461 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,462 .ppfear_buckets = MTL_SOCM_PPFEAR_NUM_ENTRIES,463 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,464 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,465 .lpm_num_maps = ADL_LPM_NUM_MAPS,466 .ltr_ignore_max = MTL_SOCM_NUM_IP_IGN_ALLOWED,467 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,468 .etr3_offset = ETR3_OFFSET,469 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,470 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,471 .lpm_en_offset = MTL_LPM_EN_OFFSET,472 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,473 .lpm_sts = mtl_socm_lpm_maps,474 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,475 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,476 .lpm_reg_index = MTL_LPM_REG_INDEX,477};478 479const struct pmc_bit_map mtl_ioep_pfear_map[] = {480 {"PMC_0", BIT(0)},481 {"OPI", BIT(1)},482 {"TCSS", BIT(2)},483 {"RSVD3", BIT(3)},484 {"SPA", BIT(4)},485 {"SPB", BIT(5)},486 {"SPC", BIT(6)},487 {"IOE_D2D_3", BIT(7)},488 489 {"RSVD8", BIT(0)},490 {"RSVD9", BIT(1)},491 {"SPE", BIT(2)},492 {"RSVD11", BIT(3)},493 {"RSVD12", BIT(4)},494 {"SPD", BIT(5)},495 {"ACE_7", BIT(6)},496 {"RSVD15", BIT(7)},497 498 {"ACE_0", BIT(0)},499 {"FIACPCB_P", BIT(1)},500 {"P2S", BIT(2)},501 {"RSVD19", BIT(3)},502 {"ACE_8", BIT(4)},503 {"IOE_D2D_0", BIT(5)},504 {"FUSE", BIT(6)},505 {"RSVD23", BIT(7)},506 507 {"FIACPCB_P5", BIT(0)},508 {"ACE_3", BIT(1)},509 {"RSF5", BIT(2)},510 {"ACE_2", BIT(3)},511 {"ACE_4", BIT(4)},512 {"RSVD29", BIT(5)},513 {"RSF10", BIT(6)},514 {"MPFPW5", BIT(7)},515 516 {"PSF9", BIT(0)},517 {"MPFPW4", BIT(1)},518 {"RSVD34", BIT(2)},519 {"RSVD35", BIT(3)},520 {"RSVD36", BIT(4)},521 {"RSVD37", BIT(5)},522 {"RSVD38", BIT(6)},523 {"RSVD39", BIT(7)},524 525 {"SBR0", BIT(0)},526 {"SBR1", BIT(1)},527 {"SBR2", BIT(2)},528 {"SBR3", BIT(3)},529 {"SBR4", BIT(4)},530 {"SBR5", BIT(5)},531 {"RSVD46", BIT(6)},532 {"RSVD47", BIT(7)},533 534 {"RSVD48", BIT(0)},535 {"FIA_P5", BIT(1)},536 {"RSVD50", BIT(2)},537 {"RSVD51", BIT(3)},538 {"RSVD52", BIT(4)},539 {"RSVD53", BIT(5)},540 {"RSVD54", BIT(6)},541 {"ACE_1", BIT(7)},542 543 {"RSVD56", BIT(0)},544 {"ACE_5", BIT(1)},545 {"RSVD58", BIT(2)},546 {"G5FPW1", BIT(3)},547 {"RSVD60", BIT(4)},548 {"ACE_6", BIT(5)},549 {"RSVD62", BIT(6)},550 {"GBETSN1", BIT(7)},551 552 {"RSVD64", BIT(0)},553 {"FIA", BIT(1)},554 {"RSVD66", BIT(2)},555 {"FIA_P", BIT(3)},556 {"TAM", BIT(4)},557 {"GBETSN", BIT(5)},558 {"IOE_D2D_2", BIT(6)},559 {"IOE_D2D_1", BIT(7)},560 561 {"SPF", BIT(0)},562 {"PMC_1", BIT(1)},563 {}564};565 566const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] = {567 mtl_ioep_pfear_map,568 NULL569};570 571const struct pmc_bit_map mtl_ioep_ltr_show_map[] = {572 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},573 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},574 {"SATA", CNP_PMC_LTR_SATA},575 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},576 {"XHCI", CNP_PMC_LTR_XHCI},577 {"SOUTHPORT_F", ADL_PMC_LTR_SPF},578 {"ME", CNP_PMC_LTR_ME},579 {"SATA1", CNP_PMC_LTR_EVA},580 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},581 {"HD_AUDIO", CNP_PMC_LTR_AZ},582 {"CNV", CNP_PMC_LTR_CNV},583 {"LPSS", CNP_PMC_LTR_LPSS},584 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},585 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},586 {"SATA2", CNP_PMC_LTR_CAM},587 {"ESPI", CNP_PMC_LTR_ESPI},588 {"SCC", CNP_PMC_LTR_SCC},589 {"Reserved", MTL_PMC_LTR_RESERVED},590 {"UFSX2", CNP_PMC_LTR_UFSX2},591 {"EMMC", CNP_PMC_LTR_EMMC},592 {"WIGIG", ICL_PMC_LTR_WIGIG},593 {"THC0", TGL_PMC_LTR_THC0},594 {"THC1", TGL_PMC_LTR_THC1},595 {"SOUTHPORT_G", MTL_PMC_LTR_SPG},596 597 /* Below two cannot be used for LTR_IGNORE */598 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},599 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},600 {}601};602 603const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = {604 {"AON2_OFF_STS", BIT(0)},605 {"AON3_OFF_STS", BIT(1)},606 {"AON4_OFF_STS", BIT(2)},607 {"AON5_OFF_STS", BIT(3)},608 {"AON1_OFF_STS", BIT(4)},609 {"TBT_PLL_OFF_STS", BIT(5)},610 {"TMU_PLL_OFF_STS", BIT(6)},611 {"BCLK_PLL_OFF_STS", BIT(7)},612 {"D2D_PLL_OFF_STS", BIT(8)},613 {"AON3_SPL_OFF_STS", BIT(9)},614 {"MPFPW4_0_PLL_OFF_STS", BIT(12)},615 {"MPFPW5_0_PLL_OFF_STS", BIT(13)},616 {"G5FPW_0_PLL_OFF_STS", BIT(14)},617 {"G5FPW_1_PLL_OFF_STS", BIT(15)},618 {"XTAL_AGGR_OFF_STS", BIT(17)},619 {"FABRIC_PLL_OFF_STS", BIT(25)},620 {"SOC_PLL_OFF_STS", BIT(26)},621 {"REF_PLL_OFF_STS", BIT(28)},622 {"RTC_PLL_OFF_STS", BIT(31)},623 {}624};625 626const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = {627 {"PMC_PGD0_PG_STS", BIT(0)},628 {"DMI_PGD0_PG_STS", BIT(1)},629 {"TCSS_PGD0_PG_STS", BIT(2)},630 {"SPA_PGD0_PG_STS", BIT(4)},631 {"SPB_PGD0_PG_STS", BIT(5)},632 {"SPC_PGD0_PG_STS", BIT(6)},633 {"IOE_D2D_PGD3_PG_STS", BIT(7)},634 {"SPE_PGD0_PG_STS", BIT(10)},635 {"SPD_PGD0_PG_STS", BIT(13)},636 {"ACE_PGD7_PG_STS", BIT(14)},637 {"ACE_PGD0_PG_STS", BIT(16)},638 {"FIACPCB_P_PGD0_PG_STS", BIT(17)},639 {"P2S_PGD0_PG_STS", BIT(18)},640 {"ACE_PGD8_PG_STS", BIT(20)},641 {"IOE_D2D_PGD0_PG_STS", BIT(21)},642 {"FUSE_PGD0_PG_STS", BIT(22)},643 {"FIACPCB_P5_PGD0_PG_STS", BIT(24)},644 {"ACE_PGD3_PG_STS", BIT(25)},645 {"PSF5_PGD0_PG_STS", BIT(26)},646 {"ACE_PGD2_PG_STS", BIT(27)},647 {"ACE_PGD4_PG_STS", BIT(28)},648 {"PSF10_PGD0_PG_STS", BIT(30)},649 {"MPFPW5_PGD0_PG_STS", BIT(31)},650 {}651};652 653const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = {654 {"PSF9_PGD0_PG_STS", BIT(0)},655 {"MPFPW4_PGD0_PG_STS", BIT(1)},656 {"SBR0_PGD0_PG_STS", BIT(8)},657 {"SBR1_PGD0_PG_STS", BIT(9)},658 {"SBR2_PGD0_PG_STS", BIT(10)},659 {"SBR3_PGD0_PG_STS", BIT(11)},660 {"SBR4_PGD0_PG_STS", BIT(12)},661 {"SBR5_PGD0_PG_STS", BIT(13)},662 {"FIA_P5_PGD0_PG_STS", BIT(17)},663 {"ACE_PGD1_PGD0_PG_STS", BIT(23)},664 {"ACE_PGD5_PGD1_PG_STS", BIT(25)},665 {"G5FPW1_PGD0_PG_STS", BIT(27)},666 {"ACE_PGD6_PG_STS", BIT(29)},667 {"GBETSN1_PGD0_PG_STS", BIT(31)},668 {}669};670 671const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = {672 {"FIA_PGD0_PG_STS", BIT(1)},673 {"FIA_P_PGD0_PG_STS", BIT(3)},674 {"TAM_PGD0_PG_STS", BIT(4)},675 {"GBETSN_PGD0_PG_STS", BIT(5)},676 {"IOE_D2D_PGD2_PG_STS", BIT(6)},677 {"IOE_D2D_PGD1_PG_STS", BIT(7)},678 {"SPF_PGD0_PG_STS", BIT(8)},679 {"PMC_PGD1_PG_STS", BIT(9)},680 {}681};682 683const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = {684 {"SPF_D3_STS", BIT(0)},685 {"SPA_D3_STS", BIT(12)},686 {"SPB_D3_STS", BIT(13)},687 {"SPC_D3_STS", BIT(14)},688 {"SPD_D3_STS", BIT(15)},689 {"SPE_D3_STS", BIT(16)},690 {"DMI_D3_STS", BIT(22)},691 {}692};693 694const struct pmc_bit_map mtl_ioep_d3_status_1_map[] = {695 {"GBETSN1_D3_STS", BIT(14)},696 {"P2S_D3_STS", BIT(24)},697 {}698};699 700const struct pmc_bit_map mtl_ioep_d3_status_2_map[] = {701 {}702};703 704const struct pmc_bit_map mtl_ioep_d3_status_3_map[] = {705 {"GBETSN_D3_STS", BIT(13)},706 {"ACE_D3_STS", BIT(23)},707 {}708};709 710const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] = {711 {"FIA_VNN_REQ_STS", BIT(17)},712 {}713};714 715const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] = {716 {"DFXAGG_VNN_REQ_STS", BIT(8)},717 {}718};719 720const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] = {721 {}722};723 724const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] = {725 {"DTS0_VNN_REQ_STS", BIT(7)},726 {"DISP_VNN_REQ_STS", BIT(19)},727 {}728};729 730const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = {731 {"CPU_C10_REQ_STS", BIT(0)},732 {"TS_OFF_REQ_STS", BIT(1)},733 {"PNDE_MET_REQ_STS", BIT(2)},734 {"PCIE_DEEP_PM_REQ_STS", BIT(3)},735 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)},736 {"NPK_VNNAON_REQ_STS", BIT(5)},737 {"VNN_SOC_REQ_STS", BIT(6)},738 {"USB_DEVICE_ATTACHED_REQ_STS", BIT(8)},739 {"FIA_EXIT_REQ_STS", BIT(9)},740 {"USB2_SUS_PG_REQ_STS", BIT(10)},741 {"PLT_GREATER_REQ_STS", BIT(11)},742 {"PCIE_CLKREQ_REQ_STS", BIT(12)},743 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},744 {"PM_SYNC_STATES_REQ_STS", BIT(14)},745 {"EA_REQ_STS", BIT(15)},746 {"MPHY_CORE_OFF_REQ_STS", BIT(16)},747 {"BRK_EV_EN_REQ_STS", BIT(17)},748 {"AUTO_DEMO_EN_REQ_STS", BIT(18)},749 {"ITSS_CLK_SRC_REQ_STS", BIT(19)},750 {"LPC_CLK_SRC_REQ_STS", BIT(20)},751 {"ARC_IDLE_REQ_STS", BIT(21)},752 {"MPHY_SUS_REQ_STS", BIT(22)},753 {"FIA_DEEP_PM_REQ_STS", BIT(23)},754 {"UXD_CONNECTED_REQ_STS", BIT(24)},755 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},756 {"USB2_VNNAON_ACT_REQ_STS", BIT(26)},757 {"PRE_WAKE0_REQ_STS", BIT(27)},758 {"PRE_WAKE1_REQ_STS", BIT(28)},759 {"PRE_WAKE2_EN_REQ_STS", BIT(29)},760 {"WOV_REQ_STS", BIT(30)},761 {"CNVI_V1P05_REQ_STS", BIT(31)},762 {}763};764 765const struct pmc_bit_map *mtl_ioep_lpm_maps[] = {766 mtl_ioep_clocksource_status_map,767 mtl_ioep_power_gating_status_0_map,768 mtl_ioep_power_gating_status_1_map,769 mtl_ioep_power_gating_status_2_map,770 mtl_ioep_d3_status_0_map,771 mtl_ioep_d3_status_1_map,772 mtl_ioep_d3_status_2_map,773 mtl_ioep_d3_status_3_map,774 mtl_ioep_vnn_req_status_0_map,775 mtl_ioep_vnn_req_status_1_map,776 mtl_ioep_vnn_req_status_2_map,777 mtl_ioep_vnn_req_status_3_map,778 mtl_ioep_vnn_misc_status_map,779 mtl_socm_signal_status_map,780 NULL781};782 783const struct pmc_reg_map mtl_ioep_reg_map = {784 .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN,785 .pfear_sts = ext_mtl_ioep_pfear_map,786 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,787 .ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES,788 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,789 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,790 .lpm_sts = mtl_ioep_lpm_maps,791 .ltr_show_sts = mtl_ioep_ltr_show_map,792 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,793 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,794 .lpm_num_maps = ADL_LPM_NUM_MAPS,795 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,796 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,797 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,798 .lpm_en_offset = MTL_LPM_EN_OFFSET,799 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,800 .lpm_reg_index = MTL_LPM_REG_INDEX,801};802 803const struct pmc_bit_map mtl_ioem_pfear_map[] = {804 {"PMC_0", BIT(0)},805 {"OPI", BIT(1)},806 {"TCSS", BIT(2)},807 {"RSVD3", BIT(3)},808 {"SPA", BIT(4)},809 {"SPB", BIT(5)},810 {"SPC", BIT(6)},811 {"IOE_D2D_3", BIT(7)},812 813 {"RSVD8", BIT(0)},814 {"RSVD9", BIT(1)},815 {"SPE", BIT(2)},816 {"RSVD11", BIT(3)},817 {"RSVD12", BIT(4)},818 {"SPD", BIT(5)},819 {"ACE_7", BIT(6)},820 {"RSVD15", BIT(7)},821 822 {"ACE_0", BIT(0)},823 {"FIACPCB_P", BIT(1)},824 {"P2S", BIT(2)},825 {"RSVD19", BIT(3)},826 {"ACE_8", BIT(4)},827 {"IOE_D2D_0", BIT(5)},828 {"FUSE", BIT(6)},829 {"RSVD23", BIT(7)},830 831 {"FIACPCB_P5", BIT(0)},832 {"ACE_3", BIT(1)},833 {"RSF5", BIT(2)},834 {"ACE_2", BIT(3)},835 {"ACE_4", BIT(4)},836 {"RSVD29", BIT(5)},837 {"RSF10", BIT(6)},838 {"MPFPW5", BIT(7)},839 840 {"PSF9", BIT(0)},841 {"MPFPW4", BIT(1)},842 {"RSVD34", BIT(2)},843 {"RSVD35", BIT(3)},844 {"RSVD36", BIT(4)},845 {"RSVD37", BIT(5)},846 {"RSVD38", BIT(6)},847 {"RSVD39", BIT(7)},848 849 {"SBR0", BIT(0)},850 {"SBR1", BIT(1)},851 {"SBR2", BIT(2)},852 {"SBR3", BIT(3)},853 {"SBR4", BIT(4)},854 {"RSVD45", BIT(5)},855 {"RSVD46", BIT(6)},856 {"RSVD47", BIT(7)},857 858 {"RSVD48", BIT(0)},859 {"FIA_P5", BIT(1)},860 {"RSVD50", BIT(2)},861 {"RSVD51", BIT(3)},862 {"RSVD52", BIT(4)},863 {"RSVD53", BIT(5)},864 {"RSVD54", BIT(6)},865 {"ACE_1", BIT(7)},866 867 {"RSVD56", BIT(0)},868 {"ACE_5", BIT(1)},869 {"RSVD58", BIT(2)},870 {"G5FPW1", BIT(3)},871 {"RSVD60", BIT(4)},872 {"ACE_6", BIT(5)},873 {"RSVD62", BIT(6)},874 {"GBETSN1", BIT(7)},875 876 {"RSVD64", BIT(0)},877 {"FIA", BIT(1)},878 {"RSVD66", BIT(2)},879 {"FIA_P", BIT(3)},880 {"TAM", BIT(4)},881 {"GBETSN", BIT(5)},882 {"IOE_D2D_2", BIT(6)},883 {"IOE_D2D_1", BIT(7)},884 885 {"SPF", BIT(0)},886 {"PMC_1", BIT(1)},887 {}888};889 890const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = {891 mtl_ioem_pfear_map,892 NULL893};894 895const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = {896 {"PSF9_PGD0_PG_STS", BIT(0)},897 {"MPFPW4_PGD0_PG_STS", BIT(1)},898 {"SBR0_PGD0_PG_STS", BIT(8)},899 {"SBR1_PGD0_PG_STS", BIT(9)},900 {"SBR2_PGD0_PG_STS", BIT(10)},901 {"SBR3_PGD0_PG_STS", BIT(11)},902 {"SBR4_PGD0_PG_STS", BIT(12)},903 {"FIA_P5_PGD0_PG_STS", BIT(17)},904 {"ACE_PGD1_PGD0_PG_STS", BIT(23)},905 {"ACE_PGD5_PGD1_PG_STS", BIT(25)},906 {"G5FPW1_PGD0_PG_STS", BIT(27)},907 {"ACE_PGD6_PG_STS", BIT(29)},908 {"GBETSN1_PGD0_PG_STS", BIT(31)},909 {}910};911 912const struct pmc_bit_map *mtl_ioem_lpm_maps[] = {913 mtl_ioep_clocksource_status_map,914 mtl_ioep_power_gating_status_0_map,915 mtl_ioem_power_gating_status_1_map,916 mtl_ioep_power_gating_status_2_map,917 mtl_ioep_d3_status_0_map,918 mtl_ioep_d3_status_1_map,919 mtl_ioep_d3_status_2_map,920 mtl_ioep_d3_status_3_map,921 mtl_ioep_vnn_req_status_0_map,922 mtl_ioep_vnn_req_status_1_map,923 mtl_ioep_vnn_req_status_2_map,924 mtl_ioep_vnn_req_status_3_map,925 mtl_ioep_vnn_misc_status_map,926 mtl_socm_signal_status_map,927 NULL928};929 930const struct pmc_reg_map mtl_ioem_reg_map = {931 .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN,932 .pfear_sts = ext_mtl_ioem_pfear_map,933 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,934 .ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES,935 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,936 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,937 .lpm_sts = mtl_ioem_lpm_maps,938 .ltr_show_sts = mtl_ioep_ltr_show_map,939 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,940 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,941 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,942 .lpm_num_maps = ADL_LPM_NUM_MAPS,943 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,944 .lpm_en_offset = MTL_LPM_EN_OFFSET,945 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,946 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,947 .lpm_reg_index = MTL_LPM_REG_INDEX,948};949 950#define PMC_DEVID_SOCM 0x7e7f951#define PMC_DEVID_IOEP 0x7ecf952#define PMC_DEVID_IOEM 0x7ebf953static struct pmc_info mtl_pmc_info_list[] = {954 {955 .guid = SOCP_LPM_REQ_GUID,956 .devid = PMC_DEVID_SOCM,957 .map = &mtl_socm_reg_map,958 },959 {960 .guid = IOEP_LPM_REQ_GUID,961 .devid = PMC_DEVID_IOEP,962 .map = &mtl_ioep_reg_map,963 },964 {965 .guid = IOEM_LPM_REQ_GUID,966 .devid = PMC_DEVID_IOEM,967 .map = &mtl_ioem_reg_map968 },969 {}970};971 972#define MTL_GNA_PCI_DEV 0x7e4c973#define MTL_IPU_PCI_DEV 0x7d19974#define MTL_VPU_PCI_DEV 0x7d1d975/*976 * Set power state of select devices that do not have drivers to D3977 * so that they do not block Package C entry.978 */979static void mtl_d3_fixup(void)980{981 pmc_core_set_device_d3(MTL_GNA_PCI_DEV);982 pmc_core_set_device_d3(MTL_IPU_PCI_DEV);983 pmc_core_set_device_d3(MTL_VPU_PCI_DEV);984}985 986static int mtl_resume(struct pmc_dev *pmcdev)987{988 mtl_d3_fixup();989 pmc_core_send_ltr_ignore(pmcdev, 3, 0);990 991 return pmc_core_resume_common(pmcdev);992}993 994int mtl_core_init(struct pmc_dev *pmcdev)995{996 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC];997 int ret;998 int func = 2;999 bool ssram_init = true;1000 1001 mtl_d3_fixup();1002 1003 pmcdev->suspend = cnl_suspend;1004 pmcdev->resume = mtl_resume;1005 pmcdev->regmap_list = mtl_pmc_info_list;1006 1007 /*1008 * If ssram init fails use legacy method to at least get the1009 * primary PMC1010 */1011 ret = pmc_core_ssram_init(pmcdev, func);1012 if (ret) {1013 ssram_init = false;1014 dev_warn(&pmcdev->pdev->dev,1015 "ssram init failed, %d, using legacy init\n", ret);1016 pmc->map = &mtl_socm_reg_map;1017 ret = get_primary_reg_base(pmc);1018 if (ret)1019 return ret;1020 }1021 1022 pmc_core_get_low_power_modes(pmcdev);1023 pmc_core_punit_pmt_init(pmcdev, MTL_PMT_DMU_GUID);1024 1025 if (ssram_init)1026 return pmc_core_ssram_get_lpm_reqs(pmcdev);1027 1028 return 0;1029}1030